semiconductor memory device

Abstract

To suppress an increase in a chip area.SOLUTION: According to an embodiment, a semiconductor storage device includes: a first memory cell array 11_1; a second memory cell array 11_2 arranged above the first memory cell array; a third memory cell array 11_3 arranged adjacent to the first memory cell array; a fourth memory cell array 11_4 arranged above the third memory cell array and arranged adjacent to the second memory cell array; a first word line WLa connected to the first and second memory cell arrays; a second word line WLb connected to the third and fourth memory cell arrays; a first bit line BLa connected to the first and fourth cell arrays; and a second bit line BLb connected to the second and third memory cell arrays.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] FIELD Embodiments of the present invention relate to a semiconductor memory device. [Background technology]

[0002] NAND flash memory is known as a semiconductor memory device. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2018-152419 [Patent Document 2] U.S. Patent No. 10,998,301 [Patent Document 3] U.S. Patent No. 10,651,153 Summary of the Invention [Problem to be solved by the invention]

[0004] An embodiment of the present invention can provide a semiconductor memory device that can suppress an increase in chip area. [Means for solving the problem]

[0005] A semiconductor memory device according to the embodiment includes a first memory cell array, a second memory cell array arranged above the first memory cell array in a first direction, a third memory cell array arranged adjacent to the first memory cell array in a second direction intersecting the first direction, a fourth memory cell array arranged above the third memory cell array in the first direction and adjacent to the second memory cell array in the second direction, first word lines connected to the first memory cell array and the second memory cell array, second word lines connected to the third memory cell array and the fourth memory cell array, first bit lines connected to the first memory cell array and the fourth memory cell array, and second bit lines connected to the second memory cell array and the third memory cell array.a first select gate line connected to the first memory cell array and the second memory cell array, and a second select gate line connected to the third memory cell array and the fourth memory cell array; Includes: [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a block diagram showing the overall configuration of a semiconductor memory device according to the first embodiment. [Figure 2] FIG. 2 is a circuit diagram of a memory cell array included in the semiconductor memory device according to the first embodiment. [Figure 3] FIG. 3 is a cross-sectional view showing the arrangement of the circuit chip 20 and the array chips 10_1 and 10_2 included in the semiconductor memory device according to the first embodiment. [Figure 4] FIG. 4 is a perspective view showing the arrangement of memory cell arrays 11_1 to 11_4 and circuit chips 20 included in the semiconductor memory device according to the first embodiment. [Figure 5] FIG. 5 is a plan view of the memory cell array 11_2 included in the semiconductor memory device according to the first embodiment. [Figure 6] FIG. 6 is a plan view of the memory cell array 11_1 included in the semiconductor memory device according to the first embodiment. [Figure 7] FIG. 7 is a cross-sectional view taken along the line A1-A2 in FIGS. [Figure 8] FIG. 8 is a cross-sectional view taken along line B1-B2 in FIGS. [Figure 9] FIG. 9 is a cross-sectional view taken along the line C1-C2 in FIGS. [Figure 10] FIG. 10 is a cross-sectional view taken along the line D1-D2 in FIGS. [Figure 11] FIG. 11 is a plan view of the BL connection portion of the array chip 10_2 included in the semiconductor memory device according to the first embodiment. [Figure 12] FIG. 12 is a cross-sectional view taken along line E1-E2 in FIG. [Figure 13] FIG. 13 is a conceptual diagram showing a case where a cell unit CU in an array unit AUa is selected in the semiconductor memory device according to the first embodiment. [Figure 14]FIG. 14 is a conceptual diagram showing a case where a cell unit CU in an array unit AUb is selected in the semiconductor memory device according to the first embodiment. [Figure 15] FIG. 15 is a diagram showing the write order of one block BLK in each memory cell array 11 in the semiconductor memory device according to the first embodiment. [Figure 16] FIG. 16 is a perspective view showing the arrangement of memory cell arrays 11_1 to 11_4 and circuit chips 20 included in the semiconductor memory device according to the second embodiment. [Figure 17] FIG. 17 is a plan view of a memory cell array 11_2 included in the semiconductor memory device according to the second embodiment. [Figure 18] FIG. 18 is a plan view of a memory cell array 11_1 included in the semiconductor memory device according to the second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] The following describes embodiments with reference to the drawings. In the following description, components having substantially the same functions and configurations are designated by the same reference numerals. Duplicate explanations may be omitted if unnecessary. Each embodiment described below exemplifies an apparatus or method for embodying the technical concept of the embodiment. The technical concept of the embodiment does not limit the materials, shapes, structures, arrangements, etc. of the components to those described below. The technical concept of the embodiment can be modified in various ways without departing from the gist of the invention. These embodiments and their variations are included in the scope of the invention described in the claims and their equivalents.

[0008] 1. First embodiment A semiconductor memory device according to a first embodiment will be described.

[0009] 1.1 Overall configuration of semiconductor memory device First, an example of the overall configuration of a semiconductor memory device 1 will be described with reference to Fig. 1. Fig. 1 is a block diagram showing the overall configuration of the semiconductor memory device 1. Note that in Fig. 1, some of the connections between the components are indicated by arrows, but the connections between the components are not limited to these.

[0010] The semiconductor memory device 1 is, for example, a three-dimensional stacked NAND flash memory. The three-dimensional stacked NAND flash memory includes a plurality of nonvolatile memory cell transistors arranged three-dimensionally on a semiconductor substrate.

[0011] As shown in FIG. 1, the semiconductor memory device 1 includes a plurality of array chips 10 and a circuit chip 20. The array chip 10 is a chip provided with an array of non-volatile memory cell transistors. The circuit chip 20 is a chip provided with a circuit for controlling the array chip 10. The semiconductor memory device 1 of this embodiment is formed by bonding together a plurality of array chips 10 and the circuit chip 20. Hereinafter, when there is no need to specify either the array chip 10 or the circuit chip 20, it will be simply referred to as a "chip."

[0012] 1, the semiconductor memory device 1 includes two array chips 10_1 and 10_2. The number of array chips 10 may be three or more. Hereinafter, when there is no limitation on either the array chip 10_1 or 10_2, it will be referred to as the array chip 10.

[0013] Each array chip 10 includes a plurality of memory cell arrays 11. The memory cell array 11 is an area in which non-volatile memory cell transistors are arranged three-dimensionally. In the example of FIG. 1, the array chip 10_1 includes memory cell arrays 11_1 and 11_3. The array chip 10_2 includes memory cell arrays 11_2 and 11_4. Note that each array chip 10 may include three or more memory cell arrays 11. Hereinafter, when there is no limitation to any of the memory cell arrays 11_1 to 11_4, it will be referred to as the memory cell array 11.

[0014] The circuit chip 20 includes a sequencer 21, a voltage generating circuit 22, multiple row decoders 23, and multiple sense amplifiers 24. In the example of FIG. 1, the semiconductor memory device 1 includes two row decoders 23a and 23b and two sense amplifiers 24a and 24b. Hereinafter, when either the row decoders 23a or 23b is not specified, it will be referred to as the row decoder 23. When either the sense amplifiers 24a or 24b is not specified, it will be referred to as the sense amplifier 24.

[0015] The sequencer 21 is a circuit that controls the semiconductor memory device 1. The sequencer 21 is connected to the voltage generation circuit 22, row decoders 23a and 23b, and sense amplifiers 24a and 24b. The sequencer 21 controls the voltage generation circuit 22, row decoders 23a and 23b, and sense amplifiers 24a and 24b. The sequencer 21 also controls the overall operation of the semiconductor memory device 1 under the control of an external controller. More specifically, the sequencer 21 executes write operations, read operations, erase operations, etc.

[0016] The voltage generation circuit 22 is a circuit that generates voltages used for write operations, read operations, erase operations, etc. The voltage generation circuit 22 is connected to the row decoders 23a and 23b, the sense amplifiers 24a and 24b, etc. The voltage generation circuit 22 supplies voltages to the row decoders 23a and 23b, the sense amplifiers 24a and 24b, etc.

[0017] The row decoder 23 is a circuit that decodes row addresses. The row address is an address signal that specifies the row-direction wiring of the memory cell array 11. The address signal is included in a write command, a read command, an erase command, etc. received from an external controller. The row decoder 23 supplies the voltage applied from the voltage generating circuit 22 to the memory cell array 11 based on the result of decoding the row address. In this embodiment, one row decoder 23 is provided for two memory cell arrays 11.

[0018] For example, the row decoder 23a is commonly connected to the memory cell arrays 11_1 and 11_2 via a plurality of word lines WLa and a plurality of select gate lines SGDa and SGSa. Similarly, the row decoder 23b is commonly connected to the memory cell arrays 11_3 and 11_4 via a plurality of word lines WLb and a plurality of select gate lines SGDb and SGSb. The word lines WLa and WLb are wirings used to control memory cell transistors. The select gate lines SGDa and SGDb, and SGSa and SGSb are wirings used to select string units SU.

[0019] More specifically, the memory cell arrays 11_1 and 11_2 share word lines WLa and select gate lines SGDa and SGSa. That is, the word lines WLa of the memory cell array 11_1 and the word lines WLa of the memory cell array 11_2 are commonly connected to a row decoder 23a. Similarly, the select gate lines SGDa of the memory cell array 11_1 and the select gate lines SGDa of the memory cell array 11_2 are commonly connected to the row decoder 23a. Furthermore, the select gate lines SGSa of the memory cell array 11_1 and the select gate lines SGSa of the memory cell array 11_2 are commonly connected to the row decoder 23a.

[0020] Similarly, the memory cell arrays 11_3 and 11_4 share word lines WLb and select gate lines SGDb and SGSb. That is, the word lines WLb of the memory cell array 11_3 and the word lines WLb of the memory cell array 11_4 are commonly connected to a row decoder 23b. Similarly, the select gate lines SGDb of the memory cell array 11_3 and the select gate lines SGDb of the memory cell array 11_4 are commonly connected to the row decoder 23b. Furthermore, the select gate lines SGSb of the memory cell array 11_3 and the select gate lines SGSb of the memory cell array 11_4 are commonly connected to the row decoder 23b.

[0021] The sense amplifier 24 is a circuit that writes and reads data. During a read operation, the sense amplifier 24 senses data read from the corresponding memory cell array 11. During a write operation, the sense amplifier 24 supplies a voltage corresponding to the write data to the memory cell array 11. In this embodiment, one sense amplifier 24 is provided for two memory cell arrays 11.

[0022] The sense amplifier 24a is commonly connected to the memory cell arrays 11_1 and 11_4 via a plurality of bit lines BLa. Similarly, the sense amplifier 24b is commonly connected to the memory cell arrays 11_2 and 11_3 via a plurality of bit lines BLb.

[0023] More specifically, the memory cell array 11_1 and the memory cell array 11_4 share a bit line BLa. That is, the bit line BLa of the memory cell array 11_1 and the bit line BLa of the memory cell array 11_4 are commonly connected to a sense amplifier 24a. Similarly, the memory cell array 11_2 and the memory cell array 11_3 share a bit line BLb. That is, the bit line BLb of the memory cell array 11_2 and the bit line BLb of the memory cell array 11_3 are commonly connected to a sense amplifier 24b.

[0024] Next, the internal configuration of the memory cell array 11 will be described. The memory cell array 11 includes a plurality of blocks BLK. A block BLK is, for example, a collection of a plurality of memory cell transistors from which data is erased collectively. The plurality of memory cell transistors in a block BLK are associated with rows and columns. In the example of FIG. 1, the memory cell array 11_1 includes BLK0_1, BLK1_1, .... The memory cell array 11_2 includes BLK0_2, BLK1_2, .... The memory cell array 11_3 includes BLK0_3, BLK1_3, .... The memory cell array 11_4 includes BLK0_4, BLK1_4, .... Hereinafter, when there is no limitation on any block of any memory cell array 11, it will be referred to as a block BLK.

[0025] Each block BLK includes multiple string units SU. The string unit SU is a set of multiple NAND strings that are collectively selected, for example, during a write or read operation. The NAND string includes a set of multiple memory cell transistors connected in series. In the example of FIG. 1, each block BLK includes four string units SU0 to SU3. More specifically, for example, block BLK0_1 includes four string units SU0_1, SU1_1, SU2_1, and SU3_1. Block BLK0_2 includes four string units SU0_2, SU1_2, SU2_2, and SU3_2. Block BLK0_3 includes four string units SU0_3, SU1_3, SU2_3, and SU3_3. Block BLK0_4 includes four string units SU0_4, SU1_4, SU2_4, and SU3_4. Hereinafter, when a string unit in any memory cell array 11 is not specified, it will be referred to as a string unit SU.

[0026] It should be noted that there may be any number of blocks BLK in the memory cell array 11 and any number of string units SU in each block BLK. The circuit configuration of the memory cell array 11 will be described later.

[0027] 1.2 Memory cell array circuit configuration Next, an example of the circuit configuration of the memory cell arrays 11_1 to 11_4 will be described with reference to Fig. 2. Fig. 2 is a circuit diagram of the memory cell arrays 11_1 to 11_4.

[0028] As shown in FIG. 2, the string unit SU includes a plurality of NAND strings NS.

[0029] The NAND string NS includes a plurality of memory cell transistors MC and select transistors ST1 and ST2. In the example of Fig. 2, the NAND string NS includes five memory cell transistors MC0 to MC4. The number of memory cell transistors MC is arbitrary.

[0030] The memory cell transistor MC stores data in a non-volatile manner. The memory cell transistor MC includes a control gate and a charge storage layer. The memory cell transistor MC may be a MONOS (Metal-Oxide-Nitride-Oxide-Silicon) type or an FG (Floating Gate) type. The MONOS type uses an insulating layer for the charge storage layer. The FG type uses a conductive layer for the charge storage layer. The following describes the case where the memory cell transistor MC is a MONOS type.

[0031] The select transistors ST1 and ST2 are used to select the string unit SU during various operations. The number of select transistors ST1 and ST2 is arbitrary. It is sufficient that the NAND string NS includes one or more select transistors ST1 and ST2.

[0032] The current paths of the memory cell transistor MC and the select transistors ST1 and ST2 in each NAND string NS are connected in series. In the example of FIG. 2, the select transistor ST2, memory cell transistors MC0, MC1, MC2, MC3, and MC4, and the select transistor ST1 are arranged in this order from the bottom to the top of the page. The current paths of each are connected in series. In other words, the select transistor ST2, memory cell transistors MC0, MC1, MC2, MC3, and MC4, and the select transistor ST1 are connected in this order from the source line SL to the bit line BL. The drain of the select transistor ST1 is connected to one of the bit lines BL. The source of the select transistor ST2 is connected to the source line SL.

[0033] The drains of the multiple select transistors ST1 in the string unit SU are connected to different bit lines BL. In the example of FIG. 2, the drains of the select transistors ST1 of n+1 (n is an integer equal to or greater than 0) NAND strings NS in the string unit SU are connected to n+1 bit lines BL, respectively. The drains of one select transistor ST1 in each string unit SU of the two memory cell arrays 11 are connected in common to one bit line BL. That is, the two memory cell arrays 11 share the bit line BL.

[0034] More specifically, the n+1 select transistors ST1 of each string unit SU of the memory cell array 11_1 and the n+1 select transistors ST1 of each string unit SU of the memory cell array 11_4 are connected in common to n+1 bit lines BLa0 to BLa(n), respectively. For example, the drains of one select transistor ST1 of each of the string units SU0_1 to SU3_1 and the string units SU0_4 to SU3_4 are connected in common to the bit line BLa0. Similarly, the n+1 select transistors ST1 of each string unit SU of the memory cell array 11_2 and the n+1 select transistors ST1 of each string unit SU of the memory cell array 11_3 are connected in common to n+1 bit lines BLb0 to BLb(n), respectively.

[0035] The control gates of the memory cell transistors MC0 to MC4 included in one block BLK of the memory cell array 11_1 and one block BLK of the memory cell array 11_2 are commonly connected to word lines WLa0 to WLa4, respectively. More specifically, the blocks BLK0_1 and BLK0_2 include a plurality of memory cell transistors MC0. The control gates of these memory cell transistors MC0 are commonly connected to one word line WLa0. The other memory cell transistors MC1 to MC4 are similarly commonly connected to word lines WLa1 to WLa4, respectively. That is, the block BLK0_1 and the block BLK0_2 share the word line WL. The same is true for the other blocks BLK of the memory cell arrays 11_1 and 11_2.

[0036] Similarly, the control gates of the memory cell transistors MC0 to MC4 included in one block BLK of the memory cell array 11_3 and one block BLK of the memory cell array 11_4 are commonly connected to word lines WLb0 to WLb4, respectively. More specifically, the blocks BLK0_3 and BLK0_4 include a plurality of memory cell transistors MC0. The control gates of these memory cell transistors MC0 are commonly connected to one word line WLb0. The other memory cell transistors MC1 to MC4 are similarly commonly connected to word lines WLb1 to WLb4, respectively. That is, the blocks BLK0_3 and BLK0_4 share the word line WL. The same is true for the other blocks BLK of the memory cell arrays 11_3 and 11_4.

[0037] The gates of the multiple select transistors ST1 included in one string unit SU in one block BLK of the memory cell array 11_1 and one string unit SU in one block BLK of the memory cell array 11_2 are commonly connected to a select gate line SGDa. For example, the string unit SU0_1 in the block BLK0_1 and the string unit SU0_2 in the block BLK0_2 each include multiple select transistors ST1. The gates of these multiple select transistors ST1 are commonly connected to a single select gate line SGDa0. That is, the string unit SU0_1 in the block BLK0_1 and the string unit SU0_2 in the block BLK0_2 share the select gate line SGDa0. Similarly, the multiple select transistors ST1 included in the string unit SU1_1 in the block BLK0_1 and the string unit SU1_2 in the block BLK0_2 are commonly connected to a select gate line SGDa1. The multiple select transistors ST1 of the string unit SU2_1 in the block BLK0_1 and the string unit SU2_2 in the block BLK0_2 are commonly connected to the select gate line SGDa2. The multiple select transistors ST1 of the string unit SU3_1 in the block BLK0_1 and the string unit SU3_2 in the block BLK0_2 are commonly connected to the select gate line SGDa3. The same applies to the other blocks BLK in the memory cell arrays 11_1 and 11_2.

[0038] Furthermore, the gates of the multiple select transistors ST1 included in one string unit SU in one block BLK of the memory cell array 11_3 and one string unit SU in one block BLK of the memory cell array 11_4 are commonly connected to a select gate line SGDb. For example, the multiple select transistors ST1 included in the string unit SU0_3 in the block BLK0_3 and the string unit SU0_4 in the block BLK0_4 are commonly connected to a select gate line SGDb0. Similarly, the multiple select transistors ST1 included in the string unit SU1_3 in the block BLK0_3 and the string unit SU1_4 in the block BLK0_4 are commonly connected to a select gate line SGDb1. The multiple select transistors ST1 included in the string unit SU2_3 in the block BLK0_3 and the string unit SU2_4 in the block BLK0_4 are commonly connected to a select gate line SGDb2. The select transistors ST1 of the string unit SU3_3 in the block BLK0_3 and the string unit SU3_4 in the block BLK0_4 are commonly connected to a select gate line SGDb3, as are the other blocks BLK of the memory cell arrays 11_3 and 11_4.

[0039] The gates of the multiple select transistors ST2 included in one block BLK of the memory cell array 11_1 and one block BLK of the memory cell array 11_2 are commonly connected to one select gate line SGSa. More specifically, for example, the blocks BLK0_1 and BLK0_2 include multiple select transistors ST2. The gates of these multiple select transistors ST2 are commonly connected to one select gate line SGSa. That is, the blocks BLK0_1 and BLK0_2 share the select gate line SGSa. The same applies to the other blocks BLK of the memory cell arrays 11_1 and 11_2. Note that the memory cell arrays 11_1 and 11_2 may share different select gate lines SGSa for each string unit SU.

[0040] Furthermore, the gates of the multiple select transistors ST2 included in one block BLK of the memory cell array 11_3 and one block BLK of the memory cell array 11_4 are commonly connected to one select gate line SGSb. More specifically, for example, blocks BLK0_3 and BLK0_4 include multiple select transistors ST2. The gates of these multiple select transistors ST2 are commonly connected to one select gate line SGSb. That is, blocks BLK0_3 and BLK0_4 share the select gate line SGSb. The same applies to the other blocks BLK of the memory cell arrays 11_3 and 11_4. Note that the memory cell arrays 11_3 and 11_4 may share different select gate lines SGSb for each string unit SU.

[0041] The source line SL is shared among, for example, a plurality of blocks BLK of the memory cell arrays 11_1 to 11_4.

[0042] Hereinafter, a set of multiple memory cell transistors MC connected to one word line WL in one string unit SU will be referred to as a "cell unit CU." For example, when a memory cell transistor MC stores one bit of data, the storage capacity of the cell unit CU is defined as "one page of data." Depending on the number of bits of data stored in the memory cell transistor MC, the cell unit CU may have a storage capacity of two or more pages of data.

[0043] In this embodiment, two cell units CU in two memory cell arrays 11 connected in common to a word line WL can be simultaneously selected during write and read operations. For example, when the row decoder 23a selects the word line WLa0 and the select gate line SGDa0 during write or read operations, two cell units CU are selected: the cell unit CU including the memory cell transistor MC0 in the string unit SU0_1, and the cell unit CU including the memory cell transistor MC0 in the string unit SU0_2. At this time, a voltage is applied from the sense amplifier 24a to the cell unit CU in the string unit SU0_1 via the bit line BLa. A voltage is applied from the sense amplifier 24b to the cell unit CU in the string unit SU0_2 via the bit line BLb. Therefore, during write or read operations, the page data of each of the two cell units CU can be processed simultaneously.

[0044] 1.3 Chip placement Next, an example of the layout of each chip will be described with reference to Fig. 3. Fig. 3 is a cross-sectional view showing the layout of the circuit chip 20 and the array chips 10_1 and 10_2. In the example of Fig. 3, for the sake of simplicity, only one word line WLa and one WLb and one bit line BLa and one BLb are shown. The select gate lines SGD and SGS and the source line SL are omitted.

[0045] Hereinafter, the direction approximately parallel to the surface of the circuit chip 20 will be referred to as the X direction. The direction that intersects with the X direction and is approximately parallel to the surface of the circuit chip 20 will be referred to as the Y direction. The direction that intersects with the X and Y directions and is approximately perpendicular to the surface of the circuit chip 20 will be referred to as the Z direction. When further limiting the Z direction, the direction from the array chip 10 toward the circuit chip 20 will be referred to as the Z1 direction, and the direction opposite to the Z1 direction will be referred to as the Z2 direction.

[0046] 3, in the Z2 direction, the array chip 10_1 is provided on the circuit chip 20. Then, the array chip 10_2 is provided on the array chip 10_1.

[0047] In the circuit chip 20, row decoders 23a and 23b and sense amplifiers 24a and 24b are provided on a semiconductor substrate 200.

[0048] In the array chip 10_1, for example, memory cell arrays 11_1 and 11_3 are arranged side by side in the Y direction. For example, in the Z2 direction, the memory cell array 11_1 is provided above the row decoder 23a and the sense amplifier 24a. Also, for example, in the Z2 direction, the memory cell array 11_3 is provided above the row decoder 23b and the sense amplifier 24b.

[0049] In the array chip 10_2, for example, memory cell arrays 11_2 and 11_4 are arranged side by side in the Y direction. In the Z2 direction, the memory cell array 11_2 is provided above the memory cell array 11_1. In the Z2 direction, the memory cell array 11_4 is provided above the memory cell array 11_3. That is, the memory cell arrays 11_1 and 11_2 are stacked in the Z direction. Similarly, the memory cell arrays 11_3 and 11_4 are stacked in the Z direction.

[0050] Hereinafter, a set of multiple memory cell arrays 11 stacked in the Z direction and connected in common by word lines WL will be referred to as an array unit AU. More specifically, for example, memory cell arrays 11_1 and 11_2 constitute an array unit AUa. Furthermore, memory cell arrays 11_3 and 11_4 constitute an array unit AUb. The semiconductor memory device 1 includes two array units AUa and AUb arranged adjacent to each other in the Y direction.

[0051] One end of the word line WLa is connected to the row decoder 23a. The word line WLa is connected in common to the memory cell arrays 11_1 and 11_2 stacked in the Z direction. One end of the word line WLb is connected to the row decoder 23b. The word line WLb is connected in common to the memory cell arrays 11_3 and 11_4 stacked in the Z direction.

[0052] The bit line BLa is connected to a sense amplifier 24a. The bit line BLa is connected in common to the memory cell arrays 11_1 and 11_4, which are located at different positions in the Z and Y directions. The bit line BLb is connected in common to the memory cell arrays 11_2 and 11_3, which are located at different positions in the Z and Y directions. That is, the bit line BL is connected in common to one memory cell array 11 in one array unit AU and one memory cell array 11 provided in a different array chip 10 in the other array unit AU. In other words, the bit line BL is connected in common to two memory cell arrays 11 that do not share word lines WL and are provided in different array chips 10.

[0053] 1.4 Memory cell array layout Next, an example of the arrangement of memory cell arrays will be described with reference to Fig. 4. Fig. 4 is a perspective view showing the arrangement of memory cell arrays 11_1 to 11_4 and the circuit chip 20. In the example of Fig. 4, for the sake of simplicity, each memory cell array 11 is shown to have one word line WLa and one WLb, one select gate line SGDa, one SGDb, one SGSa, and one SGSb, and four bit lines BLa and one BLb. Source lines SL are omitted.

[0054] As shown in FIG. 4, the memory cell array 11 includes a cell section and a WLSG connection section. The cell section is an area where memory cell transistors are arranged. The WLSG connection section is an area where a plurality of contact plugs connected to word lines WL and select gate lines SGD and SGS, respectively, are provided. For example, the word lines WLa and select gate lines SGDa and SGSa of the memory cell arrays 11_1 and 11_2 are commonly connected to a row decoder 23a of the circuit chip 20. The word lines WLb and select gate lines SGDb and SGSb of the memory cell arrays 11_3 and 11_4 are commonly connected to a row decoder 23b of the circuit chip 20.

[0055] BL connection portions are provided between the memory cell array 11_1 and the memory cell array 11_3, and between the memory cell array 11_2 and the memory cell array 11_4. The BL connection portions are connection regions for connecting the bit lines BL provided in the array chips 10_1 and 10_2 to each other. More specifically, for example, a plurality of bit lines BL extending in the Y direction are provided in the cell portion of each memory cell array 11. At the BL connection portion, the bit line BLa of the memory cell array 11_1 is connected to the bit line BLa of the memory cell array 11_4. The bit line BLa of the memory cell array 11_1 extends from the cell portion in the Z direction and is connected to the sense amplifier 24a of the circuit chip 20. At the BL connection portion, the bit line BLb of the memory cell array 11_2 is connected to the bit line BLb of the memory cell array 11_3. The bit line BLb of the memory cell array 11_3 extends from the cell portion in the Z direction and is connected to the sense amplifier 24b of the circuit chip 20.

[0056] 4, for example, near the center of the cell portion of the memory cell array 11_1, the connection portion with the sense amplifier 24a is provided in the middle portion of the bit line BLa, but this is not limited to this. For example, the connection portion may be provided at the end of the bit line BLa. Furthermore, the connection portions of each bit line BLa do not have to be arranged side by side in the X direction. The same applies to the bit line BLb.

[0057] 1.5 Planar configuration of memory cell array Next, an example of the configuration of the memory cell array 11 will be described with reference to FIGS. 5 and 6. FIG. 5 is a plan view of the memory cell array 11_2. FIG. 6 is a plan view of the memory cell array 11_1. In the examples of FIGS. 5 and 6, for the sake of simplicity, a case will be described in which each memory cell array 11 includes four blocks BLK0 to BLK3 and each block BLK includes one string unit SU. In addition, in the examples of FIGS. 5 and 6, insulating layers are omitted. The configuration of the memory cell array 11_3 is similar to that of the memory cell array 11_1. The configuration of the memory cell array 11_4 is similar to that of the memory cell array 11_2.

[0058] First, the planar configuration of the memory cell array 11_2 will be described.

[0059] As shown in FIG. 5, four blocks BLK0_2 to BLK3_2 are arranged side by side in the Y direction from the top to the bottom of the page. In each block BLK, multiple wiring layers 102 are stacked at intervals in the Z direction. For example, seven wiring layers 102 are stacked. Each wiring layer 102 extends in the X direction. Each wiring layer 102 functions as a select gate line SGS, word lines WL0 to WL4, and a select gate line SGD, respectively. A slit SLT is provided on each of the two side surfaces of each wiring layer 102 facing the Y direction. The slit SLT extends in the X and Z directions. The slit SLT separates the wiring layer 102 into blocks BLK.

[0060] The block BLK includes a cell portion and a WLSG connection portion.

[0061] The cell section is provided with a plurality of memory pillars MP. The memory pillars MP are pillars corresponding to the NAND strings NS. The structure of the memory pillars MP will be described in detail later. The memory pillars MP have a roughly cylindrical shape and extend in the Z direction. The memory pillars MP penetrate (pass through) a plurality of wiring layers 102 stacked in the Z direction.

[0062] In the example of FIG. 5, multiple memory pillars MP in a block BLK are staggered in two rows in the X direction. The arrangement of the memory pillars MP can be designed arbitrarily. For example, the arrangement of the memory pillars MP may be staggered in eight rows. The arrangement of the memory pillars MP does not have to be staggered.

[0063] Above the memory pillars MP, multiple bit lines BLb are arranged side by side in the X direction. The bit lines BLb extend in the Y direction. The memory pillars MP of each block BLK are electrically connected to one of the bit lines BLb.

[0064] The WLSG connection portion of the memory cell array 11_2 includes the CP1 region.

[0065] The CP1 region is a region where multiple contact plugs CP1 are provided. The contact plugs CP1 extend in the Z direction. Each contact plug CP1 is connected to one of the wiring layers 102 stacked at intervals in the Z direction. The contact plug CP1 is not electrically connected to the other wiring layers 102. In the example of FIG. 5, seven contact plugs CP1 are provided in one CP1 region. The seven contact plugs CP1 are respectively connected to the seven wiring layers 102 stacked at intervals in the Z direction. Hereinafter, when limiting the contact plugs CP1 connected to the wiring layers 102 corresponding to the word lines WL0, WL1, WL2, WL3, and WL4, they are referred to as contact plugs CP1_w0, CP1_w1, CP1_w2, CP1_w3, and CP1_w4. When limiting the contact plugs CP1 connected to the wiring layers 102 corresponding to the select gate lines SGD and SGS, they are referred to as contact plugs CP1_d and CP1_s. 5, contact plugs CP1_s, CP1_w0, CP1_w1, CP1_w2, CP1_w3, CP1_w4, and CP1_d are arranged in this order from the end of the memory cell array 11_2 in the X direction toward the cell portion. The arrangement of the contact plugs CP1 in each CP1 region is arbitrary. For example, the contact plugs CP1 may be arranged in two rows along the X direction.

[0066] A wiring layer 111 is provided on the contact plug CP1. The wiring layer 111 extends from the connection position with the contact plug CP1 to the block BLK adjacent in the Y direction. More specifically, the wiring layer 111 provided on the contact plug CP1 in the block BLK0_2 extends to the block BLK1_2. The wiring layer 111 provided on the contact plug CP1 in the block BLK1_2 extends to the block BLK0_2. The wiring layer 111 provided on the contact plug CP1 in the block BLK2_2 extends to the block BLK3_2. The wiring layer 111 provided on the contact plug CP1 in the block BLK3_2 extends to the block BLK2_2.

[0067] An electrode pad PD is provided on the wiring layer 111. One end of the wiring layer 111 is connected to the contact plug CP1, and the other end is electrically connected to the electrode pad PD. The electrode pad PD is used for electrical connection with other chips.

[0068] Next, the planar configuration of the memory cell array 11_1 will be described, focusing on differences from the planar configuration of the memory cell array 11_2.

[0069] As shown in Figure 6, the configuration of the cell section is the same as that of the memory cell array 11_2. Above the memory pillars MP, multiple bit lines BLa are arranged side by side in the X direction. The bit lines BLa extend in the Y direction. The memory pillars MP of each block BLK are electrically connected to one of the bit lines BLa.

[0070] The WLSG connection portion of the memory cell array 11_1 includes a CP1 region and a CP2 region.

[0071] The configuration of the CP1 region is the same as that of the memory cell array 11_2. For example, the CP1 region of the memory cell array 11_1 is disposed above the CP1 region of the memory cell array 11_2 in the Z direction.

[0072] The CP2 region is a region where a plurality of contact plugs CP2 are provided. For example, the contact plugs CP2 of the memory cell array 11_1 are arranged above the electrode pads PD electrically connected to the contact plugs CP1 of the memory cell array 11_2 in the Z direction. The contact plugs CP2 extend in the Z direction. The contact plugs CP2 penetrate the memory cell array 11_1. The contact plugs CP2 are not electrically connected to the wiring layer 102 of the memory cell array 11_1. The contact plugs CP2 are electrically connected to the contact plugs CP1 of the memory cell array 11_2 via the electrode pads PD and the wiring layer 111 of the array chip 10_2 described in FIG. 5.

[0073] More specifically, for example, the contact plug CP2 of the block BLK0_1 is electrically connected to the contact plug CP1 of the block BLK1_2 of the memory cell array 11_2. The contact plug CP2 of the block BLK1_1 is electrically connected to the contact plug CP1 of the block BLK0_2 of the memory cell array 11_2. The contact plug CP2 of the block BLK2_1 is electrically connected to the contact plug CP1 of the block BLK3_2 of the memory cell array 11_2. The contact plug CP2 of the block BLK3_1 is electrically connected to the contact plug CP1 of the block BLK2_2 of the memory cell array 11_2.

[0074] 6, seven contact plugs CP2 are provided in one CP2 region. The seven contact plugs CP2 correspond to the seven contact plugs CP1 of the memory cell array 11_2, respectively. Hereinafter, when limiting the contact plugs CP2 connected to the contact plugs CP1_w0, CP1_w1, CP1_w2, CP1_w3, and CP1_w4 of the memory cell array 11_2, respectively, they are referred to as contact plugs CP2_w0, CP2_w1, CP2_w2, CP2_w3, and CP2_w4. When limiting the contact plugs CP2 connected to the contact plugs CP1_d and CP1_s of the memory cell array 11_2, respectively, they are referred to as contact plugs CP2_d and CP2_s.

[0075] A wiring layer 111 is provided on the contact plugs CP1 and CP2. The contact plugs CP1_w0 to CP1_w4, CP1_d, and CP1_s are connected via the wiring layer 111 to the contact plugs CP2_w0 to CP2_w4, CP2_d, and CP2_s in the adjacent blocks BLK, respectively.

[0076] More specifically, for example, the contact plug CP1 in the block BLK0_1 is electrically connected to the contact plug CP2 in the block BLK1_1. The contact plug CP1 in the block BLK1_1 is electrically connected to the contact plug CP2 in the block BLK0_1. The contact plug CP1 in the block BLK2_1 is electrically connected to the contact plug CP2 in the block BLK3_1. The contact plug CP1 in the block BLK3_1 is electrically connected to the contact plug CP2 in the block BLK2_1.

[0077] That is, the word lines WLa0 to WLa4 and the select gate lines SGDa and SGSa of the block BLK0_1 are electrically connected to the word lines WLa0 to WLa4 and the select gate lines SGDa and SGSa of the block BLK0_2, respectively.

[0078] Similar to the memory cell array 11_2, electrode pads PD are provided on the wiring layer 111 above the memory cell array 11_1.

[0079] 1.6 Cross-sectional structure of memory cell array Next, the cross-sectional configuration of the memory cell array 11 will be described.

[0080] 1.6.1 Configuration of A1-A2 cross section First, an example of the configuration of the A1-A2 cross section of the semiconductor memory device 1 will be described with reference to Fig. 7. Fig. 7 is a cross section taken along the A1-A2 line in Fig. 5 and Fig. 6. The example in Fig. 7 shows memory cell arrays 11_1 and 11_2, but the same is true for memory cell arrays 11_3 and 11_4.

[0081] 7, the semiconductor memory device 1 has a configuration in which array chips 10_1 and 10_2 are bonded to a circuit chip 20. The chips are electrically connected to each other via electrode pads PD provided on each chip.

[0082] First, the internal configuration of the array chip 10_1 will be described.

[0083] The array chip 10_1 includes a memory cell array 11_1 and various wiring layers for connection to other chips.

[0084] The array chip 10_1 includes insulating layers 101, 105, 107, 110, 112, and 114, wiring layers 102, 103, 104, and 111, and conductors 106, 108, 109, 113, and 115.

[0085] In the memory cell array 11_1, a plurality of insulating layers 101 and a plurality of wiring layers 102 are alternately stacked one by one. In the example of FIG. 7, seven wiring layers 102 functioning as the select gate line SGSa, word lines WLa0 to WLa4, and select gate line SGDa are stacked in order in the Z1 direction. Hereinafter, when specifying the wiring layers 102 functioning as the word lines WLa0, WLa1, WLa2, WLa3, and WLa4, respectively, they will be referred to as wiring layers 102_w0, 102_w1, 102_w2, 102_w3, and 102_w4. When specifying the wiring layers 102 functioning as the select gate lines SGDa and SGSa, respectively, they will be referred to as wiring layers 102_d and 102_s.

[0086] The insulating layer 101 may include, for example, silicon oxide (SiO). The wiring layer 102 includes a conductive material. The conductive material may include a metal material, an n-type semiconductor, or a p-type semiconductor. For example, a titanium nitride (TiN) / tungsten (W) stacked structure is used as the conductive material of the wiring layer 102. In this case, the TiN is formed so as to cover the W. The wiring layer 102 may include a high-dielectric-constant material such as aluminum oxide (AlO). In this case, the high-dielectric-constant material is formed so as to cover the conductive material.

[0087] The multiple wiring layers 102 are separated into blocks BLK by slits SLT extending in the X direction. The slits SLT are filled with an insulating layer 105. The insulating layer 105 may contain SiO.

[0088] In the Z2 direction, a wiring layer 103 is provided above the wiring layer 102_s. An insulating layer 101 is provided between the wiring layer 102 and the wiring layer 103. The wiring layer 103 functions as a source line SL. In the Z2 direction, a wiring layer 104 is provided above the wiring layer 103. The wiring layer 104 is used as a wiring layer for electrically connecting the wiring layer 103 to other chips. The wiring layers 103 and 104 include a conductive material. The conductive material may include a metal material, an n-type semiconductor, or a p-type semiconductor.

[0089] In the Z1 direction, a contact plug CP1 is provided on each wiring layer 102. The contact plug CP1 has, for example, a cylindrical shape. The contact plug CP1 includes a conductor 106 and an insulating layer 107. The conductor 106 has, for example, a cylindrical shape. One end of the conductor 106 contacts the wiring layer 102. The insulating layer 107 is provided so as to cover the side surface (outer periphery) of the conductor 106. The insulating layer 107 has, for example, a cylindrical shape. The insulating layer 107 prevents the side surface of the conductor 106 from being electrically connected to other wiring layers 102. The conductor 106 may include a metal material such as W, Cu (copper), or Al (aluminum). The insulating layer 107 may include SiO.

[0090] 7, a contact plug CP1_w4 is provided. The contact plug CP1_w4 penetrates the wiring layer 102_d. The contact plug CP1_w4 is electrically connected to the wiring layer 102_w4.

[0091] A contact plug CP2 is provided that penetrates multiple wiring layers 102. The contact plug CP2 has, for example, a cylindrical shape. The contact plug CP2 includes a conductor 109 and an insulating layer 110. The conductor 109 has, for example, a cylindrical shape. The insulating layer 110 is provided so as to cover the side surface (outer periphery) of the conductor 109. The insulating layer 110 has, for example, a cylindrical shape. The insulating layer 110 prevents the conductor 109 from being electrically connected to the wiring layers 102.

[0092] The CP2 region where the contact plug CP2 is provided does not have the wiring layer 103 or the wiring layer 104. In addition, a conductor 108 is provided above the wiring layer 102_s in the Z2 direction. An insulating layer 101 is provided between the wiring layer 102 and the conductor 108. The conductor 108 contacts (is electrically connected to) one end of the contact plug CP2.

[0093] In the Z1 direction, a wiring layer 111 is provided above the wiring layer 102_d. The wiring layer 111 extends in the Y direction. An insulating layer 101 is provided between the wiring layer 102 and the wiring layer 111. The wiring layer 111 includes a conductive material. The conductive material may include a metal material containing Cu, Al, or the like.

[0094] The other end of the contact plug CP1 and the other end of the contact plug CP2 provided in the block BLK adjacent in the Y direction are (electrically) connected to the wiring layer 111. The contact plugs CP1 and CP2 connected to the wiring layer 111 are arranged side by side along the Y direction. In the example of FIG. 7, the contact plug CP1_w4 in the block BLK0_1 and the contact plug CP2_w4 in the block BLK1_1 are connected to the wiring layer 111 arranged so as to straddle the blocks BLK0_1 and BLK1_1. Furthermore, the contact plug CP1_w4 in the block BLK2_1 and the contact plug CP2_w4 in the block BLK3_1 are connected to the wiring layer 111 arranged so as to straddle the blocks BLK2_1 and BLK3_1.

[0095] In the Z1 direction, an insulating layer 112 is provided on the wiring layer 111 and the insulating layer 101. The insulating layer 112 may contain SiO.

[0096] A plurality of conductors 113 are provided in the insulating layer 112. The conductors 113 function as electrode pads PD. For example, one conductor 113 is provided on one wiring layer 111. The conductor 113 may include a metal material containing Cu.

[0097] In the Z2 direction, an insulating layer 114 is provided on the wiring layer 104, the insulating layer 101, and the conductors 108. The insulating layer 114 may contain SiO.

[0098] A plurality of conductors 115 are provided in the insulating layer 114. The conductors 115 function as electrode pads PD. For example, one conductor 115 is provided on one conductor 108. The conductors 115 may include a metal material containing Cu.

[0099] Next, the internal configuration of the array chip 10_2 will be described, focusing on the differences from the array chip 10_1.

[0100] In the array chip 10_2, the contact plug CP2, the conductor 108, the insulating layer 114, and the conductor 115 described in the configuration of the array chip 10_1 are eliminated. The other configurations are the same as those of the array chip 10_1. The conductor 113 of the array chip 10_2 is connected to the conductor 115 of the array chip 10_1.

[0101] For example, the wiring layer 102 of the memory cell array 11_2 is electrically connected to the wiring layer 102 of the memory cell array 11_1 via the contact plug CP1 of the array chip 10_2, the wiring layer 111 of the array chip 10_2, the conductor 113 of the array chip 10_2, the conductor 115 of the array chip 10_1, the conductor 108 of the array chip 10_1, the contact plug CP2 of the array chip 10_1, the wiring layer 111 of the array chip 10_1, and the contact plug CP1 of the array chip 10_1.

[0102] In the example of FIG. 7, the wiring layer 102_w4 of the block BLK0_2 of the memory cell array 11_2 is electrically connected to the wiring layer 102_w4 of the block BLK0_1 of the memory cell array 11_1. In other words, the word line WLa4 of the memory cell array 11_2 is electrically connected to the word line WLa4 of the memory cell array 11_1 arranged above in the Z1 direction. At this time, the contact plug CP1_w4 of the memory cell array 11_2 is electrically connected to the contact plug CP1_w4 of the memory cell array 11_1 arranged above in the Z1 direction. The same applies to the other word lines WL. Note that a contact plug CP2 and a conductor 108 may be provided in the memory cell array 11_2.

[0103] Next, the circuit chip 20 will be described.

[0104] The circuit chip 20 includes a plurality of transistors Tr and various wiring layers. The plurality of transistors Tr are used in a sequencer 21, a voltage generating circuit 22, a row decoder 23, a sense amplifier 24, and the like.

[0105] More specifically, the circuit chip 20 includes insulating layers 201, 202, and 209, a gate electrode 203, conductors 204, 206, 208, and 210, and wiring layers 205 and 207.

[0106] An isolation region is provided near the surface of the semiconductor substrate 200. The isolation region electrically separates, for example, an n-type well region and a p-type well region provided near the surface of the semiconductor substrate 200. The isolation region is filled with an insulating layer 201. The insulating layer 201 may contain SiO.

[0107] An insulating layer 202 is provided on the semiconductor substrate 200. The insulating layer 202 may include SiO.

[0108] The transistor Tr includes a gate insulating film (not shown) provided on the semiconductor substrate 200, a gate electrode 203 provided on the gate insulating film, and a source and a drain (not shown) formed on the semiconductor substrate 200. The source and the drain are each electrically connected to a wiring layer 205 via a conductor 204. The conductor 204 extends in the Z2 direction. The conductor 204 functions as a contact plug. A conductor 206 is provided on the wiring layer 205. The conductor 206 extends in the Z2 direction. The conductor 206 functions as a contact plug. A wiring layer 207 is provided on the conductor 206. A conductor 208 is provided on the wiring layer 207. The conductor 208 extends in the Z2 direction. The number of wiring layers provided on the circuit chip 20 is arbitrary. The conductor 208 functions as a contact plug. The wiring layers 205 and 207 are made of a conductive material. The conductors 204, 206, and 208 and the wiring layers 205 and 207 may include a metal material, a p-type semiconductor, or an n-type semiconductor.

[0109] In the Z2 direction, an insulating layer 209 is provided on the insulating layer 202. The insulating layer 209 may include SiO.

[0110] A plurality of conductors 210 are provided in the insulating layer 209. The conductors 210 function as electrode pads PD. For example, one conductor 210 is provided on one conductor 208. The conductor 210 may include a metal material such as Cu. The conductors 210 of the circuit chip 20 contact (are electrically connected to) the conductors 113 of the array chip 10_1.

[0111] 1.6.2 Configuration of B1-B2 cross section Next, an example of the configuration of the B1-B2 cross section of the semiconductor memory device 1 will be described with reference to Fig. 8. Fig. 8 is a cross section taken along the line B1-B2 in Fig. 5 and Fig. 6. The following description will focus on the configuration of the contact plug CP1.

[0112] 8, the memory cell arrays 11_1 and 11_2 are provided with contact plugs CP1_s, CP1_w0 to CP1_w4, and CP1_d, respectively. In the example of FIG. 8, the contact plugs CP1_s, CP1_w0 to CP1_w4, and CP1_d are arranged in this order from right to left on the page. One end of the contact plugs CP1_s, CP1_w0 to CP1_w4, and CP1_d contacts (is electrically connected to) the wiring layers 102_s, 102_w0 to 102_w4, and 102_d, respectively. The other end of the contact plugs CP1_s, CP1_w0 to CP1_w4, and CP1_d contacts (is electrically connected to) different wiring layers 111. Therefore, the lengths of the contact plugs CP1_s, CP1_w0 to CP1_w4, and CP1_d in the Z direction are different from one another.

[0113] More specifically, the contact plug CP1_s penetrates the six wiring layers 102_w0 to 102_w4 and 102_d. The contact plug CP1_s is not electrically connected to the six wiring layers 102_w0 to 102_w4 and 102_d. One end of the contact plug CP1_s is electrically connected to the wiring layer 102_s.

[0114] The contact plug CP1_w0 penetrates the five wiring layers 102_w1 to 102_w4 and 102_d. The contact plug CP1_w0 is not electrically connected to the five wiring layers 102_w1 to 102_w4 and 102_d. One end of the contact plug CP1_w0 is electrically connected to the wiring layer 102_w0.

[0115] The contact plug CP1_w1 penetrates the four wiring layers 102_w2 to 102_w4 and 102_d. The contact plug CP1_w1 is not electrically connected to the four wiring layers 102_w2 to 102_w4 and 102_d. One end of the contact plug CP1_w1 is electrically connected to the wiring layer 102_w1.

[0116] The contact plug CP1_w2 penetrates the three wiring layers 102_w3, 102_w4, and 102_d. The contact plug CP1_w2 is not electrically connected to the three wiring layers 102_w3, 102_w4, and 102_d. One end of the contact plug CP1_w2 is electrically connected to the wiring layer 102_w2.

[0117] The contact plug CP1_w3 penetrates the two wiring layers 102_w4 and 102_d. The contact plug CP1_w3 is not electrically connected to the two wiring layers 102_w4 and 102_d. One end of the contact plug CP1_w3 is electrically connected to the wiring layer 102_w3.

[0118] The contact plug CP1_w4 penetrates the wiring layer 102_d. The contact plug CP1_w4 is not electrically connected to the wiring layer 102_d. One end of the contact plug CP1_w4 is electrically connected to the wiring layer 102_w4.

[0119] One end of the contact plug CP1_d is electrically connected to the wiring layer 102_d.

[0120] 1.6.3 Configuration of C1-C2 cross section Next, an example of the configuration of the C1-C2 cross section of the semiconductor memory device 1 will be described with reference to Fig. 9. Fig. 9 is a cross section taken along the C1-C2 line in Fig. 5 and Fig. 6. The following description will focus on the configuration of the contact plug CP2.

[0121] As shown in FIG. 9, the array chip 10_1 is provided with contact plugs CP2_s, CP2_w0 to CP2_w4, and CP2_d. In the example of FIG. 8, the contact plugs CP2_s, CP2_w0 to CP2_w4, and CP2_d are arranged in this order from right to left on the page. The contact plugs CP2_s, CP2_w0 to CP2_w4, and CP2_d have approximately the same shape (the same length). The contact plugs CP2_s, CP2_w0 to CP2_w4, and CP2_d penetrate seven wiring layers 102_s, 102_w0 to 102_w4, and 102_d. The contact plugs CP2_s, CP2_w0 to CP2_w4, and CP2_d are not electrically connected to the seven wiring layers 102_s, 102_w0 to 102_w4, and 102_d. One end of each of the contact plugs CP2_s, CP2_w0 to CP2_w4, and CP2_d is connected to a different conductor 108. The other end of each of the contact plugs CP2_s, CP2_w0 to CP2_w4, and CP2_d is connected to a different wiring layer 111.

[0122] 1.6.4 Configuration of D1-D2 cross section Next, an example of the configuration of the D1-D2 cross section of the semiconductor memory device 1 will be described with reference to Fig. 10. Fig. 10 is a cross section taken along the D1-D2 line in Fig. 5 and Fig. 6. The following description will focus on the configuration of the memory pillars MP and the bit lines BL.

[0123] As shown in FIG. 10, the array chips 10_1 and 10_2 are provided with memory pillars MP.

[0124] The memory pillar MP penetrates multiple wiring layers 102. The memory pillar MP extends in the Z direction. One end of the memory pillar MP contacts the wiring layer 103. In the Z1 direction, a conductor 126 is provided on the other end of the memory pillar MP. For example, the conductor 126 has a substantially cylindrical shape. The conductor 126 functions as a contact plug CP3. A conductor 127 is provided on the conductor 126. For example, the conductor 127 has a substantially cylindrical shape. The conductor 127 functions as a contact plug CP4. In the Z1 direction, multiple wiring layers 128 are provided above the memory pillar MP. The multiple wiring layers 128 are arranged side by side in the X direction. The wiring layers 128 extend in the Y direction. The wiring layers 128 function as bit lines BL. The wiring layers 128 are electrically connected to one of the memory pillars MP via contact plugs CP3 and CP4.

[0125] The conductors 126 and 127 and the wiring layer 128 may include a metallic material such as W, Al, or Cu.

[0126] Next, the internal configuration of the memory pillar MP will be described.

[0127] The memory pillar MP includes a block insulating film 120 , a charge storage layer 121 , a tunnel insulating film 122 , a semiconductor layer 123 , a core layer 124 , and a cap layer 125 .

[0128] More specifically, holes MH are provided that penetrate multiple wiring layers 102. The holes MH correspond to memory pillars MP. The Z2-direction ends of the holes MH reach the wiring layers 103. On the side surfaces of the holes MH, a block insulating film 120, a charge storage layer 121, and a tunnel insulating film 122 are stacked in this order from the outside. For example, if the holes MH are cylindrical, the block insulating film 120, the charge storage layer 121, and the tunnel insulating film 122 each have a cylindrical shape. A semiconductor layer 123 is provided so as to contact the side surfaces of the tunnel insulating film 122. The Z2-direction ends of the semiconductor layer 123 contact the wiring layer 103. The semiconductor layer 123 is a region where the channels of the memory cell transistor MC and the select transistors ST1 and ST2 are formed. Therefore, the semiconductor layer 123 functions as a signal line that connects the current paths of the select transistor ST2, memory cell transistors MC0 to MC4, and select transistor ST1. The interior of the semiconductor layer 123 is filled with a core layer 124. A cap layer 125 is provided on the Z1-direction ends of the semiconductor layer 123 and the core layer 124, with its side surface in contact with the tunnel insulating film 122. That is, the memory pillar MP includes a semiconductor layer 123 that passes through the interiors of the multiple wiring layers 102 and extends in the Z direction.

[0129] The block insulating film 120, the tunnel insulating film 122, and the core layer 124 may include SiO. The charge storage layer 121 may include silicon nitride (SiN). The semiconductor layer 123 and the cap layer 125 may include, for example, polysilicon.

[0130] The memory pillar MP and the wiring layers 102_w0 to 102_w4 are combined to form the memory cell transistors MC0 to MC4, respectively. Similarly, the memory pillar MP and the wiring layer 102_d are combined to form the select transistor ST1. The memory pillar MP and the wiring layer 102_s are combined to form the select transistor ST2.

[0131] 1.7 Planar configuration of BL connection part Next, an example of the configuration of the BL connection portion will be described with reference to Fig. 11. Fig. 11 is a plan view of the BL connection portion of the array chip 10_2. The example of Fig. 11 shows four bit lines BLb0 to BLb3 connected to the memory cell array 11_2 and four bit lines BLa0 to BLa3 connected to the memory cell array 11_2. Note that insulating layers are omitted.

[0132] Hereinafter, when specifying the wiring layers 128 and 132 and the conductors 113, 131, and 133 corresponding to the bit line BLa, they will be referred to as wiring layers 128a and 132a and conductors 113a, 131a, and 133a. When specifying the wiring layers 128 and 132 and the conductors 113, 131, and 133 corresponding to the bit line BLb, they will be referred to as wiring layers 128b and 132b and conductors 113b, 131b, and 133b.

[0133] 11, the wiring layers 128a functioning as bit lines BLa0 to BLa3 are arranged side by side in the X direction. Similarly, the wiring layers 128b functioning as bit lines BLb0 to BLb3 are arranged side by side in the X direction. Each of the wiring layers 128a and 128b extends in the Y direction. In the example of FIG. 11, the bit lines BLa and BLb are arranged to face each other in the Y direction.

[0134] A conductor 131 is connected to an end of each wiring layer 128. The conductor 131 has a substantially cylindrical shape and extends in the Z direction. One end of the conductor 131 is connected to the wiring layer 128, and the other end is connected to the wiring layer 132. The conductor 131 functions as a contact plug CP6 that connects the wiring layer 128 and the wiring layer 132. The wiring layer 132 is provided in a layer different from the wiring layer 128. The shape of the wiring layer 132 varies depending on the wiring layer 128 to which it is electrically connected. The shape of the wiring layer 132 will be described later. A conductor 133 is connected to an end of the wiring layer 132. The conductor 133 has a substantially cylindrical shape and extends in the Z direction. One end of the conductor 133 is connected to the wiring layer 132, and the other end is connected to the conductor 113. The conductor 133 functions as a contact plug CP7 that connects the wiring layer 132 and the conductor 113.

[0135] The conductors 131 and 133 and the wiring layer 132 may include a metal material such as W, Al, or Cu.

[0136] Next, an example of the shape of the wiring layer 132 will be described.

[0137] The wiring layer 128a of the array chip 10_2 is electrically connected to the memory cell array 11_1 of the array chip 10_1. The wiring layer 128b of the array chip 10_2 is electrically connected to the memory cell array 11_3 of the array chip 10_1. Therefore, for example, the conductor 113a electrically connected to the wiring layer 128a is arranged closer to the memory cell array 11_2 than the conductor 113b electrically connected to the wiring layer 128b. In such a case, for example, the wiring layer 132b electrically connected to the wiring layer 128b extends in the Y direction. On the other hand, the wiring layer 132a electrically connected to the wiring layer 128a is shaped to bypass the wiring layer 132b. More specifically, for example, the wiring layer 132a includes three wiring portions 132a1 to 132a3. The wiring portion 132a1 extends in the X direction. One end of the wiring portion 132a1 is connected to the wiring layer 128a via the conductor 131a, and the other end is connected to one end of the wiring portion 132a2. The wiring portion 132a2 extends in the Y direction. The other end of the wiring portion 132a2 is connected to one end of the wiring portion 132a3. The wiring portion 132a3 extends in the X direction. The other end of the wiring portion 132a3 is connected to the conductor 113a via the conductor 133a.

[0138] 11, the wiring layer 132a corresponding to bit line BLa0 is disposed so as to protrude downward from the plane of the drawing and bypass the wiring layer 132b corresponding to bit line BLb0. The wiring layer 132a corresponding to bit line BLa1 is disposed so as to protrude upward from the plane of the drawing and bypass the wiring layer 132b corresponding to bit line BLb1, facing the wiring layer 132a corresponding to bit line BLa0. The wiring layers 132a and 132b corresponding to bit lines BLa2, BLa3, BLb2, and BLb3 also have similar shapes. The wiring layers 132a and 132b corresponding to bit lines BLa2, BLa3, BLb2, and BLb3 are disposed at positions different from the wiring layers 132a and 132b corresponding to bit lines BLa0, BLa1, BLb0, and BLb1 in the Y direction.

[0139] 1.8 Cross-sectional structure of BL connection part Next, an example of the cross-sectional configuration of the BL connection portion will be described with reference to Fig. 12. Fig. 12 is a cross-sectional view taken along line E1-E2 in Fig. 11. The following description focuses on the connection of the bit lines BL between the memory cell arrays 11.

[0140] Hereinafter, when the conductors 115 and 130 corresponding to the bit line BLa are limited, they will be referred to as conductors 115a and 130a. When the conductors 115 and 130 corresponding to the bit line BLb are limited, they will be referred to as conductors 115b and 130b.

[0141] As shown in FIG. 12, in the BL connection portion of the array chip 10_1, one end of the wiring layer 128 is connected to the conductor 115 via a conductor 130 extending in the Z2 direction. For example, the conductor 130 has a substantially cylindrical shape. The conductor 130 functions as a contact plug CP5. In addition, in the cell portion, a conductor 131 is provided on the wiring layer 128 in the Z1 direction. A wiring layer 132 is provided on the conductor 131 in the Z1 direction. The wiring layer 132 is connected to the conductor 113 via a conductor 133.

[0142] The electrical conductors 130 may include a metallic material such as W, Al, or Cu.

[0143] At the BL connection portion of the array chip 10_2, in the Z1 direction, a conductor 131 is provided on the wiring layer 128. A wiring layer 132 is provided on the conductor 131. The wiring layer 132 is connected to the conductor 113 via a conductor 133.

[0144] More specifically, for example, the wiring layer 128b (bit line BLb) corresponding to the memory cell array 11_2 is connected to the wiring layer 128b (bit line BLb) corresponding to the memory cell array 11_3 via the conductor 131b, the wiring layer 132b, the conductor 133b, the conductor 113b, the conductor 115b, and the conductor 130b. The wiring layer 128b (bit line BLb) corresponding to the memory cell array 11_3 is connected to the sense amplifier 24b of the circuit chip 20. Similarly, the wiring layer 128a (bit line BLa) corresponding to the memory cell array 11_4 is connected to the wiring layer 128a (bit line BLa) corresponding to the memory cell array 11_1 via the conductor 131a, the wiring layer 132a, the conductor 133a, the conductor 113a, the conductor 115a, and the conductor 130a. The wiring layer 128a (bit line BLa) corresponding to the memory cell array 11_1 is connected to the sense amplifier 24a of the circuit chip 20.

[0145] 1.9 Cell unit selection for write and read operations Next, an example of selecting a cell unit CU in a write operation and a read operation will be described with reference to Figures 13 and 14. Figure 13 is a conceptual diagram showing the case where a cell unit CU in an array unit AUa is selected. Figure 14 is a conceptual diagram showing the case where a cell unit CU in an array unit AUb is selected. In Figures 13 and 14, thick solid lines indicate a state in which voltages are applied to word lines WL and bit lines BL in a write operation or a read operation. Furthermore, the word lines WL indicated by dashed lines indicate a state in which no voltage is applied (off state).

[0146] First, the case where a cell unit CU in an array unit AUa is selected will be described.

[0147] As shown in FIG. 13, in a write operation or a read operation, one cell unit CU (memory cell transistor MC) of the memory cell array 11_1 and one cell unit CU (memory cell transistor MC) of the memory cell array 11_2, which are commonly connected to one word line WLa, are simultaneously selected. A voltage corresponding to the write operation or the read operation is applied to the memory cell array 11_1 from the sense amplifier 24a via the bit line BLa. On the other hand, a voltage corresponding to the write operation or the read operation is applied to the memory cell array 11_2 from the sense amplifier 24b via the bit line BLb. At this time, since the array unit AUb is not selected, no voltage is applied to the word line WLb.

[0148] Next, the case of selecting a cell unit CU in array unit AUb will be described.

[0149] As shown in FIG. 14, in a write operation or a read operation, one cell unit CU (memory cell transistor MC) of the memory cell array 11_3 and one cell unit CU (memory cell transistor MC) of the memory cell array 11_4, which are commonly connected to one word line WLb, are simultaneously selected. A voltage corresponding to the write operation or the read operation is applied to the memory cell array 11_4 from the sense amplifier 24a via the bit line BLa. On the other hand, a voltage corresponding to the write operation or the read operation is applied to the memory cell array 11_3 from the sense amplifier 24b via the bit line BLb. At this time, since the array unit AUa is not selected, no voltage is applied to the word line WLa.

[0150] 1.10 Data Write Order Next, the data write order will be described with reference to FIG. 15. FIG. 15 is a diagram showing the write order for one block BLK in each memory cell array 11. In the example of FIG. 15, one box in the table corresponds to one cell unit CU. The numbers beginning with "a" in the boxes indicate the case where the row decoder 23a selects the word line WLa and the select gate line SGDa, i.e., the case where the array unit AUa is selected. The numbers beginning with "b" in the boxes indicate the case where the row decoder 23b selects the word line WLb and the select gate line SGDb, i.e., the case where the array unit AUb is selected. Note that, although the example of FIG. 15 shows the case where the word lines WL are selected in order starting from word line WL4, they may also be selected in order starting from word line WL0.

[0151] First, a write operation in which the row decoder 23a selects the word line WLa and the select gate line SGDa will be described.

[0152] As shown in FIG. 15, for example, the row decoder 23a selects the word line WLa4 and the select gate line SGDa0 for the a1-th write operation. This selects the memory cell transistor MC4 of the string unit SU0_1 and the memory cell transistor MC4 of the string unit SU0_2. That is, two cell units CU of the memory cell arrays 11_1 and 11_2 are selected. In this state, the sense amplifier 24a applies a voltage corresponding to the write data to the memory cell array 11_1 via the bit line BLa. At the same time, the sense amplifier 24b applies a voltage corresponding to the write data to the memory cell array 11_2 via the bit line BLb.

[0153] Next, the row decoder 23a selects the word line WLa4 and sequentially selects the select gate lines SGDa1 to SGDa3 for the a2 to a4 write operations. In the memory cell array 11_1, the memory cell transistors MC4 of the string units SU1_1 to SU3_1 are sequentially selected in response to the a2 to a4 write operations. In the memory cell array 11_2, the memory cell transistors MC4 of the string units SU1_2 to SU3_2 are sequentially selected in response to the a2 to a4 write operations.

[0154] Next, the row decoder 23a selects the word line WLa3 and sequentially selects the select gate lines SGDa0 to SGDa3 for the a5 to a8 write operations. In the memory cell array 11_1, the memory cell transistors MC3 of the string units SU0_1 to SU3_1 are sequentially selected for the a5 to a8 write operations. In the memory cell array 11_2, the memory cell transistors MC3 of the string units SU0_2 to SU3_2 are sequentially selected for the a5 to a8 write operations.

[0155] The row decoder 23a selects the word line WLa and the select gate line SGDa in the same order in the a9th to a20th write operations.

[0156] Next, a write operation in which the row decoder 23b selects the word line WLb and the select gate line SGDb will be described.

[0157] For example, the row decoder 23b selects the word line WLb4 and the select gate line SGDb0 for the b1-th write operation. This selects the memory cell transistor MC4 of the string unit SU0_3 and the memory cell transistor MC4 of the string unit SU0_4. That is, two cell units CU are selected from the memory cell arrays 11_3 and 11_4. In this state, the sense amplifier 24b applies a voltage corresponding to the write data to the memory cell array 11_3 via the bit line BLb. At the same time, the sense amplifier 24a applies a voltage corresponding to the write data to the memory cell array 11_4 via the bit line BLa.

[0158] Next, the row decoder 23b selects the word line WLb4 and sequentially selects the select gate lines SGDb1 to SGDb3 for the b2 to b4 write operations. In the memory cell array 11_3, the memory cell transistors MC4 of the string units SU1_3 to SU3_3 are sequentially selected in response to the b2 to b4 write operations. In the memory cell array 11_4, the memory cell transistors MC4 of the string units SU1_4 to SU3_4 are sequentially selected in response to the b2 to b4 write operations.

[0159] In the b5 to b20th write operations, the row decoder 23b selects the word line WLb and the select gate line SGDb in the same order as the row decoder 23a.

[0160] 1.11 Effects of this embodiment The configuration according to this embodiment makes it possible to provide a semiconductor memory device that can suppress an increase in chip area. This effect will be described in detail.

[0161] For example, a method of stacking multiple memory cell arrays (array chips) is known to increase the integration density of semiconductor memory devices. If the word lines WL of each memory cell array are connected to a circuit chip separately, the number of word lines WL connected to the row decoder increases. As a result, the circuit size of the row decoder increases according to the number of memory cell arrays. In other words, the area of ​​the circuit chip increases.

[0162] In contrast, with the configuration according to this embodiment, the word lines WL can be commonly connected to the multiple memory cell arrays 11 stacked above the circuit chip 20. Therefore, even if the number of memory cell arrays 11, i.e., the number of stacked word line WL layers, increases, it is possible to suppress an increase in the number of word lines WL connected to the row decoder 23. This makes it possible to suppress an increase in the area of ​​the circuit chip 20.

[0163] Furthermore, the configuration according to this embodiment includes a structure in which two array units AU, each including two memory cell arrays 11 stacked above a circuit chip 20, are arranged side by side in a direction parallel to the circuit chip 20. A bit line BL is connected in common to one memory cell array 11 in one array unit AU and one memory cell array 11 provided in a different array chip 10 in the other array unit AU. This allows two cell units CU in the two memory cell arrays 11 in the array unit AU to be selected simultaneously in write and read operations. That is, page data from each of the two cell units CU can be processed simultaneously in write and read operations. This improves the processing performance of the semiconductor memory device 1.

[0164] Furthermore, with the configuration according to this embodiment, two cell units CU can be processed collectively, so the size of the block BLK in one memory cell array 11, i.e., the data size of one page, can be halved. This allows the size of the memory cell array 11 to be reduced, and therefore, an increase in the area of ​​the array chip 10 can be suppressed.

[0165] Furthermore, with the configuration according to this embodiment, the bit lines BL can be shared between the array units AU. Therefore, even if the number of stacked memory cell arrays 11 increases, the number of bit lines BL connected to the sense amplifiers can be prevented from increasing. This prevents an increase in the area of ​​the circuit chip.

[0166] Furthermore, with the configuration according to this embodiment, disturbances during write and read operations can be suppressed. This effect will be described in detail.

[0167] For example, in a write operation or a read operation, when one of the memory cell arrays 11 in the array unit AU is selected, a voltage is also applied to the word lines WL of the unselected memory cell arrays 11. Therefore, the unselected memory cell arrays 11 are also affected by the disturbance.

[0168] In contrast, with the configuration according to this embodiment, the two memory cell arrays 11 in the array unit AU can be simultaneously selected or unselected. This makes it possible to suppress the application of voltage to the word lines WL of the unselected memory cell arrays 11 during write and read operations. This makes it possible to suppress the effects of disturbance.

[0169] 2. Second embodiment Next, a second embodiment will be described. In the second embodiment, a layout of the memory cell array 11 that is different from that of the first embodiment will be described. The following description will focus on the differences from the first embodiment.

[0170] 2.1 Memory cell array layout Next, an example of the arrangement of memory cell arrays will be described with reference to Fig. 16. Fig. 16 is a perspective view showing the arrangement of memory cell arrays 11_1 to 11_4 and a circuit chip 20. In the example of Fig. 16, for the sake of simplicity, each memory cell array 11 is shown to have one word line WLa and one WLb, one select gate line SGDa, one SGDb, one SGSa, and one SGSb, and eight bit lines BLa and one BLb. Source lines SL are omitted. Also, for the sake of simplicity, BL connection portions are omitted.

[0171] As shown in FIG. 16, the memory cell array 11 includes two cell units and one WLSG connection unit. More specifically, the WLSG connection unit is provided between two cell units arranged side by side in the X direction. That is, the WLSG connection unit is provided in the center of the memory cell array 11. By providing the WLSG connection unit in the center, even if the size of the block BLK (the data size of one page) increases, the effective wiring length of the word line WL from the WLSG connection unit to the end of the cell unit is reduced, thereby reducing the delay in voltage propagation in the word line WL. For example, if the data size of one page is 8 KB in the configuration of the first embodiment, the data size of one page can be increased to 16 KB in the configuration of this embodiment while maintaining the effective wiring length of the word line WL at the same level (while reducing the delay in voltage propagation in the word line WL to the same level).

[0172] The other configurations are the same as those in Fig. 3. The bit line BLa of the memory cell array 11_4 is connected to the bit line BLa of the memory cell array 11_1. The bit line BLb of the memory cell array 11_2 is connected to the bit line BLb of the memory cell array 11_3.

[0173] 2.2 Planar configuration of memory cell array Next, an example of the configuration of the memory cell array 11 will be described with reference to FIGS. 17 and 18. FIG. 17 is a plan view of the memory cell array 11_2. FIG. 18 is a plan view of the memory cell array 11_1. In the examples of FIGS. 17 and 18, for the sake of simplicity, a case will be described in which each memory cell array 11 includes four blocks BLK0 to BLK3 and each block BLK includes one string unit SU. In addition, in the examples of FIGS. 17 and 18, insulating layers are omitted. The configuration of the memory cell array 11_3 is similar to that of the memory cell array 11_1. The configuration of the memory cell array 11_4 is similar to that of the memory cell array 11_2.

[0174] First, the planar configuration of the memory cell array 11_2 will be described.

[0175] As shown in FIG. 17, four blocks BLK0_2 to BLK3_2 are arranged side by side in the Y direction from the top to the bottom of the paper.

[0176] A cell section is provided at both ends of the memory cell array 11_2 in the X direction. The configuration of the cell section is the same as that of the first embodiment. A plurality of bit lines BLb are arranged in the X direction above the memory pillars MP. The bit lines BLb extend in the Y direction. The memory pillars MP of each block BLK are electrically connected to one of the bit lines BLb.

[0177] A WLSG connection portion is provided in the center of the memory cell array 11_2, in other words, the WLSG connection portion is provided between two cell portions aligned in the X direction.

[0178] The WLSG connection portion of each block BLK includes a CP1 region. The CP1 region of block BLK0_2 and the CP1 region of block BLK1_2 are arranged at different positions in the X direction. The CP1 region of block BLK2_2 and the CP1 region of block BLK3_2 are arranged at different positions in the X direction. In the example of FIG. 17 , as in the first embodiment, seven contact plugs CP1_s, CP1_w0, CP1_w1, CP1_w2, CP1_w3, CP1_w4, and CP1_d are arranged in this order within one CP1 region. A wiring layer 111 is provided on each contact plug CP1. The wiring layer 111 extends in the Y direction from the connection position with the contact plug CP1 to the adjacent block BLK. An electrode pad PD is provided on the wiring layer 111. One end of the wiring layer 111 is connected to the contact plug CP1, and the other end is electrically connected to the electrode pad PD. The arrangement relationship between the contact plugs CP1, the wiring layer 111, and the electrode pads PD in each block BLK is the same as in the first embodiment.

[0179] Next, the planar configuration of the memory cell array 11_1 will be described, focusing on differences from the planar configuration of the memory cell array 11_2.

[0180] As shown in Fig. 18, the configuration of the cell section is the same as that of the memory cell array 11_2. Above the memory pillars MP, multiple bit lines BLa are arranged side by side in the X direction. The bit lines BLa extend in the Y direction. The memory pillars MP of each block BLK are electrically connected to one of the bit lines BLa.

[0181] A WLSG connection portion is provided in the center of the memory cell array 11_1.

[0182] The WLSG connection portion of each block BLK includes a CP1 region and a CP2 region.

[0183] The configuration of the CP1 region is the same as that of the memory cell array 11_2. For example, the CP1 region of the memory cell array 11_1 is disposed above the CP1 region of the memory cell array 11_2 in the Z direction.

[0184] The CP2 region of each block BLK is arranged, for example, alongside the CP1 region in the X direction. Therefore, the CP2 region of block BLK0_1 and the CP2 region of block BLK1_1 are arranged at different positions in the X direction. Also, the CP2 region of block BLK2_1 and the CP2 region of block BLK3_1 are arranged at different positions in the X direction.

[0185] The CP2 region is a region where a plurality of contact plugs CP2 are provided. The contact plugs CP2 are electrically connected to the contact plugs CP1 of the memory cell array 11_2 via the electrode pads PD and the wiring layer 111 of the array chip 10_2 described in FIG.

[0186] 18, seven contact plugs CP2_s, CP2_w0, CP2_w1, CP2_w2, CP2_w3, CP2_w4, and CP2_d are arranged in this order in one CP2 region. The seven contact plugs CP2 correspond to the seven contact plugs CP1 of the memory cell array 11_2, respectively.

[0187] A wiring layer 111 is provided on the contact plugs CP1 and CP2. The contact plugs CP1_w0 to CP1_w4, CP1_d, and CP1_s are connected via the wiring layer 111 to the contact plugs CP2_w0 to CP2_w4, CP2_d, and CP2_s in the adjacent blocks BLK, respectively.

[0188] An electrode pad PD is provided on the wiring layer 111 above the memory cell array 11_1.

[0189] 2.3 Effects of this embodiment The configuration according to this embodiment provides the same effects as those of the first embodiment.

[0190] 3. Modifications, etc. The semiconductor memory device according to the above embodiment includes a first memory cell array (11_1), a second memory cell array (11_2) arranged above the first memory cell array in a first direction (Z direction), a third memory cell array (11_3) arranged adjacent to the first memory cell array in a second direction (X direction) intersecting the first direction, a fourth memory cell array (11_4) arranged above the third memory cell array in the first direction and adjacent to the second memory cell array in the second direction, a first word line (WLa) connected to the first memory cell array and the second memory cell array, a second word line (WLb) connected to the third memory cell array and the fourth memory cell array, a first bit line (BLa) connected to the first memory cell array and the fourth memory cell array, and a second bit line (BLb) connected to the second memory cell array and the third memory cell array.

[0191] By applying the above-described embodiment, it is possible to provide a semiconductor memory device that can suppress an increase in chip area.

[0192] The embodiment is not limited to the above-described embodiment, and various modifications are possible.

[0193] For example, in the above embodiment, the case where the circuit chip 20 and the two array chips 10_1 and 10_2 are bonded together has been described, but these configurations may be formed on one semiconductor substrate.

[0194] Furthermore, the term "connected" in the above embodiments also includes a state in which something else, such as a transistor or a resistor, is interposed between them and indirectly connected.

[0195] The embodiments are merely examples, and the scope of the invention is not limited thereto. [Explanation of symbols]

[0196] 1...Semiconductor memory device 10...Array chip 11...Memory cell array 20...Circuit chip 21...Sequencer 22...Voltage generation circuit 23, 23a, 23b...row decoder 24, 24a, 24b...Sense amplifier 101, 105, 107, 110, 112, 114, 201, 202, 209...insulating layers 102 to 104, 111, 128, 128a, 128b, 132, 132a, 132b, 205, 207...wiring layers 106, 108, 109, 113, 113a, 113b, 115, 115a, 115b, 126, 127, 130, 130a, 130b, 131, 131a, 131b, 133, 133a, 133b, 204, 206, 208, 210...Conductor 120...Block insulating film 121...Charge storage layer 122...Tunnel insulating film 123...Semiconductor layer 124...Core layer 125...Cap layer 132a1~132a3…Wiring part 200...Semiconductor substrate 203...Gate electrode

Claims

1. a first memory cell array; a second memory cell array arranged above the first memory cell array and facing in a first direction; a third memory cell array arranged adjacent to the first memory cell array in a second direction intersecting the first direction; a fourth memory cell array arranged above the third memory cell array in the first direction and adjacent to the second memory cell array in the second direction; a first word line connected to the first memory cell array and the second memory cell array; a second word line connected to the third memory cell array and the fourth memory cell array; a first bit line connected to the first memory cell array and the fourth memory cell array; second bit lines connected to the second memory cell array and the third memory cell array; a first select gate line connected to the first memory cell array and the second memory cell array; a second select gate line connected to the third memory cell array and the fourth memory cell array; Equipped with Semiconductor memory device.

2. The first memory cell array a first semiconductor extending in the first direction and connected to a first memory cell connected to the first word line and a first selection transistor connected to the first selection gate line; The second memory cell array a second semiconductor extending in the first direction and connected to a second memory cell connected to the first word line and a second selection transistor connected to the first selection gate line; The third memory cell array a third semiconductor extending in the first direction and connected to a third memory cell connected to the second word line and a third select transistor connected to the second select gate line; The fourth memory cell array a fourth semiconductor extending in the first direction and connected to a fourth memory cell connected to the second word line and a fourth select transistor connected to the second select gate line; 2. The semiconductor memory device according to claim 1.

3. the first bit line is connected to the first semiconductor and the fourth semiconductor; the second bit line is connected to the second semiconductor and the third semiconductor; 3. The semiconductor memory device according to claim 2.

4. In a write operation or a read operation, both the first memory cell and the second memory cell are selected.

3. The semiconductor memory device according to claim 2.

5. the first memory cell array includes a first region in which the first memory cells are provided, and a second region in which contact plugs are connected to the first word lines; the second region is provided at an end of the first memory cell array; 3. The semiconductor memory device according to claim 2.

6. The first memory cell array a fifth semiconductor extending in the first direction and connected to a fifth memory cell connected to the first word line and a fifth selection transistor connected to the first selection gate line; the first memory cell array includes a first region in which the first memory cells are provided, a second region in which contact plugs are connected to the first word lines, and a third region in which the fifth memory cells are provided; The second region is disposed between the first region and the third region.

3. The semiconductor memory device according to claim 2.

7. a first row decoder connected to the first word line; a second row decoder connected to the second word line; a first sense amplifier connected to the first bit line; a second sense amplifier connected to the second bit line; a circuit chip including the first row decoder, the second row decoder, the first sense amplifier, and the second sense amplifier; a first array chip including the first memory cell array and the third memory cell array; a second array chip including the second memory cell array and the fourth memory cell array; Further provided with the circuit chip, the first array chip, and the second array chip are attached to each other in the first direction; 2. The semiconductor memory device according to claim 1.

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