Semiconductor Devices

Abstract

To achieve lower power consumption in an interface circuit.SOLUTION: A semiconductor device has a processor, and an interface circuit including a register storing setting information. The register includes: a first storage circuit capable of storing setting information in a state where power source voltage is supplied; and a second storage circuit capable of storing the setting information in a state where the supply of power source voltage is blocked. The interface circuit operates while switching among a first state for causing the first storage circuit to store the setting information, a second state for operating based on the setting information stored in the first storage circuit, a third state for causing the second storage circuit to store the setting information stored in the first storage circuit and blocking the supply of the power source voltage, and a fourth state for restarting the supply of the power source voltage and causing the first storage circuit to store the setting information stored in the second storage circuit. The interface circuit switches from the second to fourth states according to a state of a functional device.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] One embodiment of the present invention relates to a semiconductor device, an electronic component, and an electronic device. [Background technology]

[0002] The system of an electronic device such as a smartphone comprises a processor and a display device. , a touch sensor device, a communication device, a memory device, and the like. The device is configured to be connected via an interface corresponding to the device.

[0003] In such a system, various setting information is stored in the setting registers within the interface. This operation is called initialization. The initialization is for display devices, touch sensor devices, communication devices, and memory devices. This is necessary for each interface that corresponds to the above. Settings such as whether or not a device is connected, the type of device, device specs, and device operation method This configuration enhances the scalability and versatility of the system. After initialization, the system is ready for normal operation.

[0004] The display device is a transistor having an oxide semiconductor in the channel formation region (O A configuration using a pixel transistor (S transistor) has been proposed (see, for example, Patent Document 2). S transistors have extremely low leakage current (off-state current) when they are not conducting, making them ideal for displaying still images. When displaying, the frequency of rewriting (refreshing) the video signal based on the image data is reduced, Power consumption can be reduced. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] US Patent Application Publication No. 2008 / 77725 [Patent Document 2] US Patent Application Publication No. 2011 / 149185 Summary of the Invention [Problem to be solved by the invention]

[0006] When using a display device with the configuration of Patent Document 2, the refresh of the video signal is stopped. During the period when the display is stopped or when the next image data is not sent to the display device, Display drivers, display interfaces, etc. can be disabled. By cutting off the supply of power supply voltage, it becomes possible to reduce power consumption.

[0007] In a configuration in which the supply of power supply voltage to the display interface is cut off, When switching from display to video display, i.e. the refresh rate of the display device When you switch back, the display interface will switch off the display device. Before replacing it, it is necessary to supply power voltage and restart operation.

[0008] However, the display interface configuration registers are volatile registers. The setting information is erased when the power supply voltage is cut off. As shown in the configuration in Appendix 1, you will need to start over from the initial setting. Stopping and restarting an interface has a time and power penalty Therefore, it was not possible to frequently shut off the power to the display interface. This means that even when driving a display device at a low refresh rate, The power supply voltage must be continuously supplied to the spray interface, making it difficult to reduce power consumption. It was difficult.

[0009] One aspect of the present invention is to provide a method for detecting the status of a target device connected via an interface. Accordingly, when the supply of power voltage to the interface is interrupted and then resumed, One of the objects of the present invention is to provide a semiconductor device that can reduce power consumption by eliminating re-initialization. do.

[0010] One aspect of the present invention is to provide a display device connected via a display interface. Depending on the frequency of rewriting the video signal to the display device, the display interface When the power supply voltage is cut off and then restarted, the re-initialization is eliminated, and the An object of the present invention is to provide a semiconductor device that can reduce power consumption. [Means for solving the problem]

[0011] One aspect of the present invention is an interface having a processor and a register for storing configuration information. and a semiconductor device having an interface circuit, the interface circuit being functionally linked to a processor. The register has the function of transmitting signals to and from the device. a first memory circuit capable of storing setting information in a state in which the supply of power supply voltage is cut off; a second memory circuit capable of storing setting information, and the interface circuit a first state for storing setting information in the circuit; and a second state for storing setting information in the first storage circuit. a second state in which the setting information stored in the first storage circuit is stored in a second storage circuit; The third state is when the supply of power supply voltage is cut off and the second state is when the supply of power supply voltage is resumed. A fourth state in which the setting information stored in the circuit is stored in the first memory circuit. The interface circuit has a function of switching from a first state to a second state depending on the state of the functional device. The fourth is a semiconductor device having a function of switching between states.

[0012] One aspect of the present invention is an interface having a processor and a register for storing configuration information. A semiconductor device having a base circuit and a frame memory, and the interface circuit is , which has the function of transmitting signals input and output between the processor and the display panel, and the register a first memory circuit capable of storing setting information in a state where a power supply voltage is supplied; a second memory circuit capable of storing setting information in a cut-off state, The circuit includes a first state for storing setting information in the first storage circuit, and a second state for storing setting information in the first storage circuit. a second state in which an operation is performed based on the setting information; and a second state in which the setting information stored in the first memory circuit is stored in the second memory circuit. The third state in which the supply of the power supply voltage is interrupted and the second state in which the supply of the power supply voltage is resumed are stored in the memory circuit. a fourth state in which the setting information stored in the second storage circuit is stored in the first storage circuit; The display panel has a function to change the video signal written in the pixel. The display state can be switched between a still image display state in which the video signal written to the pixels is not rewritten and a still image display state in which the video signal written to the pixels is not rewritten. The interface circuit has a function of operating in accordance with the second signal when the display panel is in a moving image display state. When the display panel switches from video display to still image display, it switches to the third state. When the display panel switches from a still image display state to a video display state, it goes through the fourth state and then to the third state. A semiconductor device having the ability to switch between states 1 and 2 is preferred.

[0013] In one embodiment of the present invention, the second memory circuit includes a first transistor and a second transistor. The first transistor has an oxide semiconductor layer in a semiconductor layer that becomes a channel formation region. the source or drain of the first transistor is connected to the second transistor The first transistor is electrically connected to the gate of the first transistor, and the first transistor is electrically connected to the gate of the first transistor. By doing so, the charge of the gate of the second transistor can be maintained. Body devices are preferred.

[0014] In one embodiment of the present invention, the frame memory includes a third transistor. The third transistor has an oxide semiconductor in a semiconductor layer that serves as a channel formation region. The third transistor is made non-conductive, and the source or A semiconductor device having a function of being able to hold charge on one side of the drain is preferred.

[0015] Other aspects of the present invention will be described in the following embodiments and and as described in the drawings. [Effects of the Invention]

[0016] One aspect of the present invention is to provide a method for detecting the status of a target device connected via an interface. Accordingly, when the supply of power voltage to the interface is interrupted and then resumed, It is possible to provide a semiconductor device that can reduce power consumption by eliminating reinitialization.

[0017] One aspect of the present invention is to provide a display device connected via a display interface. Depending on the frequency of rewriting the video signal to the display device, the display interface When the power supply voltage is cut off and then restarted, the re-initialization is eliminated, and the A semiconductor device capable of reducing power consumption can be provided. [Brief explanation of the drawings]

[0018] [Figure 1] 1A and 1B are a block diagram and a flowchart illustrating a configuration example of a semiconductor device. [Figure 2] 1A and 1B are a block diagram and a flowchart illustrating a configuration example of a semiconductor device. [Figure 3] FIG. 1 is a block diagram illustrating a configuration example of a semiconductor device. [Figure 4] FIG. 1 is a block diagram illustrating a configuration example of a semiconductor device. [Figure 5] FIG. 2 is a state transition diagram illustrating an example of a state of a semiconductor device. [Figure 6] FIG. 1 is a block diagram illustrating a configuration example of a semiconductor device. [Figure 7] FIG. 1 is a block diagram illustrating a configuration example of a semiconductor device. [Figure 8] FIG. 1 is a block diagram illustrating a configuration example of a semiconductor device. [Figure 9] FIG. 1 is a circuit diagram illustrating a configuration example of a semiconductor device. [Figure 10] 1A and 1B are a block diagram and a circuit diagram illustrating a configuration example of a semiconductor device. [Figure 11] 1A and 1B are a flowchart illustrating an example of a method for manufacturing an electronic component, a top view of a semiconductor substrate before a dicing process and an enlarged view thereof, an enlarged view of a chip, and a schematic perspective view illustrating an example of the configuration of an electronic component. [Figure 12] 1A to 1C illustrate electronic devices. DETAILED DESCRIPTION OF THE INVENTION

[0019] Hereinafter, embodiments will be described with reference to the drawings. It is understood that the present invention may be practiced in various different ways without departing from its spirit and scope. It will be readily apparent to those skilled in the art that various changes in form and details may be made. The invention should not be construed as being limited to the following description of the embodiments.

[0020] <Configuration of semiconductor device> The semiconductor device will be described with reference to FIGS.

[0021] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. For example, a semiconductor device has a processor and an interface. This is a device that is connected to a target functional device via an interface. Specific examples of devices include display devices, touch sensor devices, communication devices, media There are application processors with interfaces for memory devices. do.

[0022] FIG. 1A is a block diagram illustrating a semiconductor device according to one embodiment of the present invention.

[0023] The semiconductor device 10 includes an MPU 20 (Micro Processing Unit; simply a processor), an interface 30 (hereinafter referred to as I / F 30), and a system The I / F 30 has a bus 50. The I / F 30 has a register 32 (abbreviated as Reg. in the drawing). The register 32 includes a memory circuit 34 and a memory circuit 36 ​​.

[0024] In FIG. 1A, in addition to the semiconductor device 10, a functional device 40 is also shown. The interface 40 exchanges signals with a circuit in the semiconductor device 10, for example, with the MPU 20, via the interface 30. Sends and receives data.

[0025] The functional device 40 may be a display device, a touch sensor device, a sensor, or the like. Examples include devices, communication devices, and memory devices.

[0026] The MPU 20 may, for example, store the address of an external function device or an internal memory device. It reads the required data by specifying it, and outputs the data obtained by calculation. Signals are exchanged between other circuits within the semiconductor device 10 via a system bus 50 .

[0027] The I / F 30 is a circuit that allows the functional device 40 to receive signals output from the semiconductor device 10. or a function of receiving a signal output from the functional device 40 and converting it into a semiconductor signal. In other words, the I / F 30 has a function of connecting the MPU 20 and the functional device 10. It has the function of relaying signals input and output between the device 40 and the computer.

[0028] As an example of the I / F 30, when the functional device 40 is a display, MI(registered trademark), eDP, iDP, V-by-One HS, FPD-Link II Circuits that convert signals into those conforming to interface standards such as PPmL and Advanced In addition, when the functional device 40 is a DRAM (Dynamic RAM), , a circuit that converts signals into signals conforming to interface standards such as DDR, DDR2, and DDR3 Or, a general-purpose interface that can be used for various functional devices. Signals conforming to standards such as PCI, PCI Express, I2C, and RS-232C A circuit that converts this into a signal is included.

[0029] The register 32 of the I / F 30 stores setting information of the I / F 30. For example, the presence or absence of the target functional device, the type of the functional device, the speed of the functional device, etc. This information includes information on pecks, driving methods for functional devices, etc.

[0030] The memory circuit 34 and the memory circuit 36 ​​included in the register 32 can store setting information. The memory circuit 34 stores the setting information while the power supply voltage to the register 32 is supplied. The memory circuit 36 ​​is a memory circuit capable of storing data when the supply of power to the register 32 is cut off. It is a memory circuit that can store setting information in a certain state.

[0031] The I / F 30 having the register 32 operates by switching between first to fourth states. The state is a state in which the setting information is stored in the memory circuit 34, that is, a state in which the initialization operation is being performed. In the second state, the operation is performed based on the setting information stored in the memory circuit 34. The third state corresponds to the normal operation state. The setting information stored in the memory circuit 36 ​​is stored and the supply of the power supply voltage is cut off, that is, The fourth state corresponds to a state in which the power supply is shut off. This corresponds to the state in which the supply of power supply voltage is resumed in order to read out information to the memory circuit 34. In the specification, the state refers to the state of operation that the circuit continues to perform, as well as the state of operation that the circuit performs at a certain point in time. The first to fourth states can be rephrased as the first to fourth actions. It is also possible.

[0032] Storing the setting information stored in the memory circuit 34 in the memory circuit 36 ​​is also called storing. The setting information stored in the memory circuit 36 ​​is read out to the memory circuit 34, and this is called loading. Also called.

[0033] The first state in which the setting information is stored in the memory circuit 34 corresponds to a state in which the initialization operation is being performed. The second state in which the operation is performed based on the setting information stored in the memory circuit 34 is the normal operation. The setting information stored in the memory circuit 34 is stored in the memory circuit 36. The third state in which the supply of power supply voltage is cut off corresponds to a power-off state. By cutting off the power, it is possible to reduce the power consumption of the semiconductor device 10.

[0034] By storing the setting information from the memory circuit 34 to the memory circuit 36, the power is cut off. This also prevents the setting information from being lost from the register 32. A fourth state in which the supply of the setting information stored in the memory circuit 36 ​​is resumed and the setting information is read out to the memory circuit 34. By doing so, it is possible to omit the initialization operation when returning to normal operation. Since there is no need to perform the operation again, the power consumption associated with the initialization operation is reduced, resulting in low power consumption. It is possible to achieve this.

[0035] The second to fourth states of the register 32 described above correspond to the state of the functional device 40. For example, when a signal is transmitted between the semiconductor device 10 and the functional device 40, When input and output are subsequently performed, the semiconductor device is in the second state, i.e., normal operation. When no signal is input / output between the functional device 40 and the memory circuit 3 The semiconductor device 10 and the functional device 4 are again stored in the memory circuit 36, and the third state is established. When signals are continuously input / output between 0 and 1, the supply of power voltage is resumed and the setting information is written. The fourth state is read from the memory circuit 36 ​​to the memory circuit 34, and the second state, i.e., normal operation, is entered. This work is titled "Works."

[0036] The state in which signals are continuously input and output between the semiconductor device 10 and the functional device 40 is, for example, When the functional device 40 is a display device, this corresponds to a moving image display state. If so, the image data is subsequently output via the display interface. In a state where no signals are input or output between the semiconductor device 10 and the functional device 40, When the functional device 40 is a display device, this corresponds to the still image display state. When performing this operation, the pixel circuit of the display device must be able to store a video signal based on image data for a long period of time. By configuring the device to support the display, image data can be displayed via the display interface. It can continue to display even if it is not output to a playback device. The display will continue to operate even if the display interface is stopped and the power is turned off. The ray device can continue to display.

[0037] In this specification, image data is generated by an application processor and displayed on a display. The digital signal corresponding to the image displayed on the display device is also called a video signal. This refers to an analog signal that can be held in a gradation display.

[0038] When displaying a still image, the pixel circuit of the display device generates a video signal based on the image data. As an example of a configuration for holding a signal for a long time, a transistor in a pixel circuit may be configured to hold a signal for a long time when the transistor is in a non-conducting state. It is preferable to use a transistor with extremely low leakage current (off-state current). The transistor is preferably an OS transistor.

[0039] The memory circuit 36 ​​can continue to store the setting information even when the power is cut off. Such a memory circuit preferably includes an OS transistor. The OS transistor has a channel forming region made of silicon, for example, as the source or drain. The gate of the OS transistor is connected to the gate of the Si transistor. By turning on the gate of the Si transistor, the charge can be maintained. Even when the power is cut off, the charge according to the setting information can be continuously held.

[0040] FIG. 1B is a flow chart for explaining the first to fourth state changes in the register 32. First, in step S11, initialization is performed. Then, in step S12, Next, in step S13, the normal operation state of step S12 is continued. If the operation is to be continued, the process returns to step S12. If the operation is not to be continued, the process returns to step S13. Then, in step S14, the power is turned off. Then, in step S15, It is determined whether or not the power-off state of step S14 should be continued, and if it is to be continued, Return to step S14, and if not, proceed to step S16. In step S16, it is determined whether or not the supply of the power supply voltage is to be resumed. If it is to be resumed, the process proceeds to step S12. It transitions to normal operation, and if it does not resume, it ends the operation.

[0041] As a comparative example, FIG. 2A shows a semiconductor device 10 in FIG. 1A that does not have the memory circuit 36. The block diagram configuration of D is shown below.

[0042] In the configuration of FIG. 2(A), a memory circuit 3 is provided that can store setting information even when the power is cut off. 6, if the power supply to the I / F 30 is cut off, the settings stored in the memory circuit 34 Therefore, in the semiconductor device 10D, the power supply voltage is stored in the register 32. When the supply of power is resumed, the supply of power supply voltage is stopped as shown in the flowchart of Figure 2(B). In step S16, it is determined whether or not to resume the process. If the process is to resume, step S1 is performed again. Therefore, every time the supply of power voltage is cut off and restarted, This will cause initialization, and frequent power cuts to the I / F30 will actually increase power consumption. It will lead to an increase.

[0043] On the other hand, in the configuration of FIG. 1A according to one embodiment of the present invention, the setting information is stored in the memory circuit 34. In order to store the setting information in the circuit 36, the setting information is erased from the register 32 while the power is cut off. When the supply of the power supply voltage is resumed, the data is transferred from the memory circuit 36 ​​to the memory circuit 3. 4, the setting information is read out, so initialization can be omitted when returning to normal operation. Since there is no need to perform initialization again, the power consumption associated with initialization is reduced, leading to lower power consumption. This can be achieved.

[0044] In FIG. 1A, the semiconductor device 10 is configured as an MPU 20, an I / F 30, and a system Although a system bus 50 is illustrated, one embodiment of the present invention is not limited to this configuration. As shown in the figure, in addition to the configuration shown in FIG. 1(A), a power controller 21 (in the figure, Power Ctrl.) and static RAM 22 (hereinafter, SRAM 22).

[0045] The power controller 21 controls the power supply to the I / F 30 depending on the state of the functional device 40, for example. The power supply voltage is supplied to the register 101. The SRAM 22 can reduce standby power consumption in the MPU 20. It can be used as program memory or work memory.

[0046] In FIG. 3A, the semiconductor device 10A includes an MPU 20, an I / F 30, a power converter 31, and a Although the controller 21, SRAM 22, and system bus 50 are shown, one aspect of the present invention is For example, a semiconductor device 10B having multiple functions as shown in FIG. It has I / F30A and I / F30B corresponding to devices 40A and 40B, and further has GPU2 3 (Graphic Processing Unit) and FPGA24 (Field The MOS transistor may have a MOS transistor with a programmable gate array (Gate Array).

[0047] The plurality of functional devices 40A and 40B are not limited to a specific configuration, but may be, for example, a display. In this case, the plurality of functional devices 40A , 40B are interrelated. For example, whether or not a touch is detected on the touch sensor device. The display of the display device can be switched and operated according to the following. , when a touch is detected, power is supplied to the interface connected to the touch sensor device. If the voltage is supplied and no touch is detected, the display device will display a still image. The supply of power to the interface connected to the display device is cut off. Therefore, the power consumption of the entire system including the semiconductor device can be reduced. This can be achieved.

[0048] The GPU 23 and FPGA 24 may, for example, be used to configure the semiconductor device 10B as an application program. This configuration is effective when used as an MP It is now possible to share part of the processing of U20 with GPU23 and FPGA24, It is possible to improve the performance of the device 10B. It is also possible to configure the FPGA 24 to be mounted on the interface. It is also possible to adopt a configuration in which the head is mounted on the face. The semiconductor device has various circuits depending on the functional device, and interfaces with multiple functional devices. It is possible to connect via an interface.

[0049] <Example of application to application processor> When the semiconductor device 10 described in FIG. 1A is applied to an application processor, An example will be described with reference to FIGS.

[0050] FIG. 4 is a block diagram illustrating an application processor according to an embodiment of the present invention. Figure.

[0051] The application processor 10C includes an MPU 20, a power controller 21, and an SRA. M22, Display Interface 30C (hereinafter referred to as Display I / F30C), A memory interface 30D (hereinafter referred to as memory I / F 30D), a switch 38, and a system The display I / F 30C has a frame memory 25 and a register. The register 32 includes a storage circuit 34 and a storage circuit 36.

[0052] In FIG. 4, in addition to the application processor 10C, a display device 41 and The display device 41 includes a display controller The display unit 43 has pixels 44. The controller 42 exchanges image data with the frame memory 25 of the display I / F 30C. The DRAM 45 transmits and receives image data to and from the memory I / F 30D. cormorant.

[0053] In FIG. 4, the functional devices are a display device 41, a DRAM 45, an interface The following explains the interface using the display I / F 30C and the memory I / F 30D. However, the application processor 10C has other interfaces and functions. Such other functional devices may be configured to be connected to a touch panel. Examples include sensor devices, sensor devices, and communication devices.

[0054] The MPU 20 calculates the input data and stores the resulting data in the frame memory 25. For example, the MPU 20 performs calculations on image data input from the DRAM 45. The MPU 20 converts the image data into a predetermined format and stores it in the frame memory 25. Depending on the display status of the play device 41 and the status of the display I / F 30C, Power controller 21, SRAM 22, display I / F 30C and memory I / F Generates signals to control the 30D, etc. MPU20 and application processor 1 Signals are exchanged between other circuits within the OC via a system bus 50.

[0055] The display I / F 30C receives signals output from the application processor 10C. a function to convert the image data into a signal that can be input to the display controller 42, or The signal output from the display controller 42 is sent to the application processor 10C. In other words, the display I / F 30C has the function of converting the signal into a signal that can be input. has a function of transmitting signals input and output between the MPU 20 and the display device 41. The switch 38 is provided between the wiring that supplies the power supply voltage to the display I / F 30C. By making it non-conductive, the supply of power supply voltage can be cut off.

[0056] Examples of the display I / F 30C include DVI, HDMI (registered trademark), and digital There are RGB, analog RGB, etc.

[0057] The memory I / F 30D has a function of converting signals into signals conforming to the interface standard. An example of a memory I / F30D is an interface such as DDR, DDR2, or DDR3. A circuit that converts signals into signals conforming to the standard is also included. However, the memory I / F 30D has register 32, just like the display I / F 30C. The register 32 of the memory I / F 30D may include memory circuits 34 and 36. Alternatively, only the memory circuit 34 may be used.

[0058] The register 32 of the display I / F 30C stores the setting of the display I / F 30C. The setting information includes, for example, whether or not a target display device is present, Display device types, display device specifications, display devices This information includes information on the driving method, etc.

[0059] The memory circuit 34 and the memory circuit 36 ​​included in the register 32 can store setting information. The memory circuit 34 stores the setting information while the power supply voltage to the register 32 is supplied. The memory circuit 36 ​​is a memory circuit capable of storing data when the supply of power to the register 32 is cut off. It is a memory circuit that can store setting information in a certain state.

[0060] The display controller 42 controls the image input via the display I / F 30C. Based on the data, a video signal for performing gradation display on the display unit 43 and a drive signal for the display unit 43 are generated. The display unit 43 generates various signals such as a clock signal and a start pulse for displaying the The plurality of pixels 44 are transistors for performing gradation display in response to a video signal. The display device has a display element and a transistor.

[0061] The display I / F 30C having the register 32 is, as explained in FIG. It can take four states. That is, the first state is the initialization state, and the second state is the normal operation state. The second state is a state in which the power is shut off, and the third state is a state in which the power supply voltage is restarted. The fourth state can be taken. This operation can be performed under the control of the MPU 20. Cut.

[0062] The register 32 can be in one of the second to fourth states, so that the register This prevents the loss of configuration information from the BIOS. Since there is no need to perform the initialization operation again, the initial This reduces the power consumption associated with the synchronization operation, thereby achieving low power consumption.

[0063] The second to fourth states of the register 32 are the states of the display device 41. It is preferable that the display device 41 is switched in accordance with the display unit 43. Here, the display device 41 can display moving images or still images. An example of a possible state will be described with reference to FIG. 5(A).

[0064] The display on the display unit 43 switches between two modes as shown in FIG. In Fig. 5(A), there are two modes: a video display mode (Video mode in the figure), and a still image display mode ( In the figure, the image mode is shown. Switch from mode to still mode, or continue in still mode, or Whether to switch from still image display mode to video display mode depends on the image quality of the previous and next frame periods. For example, in video display mode, the image data can be compared to the previous and next frames. If the image data is the same during the frame period, switch from video display mode to still image display mode. Or, if the image data is different between the previous and next frame periods during the video display mode, the video display mode Or, in still image display mode, if the image data is the same between the previous and next frame periods, If so, the still image display mode continues. Or, during the still image display mode, the previous or next frame period is If the image data differs between them, the still image display mode is switched to the moving image display mode.

[0065] The transistors of the pixels 44 of the display unit 43 are OS transistors with extremely low off-state current. By using this configuration, the transistor is kept in a non-conducting state. , the pixel 44 keeps the video signal based on the image data in the still image display mode for a long time. Therefore, in the still image display mode, The image data can be displayed continuously without being output to the display controller 42. Therefore, during this time, the display I / F30C function is stopped and the power supply voltage is cut off. It can continue to be displayed even if the

[0066] Also, possible states of the display I / F 30C will be described with reference to FIG. 5(B). The first to fourth states C1 to C4 shown in FIG. 5B correspond to the first to fourth states described in FIG. In other words, the first state C1 is the initialization state (in the figure, "Set Up"), and the second state C2 is the initialization state (in the figure, "Set Up"). State C2 is the normal operation state (in the figure, Normal Op.), and the third state C3 is The setting information stored in the memory circuit 34 is stored in the memory circuit 36 ​​and the power is cut off (see FIG. In the fourth state C4, the setting information stored in the memory circuit 36 ​​is This is the state where the supply of power supply voltage is resumed to read out the data from the circuit 34 (in the figure, "Power ON"). .

[0067] For example, if the display device 41 continues to display a moving image, The play I / F 30C continues to operate in the second state, i.e., normal operation. When the play device 41 switches from a moving image display mode to a still image display mode, The RAID I / F 30C stores the setting information and sets it to the third state. If the ray device 41 continues the still image display mode, the display I / F 30C In addition, the display device 41 remains in the state of being powered off. When switching from picture display mode to video display mode, the display I / F30C The fourth state is reached when the voltage supply is resumed, and the setting information is read (loaded) and the second state is reached. do.

[0068] Next, in Figs. 6(A), (B), 7(A), and (B), the above-mentioned display I / F3 The application processor 10C and the device 10D correspond to the first to fourth states C1 to C4 of the application processor 10C. The signal flow in the display device 41 will be described below. In (A) and (B), the dashed arrows indicate the schematic flow of signals input and output between each block. This is expressed as follows.

[0069] FIG. 6A shows the state of the application corresponding to the first state C1 of the display I / F 30C described above. Explaining the signal flow in the application processor 10C and the display device 41. As shown in FIG. 6(A), in the first state C1, the SRAM 22 stored setting information D CONF is stored in register 32 via system bus 50. At this time, the power controller 34 stores the voltage in the switch 38 so that the switch 38 is in a conductive state. The above operation is controlled by the DMA (Direct Memory Access) By using a mechanism such as SRAM22, the display Setting information D for Ray I / F30C CONF The configuration to send the program, MPU20 sequentially Setting information D from SRAM22 CONF Read and write to display I / F30C The former configuration is shown in FIG. 6(A).

[0070] FIG. 6B shows the state of the application corresponding to the second state C2 of the display I / F 30C described above. Explaining the signal flow in the application processor 10C and the display device 41. As shown in FIG. 6B, in the second state C2, normal operation is performed, and the DRA The image data input from M45 is converted into a specified format by calculation in MPU20. The image data obtained by the conversion is temporarily stored in the frame memory 25 in the display I / F 30C. The display I / F 30C receives the image data D stored in the frame memory 25. SI G to the display controller 42. The display controller 42 outputs the image Data D SIG Based on the video signal V VIDEO is generated and written to the pixel 44 of the display unit 43. The display I / F 30C continuously receives image data D SIG To continue outputting Therefore, the switch 38 is in a conducting state.

[0071] FIG. 7A shows the application corresponding to the third state C3 of the display I / F 30C described above. Explaining the signal flow in the application processor 10C and the display device 41. As shown in FIG. 7A, in the third state C3, the pixel 44 receives the video signal V VID EO In this state, the display is held via the display I / F 30C. Image data D to the play controller 42 SIG Therefore, the supply of The power controller 21 turns the switch 38 off, and the display I / F 30 The supply of power supply voltage to C can be cut off. CONF teeth , because the power supply voltage is cut off, the data is stored in the memory circuit 36 ​​from the memory circuit 34. By adopting this configuration, the setting information is retained in the register 32 even if the supply of power supply voltage is cut off. Report D CONF can be stored.

[0072] FIG. 7B shows the application corresponding to the fourth state C4 of the display I / F 30C described above. Explaining the signal flow in the application processor 10C and the display device 41. As shown in FIG. 7B, in the fourth state C4, the pixel 44 receives the video signal V VID EO From this state, the pixel 44 receives the video signal V VIDEO Update Therefore, image data is transmitted to the display controller 42 via the display I / F 30C. D SIG Therefore, the power controller 21 turns on the switch 3 8 is turned on, and the supply of power supply voltage to the display I / F 30C is resumed. Setting information D in data 32 CONF is loaded from the storage circuit 36 ​​to the storage circuit 34. By configuring the EEPROM in this way, the EEPROM can be initialized in the second state C2 without passing through the first state C1 where the initialization operation is performed. Some normal operation can be resumed.

[0073] As shown in Figure 7(A), the supply of power supply voltage to the display I / F 30C is cut off. During this period, the frame memory 25 retains data for a certain period of time even if the supply of power voltage is interrupted. A memory cell capable of storing data is preferable. For example, a memory cell having an OS transistor is preferable. It is preferable that one of the source and drain of the OS transistor is a Si transistor. By connecting the OS transistor to the gate of the Si transistor and making the OS transistor non-conductive, Therefore, even if the power supply voltage is cut off, the setting information can be It is possible to continue to hold a charge according to the information.

[0074] <Memory cells applicable to registers> 8A, 8B, and 8C show examples of the configuration applicable to the register 32 described above. I will explain.

[0075] The register 32 is capable of storing data corresponding to setting information when the power supply voltage is supplied. a memory circuit and a device capable of storing data corresponding to setting information when the supply of power supply voltage is cut off; A register having such a memory circuit is shown in FIG. , a flip-flop with a backup function can be applied.

[0076] The flip-flop 33 with backup function shown in FIG. The power supply 30 includes a power supply 35 and a backup circuit 37 (shown as B / U in the figure).

[0077] The flip-flop 35 stores data inputted according to the logic of the clock signal clk. Or it has a function to output.

[0078] The backup circuit 37 outputs the backup data write signal store and the backup The backup data read signal load is input to the backup circuit 37. In response to the data write signal store, the voltage of node N in the flip-flop 35 and The voltage of node NB is applied to store the inverted logic of node N. The voltages of the nodes N and NB stored in the circuit 37 are used for backup data readout. In response to the signal load, the signals are applied to the nodes N and NB of the flip-flop 35. do.

[0079] In the flip-flop 33 with backup function, the backup circuit 37 is A plurality of flip-flops 35 may be provided. This configuration is shown in FIG. Any one of the backup circuits 37_1 to 37_k (k is a natural number) is a backup circuit. The flash memory 100 stores the flash data in response to one of the flash data write signals store_1 to store_k. The voltage of node N in flip-flop 35 and the node that stores the inverted logic of node N are The voltage of the node NB is applied. The voltages of the nodes N and NB are connected to the backup data read signal loa Depending on one of d_1 to load_k, the node N and By adopting this configuration, the register 32 can store multiple pieces of setting information. It is possible.

[0080] FIG. 9 shows an example of the configuration of the flip-flop 33 with backup function.

[0081] The flip-flop 33 with backup function is a flip-flop 35 and a backup The flip-flop 35 includes a switch 63, a switch 64, an inverter a motor circuit 65, an inverter circuit 66, an inverter circuit 67, an inverter circuit 68, a switch switch 77, switch 78, inverter circuit 79, inverter circuit 85, inverter circuit 86 and an inverter circuit 87. The backup circuit 37 includes a transistor 69, a transistor a transistor 70, a transistor 71, a capacitance element 72, a transistor 73, and a transistor 74 , a transistor 75, and a capacitor 76.

[0082] The switches 63, 64, 77 and 78 are connected to the clock signal c The conduction state of each switch is controlled by the clock signal clk. At low level, it is in a conducting state, and at high level, it is in a non-conducting state.

[0083] The flip-flop 35 is turned on when the clock signal clk goes low and then the clock signal When the signal clk goes high, the data D is captured. By keeping the switch 64 in a conductive state, the captured data D is continuously stored as an output signal Q. can.

[0084] Transistor 69 supplies a backup data write signal store to its gate. The wiring is connected to the gate of the transistor 73. The transistor 69 has a source or drain. One of the inputs is connected to node N in flip-flop 35. The other of the source and drain is connected to the gate of the transistor 71 and one electrode of the capacitor 72. Connected.

[0085] The transistor 70 has a gate that supplies a backup data read signal load. The line is connected to the gate of transistor 74. Transistor 70 has a source or drain One of the terminals is connected to a node NB in ​​the flip-flop 35. The transistor 70 is The other of the source and drain is connected to one of the source and drain of the transistor 71. can be.

[0086] The other of the source and drain of the transistor 71 is connected to the ground potential.

[0087] The other electrode of the capacitance element 72 is applied with a ground potential.

[0088] Transistor 73 supplies a backup data write signal store to its gate. The wiring is connected to the gate of the transistor 69. The transistor 73 has a source or drain. One of the inputs is connected to a node NB in ​​the flip-flop 35. The transistor 73 The other of the source and drain is connected to the gate of the transistor 75 and one electrode of the capacitor element 76. is connected.

[0089] The transistor 74 has a gate that supplies a backup data read signal load. The line is connected to the gate of transistor 70. Transistor 74 has a source or drain One of the transistors is connected to node N in flip-flop 35. The other of the source and drain of the transistor 75 is connected to the other of the source and drain of the transistor 76. do.

[0090] The other of the source and drain of the transistor 75 is connected to the ground potential.

[0091] The other electrode of the capacitance element 76 is applied with a ground potential.

[0092] The transistors 69 and 73 have a leakage current (off) when they are in a non-conducting state. The transistor is an OS transistor, which has an extremely low current. It is preferable to use an OS transistor for the transistor 69 and the transistor 73. By using a transistor, the capacitor element 72 is kept in a non-conducting state. In addition, the capacitor element 76 can hold a charge according to the potential of the data held therein.

[0093] Data is written from the flip-flop 35 to the backup circuit 37 as follows: First, the backup data write signal store is set to high level. This causes the transistors 69 and 73 to be in a conductive state. The capacitance elements 72 and 76 in FIG. 7 have capacitances that respond to the voltages of the nodes N and NB. The backup data write signal STORE is set to low level. This causes the transistors 69 and 73 to be non-conductive. and transistor 73 are kept in a non-conductive state, thereby 6 can hold a charge according to the data held therein.

[0094] The data is read from the backup circuit 37 to the flip-flop 35 as follows: First, the backup data read signal load is set to high level. This causes transistors 70 and 74 to be in a conducting state. The path 37 is connected to the channel between the transistor 71 and the transistor 75 by a charge according to the data. In this state, the supply of the power supply voltage to the backup circuit 37 is By restarting the supply of power, a potential difference can be generated between the nodes N and NB, and the back Data can be read from the up-circuit 37 to the flip-flop 35 .

[0095] <Memory cells applicable to frame memory> 10(A) to 10(F) show examples of configurations applicable to the above-mentioned frame memory 25. explain.

[0096] FIG. 10A is a block diagram illustrating an example of the configuration of the frame memory 25. In the block diagram shown in FIG. 10(A), a memory cell array 90, a word line driving circuit 91, and 1 and a bit line driver circuit 92 are shown.

[0097] The memory cell array 90 is a matrix of m rows and n columns (m and n are natural numbers). The memory cells MC are connected to the word lines WL_1 to WL_m and the bit lines WL_1 to WL_m. The memory cells MC are connected to bit lines and word lines as well as to The source line for passing current, the wiring for applying voltage to the back gate of the transistor, Alternatively, one electrode of the capacitance element may be connected to a capacitance line or the like for setting the electrode at a fixed potential.

[0098] The word line driving circuit 91 outputs a signal for selecting the memory cells MC in each row. The word lines WL_1 to WL_m are divided into separate word lines for writing and reading. There may also be a wire.

[0099] The bit line driver circuit 92 writes data to the memory cells MC in each column, or This is a circuit for reading data from memory cells MC. L_n may have separate bit lines for writing and reading.

[0100] 10B to 10F show circuit configurations that the memory cell MC described in FIG. 10A can have. An example of the configuration is shown below.

[0101] The memory cell MC_A shown in FIG. 10B includes a transistor OS1 and a capacitance element 93. The transistor OS1 is an OS transistor. Therefore, by turning off the transistor OS1, Therefore, the charge storage node SN can store a charge according to the data. Therefore, the refresh rate of the data held in the node SN can be reduced.

[0102] The memory cell MC_B shown in FIG. 10C includes a transistor OS2 and a capacitance element 93. The transistor OS2 is an OS transistor. The difference from OS1 is that the gate and back gate are electrically connected, and the word line WL is By using this configuration, the transistor OS2 is turned on. When the above condition is satisfied, the amount of current flowing between the source and the drain can be increased.

[0103] The memory cell MC_C shown in FIG. 10(D) includes a transistor OS3 and a capacitance element 93. The transistor OS3 is an OS transistor. The difference from OS1 is that the back gate and the back gate line BGL are electrically connected. The point is that a voltage different from that applied to the gate is applied to the terminal. The threshold voltage of the transistor OS3 is controlled to control the amount of current flowing between the source and drain. This can be done.

[0104] The memory cell MC_D shown in FIG. 10(E) includes a transistor OS1, a transistor M1, and a and a capacitor element 93. Either the source or the drain of the transistor OS1 is The other of the source and drain of the transistor OS1 is connected to the bit line WBL. The transistor M1 is connected to the gate of the transistor M1 and one electrode of the capacitor 93. The gate of OS1 is connected to the write word line WWL. The source or drain of the transistor M1 is connected to the read word line RWL. The other of the source and drain of the transistor M1 is connected to the read bit line RBL. The transistor M1 is connected to the source line SL. By turning off the transistor OS1, The charge storage node SN can store a charge according to the data. The transistor has silicon in the channel formation region (Si transistor). The transistor OS1 may have the same configuration as the above-described transistors OS2 and OS3. can.

[0105] The memory cell MC_E shown in FIG. 10(F) includes a transistor OS1, a transistor M1, The transistor M2 and the capacitance element 93 are connected to the source or drain of the transistor OS1. One of the inputs is connected to the write bit line WBL. The other drain is connected to the gate of the transistor M1 and one electrode of the capacitance element 93. The gate of the transistor OS1 is connected to the write word line WWL. The other electrode of the transistor M1 is connected to the capacitance line CL. One of the terminals is connected to either the source or drain of transistor M2. The other of the source and drain of the transistor M1 is connected to the source line SL. The other of the source and drain of the transistor M2 is connected to the read word line RWL. Transistor M2 is a p-channel transistor connected to a read bit line RBL. Although shown in the figure, an n-channel transistor may be used. By doing so, the charge storage node SN can store a charge according to the data. The transistor M2 is a Si transistor. The configuration can be the same as that of data OS2 and OS3.

[0106] The memory cell configurations shown in FIGS. 10(B) to 10(F) are used for storing images in the frame memory. This is particularly effective when data increases. Compared to a configuration using 1 to 3 memory cells, the circuit In particular, the memory cell configurations shown in FIGS. 10(B) to 10(D) can reduce the circuit area. It is effective in suppressing the increase of

[0107] In addition, in the frame memory, one of the memory cells shown in FIGS. 10(B) to 10(D) and the memory cell shown in FIG. A configuration using a memory cell in combination with the memory cell shown in (E) or (F) is also effective. The configurations shown in (E) and (F) are for either the source or drain of an OS transistor. and the gate of the Si transistor are electrically connected. The charge is stored in the terminals and used as a nonvolatile memory. By storing data, for example, non-volatile memory and memory cells with low refresh rates can be used. and can be mixed in the frame memory, and the decoding of image data input from the outside can be performed. can be easily realized.

[0108] This configuration is particularly effective when the amount of image data stored in the frame memory increases. When configuring the frame memory memory cells with DRAM (Dynamic RAM), It is necessary to incorporate non-volatile memory, but this complicates the manufacturing process and increases manufacturing costs. By using an OS transistor to embed non-volatile memory in the frame memory, Image data can be compressed or decompressed without increasing manufacturing costs.

[0109] Note that the circuit configurations illustrated in FIGS. 10B to 10F are merely examples and are not intended to be limiting examples of one embodiment of the present invention. Any feasible configuration may be used.

[0110] <Example of how to manufacture electronic components> FIG. 11(A) is a flowchart showing an example of a method for manufacturing an electronic component. This electronic component is also called a conductor package or IC package. There are multiple standards and names depending on the shape of the terminal. An example of this will be described.

[0111] Semiconductor devices made up of transistors are assembled on printed circuit boards through an assembly process (post-process). The plate is completed by assembling multiple detachable parts. The post-process is shown in Figure 11(A). Specifically, the device substrate obtained in the previous step can be completed by going through the steps shown below. After the plate is completed (step ST71), the back surface of the substrate is ground. At this stage, the substrate is thinned. This reduces warping of the board in the previous process and allows for miniaturization of the components. A dicing step is performed to separate the wafer into chips (step ST72).

[0112] FIG. 11(B) is a top view of the semiconductor wafer 7100 before the dicing process is performed. FIG. 11(C) is a partially enlarged view of FIG. 11(B). The circuit region 7102 is provided with a semiconductor device according to an embodiment of the present invention. A body device is provided.

[0113] Each of the multiple circuit regions 7102 is surrounded by an isolation region 7104. A separation line (also called a "dicing line") 7106 is set at a position overlapping with 104. In the dicing step ST72, the semiconductor wafer 7100 is cut along the separation lines 7106. By this, chips 7110 including circuit regions 7102 are cut out from the semiconductor wafer 7100 . FIG. 11(D) shows an enlarged view of the chip 7110.

[0114] A conductive layer or a semiconductor layer may be provided in the separation region 7104. By providing a conductive layer, ESD that may occur during the dicing process is mitigated, This prevents the reduction in yield caused by the chips. For the purpose of cooling, removing shavings, preventing static electricity, etc., carbon dioxide gas is dissolved to reduce the resistivity. This is done while supplying pure water to the cutting area. This reduces the amount of pure water used, thereby reducing the production cost of semiconductor devices. Furthermore, the productivity of the semiconductor device can be improved.

[0115] After step ST72, the separated chips are individually picked up and attached to the lead frames. Then, a die bonding process is carried out in which the semiconductor device is mounted on a die and bonded to the die (step ST73). The method for bonding the chip to the lead frame in the bonding process can be selected according to the product. For example, the adhesive can be made by using resin or tape. The chip may be mounted on the interposer and bonded. The frame leads and the electrodes on the chip are electrically connected with thin metal wires (semiconductors). (Step ST74) Silver wire or gold wire can be used for the thin metal wire. The bonding may be either ball bonding or wedge bonding.

[0116] The wire-bonded chip is sealed with epoxy resin, etc., in a molding process. The molding process is carried out (step ST75). The inside of the electronic component is filled with resin. This reduces damage to the built-in circuitry and wires caused by external mechanical forces. This also reduces the deterioration of characteristics due to moisture and dust. The leads are then cut and shaped (step ST76). This prevents the leads from rusting, ensuring a more reliable soldering when mounting the leads to a printed circuit board. This can be done by printing (marking) the surface of the package (Step S After the inspection process (step ST78), the electronic components are completed (step ST7 9) By incorporating the semiconductor device according to the above embodiment, it is possible to realize a low-power consumption, small-sized electronic device. Products can be provided.

[0117] A perspective view of the completed electronic component is shown in Figure 11(E). As an example, a perspective view of a QFP (Quad Flat Package) is shown. As shown in FIG. 11(E), the electronic component 7000 includes a lead 7001 and a chip 7110. It has.

[0118] The electronic component 7000 is mounted on, for example, a printed circuit board 7002. 7000 are combined and electrically connected to each other on a printed circuit board 7002. The completed circuit board 7004 can be mounted on an electronic device. The electronic component 7000 is installed inside the device, reducing the power consumption of the electronic device. Alternatively, it becomes easier to miniaturize electronic devices.

[0119] Electronic Components 7000 is a category that includes digital signal processing, software radio, avionics (communications equipment) , navigation systems, autopilots, flight management systems, and other aviation-related electronic equipment), ASI C prototyping, medical image processing, speech recognition, cryptography, bioinformatics ( a wide range of applications, including bioinformatics, emulators of mechanical devices, and radio telescopes in radio astronomy. It can be applied to electronic components (IC chips) in a wide range of electronic devices. Electronic devices include cameras (video cameras, digital still cameras, etc.), display devices, personal computers, and Personal computers (PCs), mobile phones, portable game consoles, portable information terminals (smartphones) smartphones, tablet-type information terminals, etc.), e-book terminals, wearable information terminals (time Monitor type, head-mounted type, goggle type, eyeglass type, armband type, bracelet type, necklace type etc.), navigation systems, sound reproduction devices (car audio, digital audio players) Layers, etc.), copiers, facsimiles, printers, printer-combined machines, automated teller machines Examples include ATMs, vending machines, and household electrical appliances.

[0120] Next, computers, portable information terminals (mobile phones, portable game consoles, sound players, etc.) (including), electronic paper, television equipment (also called television or television receiver) ) and digital video cameras, etc. Reveal.

[0121] FIG. 12A shows a portable information terminal, which includes a housing 801, a housing 802, a first display unit 8, and a The display unit 803a and the second display unit 803b are included. At least a part of the semiconductor device is provided with the semiconductor device described in the above embodiment. This will realize a portable information terminal with reduced power consumption.

[0122] The first display unit 803a is a panel with a touch input function, and for example, As shown in the left diagram of 12(A), the first display section 803a displays a selection button 804. You can choose to use "touch input" or "keyboard input". It can be displayed in a convenient size, so people of all ages can feel the ease of use. When "Keyboard Input" is selected, the first display section 803a is displayed as shown in the right diagram of FIG. 12(A). A keyboard 805 is displayed on the screen. This allows the user to input data by keystrokes in the same way as with conventional information terminals. This allows for quick text input.

[0123] In addition, the portable information terminal shown in FIG. 12(A) has a first Either the display unit 803a or the second display unit 803b can be removed. The display unit 803b is also a panel with a touch input function, making it even lighter when carried around. This allows the user to hold the housing 802 with one hand and operate it with the other, which is convenient. It is beneficial.

[0124] The portable information terminal shown in FIG. 12(A) displays various information (still images, moving images, text images, etc.). Functions that display calendars, dates, or times on the display, functions that display Functions for manipulating or editing displayed information, processing by various software (programs) In addition, external connection terminals can be provided on the back and sides of the housing. It may also be configured to include a connector (such as an earphone jack or USB terminal), a recording medium insertion section, etc.

[0125] The portable information terminal shown in FIG. 12(A) is configured to be capable of transmitting and receiving information wirelessly. You can also purchase and download desired book data from an electronic book server wirelessly. It is also possible to configure it so that it is downloaded.

[0126] Furthermore, the housing 802 shown in FIG. 12A may be provided with an antenna, a microphone function, and a wireless function, and may be used as a mobile phone. It may also be used as a mobile phone.

[0127] FIG. 12B shows an electronic book terminal 810 equipped with electronic paper, which is made up of a housing 811 and a housing 812. The display device 810 is configured with two housings, housing 811 and housing 812. The housing 811 and the housing 812 are connected to a shaft 815. The housing is connected to the shaft 815, and the opening and closing operation can be performed around the shaft 815. The housing 811 includes a power supply 816, operation keys 817, a speaker 818, etc. 1. At least one of the housings 812 is provided with the semiconductor device shown in the previous embodiment. This will enable the realization of an e-book reader with low power consumption.

[0128] FIG. 12C shows a television device, which includes a housing 821, a display unit 822, and a stand 82 The television device 820 is operated by a switch provided on the housing 821. This can be done by a switch or a remote control 824. The semiconductor device described in the previous embodiment is provided in the semiconductor device 24. A television device in which the above is achieved is realized.

[0129] FIG. 12D shows a smartphone, and a main body 830 includes a display unit 831 and a speaker. The main body 830 is provided with a keyboard 832, a microphone 833, and an operation button 834. Therefore, malfunctions are reduced and power consumption is reduced. Electrified smartphones will become a reality.

[0130] FIG. 12(E) shows a digital camera, which includes a main body 841, a display unit 842, and an operation switch 8 The main body 841 is made up of the semiconductor device shown in the previous embodiment. This allows for a digital camera with low power consumption.

[0131] As described above, the electronic devices described in this embodiment include the semiconductor device according to the above embodiment. This allows for the realization of electronic devices with reduced power consumption.

[0132] <Additional notes regarding the present specification etc.> In this specification, the ordinal numbers "first," "second," and "third" are used to avoid confusion of constituent elements. Therefore, the number of components is not limited. , the order of the components is not limited.

[0133] In this specification and the like, in the block diagram, components are classified by function and are separated into blocks independent of each other. However, in actual circuits, components are switched according to their functions. It is difficult to separate the functions, and when multiple functions are involved in one circuit, or when multiple circuits are involved, Therefore, the blocks in the block diagram may be different from those described in the specification. The components are not limited to those mentioned above, but may be rephrased appropriately depending on the situation.

[0134] In the drawings, elements that are the same or have similar functions, elements that are made of the same material, or In some cases, the same reference numerals may be used to designate elements that are formed at the same time, and repeated explanations thereof will be omitted. It may be omitted.

[0135] In this specification and the like, when describing the connection relationship of a transistor, The first electrode or the first terminal is referred to as the "source or drain" (or the first electrode or the first terminal). The other of the source and drain is referred to as the "other of the source or drain" (or second electrode, or second terminal). This means that the source and drain of a transistor are This is because the names of the source and drain of a transistor change depending on the operating conditions. In this case, the term source (drain) terminal, source (drain) electrode, etc. may be used appropriately depending on the situation. It can be replaced.

[0136] In this specification and the like, the terms voltage and potential can be interchanged as appropriate. It is the potential difference from the reference potential. For example, the reference potential is the ground potential (earth potential). If we use the term "potential"), we can translate voltage into potential. Ground potential is not necessarily 0V. It does not necessarily mean that the potential is relative, and depending on the reference potential, The potential applied to wiring etc. may be changed.

[0137] In this specification, a switch refers to a device that can be in a conducting state (ON state) or a non-conducting state (OFF state). It refers to a device that has the function of controlling whether or not current flows by entering a state where it is in a non-operating state. A switch is a device that has the function of selecting and switching a path through which a current flows.

[0138] For example, an electrical switch or a mechanical switch can be used. The switch is not limited to a specific one as long as it can control the current.

[0139] When a transistor is used as a switch, the "conduction state" of the transistor is This refers to a state in which the source and drain of a transistor can be considered to be electrically short-circuited. The "non-conducting state" of a transistor is when the source and drain of the transistor are electrically isolated. This refers to a state in which the transistor can be considered to be operating as a simple switch. In this case, the polarity (conductivity type) of the transistor is not particularly limited.

[0140] In this specification, "A and B are connected" does not mean that A and B are directly connected. In addition to those that are electrically connected, A and B are also included. Connected to means that there is an object that has some electrical effect between A and B. When this occurs, it refers to something that enables the transmission and reception of electrical signals between A and B. [Explanation of symbols]

[0141] 10 Semiconductor devices 10A Semiconductor Device 10B Semiconductor device 10C Application Processor 10D Semiconductor Devices 10E Application Processor 20 MPU 30 Interfaces 30A I / F 30B I / F 30C Display I / F 30D memory I / F 32 registers 33 Flip-Flop 34 Memory circuit 35 Flip-Flop 36 Memory circuit 37 Backup circuit 38 Switch 40 Functional Devices 40A Functional Device 40B Functional Device 41 Display Devices 42 Display Controller 43 Display section 44 pixels 45 DRAM 50 System Bus 63 Switch 64 Switch 65 Inverter circuit 66 Inverter circuit 67 Inverter Circuit 68 Inverter Circuit 69 Transistor 70 transistors 71 Transistor 72 Capacitor element 73 Transistor 74 transistors 75 transistors 76 Capacitor element 77 Switch 78 Switch 79 Inverter Circuit 85 Inverter circuit 86 Inverter circuit 90 Memory Cell Array 91 Word line driver circuit 92 Bit line driver circuit MC memory cell MC_A memory cell MC_B memory cell MC_C memory cell MC_D memory cell MC_E memory cell WL Word Line BL bit line SL Source Line WWL Write Word Line RWL Read Word Line OS1 transistor 93 Capacitor M1 transistor M2 transistor SN charge storage node S11 Step S12 Step S13 Step S14 Step S15 Step S16 Step 21 Power Controller 22 SRAM 23 GPU 24 FPGA 25 frame memory 7000 electronic components 7001 Lead 7002 Printed circuit board 7004 Circuit Board 7100 Semiconductor Wafers 7102 Circuit area 7104 Separation area 7106 Separation line 7110 chip 801 Case 802 chassis 803a Display section 803b Display section 804 Select button 805 keyboard 810 E-book reader 811 Case 812 chassis 813 Display section 814 Display section 815 Shaft 816 Power supply 817 Operation Key 818 Speaker 820 Television equipment 821 Case 822 Display section 823 Stand 824 Remote Controlled Machine 830 main unit 831 Display section 832 speakers 833 Mike 834 Operation button 841 Main Unit 842 Display section 843 Operation switch

Claims

1. A semiconductor device having a processor, a power controller, an interface circuit, and a switch connected to a power supply voltage, the interface circuit has a register for storing setting information of a display device and a frame memory; the interface circuit has a function of transmitting signals input and output between the processor and a display device; the display device includes a display controller and a display unit; the display controller transmits and receives image data to and from the frame memory; the power controller has a function of supplying the power supply voltage to the interface circuit or cutting off the supply of the power supply voltage; the switch is controlled by the power controller, and when the switch is turned on, the power supply voltage is supplied to the interface circuit, and when the switch is turned off, the supply of the power supply voltage to the interface circuit is cut off; the power supply voltage is not supplied or cut off by the power controller to the processor; the register includes a first storage circuit capable of storing the setting information when the power supply voltage is being supplied and losing the setting information when the supply of the power supply voltage is cut off, and a second storage circuit capable of storing the setting information when the supply of the power supply voltage is cut off; the second memory circuit includes a first transistor, a second transistor, and a capacitor; the first transistor includes an oxide semiconductor in a semiconductor layer that serves as a channel formation region, one of the source and the drain of the first transistor is electrically connected to the gate of the second transistor; one of a source and a drain of the first transistor is electrically connected to one electrode of the capacitor element; the first transistor has a function of holding charge on a gate of the second transistor by turning the first transistor off; the first transistor has a first gate and a second gate; different voltages are applied to the first gate and the second gate; The interface circuit a first state in which the setting information is stored in the first storage circuit; a second state in which the display device operates based on the setting information stored in the first storage circuit; a third state in which the setting information stored in the first storage circuit is stored in the second storage circuit and the supply of the power supply voltage is cut off; a fourth state in which the supply of the power supply voltage is resumed and the setting information stored in the second storage circuit is stored in the first storage circuit; the display device has a function of switching between a moving image display state in which a video signal written in a pixel of the display unit is rewritten and a still image display state in which the video signal written in the pixel is not rewritten, The interface circuit the display device switches to the second state when in the moving image display state; the display device switches to the third state when the moving image display state transitions to the still image display state; The semiconductor device has a function of switching to the second state via the fourth state when the display device transitions from the still image display state to the moving image display state.

2. In claim 1, the frame memory includes a third transistor; the third transistor includes an oxide semiconductor in a semiconductor layer that serves as a channel formation region, The third transistor has a function of holding charge at one of the source and the drain of the third transistor by turning the third transistor off.

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