Input / Output Reference Voltage Training Method in 3D Memory Devices

Abstract

To provide an input / output voltage training method in a three-dimensional (3D) memory device.SOLUTION: A method can include: (1) the step of setting a reference voltage value in an on-die termination (ODT) enable state; (2) the step of controlling a 3D memory device to perform a write training process; (3) the step of determining whether or not a further write training process is required; (4) the step of repeating operations (1), (2), and (3) in response to determination that the further write training process is required; and (5) the step of setting the reference voltage value as an optimization reference voltage value in response to determination that the further write training process is not required.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present disclosure relates generally to the field of semiconductor technology, and more particularly to methods, related systems, and related media for input / output voltage training for three-dimensional (3D) memories. [Background technology]

[0002] As memory devices shrink to smaller die sizes to reduce manufacturing costs and increase storage density, scaling down planar memory cells has become a challenge due to process technology limitations and reliability issues. Three-dimensional (3D) memory architectures, such as 3D NAND flash memory devices, can address the density and performance limitations of planar memory cells. Many conventional techniques are available for calibrating the circuits (e.g., receivers and transmitters) within 3D NAND flash memory devices to improve the accuracy of signals communicated between these devices and hosts (e.g., processor devices) or other integrated circuit (IC) devices. The initialization procedure for 3D NAND flash memory devices can include four phases: power-on and initialization, ZQ calibration, Vref DQ calibration, and read / write training. Summary of the Invention [Means for solving the problem]

[0003] In this disclosure, aspects of three-dimensional (3D) memory devices and methods for input / output voltage training are described.

[0004] One aspect of the present disclosure provides a method for input / output voltage training of a three-dimensional (3D) memory device, which may include: (1) setting a reference voltage value to an on-die termination (ODT) enabled state; (2) controlling the 3D memory device to perform a write training process; (3) determining whether a further write training process is required; (4) repeating the operations (1), (2), and (3) in response to determining that a further write training process is required; and (5) setting the reference voltage value as an optimized reference voltage value in response to determining that a further write training process is not required.

[0005] In some embodiments, setting the reference voltage value occurs in either an on-die termination (ODT) enabled state or an ODT disabled state.

[0006] In some embodiments, setting the reference voltage value includes using the first trimming signal to control a main voltage source to generate the reference voltage generation signal.

[0007] In some embodiments, setting the reference voltage value further includes controlling a voltage booster using the second trimming signal and a booster enable control signal to generate the reference voltage boost signal.

[0008] In some embodiments, setting the reference voltage value further includes generating the reference voltage value based on at least a reference voltage generation signal and a reference voltage boost signal.

[0009] In some embodiments, setting the reference voltage value further includes changing the reference voltage from a previous value to a default value during a first period of a first high level of the booster enable control signal, and changing the reference voltage from the default value to a new value for light training during a second period of a second high level of the booster enable control signal.

[0010] In some embodiments, setting the reference voltage value further includes controlling a voltage booster using the first trimming signal and the booster enable control signal to generate the reference voltage boost signal, and controlling a reference voltage start circuit using the first trimming signal and the start enable control signal to generate the reference voltage start signal.

[0011] In some embodiments, setting the reference voltage value further includes generating the reference voltage value based on at least a reference voltage generation signal, a reference voltage boost signal, and a reference voltage start signal.

[0012] In some embodiments, setting the reference voltage value further includes changing the reference voltage from a previous value to a default value during a first period when the start enable control signal is at a high level, and changing the reference voltage from a previous value to the default value during a first period when the booster enable control signal is at a high level.

[0013] In some embodiments, performing the write training process includes performing a data write operation and a data read operation, and determining whether a further write training process is required based on at least the results of the data read operation.

[0014] Another aspect of the present disclosure provides a three-dimensional (3D) memory device including a memory cell array and peripheral circuitry coupled to the memory cell array, the peripheral circuitry including a control circuit configured to (1) set a reference voltage value in an on-die termination (ODT) enabled state, (2) control the memory cell array to perform a write training process, (3) determine whether a further write training process is required, (4) in response to determining that a further write training process is required, repeat the operations of (1), (2), and (3), and (5) in response to determining that a further write training process is not required, set the reference voltage value to an optimized reference voltage value.

[0015] In some embodiments, the logic control circuit is further configured to set the reference voltage value regardless of whether the on-die termination (ODT) is enabled or disabled.

[0016] In some embodiments, the peripheral circuitry further includes a main voltage source configured to receive the first trimming signal from the logic control circuitry and to generate the reference voltage generation signal.

[0017] In some embodiments, the peripheral circuitry further includes a voltage booster configured to receive the second trimming signal and a booster enable control signal from the logic control circuitry to generate the reference voltage boost signal.

[0018] In some embodiments, the peripheral circuitry further includes a multiplexer configured to generate the reference voltage value based on at least the reference voltage generation signal and the booster enable control signal.

[0019] In some embodiments, the multiplexer is configured to change the reference voltage from a previous value to a default value during a first period of a first high level of the booster enable control signal, and to change the reference voltage from the default value to a new value for write training during a second period of a second high level of the booster enable control signal.

[0020] In some embodiments, the peripheral circuitry further includes a voltage booster configured to receive the first trimming signal and a booster enable control signal from the logic control circuit to generate a booster enable control signal, and a reference voltage start circuit configured to receive the first trimming signal and a start enable control signal from the logic control circuit to generate a reference voltage start signal.

[0021] In some embodiments, the peripheral circuitry further includes a multiplexer configured to generate the reference voltage value based on at least the reference voltage generation signal, the booster enable control signal, and the reference voltage start signal.

[0022] In some embodiments, the multiplexer is further configured to change the reference voltage from its previous value to the default value during a first period when the start enable control signal is at a high level, and to change the reference voltage from its previous value to the default value during a first period when the booster enable control signal is at a high level.

[0023] In some embodiments, the control circuitry is further configured to control the memory cell array to perform data write operations and data read operations, and to determine whether further write training processes are required based on at least the results of the data read operations.

[0024] Another aspect of the present disclosure provides a memory system including the above-described 3D memory device and a memory controller configured to control the 3D memory device.

[0025] Other aspects of the present disclosure will be apparent to those skilled in the art in light of the description, claims, and drawings of the present disclosure.

[0026] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate aspects of the disclosure and, together with the description, further serve to explain the principles of the disclosure and to enable one skilled in the relevant art to make and use the disclosure. [Brief explanation of the drawings]

[0027] [Figure 1A] FIG. 1 is a block diagram of an exemplary system having a memory device in accordance with some aspects of the present disclosure. [Figure 1B] FIG. 1 is a diagram of an exemplary memory card having a memory device in accordance with some aspects of the present disclosure. [Figure 1C] 1 is a diagram of an exemplary solid-state drive (SSD) having memory in accordance with some aspects of the present disclosure. [Figure 2] FIG. 1 is a schematic block diagram of an example hardware module configuration of a memory system, according to some aspects. [Figure 3] FIG. 1 is a schematic circuit diagram of an exemplary memory device including peripheral circuitry in accordance with some aspects of the present disclosure. [Figure 4A] 1 is a perspective view of a portion of an exemplary three-dimensional (3D) memory array structure according to some aspects of the present disclosure. FIG. [Figure 4B] 1 is a schematic diagram of an exemplary 3D memory device in a plan view, in accordance with some aspects of the present disclosure. FIG. [Figure 5] FIG. 2 is a schematic block diagram of an exemplary circuit for NAND reference voltage application, in accordance with some aspects of the present disclosure. [Figure 6] 6 illustrates a schematic flowchart of an example method 600 for IO reference voltage training of a NAND memory, in accordance with certain aspects of the present disclosure. [Figure 7] 7 illustrates a schematic timing diagram of an example operation of the method of FIG. 6 for training a first reference voltage, in accordance with some aspects of the present disclosure. [Figure 8A]FIG. 1 is a schematic block diagram of an example peripheral circuit for IO reference voltage training of a NAND memory device, in accordance with some aspects of the present disclosure. [Figure 8B] FIG. 8A shows a schematic timing diagram of an example operation of the method of FIG. 6 for training a first reference voltage, in accordance with some aspects of the present disclosure. [Figure 9A] FIG. 10 is a schematic block diagram of an example peripheral circuit for IO reference voltage training of a NAND memory device, in accordance with certain other aspects of the present disclosure. [Figure 9B] FIG. 9A shows a schematic timing diagram of an example operation of the method of FIG. 6 for training a first reference voltage, in accordance with some aspects of the present disclosure. [Figure 10A] FIG. 2 is a circuit schematic diagram of an exemplary resistive divider in accordance with some aspects of the present disclosure. [Figure 10B] FIG. 2 is a circuit schematic diagram of an exemplary combination of a reference voltage generator and an analog buffer, in accordance with some aspects of the present disclosure. [Figure 11] FIG. 1 is a schematic block diagram of an exemplary computer system in accordance with some aspects of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0028] The features and advantages of the present disclosure will become more apparent from the detailed description set forth below when taken in conjunction with the drawings, in which like reference characters identify corresponding elements throughout. In the drawings, like reference numbers indicate substantially identical functionally similar elements and / or substantially identical structurally similar elements. The drawing in which an element first appears is indicated by the left-most corresponding reference number.

[0029] Aspects of the present disclosure will be described with reference to the accompanying drawings.

[0030] While specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. Those skilled in the art will recognize that other configurations and arrangements can be used without departing from the spirit and scope of the present disclosure. Those skilled in the art will recognize that the present disclosure may be adapted for a variety of other applications.

[0031] It should be noted that, in this specification, references to "one embodiment," "an embodiment," "an example embodiment," "some embodiments," etc., indicate that the described embodiment may include a particular feature, structure, or characteristic, but that not all embodiments necessarily include the particular feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. Furthermore, when a particular feature, structure, or characteristic is described in the context of one embodiment, it is within the knowledge of one of ordinary skill in the art that such feature, structure, or characteristic also applies to other embodiments, whether or not explicitly stated.

[0032] In most cases, terminology can be understood, at least in part, from contextual usage. For example, as used herein, the term "one or more" can be used to describe any feature, structure, or characteristic in the singular or in the plural, depending at least in part on the context. Similarly, it can be understood that terms such as "a," "an," or "the" can also convey either the singular or the plural, depending at least in part on the context. It is also understood that the term "based on" does not necessarily refer to an exclusive set of factors and may allow for the presence of additional factors not necessarily expressly stated, depending at least in part on the context.

[0033] As should be readily apparent, the meanings of "on," "above," and "over" in this disclosure should be interpreted in the broadest sense, such that "on" not only means "directly on" something, but also includes "on" something with an intermediate feature or layer between them. Also, "above" or "over" can include not only meaning "above" something or "over" something, but also meaning "on" something or "above" something with no intermediate feature or layer between them (i.e., directly on top of something).

[0034] Additionally, spatially relative terms such as "beneath," "below," "lower," "above," and "upper" may be used herein for convenience of description to describe the relationship of one element or feature to another element or feature as shown in the figures. The spatially relative terms are intended to encompass various orientations of the device in use or process steps in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative terms used herein may be similarly interpreted accordingly.

[0035] As used herein, the term "substrate" refers to a material onto which subsequent layers of material are applied. A substrate has a "top" and a "bottom" side. The front side of a substrate is typically where semiconductor devices are formed, and therefore, semiconductor devices are formed on the surface of the substrate unless otherwise specified. The bottom side is opposite the front side, and therefore, the bottom side of a substrate is opposite the front side of the substrate. The substrate itself may be patterned. Materials applied onto the substrate may be patterned or may remain unpatterned. Furthermore, substrates may include a wide range of semiconductor materials, such as silicon, germanium, germanium arsenide, and phosphorus phosphide. Alternatively, substrates may be made of glass, plastic, or non-conductive materials such as a sapphire wafer.

[0036] As used herein, the term "layer" refers to a portion of material that includes a region of thickness. A layer has a top surface and a bottom surface, with the bottom surface of the layer being relatively closer to the substrate and the top surface being relatively farther from the substrate. A layer may span the entire underlying or overlying structure, or it may extend less than the extent of the underlying or overlying structure. Furthermore, a layer may be a uniform, continuous structure whose thickness is less than the thickness of the continuous structure, or a non-uniform, continuous region. For example, a layer may be present between any set of horizontal planes between the top and bottom surfaces of a continuous structure, or on the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along tapered surfaces. A substrate may be a layer, and may have one or more layers on it, above it, and / or below it. A layer may be multiple layers. For example, the interconnect layer may include one or more conductive contact layers (having contacts, interconnect lines, and / or vertical interconnect accesses (VIAs) formed therein).

[0037] For convenience in this disclosure, the term "step" is used to refer to elements that are approximately the same height along the vertical direction. For example, a word line and an underlying gate insulating layer may be referred to as a "step," and word lines that are approximately the same height may be referred to as word line steps, etc.

[0038] As used herein, the term "nominal" refers to a desired or target value of a characteristic or parameter of a component or process step established during the design phase of production or processing, with a range of values ​​above the desired value and / or a range of values ​​below the desired value. The range of values ​​may be due to minor variations in the manufacturing process or tolerances. As used herein, the term "about" indicates a value of a given quantity that may vary based on the particular technology node associated with the semiconductor device of interest. Based on the particular technology node, the term "about" can indicate, for example, a value that varies within a range of 10-30% of the value (e.g., ±10%, ±20%, or ±30% of the value).

[0039] In this disclosure, the terms "horizontal / horizontally / lateral / laterally" mean nominally parallel to the side of the substrate, and the terms "vertical" or "vertically" mean nominally perpendicular to the side of the substrate.

[0040] As used herein, the term "3D memory" refers to a three-dimensional (3D) semiconductor device in which strings of memory cell transistors (referred to herein as "memory strings", such as NAND strings) are oriented vertically in a lateral-oriented substrate such that memory columns extend perpendicularly to the substrate.

[0041] The Open NAND Flash Interface (ONFI) standard is an interface standard for NAND flash memory devices, including communication between NAND flash memory devices and other devices (e.g., hosts, such as processors). The technology-defined NAND memory device input / output (IO) interface (NAND interface) operates at a maximum speed of up to 800 megatransfers per second (MT / s). Future storage solutions target host interfaces such as Peripheral Component Interconnect Express (PCIe) Generation 3 and 4 (PCIe-Gen3 / 4) and Universal Flash Storage version 3.0 (UFS) or later for the NAND interface to accommodate larger storage capacities. To reduce the number of channels packed into the PCIe / UFS host interface, the NAND interface speed must scale up much more quickly than the IO interface speed defined by the NAND interface (e.g., up to 1600 MT / s or higher). Some recently developed NAND interfaces (e.g., toggle-mode NAND interfaces) can increase speeds up to 1200 MT / z.

[0042] Operating an IO interface at relatively high speeds (e.g., up to 1600 MT / s or greater) incurs significant AC timing margin loss due to channel loss, NAND internal variations (e.g., due to process-voltage-temperature (PVT) and internal timing mismatch), and host-side inherent losses (e.g., due to mismatch between host-side DQ (data) and DQS (clock)). These factors can result in read AC timing margin loss, i.e., inaccurate read data (e.g., data transferred from the NAND device to the host). Such loss can be particularly severe in higher-end multi-die stacking NAND memory devices. Overcoming such loss can result in excessive power consumption. Another NAND implementation involves using intermediate devices between the host and NAND memory device to accommodate larger die stacks. Operating such intermediate devices (e.g., interface chips, repeaters, retimers) at relatively high speeds can also incur significant AC timing margin loss, which can result in read timing margin loss, i.e., inaccurate read data.

[0043] The Data Training feature allows NAND devices to operate at over 800 MT / s in heavily loaded systems. Digital Command Control (DCC) Training is a feature where the NAND compensates for duty cycle mismatches on the RE_t / c signals. Read / Write DQ Training is a feature where the host aligns the DQS and DQ signals resulting from a non-aligned DQS path. Read DQ Training is a function that outputs a 16-bit user-defined pattern on each of the DQ pins. This means that a total of 16 bytes are output by the NAND device (note that some vendors may provide a 32-byte pattern).

[0044] FIG. 1A illustrates a block diagram of an exemplary system 100 including a memory device according to some aspects of the present disclosure. The system 100 may be a mobile phone, a desktop computer, a laptop computer, a tablet, a vehicle computer, a gaming console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable device including storage. As illustrated in FIG. 1A, the system 100 may include a host 108 and a memory system 102 including one or more memory devices 104 and a memory controller 106. The host 108 may be a processor of an electronic device, such as a central processing unit (CPU), or a system-on-chip (SoC), such as an application processor (AP). The host 108 may be configured to transmit data to and receive data from the memory device.

[0045] The memory device 104 may be any memory device disclosed herein, such as a NAND flash memory device. Consistent with the scope of this disclosure, the memory controller 106 may control multi-pass programming for the memory device 104 such that, in a non-last programming pass of the multi-pass programming, an NGS operation is enabled for all memory cells, even if they pass their respective verify operations. A peripheral device, such as a word line driver, may apply a low voltage, e.g., a voltage to ground (GND: GroND), to the DSC of each memory string connected to the selected word line to enable the NGS operation for all memory cells connected to the selected word line during the non-last programming pass.

[0046] In some implementations, a memory controller 106 is coupled to the memory device 104 and the host 108 and configured to control the memory device 104. The memory controller 106 can manage data stored in the memory device and communicate with the host 108. In some implementations, the memory controller 106 is designed to operate in low-duty-cycle environments, such as Secure Digital (SD) cards, Compact Flash (CF) cards, Universal Serial Bus (USB) flash drives, and other media used in electronic devices such as personal computers, digital cameras, and mobile phones. In some implementations, the memory controller 106 is designed to operate in high-duty-cycle environments, such as SSDs or embedded MultiMedia-Cards (eMMCs), used as data storage for mobile devices such as smartphones, tablets, and laptop computers, and enterprise storage arrays. The memory controller 106 may be configured to control operations of the memory device 104, such as read, erase, and program operations. The memory controller 106 may also be configured to manage various functions for data stored or to be stored in the memory device 104, including, but not limited to, bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some implementations, the memory controller 106 is further configured to process error correction codes (ECC) on data read from or written to the memory device 104. Along with the memory controller, for example, the programming memory device 104, may also perform other suitable functions. The memory controller 106 may communicate with an external device (e.g., a host 108) according to a particular communication protocol.For example, the memory controller 106 may communicate with an external device (e.g., the host 108) through at least one of a variety of interface protocols, such as a USB protocol, an MMC protocol, a Peripheral Component Interconnect (PCI) protocol, a PCI-Express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a Serial-ATA protocol, a Parallel-ATA protocol, a Small Computer Small Interface (SCCI) protocol, an Enhanced Small Disk Interface (ESDI) protocol, an Integrated Drive Electronics (IDE) protocol, a Firewire protocol, or the like.

[0047] The memory controller 106 and one or more memory devices 104 can be integrated into various types of storage devices, such as a Universal Flash Storage (UFS) package or an eMMC package. That is, the memory system 102 can be implemented and integrated into various types of end electronic products. In one example shown in FIG. 1B, the memory controller 106 and one memory device 104 can be integrated into a memory card 112. The memory card 122 can include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a SmartMedia (SM) card, a memory stack, a MultiMediaCard (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC) UFS, and the like. The memory card 112 can further include a memory card connector 114 that connects the memory card 112 to a host (e.g., the host 108 in FIG. 1A). 1C, the memory controller 106 and multiple memory devices 104 may be integrated into an SSD 116. The SSD 116 may further include an SSD connector 118 that couples the SSD 116 to a host (e.g., the host 108 in FIG. 1A). In some implementations, the storage capacity and / or operating speed of the SSD is greater than that of the memory card 112.

[0048] 2 is a diagram of an example memory device 104, e.g., a NAND flash memory, having a memory cell array 202 and peripheral circuits including a page buffer 204, a column decoder / bit line driver 206, a row decoder / word line driver 208, a voltage generator 210, control logic 212, registers 214, and an interface 216. FIG. 3 is a schematic circuit diagram of an example memory device 104 including a memory cell array 202 and peripheral circuits 302 coupled to the memory cell array 202. For ease of illustration, some components in FIGS. 2 and 3 are described together. Peripheral circuits 302 may include page buffer 204, column decoder / bit line driver 206, row decoder / word line driver 208, voltage generator 210, control logic 212, registers 214, and interface 216 in FIG. 2. It will be understood that additional peripheral circuits may also be included in some embodiments.

[0049] In some embodiments, the voltage generator 210 may include multiple charge pumps and linear regulators. In some embodiments, the memory cell array may include multiple planes (i.e., plane 0, plane 1, plane 2, and plane 3). While FIG. 2 shows four planes (plane 0, plane 1, plane 2, and plane 3), in some other embodiments, the NAND die may be divided into fewer or more than four planes (e.g., 1, 2, 6, 8, etc.). A plane includes multiple memory cells that may be grouped into a memory block. A memory block is typically the smallest erasable entity in a NAND flash die. In one example, a memory block includes a number of cells coupled to the same bit line. A memory block includes one or more pages of cells. The size of a page may vary depending on the implementation. In one example, the page size is 16 kB. Page sizes less than or greater than 16 kB are also possible (e.g., 512 B, 2 kB, 4 kB, etc.).

[0050] As shown in FIG. 3 , the memory cell array 202 can be a NAND flash memory cell array in which memory cells 306 are provided in the form of an array of NAND memory strings 308, each extending vertically above a substrate (not shown). In some implementations, each NAND memory string 308 includes multiple memory cells 306 coupled in series and stacked vertically. Each memory cell 306 can hold a continuous analog value, such as an electrical voltage or charge, depending on the number of electrons trapped within the region of the memory cell 306. Each memory cell 306 can be either a floating-gate memory cell including a floating-gate transistor or a charge-trap memory cell including a charge-trap transistor. In one example, the memory cell 306 includes a transistor with a replacement gate. A memory cell 306 with a replacement gate typically has a low-resistance gate (e.g., a tungsten gate) and a charge-trapping layer in which charge is trapped or stored between the gate and a channel, representing one or more bit values. In another example, the memory cell 306 can include a transistor with a floating gate (e.g., a high-resistance poly gate) that stores charge representing one or more bit values. Other architectures are possible.

[0051] In some implementations, each memory cell 306 is a single-level cell (SLC) with two possible memory states and can therefore store one bit of data. For example, a first memory state "0" can correspond to a first range of voltages, and a second memory state "1" can correspond to a second range of voltages. In some implementations, each memory cell 306 is a multi-level cell (MLC) that can store more than one bit of data in more than four memory states. For example, an MLC can store two bits per cell, three bits per cell (also called a triple-level cell (TLC)), or four bits per cell (also called a quad-level cell (QLC)). Each MLC can be programmed to assume a range of possible nominal storage values. As an example, if each MLC stores two bits of data, the MLC can be programmed to assume one of three possible programming levels from the erased state by writing one of three possible nominal storage values ​​to the cell. A fourth nominal storage value can be used for the erased state.

[0052] 3, each NAND memory string 308 may include a source select gate (SSG) 310 at its source end and a drain select gate (DSG) 312 at its drain end. The SSG 310 and DSG 312 are gate electrodes of the SSG and DSG transistors, respectively, and may be configured to activate a selected NAND memory string 308 (column of the array) during read and program operations. In some implementations, the SSGs 310 of NAND memory strings 308 in the same block 304 are coupled to ground via the same source line (SL) 314, e.g., a common SL. The DSGs 312 of each NAND memory string 308 are coupled to a respective bit line 316 from which data can be read via an output bus (not shown) according to some implementations. In some implementations, each NAND memory string 308 is configured to be selected or deselected by applying a select voltage (e.g., greater than or equal to the threshold voltage of the transistor having the DSG 312) or a deselect voltage (e.g., 0V) to the respective DSG 312 via one or more DSG lines 313, and / or by applying a select voltage (e.g., greater than or equal to the threshold voltage of the transistor having the SSG 310) or a deselect voltage (e.g., 0V) to the respective SSG 310 via one or more SSG lines 315.

[0053] As shown in FIG. 3 , NAND memory strings 308 can be organized into multiple blocks 304, and each block can have a common source line 314. In some implementations, each block 304 is the basic data unit for erase operations, i.e., all memory cells 306 in the same block 304 are erased simultaneously. Memory cells 306 in adjacent NAND memory strings 308 can be coupled via word lines 318, which select which row of memory cells 306 is affected by read and program operations. In some implementations, each word line 318 is coupled to a page 320 of memory cells 306, which is the basic data unit for program operations. The size of one page 320 in bits can correspond to the number of NAND memory strings 308 coupled by the word lines 318 in one block 304. Each word line 318 can include multiple control gates (gate electrodes) in each memory cell 306 in the respective page 320 and gate lines coupling the control gates. In some implementations, dummy word lines that do not contain user data can also be used in the memory array adjacent to the select gate transistors. Such dummy word lines can protect the edge data word lines from certain edge effects.

[0054] The peripheral circuitry 302 can be coupled to the memory cell array 202 via bit lines 316, word lines 318, source lines 314, SSG lines 315, and DSG lines 313. The peripheral circuitry 302 can apply voltages to the bit lines 316, word lines 318, source lines 314, SSG lines 315, and DSG lines 313 to perform multi-pass programming, including the proposed NSG scheme, in non-final programming passes. As mentioned above, the peripheral circuitry 302 can include any circuitry suitable for facilitating operation of the memory cell array 202 by applying and sensing voltage and / or current signals via the bit lines 316 to and from each target memory cell 306 via the word lines 318, source lines 314, SSG lines 315, and DSG lines 313.

[0055] A programming sequence for a group of memory cells 306 can include programming all of the intended pages to the group of memory cells 306. A programming sequence can include one or more programming passes. A programming pass (which can include one or more programming loops) can program one or more pages. A programming pass can include applying one or more valid program voltages to the cells to be programmed, followed by applying one or more verify voltages to those cells to determine which cells have finished programming (subsequent programming passes generally do not apply valid program and / or verify voltages to cells that have finished programming). Applying a valid program voltage to a cell can include changing the voltage difference between the cell's control gate and channel to change the cell's threshold voltage. Thus, the voltage of the word line (coupled to the target cell's control gate) and / or the cell's channel can be set to effectively apply a valid program voltage. Because a program voltage generally refers to the voltage applied to a word line, an effective program voltage can be the voltage difference between the cell's control gate and channel (which can be synonymous with the program voltage if the channel is held at 0V).

[0056] 4A is a perspective view of a portion of an exemplary three-dimensional (3D) memory cell array structure 400, according to some embodiments. The memory cell array structure 400 includes a substrate 430, an insulating film 431 on the substrate 430, a layer of bottom select gates (BSGs) 432 on the insulating film 431, and multiple layers of control gates 433, also referred to as "word lines" (WLs), stacked on the BSGs 432 to form an alternating film stack 435 of conductive and dielectric layers. The dielectric layers adjacent to the layer of control gates are not shown in FIG. 4 for clarity.

[0057] The control gates of each layer are separated by slit structures 416-1, 416-2 that penetrate the film stack 435. The memory cell array structure 400 also includes a layer of top select gates (TSGs) 434 on top of the stack of control gates 433. The stack of TSGs 434, control gates 4133, and BSGs 432 is also referred to as a "gate electrode." The memory cell array structure 400 further includes memory strings 412 and doped source line regions 444 in the portion of the substrate 430 between adjacent BSGs 432. Each memory string 412 includes a channel hole 436 that extends through the insulating film 431 and the film stack 435 of alternating conductive and dielectric layers. The memory string 412 also includes a memory film 437 on the sidewall of the channel hole 436, a channel layer 438 covering the memory film 437, and a core fill film 439 surrounded by the channel layer 438. A memory cell 440 can be formed at the intersection of the control gate 433 and the memory string 412. A portion of the channel layer 438 below the control gate 433 is also referred to as the channel of the memory cell 440. The memory cell array structure 400 further includes a plurality of bit lines (BLs) 441 on the TSG 434 connected to the memory strings 412. The memory cell array structure 400 also includes a plurality of metal interconnect lines 443 connected to the gate electrodes via a plurality of contact structures 414. The edges of the film stack 435 can be configured in a stepped manner and electrically connected to each layer of the gate electrodes.

[0058] For illustrative purposes, FIG. 4A shows three layers of control gates 433-1, 433-2, and 433-3, along with one layer of TSG 434 and one layer of BSG 432. In this example, each memory string 412 may include three memory cells 440-1, 440-2, and 440-3, corresponding to the control gates 433-1, 433-2, and 433-3, respectively. The number of control gates and the number of memory cells may be greater than three to increase storage capacity. The memory cell array structure 400 may also include other structures, such as TSG cut structures, common source contacts, and dummy memory strings. These structures are not shown in FIG. 4A for simplicity.

[0059] FIG. 4B is a schematic diagram of an exemplary 3D memory device 450 in a plan view according to some embodiments of the present disclosure. The 3D memory device 450 can include multiple channel structure regions, such as memory planes, memory blocks, memory fingers, etc., and one or more through array contact (TAC) structures can be formed between two adjacent channel structure regions. In some embodiments as shown in FIG. 4B, the 3D memory device 450 can include four or more memory planes 460, each of which can include multiple memory blocks 465. It should be noted that the arrangement of the memory planes 460 and the arrangement of the memory blocks 465 in each memory plane 460 of the 3D memory device 450 illustrated in FIG. 4B is used only as an example and is not intended to limit the scope of the present disclosure.

[0060] The TAC structure may include one or more bit line (BL) TAC regions 471 sandwiched between two adjacent memory blocks 465 in the bit line direction (labeled "BL" in the figure) of the three-dimensional memory device and extending along the word line direction (labeled "WL" in the figure) of the three-dimensional memory device, one or more word line (BL) TAC regions 473 sandwiched between two adjacent memory blocks 465 in the word line direction (WL) and extending along the word line direction (BL), and one or more staircase structure (SS) TAC regions 480 located at the edge of each memory plane 460.

[0061] In some embodiments, the 3D memory device 450 can include a plurality of contact pads 490 arranged in a row on the edge of the 3D memory device 450. The interconnect contacts can be used to electrically interconnect the 3D memory device 450 to any suitable device and / or interface to provide driving power, receive control signals, transmit response signals, etc.

[0062] Referring to FIG. 5, a schematic block diagram of an exemplary circuit for NAND reference voltage application is illustrated, according to some embodiments of the present disclosure. In NAND memory devices, to improve signal integrity at high speeds and save IO power, the termination style of the date line DQ[X] can be changed from center tapped termination (CTT), also known as series-stud terminated logic (SSTL), to pseudo open drain (POD). In some embodiments, a reference voltage Vrefq can be used to determine whether the signal on the date line DQ[X] is 0 or 1. Such reference voltage Vrefq can be set using a mode register and needs to be correctly set by the memory controller during a calibration phase of the reference voltage DQ.

[0063] In some embodiments, the NAND reference voltage DQ calibration can use two reference voltages: Vrefq1 for array data and feature parameter input, and Vrefq2 for command and address code input. As shown in FIG. 5, a reference voltage generator 510 can generate a first reference voltage Vrefq1 and a second reference voltage Vrefq2 and transmit the first and second reference voltages Vrefq1 and Vrefq2 to a first voltage comparator 522 and a second voltage comparator 524, respectively. Also, a signal on the date line DQ[X] is input to the first voltage comparator 522 and the second voltage comparator 524, respectively.

[0064] The output of the first voltage comparator 522 may be sent to a data path pipeline 531 and a parameter interface 533. The output of the second voltage comparator 524 may be sent to a command and address interface 535. The array data output from the data path pipeline 531 may be written to a memory cell array 542. The data parameter data output from the parameter interface 533 and the command and address data output from the command and address interface 535 may be sent to control logic 544 to generate feature parameters and command and address codes.

[0065] Referring to FIG. 6, a schematic flowchart of an exemplary method 600 for IO reference voltage training of a NAND memory device according to some aspects of the present disclosure is illustrated. In some aspects, the method 600 can adjust the IO reference voltage by using a training process and perform write and read operations to verify the data eye window. Note that in the method 600, the reference voltage Vrefq can be used to represent any one of the first reference voltage Vrefq1 and the second reference voltage Vrefq2 described above. In the following examples, the reference voltage Vrefq is used to represent the first reference voltage Vrefq1.

[0066] 6, method 600 may begin with operation 610, where a new reference voltage value may be set (e.g., set feature 23h). In some aspects, operation 610 may occur before an on-die termination (ODT) disable operation (e.g., command 18h) and after an ODT enable operation (e.g., command 1h).

[0067] Some training methods require disabling the ODT function to set the first reference voltage Vrefq1 to a non-OTD state before setting a new reference voltage value, ensuring that the parameter data for Vrefq1 is entered correctly in subsequent processing. Furthermore, after changing the reference voltage value, a separate operation is required to enable the ODT function. This conventional training method requires an additional command to set Vrefq1 to a certain level and to change the system exit setting from ODT-on to ODT-off. For non-OTD cases, when the first die performs Vrefq training and the second die provides ODT to the first die, the memory and controller design can become complicated.

[0068] In the learning method 600 of the present disclosure, it is possible to omit the ODT disable and enable operations before and after changing the reference voltage in the learning flow, thereby saving not only the time required for the ODT disable command and the ODT enable command, but also the waiting time from the ODT disable command to the set feature command, the waiting time from the set feature command to the ODT enable command, and the waiting time from the ODT enable command to the subsequent light training operation.

[0069] 6, method 600 may proceed to operations 620 and 630 to perform the write data operation (e.g., command 63h) and read data operation (e.g., command 64h) of the write training process. Note that operations 620 and 630 may be performed directly following operation 610 without executing an ODT enable command.

[0070] In some embodiments, when a write training process is performed on the sending side, the controller can issue a LUN address following command 63h. After issuing the LUN address, the host can input a data pattern and check the NAND output in the following order to confirm whether the input was successful. The data size of the write DQ can be predefined by the NAND. The host can recognize the data size using a get feature command (e.g., Feature Address=20h, B2) and input / output data according to the size. After writing data to the NAND with a write training-data-in command (e.g., command 63h), the host can read the data using the LUN address with the subsequent write training-data-out command (e.g., command 64h).

[0071] As shown in FIG. 6 , method 600 may next proceed to operation 640 where a determination is made whether the training process is performed. In some aspects, the data read back at operation 630 may be compared to “expected” data to see if further training is required. If the data read back at operation 630 substantially matches the “expected” data, it may be determined that further training is not required. In some aspects, if fewer than predefined data bytes are written, the unwritten registers will have undefined data when read back. If more than the predefined data bytes are read, the data will also be undefined and invalid. If the determination at operation 640 is negative (“N” at 640), method 600 may return to operation 610 to begin another training loop.

[0072] If the determination at operation 640 is affirmative (“Y” at 640), method 600 may proceed to operation 650, where the new reference voltage value may be set as the optimized reference voltage value (e.g., set feature 23h). After multiple loops of changing the reference voltage value and light training, the controller may ascertain the optimal reference voltage level and configure it through the set feature parameters.

[0073] Thus, method 600 can execute algorithms to align the clock and data strobes in the NAND memory device, execute algorithms to know the correct read and write delays to the NAND memory device, center the data eye for reads, and report errors when signal integrity is poor and data cannot be reliably written or read.

[0074] The above operations of the flow diagram of Figure 6 may be performed or implemented in any order or sequence, not limited to the order and sequence illustrated in the figure. Also, some of the operations of the flow diagram of Figure 6 may be performed substantially simultaneously or in parallel, where appropriate, to reduce latency and processing time. Furthermore, it should be noted that Figure 6 is provided by way of example only. At least one of the operations shown in Figure 6 may be performed in a different order than depicted, may be performed simultaneously, or may be omitted entirely.

[0075] 7, a schematic timing diagram 700 of example operations of the method 600 for training the first reference voltage Vrefq1 is illustrated, in accordance with some aspects of the present disclosure. As shown in FIG. 7, during a first operation 710 of performing a set feature command to set the Vrefq1 value: <cmd> <addr>At time t71 immediately after the cycle, a default value can be set for Vrefq1 to change the previous value of the first reference voltage. During the period from time t72 to time t73, the default value of Vrefq1 can be set to<Parameter data> After operation 710, in a wait operation 720, the first reference voltage Vrefq1 can be set to a new value. In some embodiments, the wait operation 720 can last for any suitable time, such as any value between about 0.1 μs and about 2 μs (e.g., about 1 μs), until the first reference voltage Vrefq1 stabilizes at the new value. After the wait operation 720, a light training operation 730 can be performed. During the period from time t74 to time t75, the light training <data>During the cycle, Vrefq1 with a new value for write training can be used. Note that the value of the second reference voltage Vrefq2 can maintain the same level during the whole process.

[0076] Referring to FIG. 8A, a schematic block diagram 800 of an example peripheral circuit for IO reference voltage training of a NAND memory device is illustrated, in accordance with some aspects of the present disclosure.

[0077] As shown in FIG. 8A, the logic control circuit 810 controls a first trimming voltage (e.g., Trim1 ) to control the output voltage (e.g., first reference voltage generation signal Vregq1_gen) of the first main voltage source 822. <n:0>) can be generated and transmitted to the first main voltage source 822. The logic control circuit 810 can generate and transmit a second trimming voltage (e.g., Trim2) to control the output voltage (e.g., first reference voltage boost signal Vrefq1_bst) voltage booster 826. <n:0>), and a booster enable control signal (e.g., En_bst). The reference voltage pad 830 can generate a reference voltage extension signal (e.g., Vrefq_ext). Based on the received first reference voltage generation signal Vregq1_gen, first reference voltage boost signal Vrefq1_bst, reference voltage extension signal Vrefq_ext, and the control signal directly sent from the logic control circuit 810, the multiplexer 840 can output the first reference voltage Vrefq1. Furthermore, the logic control circuit 810 can output a third trimming voltage (e.g., Trim3) to the second main voltage source 824 to generate the second reference voltage Vrefq2. <n:0>) can be generated and transmitted. Both the first reference voltage Vrefq1 and the second reference voltage Vrefq2 can be transmitted to the IO circuit 850 for use.

[0078] 8B, a schematic timing diagram 899 of exemplary operations of the method 600 for training the first reference voltage Vrefq1 is illustrated according to some aspects of the present disclosure based on FIG. 8A. Comparing the schematic timing diagram 899 with the schematic timing diagram 700 described above, the booster enable control signal En_bst can be used to control the first reference voltage boost signal Vrefq1_bst to speed up the stabilization of the new voltage level of the first reference voltage Vrefq1 in the training process.

[0079] As shown in FIG. 8B, during a first operation 891 of performing a set feature command to set the Vrefq1 value: <cmd> <addr>Immediately after the cycle, at time t81, a default value may be set for Vrefq1 to replace the previous value of the first reference voltage. The booster enable control signal En_bst may be switched from low (e.g., a "0" level) to high (e.g., a "1" level) at time t81. Once the first reference voltage Vrefq1 has been pumped up and is maintained stable at the default value, the booster enable control signal En_bst may be switched from high to low at time t82. In some aspects, the duration of the first high-level booster enable control signal En_bst from time t81 to time t82 may be in the range of about 20 ns to about 100 ns, such as, for example, about 50 ns.

[0080] After the operation, the first reference voltage Vrefq1 may be set to a new value in a wait operation 892.<Parameter data> At time t83 immediately after the cycle, a new value for write training may be set to Vrefq1, replacing the default value of the first reference voltage. The booster enable control signal En_bst may be switched from low (e.g., level "0") to high (e.g., level "1") at time t83. Once the first reference voltage Vrefq1 has been pumped down and is maintained stable at the new value, the booster enable control signal En_bst may be switched from high to low at time t84. In some aspects, the period of the second high-level booster control signal En_bst from time t83 to time t84 may be in the range of about 10 ns to about 800 ns, e.g., about 600 ns.

[0081] Referring to FIG. 9A, a schematic block diagram 900 of an example peripheral circuit for IO reference voltage training of a NAND memory device is illustrated, in accordance with some other aspects of the present disclosure.

[0082] As shown in FIG. 9A, the logic control circuit 910 controls a first trimming voltage (e.g., Trim1 <n:0>) and send it to the first main voltage source 922 and the voltage booster 926 simultaneously. The logic control circuit 910 can further generate a booster enable control signal (e.g., En_bst) and send it to the voltage booster 926. The logic control circuit 910 can further generate a start enable control signal (e.g., En_int) and send it to the reference voltage start circuit 928. The multiplexer 940 can output the first reference voltage Vrefq1 based on the first reference voltage generation signal Vrefq1_gen output from the first main voltage source 922, the first reference voltage boost signal Vrefq1_bst output from the voltage booster 926, the first reference voltage start signal Vrefq1_int output from the reference voltage start circuit 928, the reference voltage extension signal Vrefq_ext output from the reference voltage pad 930, and the control signal sent directly from the logic control circuit 910. Furthermore, the logic control circuit 910 supplies a third trimming voltage (e.g., Trim3) to the second main voltage source 924 for generating the second reference voltage Vrefq2. <n:0>) can be generated and transmitted. Both the first reference voltage Vrefq1 and the second reference voltage Vrefq2 can be transmitted to the IO circuit 950 for use.

[0083] 9B, a schematic timing diagram 999 of exemplary operations of the method 600 for training the first reference voltage Vrefq1 is illustrated, in accordance with certain other aspects of the present disclosure. Comparing the schematic timing diagram 999 with the schematic timing diagrams 700 and 899 described above, a start enable control signal En_int can be used to control the reference voltage start circuit 928 to initiate voltage level changes of the first reference voltage Vrefq1 during the training process.

[0084] As shown in FIG. 9, during a first operation 991 of executing a set function command to set the Vrefq1 value: <cmd> <addr>Immediately after the cycle, at time t91, a default value may be set to Vrefq1 to replace the previous value of the first reference voltage. The start enable control signal En_int may be switched from low (e.g., a “0” level) to high (e.g., a “1” level) at time t91. Once the first reference voltage Vrefq1 has been pumped up and is maintained stable at the default value, the start enable control signal En_int may be switched from high to low at time t92. In some aspects, the duration of the start enable control signal En_int from time t91 to time t92 may be in a range from about 20 ns to about 100 ns, e.g., about 50 ns.

[0085] After operation 991, the first reference voltage Vrefq1 may be set to a new value in a wait operation 992.<Parameter data> At time t93 immediately after the cycle, a new value for write training may be set to Vrefq1, replacing the default value of the first reference voltage. The booster enable control signal En_bst may be switched from low (e.g., "0" level) to high (e.g., "1" level) at time t93. Once the first reference voltage Vrefq1 has been pumped down and is maintained stable at the new value, the booster enable control signal En_bst may be switched from high to low at time t94. In some aspects, the duration of the high-level booster enable control signal En_bst from time t93 to time t94 may be in a range from approximately 10 ns to approximately 800 ns, e.g., approximately 600 ns.

[0086] 10A, a schematic circuit diagram of an exemplary resistor divider 1000A is shown, according to some other aspects of the present disclosure. As shown, multiple resistors may be connected in series. Multiple interconnection points between pairs of adjacent resistors may be connected to multiple input lines of a multiplexer 1040. The received trimming voltage Trim <n:0>The multiplexer 1040 can output the reference voltage Vrefq_out based on Vrefq_out. Note that the disclosed resistor divider 1000A can be used in any one of the first main voltage source, the second main voltage source, the voltage booster, and the reference voltage starting circuit described above.

[0087] 10B, a schematic circuit diagram 1000B of an exemplary combination of a reference voltage generator and an analog buffer according to some other aspects of the present disclosure is illustrated. As shown, a reference voltage generator 1070 can generate a reference voltage signal Vref as a first input of an analog buffer 1080. An output Vrefq_out of the analog buffer 1080 can be transmitted back to a second input of the analog buffer 1080. It should be noted that the disclosed circuit 1000B can be used for any one of the first main voltage source, the second main voltage source, the voltage booster, and the reference voltage starting circuit described above.

[0088] Various disclosed aspects can be implemented using one or more computer systems, such as, for example, computer system 1100 shown in FIG. 11 . Computer system 1100 can be any known computer capable of performing the functions described herein, such as memory system 102 of FIG. 1 . Computer system 1100 includes one or more processors (also referred to as central processing units, or CPUs), such as processor 1104. Processor 1104 is connected to a communications infrastructure 1106 (e.g., a bus). Computer system 1100 also includes user input / output devices 1103, such as a monitor, keyboard, pointing device, etc., and communicates with communications infrastructure 1106 via user input / output interface 1102. Computer system 1100 also includes main or primary memory 1108, such as random access memory (RAM). Main memory 1108 can include one or more levels of cache. Main memory 1108 stores control logic (e.g., computer software) and / or data therein.

[0089] Computer system 1100 may also include one or more secondary storage devices or memories 1110. The secondary memory 1110 may include, for example, a hard disk drive 1112 and / or a removable storage device or drive 1114. The removable storage drive 1114 may be a floppy disk drive, a magnetic tape drive, a compact disk drive, an optical storage device, a tape backup device, and / or any other storage device / drive.

[0090] The removable storage drive 1114 can interface with a removable storage unit 1118. The removable storage unit 1118 includes a computer-usable or readable storage device on which computer software (control logic) and / or data is stored. The removable storage unit 1118 can be a floppy disk, magnetic tape, compact disk, DVD, optical storage disk, and / or any other computer data storage device. The removable storage drive 1114 reads from and / or writes to the removable storage unit 1118 in a well-known manner.

[0091] In some embodiments, secondary memory 1110 may include other means, tools, or approaches for allowing computer programs and / or other instructions and / or data to be accessed by computer system 1100. Such means, tools, or approaches may include, for example, removable storage unit 1222 and interface 1220. Examples of removable storage unit 1222 and interface 1220 may include a program cartridge and cartridge interface (such as found in a video game device), a removable memory chip (such as an EPROM or PROM) and associated socket, a memory stick and USB port, a memory card and associated memory card slot, and / or any other removable storage unit and associated interface.

[0092] Computer system 1100 may further include a communications or network interface 1224. Communications interface 1224 enables computer system 1100 to communicate and interact with any combination of remote devices, remote networks, remote entities, etc. (individually and collectively referred to by reference numeral 1228). For example, communications interface 1224 may enable computer system 1100 to communicate with remote devices 1228 via communications path 1226, which may be wired and / or wireless and may include any combination of a LAN, a WAN, the Internet, etc. Control logic and / or data may be transmitted to and from computer system 1100 via communications path 1226.

[0093] The operations in the above-described embodiments may be implemented in a wide variety of configurations and arrangements. Thus, some or all of the operations in the above-described embodiments may be implemented in hardware, software, or both. In some embodiments, a tangible, non-transitory device or article of manufacture includes, but is not limited to, a tangible, non-transitory, available or readable medium having control logic (software) stored thereon, also referred to herein as a computer program product or program storage device. This includes, but is not limited to, any tangible article of manufacture embodying the computer system 1100, the main memory 1108, the secondary memory 1110, and the removable storage units 1118, 1222, as well as any combination thereof. Such control logic, when executed by one or more data processing devices (e.g., the computer system 1100), causes such data processing devices to operate as described herein.

[0094] Based on the teachings contained herein, one skilled in the art will know how to make and use embodiments of the present disclosure using data processing apparatus, computer systems, and / or computer architectures other than those shown in Figure 11. In particular, embodiments may be operated by software, hardware, and / or operating system implementations for input / output voltage training of three-dimensional (3D) memory devices.

[0095] Thus, the disclosed system, method, and medium during input / output voltage training of a three-dimensional (3D) memory device can set the reference voltage value without using an ODT disable command or an ODT enable command, thereby reducing operation time, avoiding complex designs in the case of non-targeted ODT, and avoiding parameter data input errors.

[0096] One aspect of the present disclosure provides a method for input / output voltage training of a three-dimensional (3D) memory device, which may include the following operations: (1) setting a reference voltage value in an on-die termination (ODT) enabled state; (2) controlling the 3D memory device to perform a write training process; (3) determining whether a further write training process is required; (4) repeating operations (1), (2), and (3) in response to determining that a further write training process is required; and (5) setting the reference voltage value as an optimized reference voltage value in response to determining that a further write training process is not required.

[0097] It is noted that the above operations (1)-(5) may be performed or conducted in any order or sequence, not limited to the order and sequence following the serial numbers used to distinguish the various operations. Also, some of operations (1)-(5) may be performed or conducted substantially simultaneously or in parallel, as needed, to reduce waiting and processing times. That is, one or more of operations (1)-(5) may be performed in an order other than that presented, may be performed simultaneously, or may be omitted entirely.

[0098] In some embodiments, setting the reference voltage value occurs regardless of whether the on-die termination (ODT) is enabled or disabled.

[0099] In some embodiments, setting the reference voltage value includes controlling a main voltage source to generate the reference voltage generation signal by using the first trimming signal.

[0100] In some embodiments, setting the reference voltage value further includes controlling a voltage booster to generate the reference voltage signal by using the second trimming signal and the booster enable control signal.

[0101] In some embodiments, setting the reference voltage value further includes generating the reference voltage value based on at least the reference voltage generation signal and the reference voltage boost signal.

[0102] In some embodiments, setting the reference voltage value further includes changing the reference voltage value from a previous value to a default value during a first period of a first high level of the booster enable control signal, and changing the reference voltage from the default value to a new value during a second period of a second high level of the booster enable control signal.

[0103] In some embodiments, setting the reference voltage value further includes controlling a voltage booster to generate a reference voltage boost signal by using the first trimming signal and the booster enable control signal, and controlling a reference voltage start circuit to generate a reference voltage start signal by using the first trimming signal and the start enable control signal.

[0104] In some embodiments, setting the reference voltage value further includes raising the reference voltage value based on at least a reference voltage generation signal, a reference voltage boost signal, and a reference voltage start signal.

[0105] In some embodiments, setting the reference voltage value further includes changing the reference voltage value from a previous value to a default value during a first period of a high level of the start enable control signal, and changing the reference voltage from a previous value to a new value during a first period of a high level of the booster enable control signal.

[0106] In some embodiments, performing the write training process includes performing a data write operation and a data read operation, and determining whether further write training processes are required based on at least a result of the data read operation.

[0107] Another aspect of the present disclosure provides a three-dimensional (3D) memory device including a memory cell array and peripheral circuits coupled to the memory cell array, including a control circuit configured to: (1) set a reference voltage value in an on-die termination (ODT) enabled state; (2) control the memory cell array to perform a write training process; (3) determine whether a further write training process is required; (4) repeat operations (1), (2), and (3) in response to determining that a further write training process is required; and (5) set the reference voltage value as an optimized reference voltage value in response to determining that a further write training process is not required.

[0108] In some embodiments, the logic control circuit is further configured to set the reference voltage value regardless of whether the on-die termination (ODT) is enabled or disabled.

[0109] In some embodiments, the peripheral circuitry further comprises a main voltage source configured to receive the first trimming signal from the logic control circuit and to generate the reference voltage generation signal.

[0110] In some embodiments, the peripheral circuitry further comprises a voltage booster configured to receive the second trimming signal and the booster enable control signal from the logic control circuitry and to generate the reference voltage boost signal.

[0111] In some embodiments, the peripheral circuitry further comprises a multiplexer configured to generate the reference voltage value based on at least the reference voltage generation signal and the booster enable control signal.

[0112] In some embodiments, the multiplexer is configured to change the reference voltage value from a previous value to a default value during a first period of a first high level of the booster enable control signal, and to change the reference voltage from the default value to a new value during a second period of a second high level of the booster enable control signal.

[0113] In some embodiments, the peripheral circuitry further includes a voltage booster configured to receive the first trimming signal and the booster enable control signal from the logic control circuitry and generate a booster enable control signal, and a reference voltage start circuit configured to receive the first trimming signal and the start enable control signal from the logic control circuitry and generate a reference voltage start signal.

[0114] In some embodiments, the peripheral circuitry further comprises a multiplexer configured to generate a reference voltage value based on at least the reference voltage generation signal, the booster enable control signal, and the reference voltage start signal.

[0115] In some embodiments, the multiplexer is further configured to change the reference voltage from a previous value to a default value during a first period when the start enable control signal is at a high level, and to change the reference voltage from a previous value to the default value during a first period when the booster enable control signal is at a high level.

[0116] In some embodiments, the control circuitry is further configured to control the memory cell array to perform data write operations and data read operations, and to determine whether further write training processes are required based on at least the results of the data read operations.

[0117] Another aspect of the present disclosure provides a memory system comprising the 3D memory device described above and a memory controller configured to control the 3D memory device.

[0118] The foregoing description of specific embodiments makes fully clear the broad nature of the present disclosure such that others may readily modify and / or adapt such specific embodiments to various uses by applying knowledge within the skill of the art without undue experimentation and without departing from the general concept of the present disclosure. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the present disclosure, based on the present disclosure and guidance provided herein. It should be understood that certain terms of art or technical terminology used herein are for the convenience of description and not of limitation, and that certain terms of art or technical terminology used herein are to be interpreted by those skilled in the art in light of the present disclosure and guidance.

[0119] Aspects of the present disclosure have been described above with the aid of functional building blocks illustrating implementation forms of specific functions and their relationships. The boundaries of such functional building blocks have been arbitrarily defined herein for the convenience of description. Alternative boundaries may be defined as long as the specific functions and their relationships are appropriately achieved.

[0120] The Summary and Abstract section may set forth one or more exemplary aspects of the disclosure that are not all encompassing as the inventors have embraced the possibilities thereof, and therefore is not intended to limit the scope of the disclosure and the appended claims in any way.

[0121] The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary aspects, but should be defined only in accordance with the following claims and their equivalents. [Explanation of symbols]

[0122] 104 Memory Devices 106 Memory Controller 108 Host 202 Memory Cell Array 204 page buffer 206 Column decoder / BL driver 208 Row decoder / WL driver 210 Voltage Generator 212 Control Logic 214 registers 302 Peripheral Circuit 306 memory cells 308 NAND memory string array 313 DSG line 314 Source Line 315 SSG Line 316 bit lines 318 Word Line 320 pages 522 first voltage comparator 524 Second Voltage Comparator 533 Parameter Interface 535 Command-Address Interface 542 Memory Cell Array 544 Control Logic 1104 processor 1102 User Input / Output Interface 1103 User Input / Output Devices 1106 Communications Infrastructure 1108 Main Memory 1110 Secondary Memory 1112 hard disk drive 1114 Removable Storage Drive 1118 Removable Storage Unit 1120 Interface 1122 Removable Storage Unit 1124 Communication Interface 1126 Communication Path 1128 Remote Devices, Networks, and Entities < / addr> < / cmd> < / addr> < / cmd> < / data> < / addr> < / cmd>

Claims

1. a memory cell array; a peripheral circuit coupled to the memory cell array, the peripheral circuit comprising: (1) Setting the reference voltage value (2) controlling the memory cell array to perform a write training process, the write training process including performing a data write operation and a data read operation; (3) determining whether further light training processes are required; and (4) repeating operations (1), (2), and (3) in response to determining that a further light training process is required; and (5) a peripheral circuit including a control circuit configured to set the reference voltage value as an optimized reference voltage value in response to determining that the further light training process is not required; and A three-dimensional (3D) memory device comprising:

2. 10. The device of claim 1, wherein the peripheral circuitry is further configured to set the reference voltage value regardless of whether an on-die termination (ODT) is enabled or disabled.

3. The peripheral circuit further comprises: The device of claim 1 , configured to receive a setting characteristic signal and configured to set a reference voltage value using the setting characteristic signal.

4. The peripheral circuit further comprises: a primary voltage source configured to receive a first trimming signal from the peripheral circuit and generate a reference voltage generation signal; a voltage booster configured to receive a second trimming signal and a booster enable control signal from the peripheral circuit and generate a reference voltage boost signal; a multiplexer configured to generate the reference voltage value based on at least the reference voltage generation signal and the booster enable control signal.

10. The device of claim 1.

5. The multiplexer changing a reference voltage from a previous value to a default value during a first period of a first high level of the booster enable control signal; and changing the reference voltage from the default value to a new value for write training during a second period of a second high level of the booster enable control signal.

6. The peripheral circuit further comprises: a voltage booster configured to receive the first trimming signal and a booster enable control signal from the peripheral circuit and generate a booster enable control signal; a reference voltage start circuit configured to receive the first trimming signal and a start enable control signal from the peripheral circuitry and to generate a reference voltage start signal.

7. The peripheral circuit further comprises: The device of claim 6 , comprising a multiplexer configured to generate the reference voltage value based on at least the reference voltage generation signal, the booster enable control signal, and the reference voltage start signal.

8. The multiplexer further comprises: changing a reference voltage from a previous value to a default value during a first period of time when the start enable control signal is at a high level; 8. The device of claim 7, configured to change the reference voltage from a previous value to a default value during a first period of a high level of the booster enable control signal.

9. The peripheral circuit further comprises: receiving a first write training command, wherein performing the write training process includes performing a data write operation; receiving a second write training command, wherein performing the write training process includes performing a data read operation; and determining whether the further write training process is required based on at least a result of the data read operation.

10. 10. A memory system comprising: the 3D memory device of claim 1; and a memory controller configured to control the 3D memory device.

11. the memory controller is configured to send a setting feature signal, a first write training command, and a second write training command to the 3D memory device; the 3D memory device receiving the setting characteristic signal and setting a reference voltage value by using the setting characteristic signal; receiving the first write training command, wherein performing the write training process includes performing a data write operation; receiving the second write training command, wherein performing the write training process includes performing a data read operation; The memory system of claim 10 configured to:

12. 1. A method for input / output voltage training of a three-dimensional (3D) memory device, comprising: (6) Setting the reference voltage value (7) controlling the memory cell array to perform a write training process, the write training process including performing a data write operation and a data read operation; (8) determining whether further light training processes are required; and (9) repeating operations (6), (7), and (8) in response to determining that a further light training process is required; and (10) in response to determining that the further light training process is not required, setting the reference voltage value as an optimized reference voltage value. method.

13. 13. The method of claim 12, further comprising setting the reference voltage value regardless of whether an on-die termination (ODT) is enabled or disabled.

14. The method of claim 12 , further comprising receiving a setting characteristic signal and setting a reference voltage value using the setting characteristic signal.

15. receiving a first trimming signal from a peripheral circuit and generating a reference voltage generating signal; receiving a second trimming signal and a booster enable control signal from the peripheral circuit and generating a reference voltage boost signal; generating the reference voltage value based on at least the reference voltage generation signal and the booster enable control signal; 13. The method of claim 12, further comprising:

16. changing a reference voltage from a previous value to a default value during a first period of a first high level of the booster enable control signal; changing the reference voltage from the default value to a new value for write training during a second period of a second high level of the booster enable control signal; 16. The method of claim 15, further comprising:

17. receiving the first trimming signal and a booster enable control signal from the peripheral circuit and generating a booster enable control signal; receiving the first trimming signal and a start enable control signal from the peripheral circuit and generating a reference voltage start signal; 16. The method of claim 15, further comprising:

18. generating the reference voltage value based on at least the reference voltage generation signal, the booster enable control signal, and the reference voltage start signal.

18. The method of claim 17.

19. changing a reference voltage from a previous value to a default value during a first period of time when the start enable control signal is at a high level; changing the reference voltage from a previous value to a default value during a first period when the booster enable control signal is at a high level; 20. The method of claim 18, further comprising:

20. receiving a first write training command, wherein performing the write training process includes performing a data write operation; receiving a second write training command, wherein performing the write training process includes performing a data read operation; determining whether a further write training process is required based on at least a result of the data read operation; 13. The method of claim 12, further comprising:

Images