Semiconductor Devices

Abstract

To provide a semiconductor device with a small variation in transistor characteristics.SOLUTION: There is provided a semiconductor device including a transistor 200. The transistor includes: an oxide semiconductor 230; a first conductor 242a and a second conductor 242b over the oxide semiconductor; a first insulator 271a in contact with a top surface of the first conductor; a second insulator 271b in contact with a top surface of the second conductor; a third insulator 275 which is positioned over the first insulator and the second insulator and in which an opening overlapping with a region between the first conductor and the second conductor is formed; a fourth insulator 250 positioned over the oxide semiconductor and in the region between the first conductor and the second conductor; and a third conductor 260 over the fourth insulator. Each of the first insulator and the second insulator is a metal oxide including an amorphous structure.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] 1. Field of the Invention

[0003] One embodiment of the present invention relates to a transistor, a semiconductor device, and an electronic device. Another embodiment of the present invention relates to a method for manufacturing a semiconductor device. Another embodiment of the present invention relates to a semiconductor wafer and a module.

[0002] In this specification and the like, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics. Semiconductor elements such as transistors, semiconductor circuits, arithmetic devices, and memory devices are all embodiments of semiconductor devices. Display devices (liquid crystal display devices, light-emitting display devices, etc.), projection devices, lighting devices, electro-optical devices, power storage devices, memory devices, semiconductor circuits, imaging devices, electronic devices, and the like may be considered to include semiconductor devices.

[0003] Note that one aspect of the present invention is not limited to the above technical fields. One aspect of the invention disclosed in this specification relates to an object, a method, or a manufacturing method. Alternatively, one aspect of the present invention relates to a process, a machine, a manufacture, or a composition of matter. [Background technology]

[0004] In recent years, the development of semiconductor devices has progressed significantly, particularly in the development of LSIs (Large Scale Integrated Circuits), CPUs (Central Processing Units), and memories. A CPU is a collection of semiconductor elements that have semiconductor integrated circuits (at least transistors and memories) separated from a semiconductor wafer and on which electrodes serving as connection terminals are formed.

[0005] Semiconductor circuits (IC chips) such as LSIs, CPUs, and memories are mounted on circuit boards, such as printed wiring boards, and are used as components in a variety of electronic devices.

[0006] Furthermore, technology for constructing transistors using semiconductor thin films formed on substrates with insulating surfaces has been attracting attention. Such transistors are widely used in electronic devices such as integrated circuits (ICs) and image display devices (also simply referred to as display devices). Silicon-based semiconductor materials are widely known as semiconductor thin films applicable to transistors, but oxide semiconductors have also attracted attention as other materials.

[0007] Furthermore, transistors using oxide semiconductors are known to have extremely low leakage current in a non-conducting state. For example, a low-power CPU utilizing the low leakage current characteristic of transistors using oxide semiconductors has been disclosed (see Patent Document 1). Also, for example, a memory device capable of retaining stored data for a long period of time utilizing the low leakage current characteristic of transistors using oxide semiconductors has been disclosed (see Patent Document 2).

[0008] Furthermore, in recent years, with the trend toward smaller and lighter electronic devices, there has been an increasing demand for higher density integrated circuits, and there is also a demand for improved productivity in semiconductor devices including integrated circuits. [Prior art documents] [Patent documents]

[0009] [Patent Document 1] Japanese Patent Application Laid-Open No. 2012-257187 [Patent Document 2] Japanese Patent Application Laid-Open No. 2011-151383 Summary of the Invention [Problem to be solved by the invention]

[0010] An object of one embodiment of the present invention is to provide a semiconductor device with little variation in transistor characteristics. Another object of one embodiment of the present invention is to provide a semiconductor device with high reliability. Another object of one embodiment of the present invention is to provide a semiconductor device with good electrical characteristics. Another object of one embodiment of the present invention is to provide a semiconductor device with high on-state current. Another object of one embodiment of the present invention is to provide a semiconductor device that can be miniaturized or highly integrated. Another object of one embodiment of the present invention is to provide a semiconductor device with low power consumption.

[0011] Note that the description of these problems does not preclude the existence of other problems. Note that one embodiment of the present invention does not necessarily solve all of these problems. Note that problems other than these will become apparent from the description of the specification, drawings, claims, etc., and it is possible to extract other problems from the description of the specification, drawings, claims, etc. [Means for solving the problem]

[0012] One embodiment of the present invention is a semiconductor device including an oxide semiconductor, a first conductor and a second conductor on the oxide semiconductor, a first insulator in contact with a top surface of the first conductor, a second insulator in contact with a top surface of the second conductor, a third insulator disposed on the first insulator and the second insulator and having an opening overlapping a region between the first conductor and the second conductor, a fourth insulator disposed on the oxide semiconductor and in a region between the first conductor and the second conductor, and the third conductor on the fourth insulator, wherein the first insulator and the second insulator are metal oxides having an amorphous structure.

[0013] One embodiment of the present invention is a semiconductor device including an oxide semiconductor, a first conductor and a second conductor over the oxide semiconductor, a first insulator covering the first conductor and the second conductor and having an opening overlapping a region between the first conductor and the second conductor, a second insulator disposed on the first insulator and having an opening overlapping a region between the first conductor and the second conductor, a third insulator disposed on the oxide semiconductor and in a region between the first conductor and the second conductor, and a third conductor over the third insulator, wherein the first insulator is a metal oxide having an amorphous structure.

[0014] One embodiment of the present invention is a semiconductor device including an oxide semiconductor, a first conductor and a second conductor over the oxide semiconductor, a first insulator in contact with a top surface of the first conductor, a second insulator in contact with a top surface of the second conductor, a third insulator covering the first insulator and the second insulator and having an opening overlapping with a region between the first conductor and the second conductor, a fourth insulator disposed on the third insulator and having an opening overlapping with a region between the first conductor and the second conductor, a fifth insulator disposed on the oxide semiconductor and in a region between the first conductor and the second conductor, and the third conductor over the fifth insulator, wherein the first insulator, the second insulator, and the third insulator are metal oxides having amorphous structures.

[0015] In the above, it is preferable that the semiconductor device has a sixth insulator below the oxide semiconductor, and a seventh insulator in contact with the upper surfaces of the fourth insulator and the third conductor, and that the sixth insulator and the seventh insulator are metal oxides having an amorphous structure.

[0016] In the above, it is preferable that the semiconductor device has an eighth insulator that covers the seventh insulator and contacts the upper surface of the sixth insulator in an area that does not overlap with the fifth insulator, and that the eighth insulator is a metal oxide having an amorphous structure.

[0017] In the above, it is preferable that the semiconductor device has a ninth insulator in contact with the lower surface of the sixth insulator and a tenth insulator in contact with the upper surface of the seventh insulator, and that the ninth insulator and the tenth insulator are silicon nitride.

[0018] In the above, it is preferable that the semiconductor device has a dielectric and a fourth conductor, and that openings reaching the second conductor are formed in the second insulator, the third insulator, and the fourth insulator, the dielectric is disposed in the opening and contacts the top surface of the second conductor, the side surfaces of the second insulator, the side surfaces of the third insulator, and the side surfaces of the fourth insulator, and the fourth conductor is disposed in the opening and contacts the top surface of the dielectric.

[0019] In the above, it is preferable that the semiconductor device has a first nitride insulator arranged between the first insulator and the third insulator, and a second nitride insulator arranged between the second insulator and the third insulator, and that the first nitride insulator and the second nitride insulator are silicon nitride.

[0020] In the above semiconductor device, the top surface of the first insulator and the top surface of the second insulator are preferably in contact with the third insulator.

[0021] In the above, the metal oxide having an amorphous structure is AlO x (x is any number greater than 0), preferably. [Effects of the Invention]

[0022] According to one embodiment of the present invention, a semiconductor device with little variation in transistor characteristics can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with high reliability can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with good electrical characteristics can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with high on-state current can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with low power consumption can be provided.

[0023] Note that the description of these effects does not preclude the existence of other effects. Note that one embodiment of the present invention does not necessarily have all of these effects. Note that effects other than these will become apparent from the description in the specification, drawings, claims, etc., and it is possible to extract other effects from the description in the specification, drawings, claims, etc. [Brief explanation of the drawings]

[0024] [Figure 1] 1A is a top view of a semiconductor device according to one embodiment of the present invention, and FIGS. 1B to 1D are cross-sectional views of the semiconductor device according to one embodiment of the present invention. [Figure 2] FIG. 2 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Figure 3] Figure 3A is a diagram explaining the classification of IGZO crystal structures, Figure 3B is a diagram explaining the XRD spectrum of a CAAC-IGZO film, and Figure 3C is a diagram explaining the electron microbeam diffraction pattern of a CAAC-IGZO film. [Figure 4] 4A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 4B to 4D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 5] 5A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 5B to 5D are cross-sectional views illustrating the method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 6] 6A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 6B to 6D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 7] 7A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 7B to 7D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 8] 8A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 8B to 8D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 9] 9A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 9B to 9D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 10] 10A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 10B to 10D are cross-sectional views illustrating the method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 11] 11A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 11B to 11D are cross-sectional views illustrating the method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 12] 12A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 12B to 12D are cross-sectional views illustrating the method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 13] 13A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 13B to 13D are cross-sectional views illustrating the method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 14] 14A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 14B to 14D are cross-sectional views illustrating the method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 15] 15A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 15B to 15D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 16] 16A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 16B to 16D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 17] FIG. 17 is a top view illustrating a microwave processing apparatus according to one embodiment of the present invention. [Figure 18] FIG. 18 is a cross-sectional view illustrating a microwave processing apparatus according to one embodiment of the present invention. [Figure 19] FIG. 19 is a cross-sectional view illustrating a microwave processing apparatus according to one embodiment of the present invention. [Figure 20] 20A is a top view of a semiconductor device according to one embodiment of the present invention, and FIGS. 20B to 20D are cross-sectional views of the semiconductor device according to one embodiment of the present invention. [Figure 21] 21A is a top view of a semiconductor device according to one embodiment of the present invention, and FIGS. 21B to 21D are cross-sectional views of the semiconductor device according to one embodiment of the present invention. [Figure 22] 22A is a top view of a semiconductor device according to one embodiment of the present invention, and FIGS. 22B to 22D are cross-sectional views of the semiconductor device according to one embodiment of the present invention. [Figure 23] 23A is a top view of a semiconductor device according to one embodiment of the present invention, and FIGS. 23B to 23D are cross-sectional views of the semiconductor device according to one embodiment of the present invention. [Figure 24] 24A and 24B are cross-sectional views of a semiconductor device according to one embodiment of the present invention. [Figure 25] FIG. 25 is a cross-sectional view illustrating a configuration of a memory device according to one embodiment of the present invention. [Figure 26] FIG. 26 is a cross-sectional view illustrating a configuration of a memory device according to one embodiment of the present invention. [Figure 27] 27A and 27B are cross-sectional views of a semiconductor device according to one embodiment of the present invention. [Figure 28] 28A and 28B are cross-sectional views of a semiconductor device according to one embodiment of the present invention. [Figure 29] FIG. 29 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Figure 30] FIG. 30 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Figure 31] 31A and 31B are block diagrams illustrating a configuration example of a storage device according to one embodiment of the present invention. [Figure 32] 32A to 32H are circuit diagrams illustrating configuration examples of a memory device according to one embodiment of the present invention. [Figure 33] FIG. 33 is a diagram showing various storage devices by hierarchy. [Figure 34]34A and 34B are block diagrams and schematic diagrams of a semiconductor device according to one embodiment of the present invention. [Figure 35] 35A and 35B are diagrams illustrating an example of an electronic component. [Figure 36] 36A to 36E are schematic diagrams of a memory device according to one embodiment of the present invention. [Figure 37] 37A to 37H are diagrams showing electronic devices according to one embodiment of the present invention. [Figure 38] 38A to 38C are schematic diagrams illustrating a method for calculating the operating frequency according to this embodiment. [Figure 39] Fig. 39A is a diagram showing electrical characteristics of a sample according to this example, and Fig. 39B is a diagram showing the results of calculating the operating frequency of the sample according to this example. [Figure 40] 40A and 40B are diagrams showing the stress time dependency of ΔVsh in the +GBT stress test according to this example. [Figure 41] FIG. 41 is a schematic diagram of a sample according to this example. [Figure 42] Figure 42A is a TEM image according to this example, and Figure 42B is an FFT image according to this example. [Figure 43] Figure 43A is a TEM image according to this example, and Figure 43B is an FFT image according to this example. [Figure 44] Figure 44A is a TEM image according to this example, and Figure 44B is an FFT image according to this example. [Figure 45] FIG. 45 is a diagram showing the deuterium concentration of the sample according to this example. DETAILED DESCRIPTION OF THE INVENTION

[0025] Hereinafter, embodiments will be described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different ways and that various changes in form and details can be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the following embodiments.

[0026] In addition, in the drawings, sizes, layer thicknesses, or regions may be exaggerated for clarity. Therefore, the drawings are not necessarily limited to the scale. The drawings are schematic representations of ideal examples and are not limited to the shapes or values ​​shown in the drawings. For example, in actual manufacturing processes, layers, resist masks, etc. may be unintentionally thinned by processes such as etching, but this may not be reflected in the drawings to facilitate understanding. In addition, in the drawings, the same symbols are used for identical parts or parts having similar functions across different drawings, and repeated explanations may be omitted. When referring to similar functions, the same hatch pattern may be used and no particular symbols may be assigned.

[0027] In order to make the invention easier to understand, particularly in top views (also called "plan views") and perspective views, some components may be omitted from the drawings. Also, some hidden lines may be omitted from the drawings.

[0028] In addition, in this specification, ordinal numbers such as first, second, etc. are used for convenience and do not indicate the order of processes or stacking. Therefore, for example, "first" can be appropriately replaced with "second" or "third," etc. in the description. Furthermore, the ordinal numbers used to identify one embodiment of the present invention may not match the ordinal numbers used in this specification.

[0029] Furthermore, in this specification, terms indicating arrangement such as "above" and "below" are used for convenience in describing the positional relationship between components with reference to the drawings. Furthermore, the positional relationship between components changes as appropriate depending on the direction in which each component is depicted. Therefore, the terms are not limited to those described in the specification, and can be rephrased appropriately depending on the situation.

[0030] Furthermore, when it is explicitly stated in this specification that X and Y are connected, it is understood that the present specification also discloses cases in which X and Y are electrically connected, cases in which X and Y are functionally connected, and cases in which X and Y are directly connected. Therefore, it is not limited to a specific connection relationship, for example, a connection relationship shown in a figure or text, and it is understood that connections other than those shown in a figure or text are also disclosed in a figure or text. Here, X and Y are assumed to be objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.).

[0031] In this specification and the like, a transistor is an element having at least three terminals including a gate, a drain, and a source. A transistor has a region (hereinafter also referred to as a channel formation region) where a channel is formed between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode), and a current can flow between the source and the drain through the channel formation region. In this specification and the like, the channel formation region refers to a region through which a current mainly flows.

[0032] Furthermore, when a transistor with a polarity different from that described in the specification or drawings is used, or when the direction of current changes during circuit operation, the functions of the source and drain may be interchanged. For this reason, the terms source and drain may be used interchangeably in this specification.

[0033] Note that the channel length refers to, for example, a region where the semiconductor (or a portion in the semiconductor through which current flows when the transistor is on) and the gate electrode overlap in a top view of a transistor, or the distance between the source (source region or source electrode) and the drain (drain region or drain electrode) in the channel formation region. Note that the channel length of one transistor does not necessarily have the same value in all regions. That is, the channel length of one transistor may not be fixed to a single value. Therefore, in this specification, the channel length is defined as any one value, maximum value, minimum value, or average value in the channel formation region.

[0034] The channel width refers to, for example, the length of a channel formation region in a region where a semiconductor (or a portion of the semiconductor through which current flows when the transistor is on) and a gate electrode overlap in a top view of a transistor, or the length of the channel formation region in a direction perpendicular to the channel length direction in the channel formation region. Note that the channel width of a single transistor does not necessarily have the same value in all regions. That is, the channel width of a single transistor may not be determined to a single value. Therefore, in this specification, the channel width refers to any one value, maximum value, minimum value, or average value in the channel formation region.

[0035] In this specification and the like, depending on the structure of a transistor, the channel width in a region where a channel is actually formed (hereinafter also referred to as an "effective channel width") may differ from the channel width shown in a top view of the transistor (hereinafter also referred to as an "apparent channel width"). For example, when a gate electrode covers the side surface of a semiconductor, the effective channel width may be larger than the apparent channel width, and the influence thereof may not be negligible. For example, in a fine transistor in which a gate electrode covers the side surface of a semiconductor, the proportion of the channel formation region formed on the side surface of the semiconductor may be large. In such a case, the effective channel width is larger than the apparent channel width.

[0036] In such cases, it may be difficult to estimate the effective channel width by actual measurement. For example, in order to estimate the effective channel width from the design value, it is necessary to assume that the shape of the semiconductor is known. Therefore, if the shape of the semiconductor is not accurately known, it is difficult to accurately measure the effective channel width.

[0037] In this specification, when simply referred to as a channel width, it may refer to an apparent channel width. Alternatively, when simply referred to as a channel width, it may refer to an effective channel width. Note that values ​​of the channel length, channel width, effective channel width, apparent channel width, etc. can be determined by analyzing a cross-sectional TEM image, etc.

[0038] Note that impurities in semiconductors refer to, for example, elements other than the main components constituting the semiconductor. For example, an element with a concentration of less than 0.1 atomic % can be considered an impurity. The presence of impurities can, for example, increase the defect state density of the semiconductor or reduce the crystallinity. When the semiconductor is an oxide semiconductor, impurities that change the characteristics of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components of the oxide semiconductor, such as hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. Note that water can also function as an impurity. For example, the inclusion of impurities can cause oxygen deficiency (V) in the oxide semiconductor. O :oxygen vacancy) may be formed.

[0039] In this specification and the like, an oxynitride is a material whose composition contains more oxygen than nitrogen. For example, silicon oxynitride is a material whose composition contains more oxygen than nitrogen. Furthermore, a nitride oxide is a material whose composition contains more nitrogen than oxygen. For example, silicon nitride oxide is a material whose composition contains more nitrogen than oxygen.

[0040] In this specification and the like, the term "insulator" can be replaced with an insulating film or an insulating layer, the term "conductor" can be replaced with a conductive film or a conductive layer, and the term "semiconductor" can be replaced with a semiconductor film or a semiconductor layer.

[0041] Furthermore, in this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, it also includes cases in which the angle is -5 degrees or more and 5 degrees or less. Furthermore, "substantially parallel" refers to a state in which two straight lines are arranged at an angle of -30 degrees or more and 30 degrees or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, it also includes cases in which the angle is 85 degrees or more and 95 degrees or less. Furthermore, "substantially perpendicular" refers to a state in which two straight lines are arranged at an angle of 60 degrees or more and 120 degrees or less.

[0042] In this specification and the like, the term "metal oxide" refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as "oxide semiconductors" or simply as "OSs"). For example, when a metal oxide is used in a semiconductor layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. In other words, an OS transistor can be rephrased as a transistor including a metal oxide or an oxide semiconductor.

[0043] Furthermore, in this specification and the like, normally off means that when no potential is applied to the gate or when a ground potential is applied to the gate, the drain current flowing through the transistor per 1 μm of channel width is 1×10 -20 A or less, 1 x 10 at 85°C -18 A or less, or 1 x 10 at 125°C -16 This means that it is A or below.

[0044] (Embodiment 1) In this embodiment, an example of a semiconductor device including a transistor 200 according to one embodiment of the present invention and a manufacturing method thereof will be described with reference to FIGS.

[0045] <Configuration example of semiconductor device> The structure of a semiconductor device including a transistor 200 will be described with reference to FIGS. 1A to 1D. FIG. 1A is a top view of the semiconductor device. FIGS. 1B to 1D are cross-sectional views of the semiconductor device. FIG. 1B is a cross-sectional view of a portion indicated by a dashed dotted line A1-A2 in FIG. 1A, and is also a cross-sectional view of the transistor 200 in the channel length direction. FIG. 1C is a cross-sectional view of a portion indicated by a dashed dotted line A3-A4 in FIG. 1A, and is also a cross-sectional view of the transistor 200 in the channel width direction. FIG. 1D is a cross-sectional view of a portion indicated by a dashed dotted line A5-A6 in FIG. 1A. Note that some elements are omitted from the top view of FIG. 1A for clarity.

[0046] A semiconductor device of one embodiment of the present invention includes an insulator 212 over a substrate (not shown), an insulator 214 over the insulator 212, a transistor 200 over the insulator 214, an insulator 280 over the transistor 200, an insulator 282 over the insulator 280, and an insulator 283 over the insulator 282. The insulators 212, 214, 280, 282, and 283 function as interlayer films. The semiconductor device also includes a conductor 240 (conductor 240a and conductor 240b) that is electrically connected to the transistor 200 and functions as a plug. Note that an insulator 241 (insulator 241a and insulator 241b) is provided in contact with a side surface of the conductor 240 that functions as a plug. In addition, conductors 246 (conductors 246a and 246b) that are electrically connected to the conductor 240 and function as wiring are provided on the insulator 283 and the conductor 240. In addition, an insulator 286 is provided on the conductor 246 and the insulator 283.

[0047] Insulator 241a is provided in contact with the inner walls of the openings of insulators 280, 282, and 283. A first conductor of conductor 240a is provided in contact with the side surface of insulator 241a, and a second conductor of conductor 240a is provided further inward. Insulator 241b is provided in contact with the inner walls of the openings of insulators 280, 282, and 283. A first conductor of conductor 240b is provided in contact with the side surface of insulator 241b, and a second conductor of conductor 240b is provided further inward. Here, the height of the top surface of conductor 240 and the height of the top surface of insulator 283 in the region overlapping with conductor 246 can be made approximately the same. Note that, although the transistor 200 illustrates a configuration in which the first conductor of conductor 240 and the second conductor of conductor 240 are stacked, the present invention is not limited to this. For example, the conductor 240 may be configured to have a single layer or a laminated structure of three or more layers. When the structure has a laminated structure, the layers may be distinguished by assigning ordinal numbers to indicate the order of formation.

[0048] [Transistor 200] As shown in FIGS. 1A to 1D , the transistor 200 includes an insulator 216 on an insulator 214, conductors 205 (conductors 205a, 205b, and 205c) disposed so as to be embedded in the insulator 216, an insulator 222 on the insulator 216 and on the conductor 205, an insulator 224 on the insulator 222, an oxide 230a on the insulator 224, an oxide 230b on the oxide 230a, an oxide 243 (oxides 243a and 243b) on the oxide 230b, a conductor 242a on the oxide 243a, an insulator 271a on the conductor 242a, an insulator 273a on the insulator 271a, and an oxide 243b on the oxide 243a. conductor 242b on oxide 230b, insulator 271b on conductor 242b, insulator 273b on insulator 271b, insulator 250 on oxide 230b, conductor 260 (conductor 260a and conductor 260b) located on insulator 250 and overlapping with part of oxide 230b, insulator 272a in contact with the side of oxide 230b, the side of oxide 243a and the side of conductor 242a, insulator 272b in contact with the side of oxide 230b, the side of oxide 243b and the side of conductor 242b, and insulator 275 arranged on insulator 224, insulator 272a, insulator 272b, insulator 273a and insulator 273b. 1B and 1C, the upper surface of conductor 260 is disposed so as to be at approximately the same height as at least a portion of the upper surface of insulator 250 and at least a portion of the upper surface of insulator 280. Insulator 282 contacts at least a portion of the upper surfaces of conductor 260, insulator 250, and insulator 280.

[0049] In the following, the oxide 230a and the oxide 230b may be collectively referred to as the oxide 230. The insulators 271a and 271b may be collectively referred to as the insulator 271. The insulators 272a and 272b may be collectively referred to as the insulator 272. The insulators 273a and 273b may be collectively referred to as the insulator 273. The conductors 242a and 242b may be collectively referred to as the conductor 242.

[0050] The insulator 280 and the insulator 275 have openings that reach the oxide 230b. The insulator 250 and the conductor 260 are disposed in the openings. In addition, in the channel length direction of the transistor 200, the conductor 260 and the insulator 250 are disposed between the insulator 271a, the insulator 273a, the conductor 242a, and the oxide 243a and the insulator 271b, the insulator 273b, the conductor 242b, and the oxide 243b. The insulator 250 has a region that contacts the side surface of the conductor 260 and a region that contacts the bottom surface of the conductor 260.

[0051] The oxide 230 preferably includes an oxide 230a disposed on the insulator 224 and an oxide 230b disposed on the oxide 230a. By providing the oxide 230a below the oxide 230b, it is possible to suppress the diffusion of impurities from structures formed below the oxide 230a to the oxide 230b.

[0052] Note that in the transistor 200, the oxide 230 has a two-layer structure of the oxide 230a and the oxide 230b, but the present invention is not limited to this. For example, the oxide 230b may have a single layer or a stacked structure of three or more layers, or each of the oxide 230a and the oxide 230b may have a stacked structure.

[0053] The conductor 260 functions as a first gate (also referred to as a top gate) electrode, and the conductor 205 functions as a second gate (also referred to as a back gate) electrode. The insulator 250 functions as a first gate insulator, and the insulator 224 functions as a second gate insulator. The conductor 242a functions as one of a source and a drain, and the conductor 242b functions as the other of the source and the drain. At least a part of a region of the oxide 230 that overlaps with the conductor 260 functions as a channel formation region.

[0054] FIG. 2 shows an enlarged view of the vicinity of the channel formation region in FIG. 1B. As shown in FIG. 2, the oxide 230b has a region 230bc that functions as a channel formation region of the transistor 200, and regions 230ba and 230bb that are provided on either side of the region 230bc and function as source and drain regions. The region 230bc at least partially overlaps with the conductor 260. In other words, the region 230bc is provided in a region between the conductor 242a and the conductor 242b. The region 230ba is provided overlapping with the conductor 242a, and the region 230bb is provided overlapping with the conductor 242b.

[0055] The region 230bc, which functions as a channel formation region, has fewer oxygen vacancies or a lower impurity concentration than the regions 230ba and 230bb, and is therefore a high-resistance region with a low carrier concentration. The regions 230ba and 230bb, which function as a source region or drain region, have many oxygen vacancies or high impurity concentrations such as hydrogen, nitrogen, and metal elements, which increases the carrier concentration and reduces the resistance. In other words, the regions 230ba and 230bb have a higher carrier concentration and lower resistance than the region 230bc.

[0056] Here, the carrier concentration of the region 230bc that functions as a channel forming region is 1×10 18 cm -3 Preferably, it is 1×10 or less. 17 cm -3 More preferably, it is less than 1×10 16 cm -3 More preferably, it is less than 1×10 13 cm -3 More preferably, it is less than 1×10 12 cm -3 The lower limit of the carrier concentration of the region 230bc that functions as a channel formation region is not particularly limited, but is preferably, for example, 1×10 -9 cm -3 It can be said that:

[0057] Furthermore, a region may be formed between region 230bc and region 230ba or region 230bb, whose carrier concentration is equal to or lower than that of region 230ba and region 230bb, and equal to or higher than that of region 230bc. That is, this region functions as a junction region between region 230bc and region 230ba or region 230bb. The junction region may have a hydrogen concentration equal to or lower than that of region 230ba and region 230bb, and equal to or higher than that of region 230bc. The junction region may also have oxygen vacancies equal to or lower than those of region 230ba and region 230bb, and equal to or higher than those of region 230bc.

[0058] 2 shows an example in which the regions 230ba, 230bb, and 230bc are formed in the oxide 230b, but the present invention is not limited to this. For example, each of the above regions may be formed not only in the oxide 230b but also in the oxide 230a.

[0059] Furthermore, it may be difficult to clearly detect the boundaries between regions in the oxide 230. The concentrations of metal elements and impurity elements such as hydrogen and nitrogen detected in each region may not necessarily vary stepwise from region to region, but may also vary continuously within each region. In other words, it is sufficient that the concentrations of metal elements and impurity elements such as hydrogen and nitrogen decrease in regions closer to the channel formation region.

[0060] In the transistor 200, the oxide 230 including the channel formation region (the oxide 230a and the oxide 230b) is preferably a metal oxide that functions as a semiconductor (hereinafter also referred to as an oxide semiconductor).

[0061] The metal oxide functioning as a semiconductor preferably has a band gap of 2 eV or more, preferably 2.5 eV or more. By using such a metal oxide with a wide band gap, the off-state current of the transistor can be reduced.

[0062] For example, a metal oxide such as In-M-Zn oxide containing indium, element M, and zinc (element M is one or more selected from aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc.) may be used as oxide 230. Alternatively, In-M oxide, In-Ga oxide, In-Zn oxide, indium oxide, M-Zn oxide, or an oxide of element M may be used as oxide 230.

[0063] Here, it is preferable that the atomic ratio of In to element M in the metal oxide used for oxide 230b is greater than the atomic ratio of In to element M in the metal oxide used for oxide 230a.

[0064] In this way, by disposing the oxide 230a below the oxide 230b, it is possible to suppress the diffusion of impurities and oxygen from structures formed below the oxide 230a into the oxide 230b.

[0065] Furthermore, since the oxide 230a and the oxide 230b have a common element other than oxygen (as a main component), the defect state density at the interface between the oxide 230a and the oxide 230b can be reduced. Because the defect state density at the interface between the oxide 230a and the oxide 230b can be reduced, the effect of interface scattering on carrier conduction is reduced, and a high on-current can be obtained.

[0066] The oxide 230b preferably has crystallinity, and it is particularly preferable to use c-axis aligned crystalline oxide semiconductor (CAAC-OS) as the oxide 230b.

[0067] CAAC-OS has a highly crystalline and dense structure, and is free of impurities and defects (e.g., oxygen vacancies (V O ) and the like. In particular, by subjecting the formed metal oxide to heat treatment at a temperature (e.g., 400°C or higher and 600°C or lower) at which the metal oxide does not polycrystallize, the CAAC-OS can be made to have a dense structure with higher crystallinity. In this way, the density of the CAAC-OS can be increased, thereby further reducing the diffusion of impurities or oxygen in the CAAC-OS.

[0068] On the other hand, since it is difficult to identify clear grain boundaries in CAAC-OS, it is said that the decrease in electron mobility due to grain boundaries is unlikely to occur. Therefore, metal oxides with CAAC-OS have stable physical properties. As a result, metal oxides with CAAC-OS are heat-resistant and highly reliable.

[0069] In a transistor using an oxide semiconductor, if impurities and oxygen vacancies exist in a region where a channel is formed in the oxide semiconductor, the electrical characteristics are likely to fluctuate and the reliability may be reduced. In addition, hydrogen in the vicinity of the oxygen vacancy is converted into a defect where hydrogen enters the oxygen vacancy (hereinafter referred to as V O H.) and generate electrons that serve as carriers. Therefore, if oxygen vacancies are present in the region where a channel is formed in an oxide semiconductor, the transistor is likely to have normally-on characteristics (a channel exists and current flows through the transistor even when no voltage is applied to the gate electrode). Therefore, in the region where a channel is formed in an oxide semiconductor, impurities, oxygen vacancies, and V O It is preferable that H is reduced as much as possible. In other words, it is preferable that the region in the oxide semiconductor where a channel is formed has a reduced carrier concentration and is i-type (intrinsic) or substantially i-type.

[0070] In response to this problem, an insulator containing oxygen that is released by heating (hereinafter may be referred to as excess oxygen) is provided near the oxide semiconductor, and heat treatment is performed to supply oxygen from the insulator to the oxide semiconductor, thereby eliminating oxygen vacancies and V O H can be reduced. However, if an excessive amount of oxygen is supplied to the source region or the drain region, this may cause a decrease in the on-state current or a decrease in the field-effect mobility of the transistor 200. Furthermore, variations in the amount of oxygen supplied to the source region or the drain region within the substrate surface will cause variations in the characteristics of a semiconductor device having the transistor.

[0071] Therefore, in the oxide semiconductor, the region 230bc that functions as a channel formation region preferably has a reduced carrier concentration and is i-type or substantially i-type, whereas the regions 230ba and 230bb that function as source and drain regions preferably have a high carrier concentration and are n-type. O It is preferable to reduce H so that an excessive amount of oxygen is not supplied to the regions 230ba and 230bb.

[0072] Therefore, in this embodiment, in a state where the conductors 242a and 242b are provided on the oxide 230b, microwave processing is performed in an atmosphere containing oxygen to remove oxygen vacancies in the region 230bc and V O The microwave treatment here refers to a treatment using a device with a power source that generates high-density plasma using microwaves, for example.

[0073] By performing microwave processing in an atmosphere containing oxygen, oxygen gas can be converted into plasma using microwaves or high frequency waves such as RF, and the oxygen plasma can be activated. At this time, microwaves or high frequency waves such as RF can also be irradiated onto the region 230bc. The V of the region 230bc can be activated by the action of the plasma, microwaves, etc. OH is split off, hydrogen H is removed from the region 230bc, and oxygen vacancy V is formed. O can be compensated with oxygen. O H → H + V O " occurs, and the hydrogen concentration in the region 230bc can be reduced. Therefore, oxygen vacancies and V O H can be reduced to lower the carrier concentration.

[0074] Furthermore, when microwave processing is performed in an atmosphere containing oxygen, the effects of microwaves, high frequency waves such as RF, oxygen plasma, etc. are shielded by the conductors 242a and 242b and do not reach the regions 230ba and 230bb. Furthermore, the effects of oxygen plasma can be reduced by the insulators 271, 273, 275, and 280 that are provided to cover the oxide 230b and the conductor 242. As a result, during microwave processing, V O Since there is no reduction in H and no excessive supply of oxygen, it is possible to prevent a decrease in the carrier concentration.

[0075] In this way, oxygen vacancies and V are selectively formed in the oxide semiconductor region 230bc. O By removing H, the region 230bc can be made i-type or substantially i-type. Furthermore, the supply of excess oxygen to the regions 230ba and 230bb, which function as source and drain regions, can be suppressed, maintaining the n-type conductivity. This suppresses fluctuations in the electrical characteristics of the transistor 200 and suppresses variations in the electrical characteristics of the transistor 200 within the substrate surface.

[0076] By adopting the above-described configuration, it is possible to provide a semiconductor device with less variation in transistor characteristics, a highly reliable semiconductor device, and a semiconductor device with good electrical characteristics.

[0077] 1 and other figures, the side of the opening into which the conductor 260 and the like are embedded, including the groove in the oxide 230b, is generally perpendicular to the surface on which the oxide 230b is to be formed, but this embodiment is not limited to this. For example, the bottom of the opening may be gently curved, i.e., U-shaped. Also, for example, the side of the opening may be inclined relative to the surface on which the oxide 230b is to be formed.

[0078] 1C , in a cross-sectional view of the transistor 200 in the channel width direction, a curved surface may be formed between the side surface of the oxide 230b and the top surface of the oxide 230b. That is, the end of the side surface and the end of the top surface may be curved (also referred to as rounded).

[0079] The radius of curvature of the curved surface is preferably greater than 0 nm and smaller than the film thickness of the oxide 230b in the region overlapping with the conductor 242, or smaller than half the length of the region not having the curved surface. Specifically, the radius of curvature of the curved surface is greater than 0 nm and smaller than 20 nm, preferably greater than 1 nm and smaller than 15 nm, and more preferably greater than 2 nm and smaller than 10 nm. This shape can improve the coverage of the oxide 230b with the insulator 250 and the conductor 260.

[0080] The oxide 230 preferably has a stacked structure of multiple oxide layers with different chemical compositions. Specifically, in the metal oxide used for the oxide 230a, the atomic ratio of the element M to the metal element that is the main component is preferably larger than the atomic ratio of the element M to the metal element that is the main component in the metal oxide used for the oxide 230b. Furthermore, in the metal oxide used for the oxide 230a, the atomic ratio of the element M to In is preferably larger than the atomic ratio of the element M to In in the metal oxide used for the oxide 230b. Furthermore, in the metal oxide used for the oxide 230b, the atomic ratio of In to the element M is preferably larger than the atomic ratio of In to the element M in the metal oxide used for the oxide 230a.

[0081] Furthermore, the oxide 230b is preferably a crystalline oxide such as CAAC-OS. Crystalline oxides such as CAAC-OS have few impurities and defects (such as oxygen vacancies), and have a highly crystalline and dense structure. This can prevent the source or drain electrode from extracting oxygen from the oxide 230b. This reduces the extraction of oxygen from the oxide 230b even during heat treatment, making the transistor 200 stable against high temperatures (so-called thermal budget) during the manufacturing process.

[0082] Here, the conduction band minimum changes gradually at the junction between the oxide 230a and the oxide 230b. In other words, the conduction band minimum at the junction between the oxide 230a and the oxide 230b changes continuously or can be said to be a continuous junction. To achieve this, it is advisable to reduce the defect level density of the mixed layer formed at the interface between the oxide 230a and the oxide 230b.

[0083] Specifically, when the oxide 230a and the oxide 230b contain a common element other than oxygen as a main component, a mixed layer with a low density of defect states can be formed. For example, when the oxide 230b is an In-M-Zn oxide, the oxide 230a may be an In-M-Zn oxide, an M-Zn oxide, an oxide of element M, an In-Zn oxide, an indium oxide, or the like.

[0084] Specifically, the oxide 230a may be a metal oxide having an atomic ratio of In:M:Zn=1:3:4 or a similar composition, or an atomic ratio of In:M:Zn=1:1:0.5 or a similar composition. The oxide 230b may be a metal oxide having an atomic ratio of In:M:Zn=1:1:1 or a similar composition, or an atomic ratio of In:M:Zn=4:2:3 or a similar composition. Note that a similar composition includes a range of ±30% of the desired atomic ratio. Gallium is preferably used as the element M.

[0085] When a metal oxide film is formed by sputtering, the atomic ratio is not limited to the atomic ratio of the formed metal oxide film, but may be the atomic ratio of a sputtering target used to form the metal oxide film.

[0086] By configuring the oxide 230a and the oxide 230b as described above, the defect state density at the interface between the oxide 230a and the oxide 230b can be reduced, which reduces the influence of interface scattering on carrier conduction, and the transistor 200 can achieve a large on-state current and high frequency characteristics.

[0087] At least one of the insulators 212, 214, 271, 272, 275, 282, 283, and 286 preferably functions as a barrier insulating film that suppresses the diffusion of impurities such as water and hydrogen from the substrate side or from above the transistor 200 into the transistor 200. Therefore, at least one of the insulators 212, 214, 271, 272, 275, 282, 283, and 286 is preferably an insulating material that suppresses the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (such as NO, NO, and NO), and copper atoms (i.e., through which the above impurities are less likely to permeate). Alternatively, it is preferably an insulating material that suppresses the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.) (i.e., through which the above oxygen is less likely to permeate).

[0088] In this specification, a barrier insulating film refers to an insulating film having barrier properties. In this specification, the barrier properties refer to a function of suppressing the diffusion of a corresponding substance (also referred to as low permeability) or a function of capturing and fixing (also referred to as gettering) a corresponding substance.

[0089] For the insulators 212, 214, 271, 272, 275, 282, 283, and 286, it is preferable to use insulators that have the function of suppressing the diffusion of impurities such as water and hydrogen, and oxygen. For example, aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, or silicon nitride oxide can be used. For example, it is preferable to use silicon nitride, which has a high hydrogen barrier property, for the insulators 212, 272, 283, and 286. Furthermore, it is preferable to use aluminum oxide or magnesium oxide, which has a high hydrogen capture and fixation function, for the insulators 214, 271, 275, and 282. This can suppress the diffusion of impurities such as water and hydrogen from the substrate side to the transistor 200 side through the insulators 212 and 214. Alternatively, impurities such as water and hydrogen can be prevented from diffusing toward the transistor 200 from an interlayer insulating film disposed outside the insulator 286. Alternatively, oxygen contained in the insulator 224 and the like can be prevented from diffusing toward the substrate through the insulators 212 and 214. Alternatively, oxygen contained in the insulator 280 and the like can be prevented from diffusing upward from the transistor 200 through the insulator 282 and the like. In this way, it is preferable to have a structure in which the transistor 200 is surrounded by the insulators 212, 214, 271, 272, 275, 282, 283, and 286, which have the function of preventing the diffusion of impurities such as water and hydrogen, and oxygen.

[0090] Here, it is preferable to use an oxide having an amorphous structure as the insulators 212, 214, 271, 272, 275, 282, 283, and 286. For example, AlO x (x is any number greater than 0), or MgO yIt is preferable to use a metal oxide such as y (where y is any number greater than 0). In such metal oxides having an amorphous structure, oxygen atoms have dangling bonds, and the dangling bonds may have the property of capturing or fixing hydrogen. By using such a metal oxide having an amorphous structure as a component of the transistor 200 or providing it around the transistor 200, hydrogen contained in the transistor 200 or hydrogen present around the transistor 200 can be captured or fixed. In particular, it is preferable to capture or fix hydrogen contained in the channel formation region of the transistor 200. By using a metal oxide having an amorphous structure as a component of the transistor 200 or providing it around the transistor 200, a highly reliable transistor 200 and a semiconductor device can be manufactured that have excellent characteristics.

[0091] Furthermore, the insulators 212, 214, 271, 272, 275, 282, 283, and 286 preferably have an amorphous structure, but may have a polycrystalline structure in some areas. The insulators 212, 214, 271, 272, 275, 282, 283, and 286 may have a multilayer structure in which an amorphous layer and a polycrystalline layer are stacked. For example, they may have a stacked structure in which a polycrystalline layer is formed on an amorphous layer.

[0092] The insulators 212, 214, 271, 272, 275, 282, 283, and 286 may be deposited by, for example, sputtering. Sputtering does not require the use of hydrogen as a deposition gas, and therefore can reduce the hydrogen concentration of the insulators 212, 214, 271, 272, 275, 282, 283, and 286. Note that the deposition method is not limited to sputtering, and other methods such as chemical vapor deposition (CVD), molecular beam epitaxy (MBE), pulsed laser deposition (PLD), and atomic layer deposition (ALD) may also be used as appropriate.

[0093] It may also be preferable to reduce the resistivity of the insulators 212, 283, and 286. For example, it may be preferable to reduce the resistivity of the insulators 212, 283, and 286 to approximately 1×10 13 By setting the resistivity to Ωcm, the insulator 212, the insulator 283, and the insulator 286 may be able to reduce charge-up of the conductor 205, the conductor 242, the conductor 260, or the conductor 246 during treatment using plasma or the like in the semiconductor device manufacturing process. The resistivity of the insulator 212, the insulator 283, and the insulator 286 is preferably 1×10 10 Ωcm or more 1×10 15 Ωcm or less.

[0094] Furthermore, the insulators 216 and 280 preferably have a lower dielectric constant than the insulator 214. Using a material with a low dielectric constant as an interlayer film can reduce parasitic capacitance between wirings. For example, the insulators 216 and 280 may be made of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine has been added, silicon oxide to which carbon has been added, silicon oxide to which carbon and nitrogen have been added, silicon oxide having vacancies, or the like, as appropriate.

[0095] The conductor 205 is disposed so as to overlap the oxide 230 and the conductor 260. Here, the conductor 205 is preferably provided so as to be embedded in an opening formed in the insulator 216. Note that a portion of the conductor 205 may be provided so as to be embedded in the insulator 214.

[0096] The conductor 205 includes conductor 205a, conductor 205b, and conductor 205c. The conductor 205a is provided in contact with the bottom surface and sidewall of the opening. The conductor 205b is provided so as to be embedded in a recess formed in the conductor 205a. Here, the upper surface of the conductor 205b is lower than the upper surface of the conductor 205a and the upper surface of the insulator 216. The conductor 205c is provided in contact with the upper surface of the conductor 205b and the side surface of the conductor 205a. Here, the height of the upper surface of the conductor 205c is approximately the same as the height of the upper surface of the conductor 205a and the height of the upper surface of the insulator 216. In other words, the conductor 205b is configured to be enclosed by the conductors 205a and 205c.

[0097] Here, the conductors 205a and 205c are preferably made of a conductive material that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (NO, NO, NO, etc.), copper atoms, etc. Alternatively, it is preferable to use a conductive material that has the function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.).

[0098] By using a conductive material capable of reducing hydrogen diffusion for the conductor 205a and the conductor 205c, impurities such as hydrogen contained in the conductor 205b can be prevented from diffusing into the oxide 230 via the insulator 224 or the like. Furthermore, by using a conductive material capable of suppressing oxygen diffusion for the conductor 205a and the conductor 205c, it is possible to prevent the conductor 205b from being oxidized and its conductivity from decreasing. Examples of conductive materials capable of suppressing oxygen diffusion include titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, and ruthenium oxide. Therefore, the conductor 205a may be a single layer or a multilayer of the above conductive materials. For example, the conductor 205a may be made of titanium nitride.

[0099] The conductor 205b is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component, for example, tungsten.

[0100] The conductor 205 may function as a second gate electrode. In this case, the threshold voltage (Vth) of the transistor 200 can be controlled by changing the potential applied to the conductor 205 independently of the potential applied to the conductor 260. In particular, applying a negative potential to the conductor 205 can increase the Vth of the transistor 200 and reduce the off-state current. Therefore, applying a negative potential to the conductor 205 can reduce the drain current when the potential applied to the conductor 260 is 0 V compared to not applying a negative potential to the conductor 205.

[0101] The electrical resistivity of the conductor 205 is designed taking into consideration the potential applied to the conductor 205, and the film thickness of the conductor 205 is set to match this electrical resistivity. The film thickness of the insulator 216 is approximately the same as that of the conductor 205. Here, it is preferable to make the film thicknesses of the conductor 205 and the insulator 216 thin within the range permitted by the design of the conductor 205. By making the film thickness of the insulator 216 thin, the absolute amount of impurities such as hydrogen contained in the insulator 216 can be reduced, thereby reducing the diffusion of the impurities into the oxide 230.

[0102] As shown in FIG. 1A, the conductor 205 is preferably larger than the area of ​​the oxide 230 that does not overlap with the conductors 242a and 242b. In particular, as shown in FIG. 1C, the conductor 205 preferably extends to areas outside the ends of the oxides 230a and 230b that intersect with the channel width direction. In other words, the conductor 205 and the conductor 260 preferably overlap with each other via an insulator outside the side surfaces of the oxide 230 in the channel width direction. This structure allows the channel formation region of the oxide 230 to be electrically surrounded by the electric field of the conductor 260, which functions as the first gate electrode, and the electric field of the conductor 205, which functions as the second gate electrode. In this specification, a transistor structure in which the channel formation region is electrically surrounded by the electric fields of the first and second gates is referred to as a surrounded channel (S-channel) structure.

[0103] In this specification and the like, a transistor with an S-channel structure refers to a transistor structure in which a channel formation region is electrically surrounded by the electric fields of one and the other of a pair of gate electrodes. The S-channel structure disclosed in this specification and the like differs from a fin structure and a planar structure. By adopting the S-channel structure, the transistor can be made more resistant to the short-channel effect, in other words, less susceptible to the short-channel effect.

[0104] 1C, the conductor 205 is extended to function as wiring. However, the present invention is not limited to this, and a conductor functioning as wiring may be provided below the conductor 205. Furthermore, it is not necessary to provide one conductor 205 for each transistor. For example, the conductor 205 may be shared by multiple transistors.

[0105] Note that, in the transistor 200, the conductor 205 has a stacked structure of conductors 205a, 205b, and 205c, but the present invention is not limited to this. The conductor 205 may have a single-layer, two-layer, or four or more-layer structure. For example, the conductor 205 may have a two-layer structure of conductors 205a and 205b.

[0106] Insulator 222 and insulator 224 function as gate insulators.

[0107] The insulator 222 preferably has a function of suppressing the diffusion of hydrogen (e.g., at least one of hydrogen atoms, hydrogen molecules, etc.). The insulator 222 also preferably has a function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.). For example, the insulator 222 preferably has a function of suppressing the diffusion of one or both of hydrogen and oxygen more than the insulator 224.

[0108] The insulator 222 may be an insulator containing an oxide of one or both of aluminum and hafnium, which are insulating materials. Aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate) is preferably used as the insulator. When the insulator 222 is formed using such a material, the insulator 222 functions as a layer that suppresses oxygen release from the oxide 230 to the substrate side and the diffusion of impurities such as hydrogen from the periphery of the transistor 200 to the oxide 230. Therefore, the insulator 222 can suppress the diffusion of impurities such as hydrogen into the inside of the transistor 200 and the generation of oxygen vacancies in the oxide 230. Furthermore, the conductor 205 can be prevented from reacting with the insulator 224 or the oxygen contained in the oxide 230.

[0109] Alternatively, the insulator may contain, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide. Alternatively, these insulators may be nitrided. Furthermore, the insulator 222 may be formed by stacking silicon oxide, silicon oxynitride, or silicon nitride on these insulators.

[0110] The insulator 222 may be a single layer or a multilayer of an insulator containing a so-called high-k material, such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba,Sr)TiO3 (BST). As transistors become smaller and more highly integrated, thinning the gate insulator can cause problems such as leakage current. Using a high-k material for the insulator that functions as the gate insulator allows for a reduction in the gate potential during transistor operation while maintaining the physical film thickness.

[0111] The insulator 224 in contact with the oxide 230 preferably contains excess oxygen (oxygen is released by heating). For example, the insulator 224 may be made of silicon oxide, silicon oxynitride, or the like as appropriate. By providing an insulator containing oxygen in contact with the oxide 230, oxygen vacancies in the oxide 230 can be reduced, and the reliability of the transistor 200 can be improved.

[0112] Specifically, it is preferable to use an oxide material from which a portion of oxygen is released by heating, in other words, an insulator material having an excess oxygen region, as the insulator 224. The oxide material from which oxygen is released by heating is an oxide material from which the amount of released oxygen molecules is 1.0×10 18 molecules / cm 3 or more, preferably 1.0 × 10 19 molecules / cm 3 More preferably, 2.0 × 10 19 molecules / cm 3 or more, or 3.0 x 10 20 molecules / cm 3 The oxide film is one having the above-mentioned properties. The surface temperature of the film during the TDS analysis is preferably in the range of 100°C or higher and 700°C or lower, or 100°C or higher and 400°C or lower.

[0113] In addition, during the manufacturing process of the transistor 200, it is preferable to perform heat treatment while the surface of the oxide 230 is exposed. The heat treatment may be performed, for example, at a temperature of 100°C or higher and 600°C or lower, more preferably 350°C or higher and 550°C or lower. Note that the heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing an oxidizing gas at 10 ppm or higher, 1% or higher, or 10% or higher. For example, the heat treatment is preferably performed in an oxygen atmosphere. This supplies oxygen to the oxide 230, thereby eliminating oxygen vacancies (V O) can be reduced. The heat treatment may be performed under reduced pressure. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas after the heat treatment in a nitrogen gas or inert gas atmosphere to compensate for the desorbed oxygen. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas, and then the heat treatment may be performed in a nitrogen gas or inert gas atmosphere.

[0114] By subjecting the oxide 230 to oxygen addition treatment, oxygen vacancies in the oxide 230 are repaired by the supplied oxygen. In other words, O Furthermore, the reaction of the hydrogen remaining in the oxide 230 with the supplied oxygen can be removed as H2O (dehydration). As a result, the hydrogen remaining in the oxide 230 recombines with the oxygen vacancies to form V O The formation of H can be suppressed.

[0115] The insulators 222 and 224 may have a stacked structure of two or more layers. In this case, the stacked structure is not limited to a stacked structure made of the same material, and may be a stacked structure made of different materials. The insulator 224 may be formed in an island shape by overlapping with the oxide 230a. In this case, the insulator 275 is configured to contact the side surface of the insulator 224 and the top surface of the insulator 222.

[0116] An oxide 243a and an oxide 243b are provided on the oxide 230b. The oxide 243a and the oxide 243b are provided to be spaced apart with the conductor 260 interposed therebetween.

[0117] The oxide 243 (oxide 243a and oxide 243b) preferably has a function of suppressing oxygen permeation. By disposing the oxide 243, which has a function of suppressing oxygen permeation, between the conductor 242, which functions as a source electrode or a drain electrode, and the oxide 230b, the electrical resistance between the conductor 242 and the oxide 230b is reduced, which is preferable. This structure can improve the electrical characteristics and reliability of the transistor 200. Note that if the electrical resistance between the conductor 242 and the oxide 230b can be sufficiently reduced, the oxide 243 may not be provided.

[0118] A metal oxide containing element M may be used as oxide 243. In particular, element M may be aluminum, gallium, yttrium, or tin. Preferably, oxide 243 has a higher concentration of element M than oxide 230b. Alternatively, oxide 243 may be gallium oxide. Alternatively, oxide 243 may be a metal oxide such as In-M-Zn oxide. Specifically, the atomic ratio of element M to In in the metal oxide used for oxide 243 is preferably greater than the atomic ratio of element M to In in the metal oxide used for oxide 230b. Furthermore, the film thickness of oxide 243 is preferably 0.5 nm to 5 nm, more preferably 1 nm to 3 nm, and even more preferably 1 nm to 2 nm. Furthermore, oxide 243 preferably has crystallinity. When oxide 243 has crystallinity, oxygen release from oxide 230 can be effectively suppressed. For example, oxide 243 with a hexagonal or other crystal structure may be able to suppress oxygen release from oxide 230.

[0119] The conductor 242a is preferably provided in contact with the top surface of the oxide 243a, and the conductor 242b is preferably provided in contact with the top surface of the oxide 243b. The conductor 242a and the conductor 242b function as a source electrode and a drain electrode of the transistor 200, respectively.

[0120] As the conductor 242 (conductor 242a and conductor 242b), it is preferable to use, for example, a nitride containing tantalum, a nitride containing titanium, a nitride containing molybdenum, a nitride containing tungsten, a nitride containing tantalum and aluminum, or a nitride containing titanium and aluminum. In one embodiment of the present invention, a nitride containing tantalum is particularly preferable. Also, for example, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel may be used. These materials are preferable because they are conductive materials that are resistant to oxidation or that maintain conductivity even when they absorb oxygen.

[0121] Note that hydrogen contained in the oxide 230b and the like may diffuse into the conductor 242a or the conductor 242b. In particular, by using a nitride containing tantalum for the conductor 242a and the conductor 242b, hydrogen contained in the oxide 230b and the like is likely to diffuse into the conductor 242a or the conductor 242b, and the diffused hydrogen may bond with nitrogen contained in the conductor 242a or the conductor 242b. In other words, hydrogen contained in the oxide 230b and the like may be absorbed by the conductor 242a or the conductor 242b.

[0122] Preferably, no curved surface is formed between the side surface of the conductor 242 and the top surface of the conductor 242. By forming the conductor 242 without such a curved surface, the cross-sectional area of ​​the conductor 242 in the cross section in the channel width direction can be increased, as shown in FIG. 1D. This increases the conductivity of the conductor 242 and the on-state current of the transistor 200.

[0123] The insulator 271a is provided in contact with the top surface of the conductor 242a, and the insulator 271b is provided in contact with the top surface of the conductor 242b. The insulator 271 preferably functions as a barrier insulating film against oxygen. Therefore, the insulator 271 preferably has a function of suppressing oxygen diffusion. For example, the insulator 271 preferably has a function of suppressing oxygen diffusion more than the insulator 280. For example, a nitride containing silicon, such as silicon nitride, may be used as the insulator 271. The insulator 271 preferably has a function of capturing impurities such as hydrogen. In this case, the insulator 271 may be an insulator such as a metal oxide having an amorphous structure, such as aluminum oxide or magnesium oxide. In particular, using aluminum oxide having an amorphous structure or aluminum oxide having an amorphous structure as the insulator 271 is preferable because it may be able to more effectively capture or fix hydrogen. This enables the manufacture of a transistor 200 and a semiconductor device with excellent characteristics and high reliability.

[0124] The insulator 273a is provided in contact with the top surface of the insulator 271a, and the insulator 273b is provided in contact with the top surface of the insulator 271b. Preferably, the top surface of the insulator 273a is in contact with the insulator 275, and a side surface of the insulator 273a is in contact with the insulator 250. Preferably, the top surface of the insulator 273b is in contact with the insulator 275, and a side surface of the insulator 273b is in contact with the insulator 250. Like the insulator 224, the insulator 273 preferably has an excess oxygen region or excess oxygen. Preferably, the insulator 273 has a reduced concentration of impurities such as water and hydrogen. For example, the insulator 273 may be formed using an oxide or nitride containing silicon, such as silicon oxide, silicon oxynitride, silicon nitride, or silicon nitride oxide, as appropriate. By providing an insulator containing excess oxygen in contact with insulator 250, oxygen diffused into oxide 230 through insulator 250 can reduce oxygen vacancies in oxide 230 and improve the reliability of transistor 200.

[0125] Note that if sufficient oxygen can be supplied to the oxide 230 from the insulator 224 and the insulator 280, the insulator 273 may not be provided.

[0126] The insulator 272a is provided in contact with side surfaces of the oxide 230a, the oxide 230b, the oxide 243a, the conductor 242a, the insulator 271a, and the insulator 273a. The insulator 272b is provided in contact with side surfaces of the oxide 230a, the oxide 230b, the oxide 243b, the conductor 242b, the insulator 271b, and the insulator 273b. The insulators 272a and 272b are provided in contact with the top surface of the insulator 224. The insulator 272 preferably functions as a barrier insulating film against oxygen. Therefore, the insulator 272 preferably has a function of suppressing oxygen diffusion. For example, the insulator 272 preferably has a function of suppressing oxygen diffusion more than the insulator 280. For example, a nitride containing silicon, such as silicon nitride, may be used as the insulator 272.

[0127] By providing the insulators 271 and 272 as described above, the conductor 242 can be surrounded by an insulator that has a barrier property against oxygen. In other words, oxygen added when the insulator 275 is formed or oxygen contained in the insulator 273 can be prevented from diffusing into the conductor 242. This makes it possible to suppress the conductor 242 from being directly oxidized by oxygen added when the insulator 275 is formed or oxygen contained in the insulator 273, which would increase the resistivity and reduce the on-current.

[0128] 1B and other figures show a configuration in which insulator 272 is in contact with the side surfaces of oxide 230a, oxide 230b, oxide 243, conductor 242, insulator 271, and insulator 273, but insulator 272 only needs to be in contact with the side surfaces of at least insulator 271 and conductor 242. For example, there may be a configuration in which insulator 272 is in contact with the side surfaces of oxide 230a, oxide 230b, oxide 243, conductor 242, and insulator 271, but is not in contact with insulator 273. In this case, the side surface of insulator 273 is in contact with insulator 275.

[0129] Note that if the insulator 275 has sufficient barrier properties against oxygen and the like, one or both of the insulators 271 and 272 may be omitted.

[0130] The insulator 275 covers the insulators 224, 272, and 273, and has openings in the regions where the insulator 250 and the conductor 260 are provided. The insulator 275 is preferably provided in contact with the top surface of the insulator 224, the side surface of the insulator 272, and the top surface of the insulator 273. The insulator 275 preferably functions as a barrier insulating film that suppresses oxygen permeation. The insulator 275 preferably functions as a barrier insulating film that suppresses impurities such as water and hydrogen from diffusing from above into the insulator 224 or the insulator 273, and preferably has a function of capturing impurities such as hydrogen. In this case, the insulator 275 preferably includes an insulator such as a metal oxide having an amorphous structure, such as aluminum oxide or magnesium oxide. The insulator 275 may be, for example, a single layer or a stack of insulators such as aluminum oxide and silicon nitride. When aluminum oxide and silicon nitride are stacked as the insulator 275, it is preferable to provide the aluminum oxide in contact with the insulators 224, 272, and 273, and to provide silicon nitride on the aluminum oxide. When the insulator 272 is not provided, the insulator 275 is in contact with the side surfaces of the oxide 230a, the oxide 230b, the oxide 243, the conductor 242, and the insulator 271. When aluminum oxide is used for at least a portion of the insulator 275, it is preferable that the aluminum oxide be aluminum oxide having an amorphous structure or aluminum oxide having an amorphous structure. Metal oxides having an amorphous structure, particularly aluminum oxide having an amorphous structure and aluminum oxide having an amorphous structure, can sometimes capture or fix hydrogen present in the surrounding area, thereby enabling the manufacture of a transistor 200 and a semiconductor device with excellent characteristics and high reliability.

[0131] By providing an insulator 275 that has the function of capturing impurities such as hydrogen and is in contact with the insulator 280, the insulator 224, or the insulator 273 in the region sandwiched between the insulator 212 and the insulator 283, the impurities such as hydrogen contained in the insulator 280, the insulator 224, the insulator 273, or the like can be captured, and the amount of hydrogen in the region can be kept constant. In this case, it is preferable to use aluminum oxide or the like as the insulator 275.

[0132] The insulator 250 functions as a gate insulator. The insulator 250 is preferably disposed in contact with the upper surface of the oxide 230b. The insulator 250 can be made of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, silicon oxide having vacancies, or the like. Silicon oxide and silicon oxynitride are particularly preferred because they are stable against heat.

[0133] The insulator 250 preferably has a reduced concentration of impurities such as water and hydrogen, similar to the insulator 224. The thickness of the insulator 250 is preferably 1 nm or more and 20 nm or less.

[0134] Although the insulator 250 is illustrated as a single layer in FIGS. 1B and 1C, it may have a laminated structure of two or more layers. When the insulator 250 has a laminated structure of two layers, it is preferable that the lower layer of the insulator 250 is formed using an insulator that releases oxygen when heated, and the upper layer of the insulator 250 is formed using an insulator that has the function of suppressing oxygen diffusion. This configuration can suppress the diffusion of oxygen contained in the lower layer of the insulator 250 into the conductor 260. In other words, it can suppress a decrease in the amount of oxygen supplied to the oxide 230. It can also suppress oxidation of the conductor 260 due to oxygen contained in the lower layer of the insulator 250. For example, the lower layer of the insulator 250 can be formed using a material that can be used for the insulator 250 described above, and the upper layer of the insulator 250 can be formed using a material similar to that of the insulator 222.

[0135] When silicon oxide or silicon oxynitride is used for the lower layer of the insulator 250, the upper layer of the insulator 250 may be made of an insulating material, such as a high-k material with a high dielectric constant. By forming the gate insulator into a laminated structure of the lower layer of the insulator 250 and the upper layer of the insulator 250, a laminated structure that is stable against heat and has a high dielectric constant can be achieved. This makes it possible to reduce the gate potential applied during transistor operation while maintaining the physical thickness of the gate insulator. It also makes it possible to reduce the equivalent oxide thickness (EOT) of the insulator that functions as the gate insulator.

[0136] Specifically, the upper layer of the insulator 250 can be a metal oxide containing one or more elements selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, etc., or a metal oxide that can be used as the oxide 230. In particular, it is preferable to use an insulator containing an oxide of one or both of aluminum and hafnium. For example, the insulator 250 can be a stacked structure containing silicon oxide and hafnium oxide on the silicon oxide.

[0137] Furthermore, a metal oxide may be provided between the insulator 250 and the conductor 260. The metal oxide preferably suppresses the diffusion of oxygen from the insulator 250 to the conductor 260. By providing a metal oxide that suppresses the diffusion of oxygen, the diffusion of oxygen from the insulator 250 to the conductor 260 is suppressed. In other words, a decrease in the amount of oxygen supplied to the oxide 230 can be suppressed. Furthermore, oxidation of the conductor 260 by oxygen from the insulator 250 can be suppressed.

[0138] The metal oxide may function as part of the first gate electrode. For example, the metal oxide that can be used as the oxide 230 may be used as the metal oxide. In this case, the electrical conductor 260a may be formed by sputtering to reduce the electrical resistance of the metal oxide, thereby making it a conductor. This may be called an OC (Oxide Conductor) electrode.

[0139] The inclusion of the metal oxide can improve the on-state current of the transistor 200 without weakening the influence of the electric field from the conductor 260. Furthermore, the physical thickness of the insulator 250 and the metal oxide can maintain a distance between the conductor 260 and the oxide 230, thereby suppressing leakage current between the conductor 260 and the oxide 230. Furthermore, the provision of a stacked structure of the insulator 250 and the metal oxide can easily and appropriately adjust the physical distance between the conductor 260 and the oxide 230 and the electric field strength applied from the conductor 260 to the oxide 230.

[0140] The conductor 260 functions as a first gate electrode of the transistor 200. The conductor 260 preferably includes a conductor 260a and a conductor 260b disposed on the conductor 260a. For example, the conductor 260a is preferably disposed so as to surround the bottom and side surfaces of the conductor 260b. As shown in FIGS. 1B and 1C, the top of the upper surface of the conductor 260 is substantially aligned with the top of the upper surface of the insulator 250. Although the conductor 260 is shown in FIGS. 1B and 1C as having a two-layer structure of the conductor 260a and the conductor 260b, it may have a single-layer structure or a stacked structure of three or more layers.

[0141] The conductor 260a is preferably made of a conductive material that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, copper atoms, etc. Alternatively, it is preferably made of a conductive material that has the function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.).

[0142] Furthermore, since the conductor 260a has the function of suppressing oxygen diffusion, it is possible to suppress a decrease in conductivity due to oxidation of the conductor 260b caused by oxygen contained in the insulator 250. As a conductive material having the function of suppressing oxygen diffusion, it is preferable to use, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, or ruthenium oxide.

[0143] Furthermore, since the conductor 260 also functions as wiring, it is preferable to use a conductor with high conductivity. For example, the conductor 260b can be made of a conductive material containing tungsten, copper, or aluminum as a main component. The conductor 260b may also have a layered structure, such as a layered structure of titanium or titanium nitride and the above-mentioned conductive material.

[0144] Furthermore, in the transistor 200, the conductor 260 is formed in a self-aligned manner so as to fill an opening formed in the insulator 280 or the like. By forming the conductor 260 in this manner, the conductor 260 can be reliably placed in the region between the conductor 242a and the conductor 242b without alignment.

[0145] 1C , in the channel width direction of the transistor 200, the height of the bottom surface of the conductor 260 in a region where the conductor 260 and the oxide 230b do not overlap is preferably lower than the height of the bottom surface of the oxide 230b, relative to the bottom surface of the insulator 222. The conductor 260, which functions as a gate electrode, covers the side and top surfaces of the channel formation region of the oxide 230b via the insulator 250 or the like, making it easier for the electric field of the conductor 260 to act on the entire channel formation region of the oxide 230b. This increases the on-state current of the transistor 200 and improves its frequency characteristics. The difference between the height of the bottom surface of the conductor 260 and the height of the bottom surface of the oxide 230b in a region where the oxides 230a and 230b do not overlap with the conductor 260, relative to the bottom surface of the insulator 222, is 0 nm or more and 100 nm or less, preferably 3 nm or more and 50 nm or less, and more preferably 5 nm or more and 20 nm or less.

[0146] The insulator 280 is provided on the insulator 275, and openings are formed in the regions where the insulator 250 and the conductor 260 are to be provided. The top surface of the insulator 280 may be flattened.

[0147] The insulator 280, which functions as an interlayer film, preferably has a low dielectric constant. Using a material with a low dielectric constant as the interlayer film can reduce the parasitic capacitance that occurs between wirings. The insulator 280 is preferably formed using, for example, the same material as the insulator 216. In particular, silicon oxide and silicon oxynitride are preferred because they are thermally stable. In particular, materials such as silicon oxide, silicon oxynitride, and silicon oxide with vacancies are preferred because they can easily form regions containing oxygen that is released by heating.

[0148] Like the insulator 224, the insulator 280 preferably has an excess oxygen region or excess oxygen. Furthermore, the concentrations of impurities such as water and hydrogen in the insulator 280 are preferably reduced. For example, the insulator 280 may be formed using an oxide containing silicon, such as silicon oxide or silicon oxynitride, as appropriate. By providing an insulator having excess oxygen in contact with the oxide 230, oxygen vacancies in the oxide 230 can be reduced, and the reliability of the transistor 200 can be improved.

[0149] The insulator 282 preferably functions as a barrier insulating film that suppresses the diffusion of impurities such as water and hydrogen from above into the insulator 280 and preferably has a function of capturing impurities such as hydrogen. The insulator 282 also preferably functions as a barrier insulating film that suppresses oxygen permeation. The insulator 282 may be an insulator made of a metal oxide having an amorphous structure, such as aluminum oxide. By providing the insulator 282, which is in contact with the insulator 280 and has a function of capturing impurities such as hydrogen, in the region sandwiched between the insulator 212 and the insulator 283, the insulator 282 can capture impurities such as hydrogen contained in the insulator 280 and maintain a constant amount of hydrogen in the region. In particular, using aluminum oxide having an amorphous structure or aluminum oxide having an amorphous structure as the insulator 282 is preferable because it may be able to capture or fix hydrogen more effectively. This enables the manufacture of a highly reliable transistor 200 and semiconductor device with excellent characteristics.

[0150] The insulator 283 functions as a barrier insulating film that prevents impurities such as water and hydrogen from diffusing from above into the insulator 280. The insulator 283 is disposed on the insulator 282. It is preferable to use a nitride containing silicon, such as silicon nitride or silicon nitride oxide, as the insulator 283. For example, silicon nitride formed by a sputtering method can be used as the insulator 283. By forming the insulator 283 by a sputtering method, a silicon nitride film that is high in density and less likely to form voids can be formed. Alternatively, the insulator 283 may be formed by stacking a silicon nitride film formed by a CVD method on a silicon nitride film formed by a sputtering method.

[0151] The conductors 240a and 240b are preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. The conductors 240a and 240b may have a layered structure.

[0152] Furthermore, when the conductor 240 has a layered structure, it is preferable to use a conductive material that has the function of suppressing the permeation of impurities such as water and hydrogen for the conductors in contact with the insulators 283, 282, 280, 275, 273, and 271. For example, it is preferable to use tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, or ruthenium oxide. Furthermore, the conductive material that has the function of suppressing the permeation of impurities such as water and hydrogen may be used in a single layer or a layered structure. Furthermore, it is possible to suppress impurities such as water and hydrogen contained in layers above the insulator 283 from mixing into the oxide 230 through the conductors 240a and 240b.

[0153] The insulators 241a and 241b may be made of, for example, silicon nitride, aluminum oxide, or silicon nitride oxide. The insulators 241a and 241b are provided in contact with the insulators 283, 282, 275, and 271, and thus can prevent impurities such as water and hydrogen contained in the insulator 280 from entering the oxide 230 through the conductors 240a and 240b. Silicon nitride is particularly suitable because it has a high barrier property against hydrogen. Furthermore, it can prevent oxygen contained in the insulator 280 from being absorbed by the conductors 240a and 240b.

[0154] Conductors 246 (conductors 246a and 246b) may be disposed in contact with the upper surfaces of the conductors 240a and 240b, functioning as wiring. Conductor 246 is preferably made of a conductive material containing tungsten, copper, or aluminum as its main component. The conductor may have a layered structure, for example, a layered structure of titanium or titanium nitride and the above-mentioned conductive material. The conductor may be formed so as to be embedded in an opening provided in an insulator.

[0155] The insulator 286 is provided on the conductor 246 and on the insulator 283. As a result, the upper surface and side surfaces of the conductor 246 contact the insulator 286, and the lower surface of the conductor 246 contacts the insulator 283. In other words, the conductor 246 can be configured to be surrounded by the insulators 283 and 286. This configuration can suppress the permeation of oxygen from the outside and prevent oxidation of the conductor 246. This is also preferable because it can prevent impurities such as water and hydrogen from diffusing from the conductor 246 to the outside.

[0156] <Materials for semiconductor devices> The following describes constituent materials that can be used in semiconductor devices.

[0157] <<Substrate>> The substrate on which the transistor 200 is formed may be, for example, an insulating substrate, a semiconductor substrate, or a conductive substrate. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (e.g., yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, and gallium oxide. Examples of semiconductor substrates include those having an insulating region within the semiconductor substrate, such as an SOI (Silicon-On-Insulator) substrate. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Other examples include substrates having a metal nitride and a metal oxide. Examples of other substrates include a substrate in which a conductor or semiconductor is provided on an insulating substrate, a substrate in which a conductor or insulator is provided on a semiconductor substrate, and a substrate in which a semiconductor or insulator is provided on a conductive substrate. Alternatively, a substrate provided with elements may be used, such as a capacitor element, a resistor element, a switch element, a light-emitting element, a memory element, and the like.

[0158] <<Insulators>> Examples of the insulator include oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, and metal nitride oxides, all of which have insulating properties.

[0159] For example, as transistors become more miniaturized and highly integrated, thinner gate insulators can cause problems such as leakage current. Using a high-k material for the gate insulator allows for lower voltage operation of the transistor while maintaining the physical film thickness. On the other hand, using a material with a low dielectric constant for the interlayer insulator can reduce the parasitic capacitance between wiring. Therefore, it is best to select materials based on the insulator's function.

[0160] Furthermore, examples of insulators with a high relative dielectric constant include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0161] Examples of insulators with a low dielectric constant include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with fluorine added, silicon oxide with carbon added, silicon oxide with carbon and nitrogen added, silicon oxide with voids, and resin.

[0162] Furthermore, a transistor using a metal oxide can have stable electrical characteristics by being surrounded by an insulator that has a function of suppressing the permeation of impurities such as hydrogen and oxygen. Examples of insulators that have a function of suppressing the permeation of impurities such as hydrogen and oxygen include insulators containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum, and can be used in a single layer or a stacked layer. Specifically, examples of insulators that have a function of suppressing the permeation of impurities such as hydrogen and oxygen include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, and metal nitrides such as aluminum nitride, silicon nitride oxide, and silicon nitride.

[0163] The insulator functioning as the gate insulator is preferably an insulator having a region containing oxygen that is released by heating. For example, by using a structure in which silicon oxide or silicon oxynitride having a region containing oxygen that is released by heating is in contact with the oxide 230, oxygen vacancies in the oxide 230 can be compensated for.

[0164] <<Conductors>> The conductor is preferably a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above metal elements as a component, or an alloy combining the above metal elements. For example, tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. Furthermore, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferred because they are conductive materials that are resistant to oxidation or maintain conductivity even when absorbing oxygen. Furthermore, semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicide may also be used.

[0165] Furthermore, a plurality of conductive layers formed from the above materials may be stacked. For example, a stacked structure may be formed by combining the above-described material containing a metal element and a conductive material containing oxygen. A stacked structure may be formed by combining the above-described material containing a metal element and a conductive material containing nitrogen. A stacked structure may be formed by combining the above-described material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen.

[0166] When an oxide is used for the channel formation region of a transistor, a conductor functioning as a gate electrode preferably has a stacked structure in which a material containing the metal element and a conductive material containing oxygen are combined. In this case, the conductive material containing oxygen is preferably provided on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen released from the conductive material is easily supplied to the channel formation region.

[0167] In particular, as a conductor functioning as a gate electrode, it is preferable to use a conductive material containing oxygen and a metal element contained in the metal oxide in which the channel is formed. Alternatively, a conductive material containing the aforementioned metal element and nitrogen may be used. For example, a conductive material containing nitrogen, such as titanium nitride or tantalum nitride, may be used. Alternatively, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide doped with silicon may be used. Furthermore, indium gallium zinc oxide containing nitrogen may be used. Using such a material may allow hydrogen contained in the metal oxide in which the channel is formed to be captured. Alternatively, hydrogen introduced from an external insulator or the like may be captured.

[0168] <<Metal oxides>> It is preferable to use a metal oxide (oxide semiconductor) that functions as a semiconductor as the oxide 230. Hereinafter, metal oxides that can be used as the oxide 230 and the oxide 243 according to the present invention will be described.

[0169] The metal oxide preferably contains at least indium or zinc. It is particularly preferable that it contains indium and zinc. It is also preferable that it contains aluminum, gallium, yttrium, tin, or the like in addition to these. It may also contain one or more elements selected from boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, and the like.

[0170] Here, we consider a case where the metal oxide is an In-M-Zn oxide containing indium, element M, and zinc. The element M is aluminum, gallium, yttrium, or tin. Other elements that can be used for element M include boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and cobalt. However, there are cases where a combination of the aforementioned elements can be used as element M.

[0171] In this specification and the like, nitrogen-containing metal oxides may also be collectively referred to as metal oxides. Nitrogen-containing metal oxides may also be referred to as metal oxynitrides.

[0172] <Classification of crystal structures> First, classification of crystal structures in oxide semiconductors will be explained using Fig. 3A. Fig. 3A is a diagram for explaining classification of crystal structures of oxide semiconductors, typically IGZO (metal oxide containing In, Ga, and Zn).

[0173] As shown in FIG. 3A, oxide semiconductors are broadly classified into "amorphous," "crystalline," and "crystal." "Amorphous" includes completely amorphous. "Crystalline" includes c-axis-aligned crystalline (CAAC), nanocrystalline (nc), and cloud-aligned composite (CAC) (excluding single crystal and polycrystal). "Crystalline" excludes single crystal, polycrystal, and completely amorphous. "Crystalline" includes single crystal and polycrystal.

[0174] The structure within the bold frame in Figure 3A is an intermediate state between "amorphous" and "crystal," and is a structure that belongs to a new boundary region (new crystalline phase). In other words, this structure can be described as a structure that is completely different from the energetically unstable "amorphous" or "crystal."

[0175] The crystalline structure of a film or substrate can be evaluated using X-ray diffraction (XRD) spectroscopy. Figure 3B shows the XRD spectrum obtained by GIXD (Grazing-Incidence XRD) measurement of a CAAC-IGZO film classified as "Crystalline." The GIXD method is also known as the thin-film method or the Seemann-Bohlin method. Hereafter, the XRD spectrum obtained by GIXD measurement shown in Figure 3B will simply be referred to as the XRD spectrum. The composition of the CAAC-IGZO film shown in Figure 3B is approximately In:Ga:Zn = 4:2:3 [atomic ratio]. The thickness of the CAAC-IGZO film shown in Figure 3B is 500 nm.

[0176] As shown in Figure 3B, a clear peak indicating crystallinity is detected in the XRD spectrum of the CAAC-IGZO film. Specifically, a peak indicating c-axis orientation is detected near 2θ=31° in the XRD spectrum of the CAAC-IGZO film. Furthermore, as shown in Figure 3B, the peak near 2θ=31° is asymmetrical with respect to the angle at which the peak intensity is detected.

[0177] The crystalline structure of a film or substrate can be evaluated by the diffraction pattern (also called the nanobeam electron diffraction pattern) observed using nanobeam electron diffraction (NBED). Figure 3C shows the diffraction pattern of a CAAC-IGZO film. Figure 3C shows a diffraction pattern observed using NBED, in which an electron beam is incident parallel to the substrate. The composition of the CAAC-IGZO film shown in Figure 3C is approximately In:Ga:Zn = 4:2:3 [atomic ratio]. In the nanobeam electron diffraction method, electron diffraction is performed using a probe diameter of 1 nm.

[0178] As shown in Figure 3C, multiple spots indicating c-axis orientation are observed in the diffraction pattern of the CAAC-IGZO film.

[0179] <<Oxide semiconductor structure>> Note that oxide semiconductors may be classified differently from that shown in FIG. 3A when focusing on their crystal structures. For example, oxide semiconductors are divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. Examples of non-single-crystal oxide semiconductors include the above-mentioned CAAC-OS and nc-OS. Non-single-crystal oxide semiconductors include polycrystalline oxide semiconductors, amorphous-like oxide semiconductors (a-like OSs), amorphous oxide semiconductors, and the like.

[0180] Here, the above-mentioned CAAC-OS, nc-OS, and a-like OS will be described in detail.

[0181] [CAAC-OS] CAAC-OS is an oxide semiconductor having multiple crystalline regions, each with its c-axis aligned in a specific direction. The specific direction can be the thickness direction of the CAAC-OS film, the normal direction to the surface on which the CAAC-OS film is formed, or the normal direction to the surface of the CAAC-OS film. A crystalline region is a region with periodic atomic arrangement. If the atomic arrangement is considered as a lattice arrangement, a crystalline region can also be a region with a uniform lattice arrangement. Furthermore, CAAC-OS has a region where multiple crystalline regions are connected in the ab-plane direction, and the region may have distortion. Note that distortion refers to a location where the lattice arrangement changes between a region with a uniform lattice arrangement and a region with a different uniform lattice arrangement in the region where multiple crystalline regions are connected. In other words, CAAC-OS is an oxide semiconductor with a c-axis aligned but no clear orientation in the ab-plane direction.

[0182] Each of the multiple crystalline regions is composed of one or more minute crystals (crystals with a maximum diameter of less than 10 nm). When a crystalline region is composed of one minute crystal, the maximum diameter of the crystalline region is less than 10 nm. When a crystalline region is composed of many minute crystals, the size of the crystalline region may be several tens of nm.

[0183] In an In-M-Zn oxide (wherein M is one or more elements selected from aluminum, gallium, yttrium, tin, titanium, etc.), the CAAC-OS tends to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium (In) and oxygen (hereinafter referred to as an In layer) and a layer containing M, zinc (Zn), and oxygen (hereinafter referred to as an (M, Zn) layer) are stacked. Note that indium and the element M are mutually substituted. Therefore, the (M, Zn) layer may contain indium. The In layer may contain M. The In layer may contain Zn. The layered structure is observed as a lattice image in a high-resolution TEM image, for example.

[0184] When the CAAC-OS film is subjected to structural analysis using, for example, an XRD apparatus, a peak indicating c-axis orientation is detected at or near 2θ=31° in out-of-plane XRD measurement using θ / 2θ scan. Note that the position of the peak indicating c-axis orientation (2θ value) may vary depending on the type and composition of the metallic elements constituting the CAAC-OS.

[0185] Furthermore, for example, in the electron diffraction pattern of the CAAC-OS film, multiple bright spots are observed, and the spots are observed at positions that are point-symmetric with respect to the spot of the incident electron beam that has passed through the sample (also called the direct spot).

[0186] When the crystalline region is observed from the specific direction, the lattice arrangement within the crystalline region is basically a hexagonal lattice, but the unit cell is not necessarily a regular hexagon and may be non-regular hexagonal. Furthermore, the distortion may have a pentagonal, heptagonal, or other lattice arrangement. In the CAAC-OS, no clear grain boundaries are observed even near the distortion. This indicates that the formation of grain boundaries is suppressed by the distortion of the lattice arrangement. This is thought to be because the CAAC-OS can tolerate distortion due to the lack of close-packed oxygen atom arrangement in the ab-plane direction and the change in interatomic bond distance caused by metal atom substitution.

[0187] A crystal structure with clear grain boundaries is called polycrystalline. Grain boundaries act as recombination centers, trapping carriers and potentially causing a decrease in the on-state current and field-effect mobility of a transistor. Therefore, CAAC-OS, which lacks clear grain boundaries, is one of the crystalline oxides with a crystal structure suitable for use in the semiconductor layer of a transistor. Zn is preferred for use in CAAC-OS. For example, In-Zn oxide and In-Ga-Zn oxide are suitable because they can suppress the generation of grain boundaries more effectively than In oxide.

[0188] CAAC-OS is an oxide semiconductor with high crystallinity and no clear grain boundaries. Therefore, it can be said that the CAAC-OS is less susceptible to a decrease in electron mobility due to grain boundaries. Furthermore, since the crystallinity of an oxide semiconductor can be reduced by impurities or defects, the CAAC-OS can be said to be an oxide semiconductor with few impurities or defects (such as oxygen vacancies). Therefore, oxide semiconductors with CAAC-OS have stable physical properties. Therefore, oxide semiconductors with CAAC-OS are heat-resistant and highly reliable. Furthermore, the CAAC-OS is stable even under high temperatures (so-called thermal budget) during the manufacturing process. Therefore, using a CAAC-OS for an OS transistor can increase the flexibility of the manufacturing process.

[0189] [nc-OS] The nc-OS has periodic atomic arrangement in a microscopic region (e.g., a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). In other words, the nc-OS has microcrystalline structures. The size of the microcrystalline structures is, for example, 1 nm to 10 nm, particularly 1 nm to 3 nm, and therefore these microcrystalline structures are also called nanocrystalline structures. Furthermore, the nc-OS exhibits no regularity in the crystal orientation between different nanocrystalline structures. Therefore, the entire film lacks orientation. Therefore, depending on the analytical method, the nc-OS may be indistinguishable from an a-like OS or an amorphous oxide semiconductor. For example, when a structural analysis of an nc-OS film is performed using an XRD system, no peaks indicating crystallinity are detected in out-of-plane XRD measurements using θ / 2θ scanning. Furthermore, when an nc-OS film is subjected to electron diffraction (also known as selected-area electron diffraction) using an electron beam with a probe diameter larger than that of nanocrystalline structures (e.g., 50 nm or larger), a halo-like diffraction pattern is observed. On the other hand, when electron diffraction (also called nanobeam electron diffraction) is performed on an nc-OS film using an electron beam with a probe diameter close to or smaller than the size of the nanocrystals (for example, 1 nm to 30 nm), an electron diffraction pattern can be obtained in which multiple spots are observed within a ring-shaped region centered on the direct spot.

[0190] [a-like OS] The a-like OS is an oxide semiconductor having a structure between the nc-OS and the amorphous oxide semiconductor. The a-like OS has a pore or low-density region. That is, the a-like OS has lower crystallinity than the nc-OS and CAAC-OS. Furthermore, the a-like OS has a higher hydrogen concentration in the film than the nc-OS and CAAC-OS.

[0191] <<Oxide semiconductor structure>> Next, the above-mentioned CAC-OS will be described in detail, which relates to the material composition.

[0192] [CAC-OS] CAC-OS is a material structure in which elements constituting a metal oxide are unevenly distributed in a size range of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or a similar size range. Hereinafter, a metal oxide in which one or more metal elements are unevenly distributed and the regions containing the metal elements are mixed in a size range of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or a similar size range, is also referred to as a mosaic or patch state.

[0193] Furthermore, CAC-OS has a mosaic structure in which the material is separated into first and second regions, and the first regions are distributed throughout the film (also called a cloud structure). That is, CAC-OS is a composite metal oxide having a structure in which the first and second regions are mixed.

[0194] Here, the atomic ratios of In, Ga, and Zn to the metal elements constituting the CAC-OS in the In-Ga-Zn oxide are denoted as [In], [Ga], and [Zn], respectively. For example, in the CAC-OS in the In-Ga-Zn oxide, the first region is a region where [In] is larger than [In] in the composition of the CAC-OS film. The second region is a region where [Ga] is larger than [Ga] in the composition of the CAC-OS film. Alternatively, for example, the first region is a region where [In] is larger than [In] in the second region and [Ga] is smaller than [Ga] in the second region. The second region is a region where [Ga] is larger than [Ga] in the first region and [In] is smaller than [In] in the first region.

[0195] Specifically, the first region is a region whose main component is indium oxide, indium zinc oxide, or the like. The second region is a region whose main component is gallium oxide, gallium zinc oxide, or the like. In other words, the first region can be rephrased as a region whose main component is In. The second region can be rephrased as a region whose main component is Ga.

[0196] It should be noted that there are cases where a clear boundary between the first region and the second region cannot be observed.

[0197] For example, in the case of CAC-OS in In-Ga-Zn oxide, EDX mapping obtained using EDX (Energy Dispersive X-ray spectroscopy) confirms that the CAC-OS has a structure in which a region mainly composed of In (first region) and a region mainly composed of Ga (second region) are unevenly distributed and mixed.

[0198] When CAC-OS is used in a transistor, the conductivity due to the first region and the insulating property due to the second region act in a complementary manner, thereby providing the CAC-OS with a switching function (the ability to turn on and off). In other words, CAC-OS has a conductive function in part of the material and an insulating function in part of the material, and the material as a whole functions as a semiconductor. By separating the conductive function from the insulating function, both functions can be maximized. Therefore, by using CAC-OS in a transistor, a high on-current (I on ), high field-effect mobility (μ), and good switching behavior can be achieved.

[0199] Oxide semiconductors have a variety of structures, each with different characteristics. The oxide semiconductor of one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, a CAC-OS, an nc-OS, and a CAAC-OS.

[0200] <Transistors containing oxide semiconductors> Next, a case where the oxide semiconductor is used in a transistor will be described.

[0201] By using the oxide semiconductor for a transistor, a transistor with high field-effect mobility and high reliability can be realized.

[0202] An oxide semiconductor with a low carrier concentration is preferably used for a channel formation region of a transistor. For example, the carrier concentration of the channel formation region of an oxide semiconductor is 1×10 17 cm -3 Less than 1 × 10 15 cm -3 or less, more preferably 1 × 10 13 cm -3 Less than 1×10, more preferably 11 cm -3 or less, more preferably 1 × 10 10 cm -3Less than 1 x 10 -9 cm -3 The above is the case. Note that in order to reduce the carrier concentration of an oxide semiconductor film, the impurity concentration in the oxide semiconductor film may be reduced to reduce the density of defect states. In this specification and the like, a semiconductor having a low impurity concentration and a low density of defect states is referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor. Note that an oxide semiconductor having a low carrier concentration may also be referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor.

[0203] Furthermore, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a low density of defect states, and therefore the density of trap states may also be low.

[0204] Furthermore, charges trapped in the trap states of an oxide semiconductor take a long time to disappear and may behave like fixed charges. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor with a high density of trap states may have unstable electrical characteristics.

[0205] Therefore, in order to stabilize the electrical characteristics of a transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. Furthermore, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in the adjacent film. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon.

[0206] <Impurities> Here, the influence of each impurity in an oxide semiconductor will be described.

[0207] When an oxide semiconductor contains silicon or carbon, which is one of the Group 14 elements, defect levels are formed in the oxide semiconductor. Therefore, the concentrations of silicon and carbon in the channel formation region of the oxide semiconductor and the silicon and carbon near the interface with the channel formation region of the oxide semiconductor (concentrations obtained by secondary ion mass spectrometry (SIMS)) are calculated to be 2×10 18atoms / cm 3 Less than or equal to 2 x 10 17 atoms / cm 3 The following applies.

[0208] Furthermore, when an oxide semiconductor contains an alkali metal or alkaline earth metal, defect states may be formed and carriers may be generated. Therefore, a transistor using an oxide semiconductor containing an alkali metal or alkaline earth metal is likely to have normally-on characteristics. For this reason, when the concentration of the alkali metal or alkaline earth metal in the channel formation region of the oxide semiconductor obtained by SIMS is set to 1×10 18 atoms / cm 3 Less than or equal to 2 x 10 16 atoms / cm 3 Do the following:

[0209] Furthermore, when nitrogen is contained in an oxide semiconductor, electrons serving as carriers are generated, the carrier concentration increases, and the semiconductor is likely to become n-type. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor tends to have normally-on characteristics. Alternatively, when nitrogen is contained in an oxide semiconductor, trap states may be formed. As a result, the electrical characteristics of the transistor may become unstable. For this reason, the nitrogen concentration in the channel formation region of an oxide semiconductor obtained by SIMS is set to 5×10 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 Less than 1×10, more preferably 18 atoms / cm 3 Less than 5 × 10, more preferably 17 atoms / cm 3 Do the following:

[0210] Furthermore, hydrogen contained in an oxide semiconductor may react with oxygen bonded to a metal atom to form water, which may form an oxygen vacancy. When hydrogen enters the oxygen vacancy, electrons serving as carriers may be generated. Furthermore, some of the hydrogen may bond with oxygen bonded to a metal atom to generate electrons serving as carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen is likely to have normally-on characteristics. For this reason, it is preferable to reduce the amount of hydrogen in the channel formation region of the oxide semiconductor as much as possible. Specifically, the hydrogen concentration measured by SIMS in the channel formation region of the oxide semiconductor is 1×10 20 atoms / cm 3 Less than 5 x 10 19 atoms / cm 3 less than 1×10 19 atoms / cm 3 less than 5 × 10 18 atoms / cm 3 less than 1×10 18 atoms / cm 3 Make it less than.

[0211] When an oxide semiconductor with sufficiently reduced impurities is used for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0212] <<Other semiconductor materials>> The semiconductor material that can be used for the oxide 230 is not limited to the metal oxides described above. A semiconductor material having a band gap (a semiconductor material that is not a zero-gap semiconductor) may also be used for the oxide 230. For example, it is preferable to use a semiconductor of a simple element such as silicon, a compound semiconductor such as gallium arsenide, or a layered material that functions as a semiconductor (also called an atomic layer material or a two-dimensional material). In particular, it is preferable to use a layered material that functions as a semiconductor.

[0213] In this specification and the like, a layered material is a general term for a group of materials having a layered crystal structure. A layered crystal structure is a structure in which layers formed by covalent bonds or ionic bonds are stacked via bonds weaker than covalent bonds or ionic bonds, such as van der Waals forces. A layered material has high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, a transistor with a large on-current can be provided.

[0214] Layered materials include graphene, silicene, and chalcogenides. Chalcogenides are compounds containing chalcogen. Chalcogen is a general term for elements in Group 16, including oxygen, sulfur, selenium, tellurium, polonium, and livermorium. Chalcogenides also include transition metal chalcogenides and Group 13 chalcogenides.

[0215] It is preferable to use, for example, a transition metal chalcogenide that functions as a semiconductor as the oxide 230. Specific examples of transition metal chalcogenides that can be used as the oxide 230 include molybdenum sulfide (typically MoS2), molybdenum selenide (typically MoSe2), molybdenum tellurium (typically MoTe2), tungsten sulfide (typically WS2), tungsten selenide (typically WSe2), tungsten tellurium (typically WTe2), hafnium sulfide (typically HfS2), hafnium selenide (typically HfSe2), zirconium sulfide (typically ZrS2), and zirconium selenide (typically ZrSe2).

[0216] <Method for manufacturing semiconductor device> Next, a manufacturing method of the semiconductor device shown in FIGS. 1A to 1D, which is one embodiment of the present invention, will be described with reference to FIGS. 4A to 16A, 4B to 16B, 4C to 16C, and 4D to 16D.

[0217] 4A to 16A are top views. Also, FIGS. 4B to 16B are cross-sectional views corresponding to the portion indicated by the dashed dotted line A1-A2 in FIGS. 4A to 16A, and are also cross-sectional views in the channel length direction of the transistor 200. Also, FIGS. 4C to 16C are cross-sectional views corresponding to the portion indicated by the dashed dotted line A3-A4 in FIGS. 4A to 16A, and are also cross-sectional views in the channel width direction of the transistor 200. Also, FIGS. 4D to 16D are cross-sectional views of the portion indicated by the dashed dotted line A5-A6 in FIGS. 4A to 16A. Note that some elements are omitted from the top views in FIGS. 4A to 16A for clarity.

[0218] In the following, insulating materials for forming insulators, conductive materials for forming conductors, or semiconductor materials for forming semiconductors can be formed as films using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like, as appropriate.

[0219] There are three types of sputtering methods: RF sputtering, which uses a high-frequency power supply for sputtering; DC sputtering, which uses a direct current power supply; and pulsed DC sputtering, which changes the voltage applied to the electrode in a pulsed manner. RF sputtering is mainly used to deposit insulating films, while DC sputtering is mainly used to deposit metal conductive films. Pulsed DC sputtering is mainly used to deposit compounds such as oxides, nitrides, and carbides using reactive sputtering.

[0220] CVD methods can be classified into plasma-enhanced CVD (PECVD), which uses plasma, thermal CVD (TCVD), which uses heat, and photo-CVD (Photo-CVD), which uses light. They can also be further divided into metal CVD (MCVD) and metal-organic CVD (MOCVD), depending on the source gas used.

[0221] The plasma CVD method can produce high-quality films at relatively low temperatures. Furthermore, because the thermal CVD method does not use plasma, it is a film formation method that can minimize plasma damage to the workpiece. For example, wiring, electrodes, elements (transistors, capacitors, etc.) included in a semiconductor device may become charged up by receiving electric charge from the plasma. In this case, the accumulated electric charge may destroy the wiring, electrodes, elements, etc. included in the semiconductor device. On the other hand, the thermal CVD method, which does not use plasma, does not cause such plasma damage, and therefore can increase the yield of semiconductor devices. Furthermore, because the thermal CVD method does not cause plasma damage during film formation, it can produce films with fewer defects.

[0222] As the ALD method, a thermal ALD method in which a reaction between a precursor and a reactant is carried out using only thermal energy, a plasma enhanced ALD method in which a plasma excited reactant is used, or the like can be used.

[0223] Furthermore, the ALD method utilizes the self-regulating properties of atoms to deposit atoms layer by layer, enabling the formation of ultrathin films, films with high aspect ratios, films with fewer defects such as pinholes, films with excellent coverage, and films at low temperatures. The PEALD method utilizes plasma, which can be preferable because it allows film formation at lower temperatures. Note that some precursors used in the ALD method contain impurities such as carbon. Therefore, films formed by the ALD method may contain higher amounts of impurities such as carbon than films formed by other film formation methods. Quantitative determination of impurities can be performed using X-ray photoelectron spectroscopy (XPS).

[0224] Unlike film formation methods in which particles emitted from a target or the like are deposited, CVD and ALD are film formation methods in which a film is formed by a reaction on the surface of the workpiece. Therefore, these film formation methods are less affected by the shape of the workpiece and have good step coverage. In particular, ALD has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surface of openings with high aspect ratios. However, because ALD has a relatively slow film formation rate, it may be preferable to use it in combination with other film formation methods, such as CVD, which has a faster film formation rate.

[0225] The CVD method and the ALD method can control the composition of the resulting film by adjusting the flow rate ratio of the source gases. For example, the CVD method and the ALD method can form a film of any composition by adjusting the flow rate ratio of the source gases. Furthermore, for example, the CVD method and the ALD method can form a film with a continuously changing composition by changing the flow rate ratio of the source gases while forming the film. When forming a film while changing the flow rate ratio of the source gases, the time required for film formation can be shortened compared to when forming a film using multiple film formation chambers because no time is required for transportation and pressure adjustment. Therefore, the productivity of semiconductor devices can be improved in some cases.

[0226] First, a substrate (not shown) is prepared, and the insulator 212 is formed on the substrate (see FIGS. 4A to 4D). The insulator 212 is preferably formed by sputtering. By using sputtering, which does not require the use of hydrogen as a deposition gas, the hydrogen concentration in the insulator 212 can be reduced. However, the method for forming the insulator 212 is not limited to sputtering, and a CVD method, an MBE method, a PLD method, an ALD method, or the like may also be used as appropriate.

[0227] In this embodiment, a silicon nitride film is formed as the insulator 212 by pulsed DC sputtering using a silicon target in an atmosphere containing nitrogen gas. By using pulsed DC sputtering, particle generation due to arcing on the target surface can be suppressed, resulting in a more uniform film thickness distribution. Furthermore, by using a pulsed voltage, the rise and fall of the discharge can be made steeper than with a high-frequency voltage. This allows for more efficient supply of power to the electrodes, improving the sputtering rate and film quality.

[0228] By using an insulator that is impermeable to impurities such as water and hydrogen, such as silicon nitride, it is possible to suppress the diffusion of impurities such as water and hydrogen contained in layers below the insulator 212. Furthermore, by using an insulator that is impermeable to copper, such as silicon nitride, as the insulator 212, even if a metal that easily diffuses, such as copper, is used for a conductor in a layer (not shown) below the insulator 212, it is possible to suppress the upward diffusion of the metal through the insulator 212.

[0229] Next, the insulator 214 is deposited on the insulator 212 (see FIGS. 4A to 4D). The insulator 214 is preferably deposited by sputtering. By using sputtering, which does not require the use of hydrogen as a deposition gas, the hydrogen concentration in the insulator 214 can be reduced. However, the deposition of the insulator 214 is not limited to sputtering, and CVD, MBE, PLD, ALD, or the like may also be used as appropriate.

[0230] In this embodiment, an aluminum oxide film is formed by pulse DC sputtering using an aluminum target in an atmosphere containing oxygen gas as the insulator 214. By using the pulse DC sputtering method, the film thickness distribution can be made more uniform, and the sputtering rate and film quality can be improved.

[0231] It is preferable to use a metal oxide having an amorphous structure, such as aluminum oxide, which has a high ability to capture and fix hydrogen, as the insulator 214. This allows hydrogen contained in the insulator 216 to be captured or fixed and prevents the hydrogen from diffusing into the oxide 230. In particular, using aluminum oxide having an amorphous structure or aluminum oxide having an amorphous structure as the insulator 214 is preferable because it may be possible to more effectively capture or fix hydrogen. This enables the manufacture of a highly reliable transistor 200 and semiconductor device with favorable characteristics.

[0232] Next, the insulator 216 is deposited over the insulator 214. The insulator 216 is preferably deposited by sputtering. By using sputtering, which does not require the use of hydrogen as a deposition gas, the hydrogen concentration in the insulator 216 can be reduced. However, the deposition of the insulator 216 is not limited to sputtering, and a CVD method, an MBE method, a PLD method, an ALD method, or the like may also be used as appropriate.

[0233] In this embodiment, a silicon oxide film is formed by pulse DC sputtering using a silicon target in an atmosphere containing oxygen gas as the insulator 216. By using the pulse DC sputtering method, the film thickness distribution can be made more uniform, and the sputtering rate and film quality can be improved.

[0234] The insulators 212, 214, and 216 are preferably successively deposited without exposure to the atmosphere. For example, a multi-chamber deposition apparatus can be used. This allows the insulators 212, 214, and 216 to be deposited with reduced hydrogen content and also reduces the amount of hydrogen mixed into the films between deposition steps.

[0235] Next, an opening is formed in the insulator 216, reaching the insulator 214. The opening may be, for example, a groove or a slit. The region where the opening is formed may also be referred to as an opening. The opening may be formed by wet etching, but dry etching is preferable for fine processing. For the insulator 214, it is preferable to select an insulator that functions as an etching stopper film when etching the insulator 216 to form the groove. For example, if silicon oxide or silicon oxynitride is used for the insulator 216 that forms the groove, it is preferable to use silicon nitride, aluminum oxide, or hafnium oxide for the insulator 214.

[0236] The dry etching apparatus may be a capacitively coupled plasma (CCP) etching apparatus having parallel-plate electrodes. The capacitively coupled plasma etching apparatus having parallel-plate electrodes may be configured to apply a high-frequency voltage to one of the parallel-plate electrodes. Alternatively, it may be configured to apply a plurality of different high-frequency voltages to one of the parallel-plate electrodes. Alternatively, it may be configured to apply a high-frequency voltage of the same frequency to each of the parallel-plate electrodes. Alternatively, it may be configured to apply high-frequency voltages of different frequencies to each of the parallel-plate electrodes. Alternatively, a dry etching apparatus having a high-density plasma source may be used. For example, an inductively coupled plasma (ICP) etching apparatus may be used as the dry etching apparatus having a high-density plasma source.

[0237] After the openings are formed, the conductive film 205A is formed (see FIGS. 4A to 4D). The conductive film 205A preferably includes a conductor that suppresses oxygen permeation. For example, tantalum nitride, tungsten nitride, titanium nitride, or the like can be used. Alternatively, the conductive film 205A may be a stacked film of a conductor that suppresses oxygen permeation and tantalum, tungsten, titanium, molybdenum, aluminum, copper, or a molybdenum-tungsten alloy. The conductive film 205A can be formed by sputtering, CVD, MBE, PLD, ALD, or the like.

[0238] In this embodiment, titanium nitride is formed as the conductive film 205A. By using such a metal nitride as the lower layer of the conductor 205b, it is possible to prevent the conductor 205b from being oxidized by the insulator 216 or the like. Furthermore, even if a metal that easily diffuses, such as copper, is used as the conductor 205b, it is possible to prevent the metal from diffusing out of the conductor 205a.

[0239] Next, a conductive film 205B is formed (see FIGS. 4A to 4D). The conductive film 205B can be formed using tantalum, tungsten, titanium, molybdenum, aluminum, copper, a molybdenum-tungsten alloy, or the like. The conductive film can be formed by a plating method, a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, tungsten is formed as the conductive film 205B.

[0240] Next, CMP processing is performed to remove parts of the conductive film 205A and the conductive film 205B, thereby exposing the insulator 216 (see FIGS. 5A to 5D). As a result, the conductors 205a and 205b remain only in the openings. Note that the CMP processing may remove part of the insulator 216.

[0241] Next, etching is performed to remove the upper portion of the conductor 205b (see FIGS. 6A to 6D). As a result, the upper surface of the conductor 205b becomes lower than the upper surfaces of the conductor 205a and the insulator 216. The conductor 205b can be etched by dry etching or wet etching, but dry etching is preferable for fine processing.

[0242] Next, the conductive film 205C is formed over the insulator 216, the conductor 205a, and the conductor 205b (see FIGS. 7A to 7D). The conductive film 205C preferably includes a conductor that has a function of suppressing oxygen permeation, similar to the conductive film 205A.

[0243] In this embodiment, titanium nitride is formed as the conductive film 205C. By using such a metal nitride as the upper layer of the conductor 205b, it is possible to prevent the conductor 205b from being oxidized by the insulator 222 or the like. Furthermore, even if a metal that easily diffuses, such as copper, is used as the conductor 205b, it is possible to prevent the metal from diffusing out of the conductor 205c.

[0244] Next, a portion of the conductive film 205C is removed by CMP processing, exposing the insulator 216 (see FIGS. 8A to 8D). As a result, the conductors 205a, 205b, and 205c remain only in the openings. This allows the formation of a conductor 205 with a flat upper surface. Furthermore, the conductor 205b is surrounded by the conductors 205a and 205c. This prevents impurities such as hydrogen from the conductor 205b from diffusing out of the conductors 205a and 205c, and also prevents oxygen from entering the conductors 205a and 205c and oxidizing the conductor 205b. Note that the CMP processing may remove a portion of the insulator 216.

[0245] Next, the insulator 222 is formed over the insulator 216 and the conductor 205 (see FIGS. 9A to 9D). The insulator 222 may be an insulator containing one or both of aluminum and hafnium oxides. Aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate) is preferably used as the insulator containing one or both of aluminum and hafnium oxides. An insulator containing one or both of aluminum and hafnium oxides has barrier properties against oxygen, hydrogen, and water. The insulator 222 having barrier properties against hydrogen and water prevents hydrogen and water contained in structures provided around the transistor 200 from diffusing into the inside of the transistor 200 through the insulator 222, thereby preventing oxygen vacancies from being generated in the oxide 230.

[0246] The insulator 222 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, hafnium oxide is formed by a sputtering method as the insulator 222. By using a sputtering method that does not require the use of hydrogen as a deposition gas, the hydrogen concentration in the insulator 222 can be reduced.

[0247] Subsequently, heat treatment is preferably performed. The heat treatment may be performed at a temperature of 250°C to 650°C, preferably 300°C to 500°C, and more preferably 320°C to 450°C. The heat treatment may be performed in a nitrogen gas or inert gas atmosphere, or in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, when the heat treatment is performed in a mixed atmosphere of nitrogen gas and oxygen gas, the oxygen gas concentration may be about 20%. The heat treatment may also be performed under reduced pressure. Alternatively, the heat treatment may be performed in a nitrogen gas or inert gas atmosphere, followed by another heat treatment in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to compensate for the desorbed oxygen.

[0248] The gas used in the heat treatment is preferably highly purified. For example, the amount of moisture contained in the gas used in the heat treatment is 1 ppb or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less. By performing the heat treatment using a highly purified gas, moisture and the like can be prevented from being introduced into the insulator 222 as much as possible.

[0249] In this embodiment, after the insulator 222 is formed, heat treatment is performed at 400° C. for 1 hour with a flow rate ratio of nitrogen gas and oxygen gas set to 4 slm:1 slm. This heat treatment can remove impurities such as water and hydrogen contained in the insulator 222. When an oxide containing hafnium is used as the insulator 222, the heat treatment may cause part of the insulator 222 to crystallize. The heat treatment can also be performed at a timing such as after the insulator 224 is formed.

[0250] Next, the insulator 224 is deposited on the insulator 222 (see FIGS. 9A to 9D). The insulator 224 can be deposited by sputtering, CVD, MBE, PLD, ALD, or the like. In this embodiment, silicon oxide is deposited by sputtering, which does not require the use of hydrogen as a deposition gas. The hydrogen concentration in the insulator 224 can be reduced by using the sputtering method, which does not require the use of hydrogen as a deposition gas. Because the insulator 224 will come into contact with the oxide 230a in a later step, it is preferable that the hydrogen concentration be reduced in this manner.

[0251] Here, to form an excess oxygen region in the insulator 224, a plasma treatment containing oxygen may be performed under reduced pressure. For the plasma treatment containing oxygen, it is preferable to use an apparatus having a power source that generates high-density plasma using, for example, microwaves. Alternatively, a power source that applies RF (radio frequency) to the substrate side may be provided. By using high-density plasma, high-density oxygen radicals can be generated, and by applying RF to the substrate side, the oxygen radicals generated by the high-density plasma can be efficiently guided into the insulator 224. Alternatively, after performing a plasma treatment containing an inert gas using this apparatus, a plasma treatment containing oxygen may be performed to replenish the desorbed oxygen. Note that impurities such as water and hydrogen contained in the insulator 224 can be removed by appropriately selecting the conditions for the plasma treatment. In this case, heat treatment is not required.

[0252] Here, after forming an aluminum oxide film on the insulator 224 by, for example, a sputtering method, CMP processing may be performed until the aluminum oxide reaches the insulator 224. This CMP processing can planarize and smooth the surface of the insulator 224. By placing the aluminum oxide on the insulator 224 and performing the CMP processing, it becomes easier to detect the end point of the CMP processing. Furthermore, the CMP processing may polish a portion of the insulator 224, resulting in a thinner film of the insulator 224. However, the film thickness can be adjusted during the formation of the insulator 224. Planarizing and smoothing the surface of the insulator 224 may prevent a deterioration in the coverage of the oxide film to be formed later and may prevent a decrease in the yield of the semiconductor device. Furthermore, forming an aluminum oxide film on the insulator 224 by a sputtering method is preferable because it allows oxygen to be added to the insulator 224.

[0253] Next, oxide films 230A and 230B are sequentially formed on insulator 224 (see FIGS. 9A to 9D). Preferably, oxide films 230A and 230B are formed consecutively without being exposed to the atmosphere. By forming the films without being exposed to the atmosphere, it is possible to prevent impurities or moisture from the atmosphere from adhering to oxide films 230A and 230B, and to keep the vicinity of the interface between oxide films 230A and 230B clean.

[0254] The oxide film 230A and the oxide film 230B can be formed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0255] For example, when the oxide film 230A and the oxide film 230B are formed by sputtering, oxygen or a mixed gas of oxygen and a rare gas is used as the sputtering gas. By increasing the proportion of oxygen contained in the sputtering gas, the amount of excess oxygen in the formed oxide film can be increased. Furthermore, when the oxide film is formed by sputtering, the above-mentioned In-M-Zn oxide target can be used.

[0256] In particular, during the formation of the oxide film 230A, some of the oxygen contained in the sputtering gas may be supplied to the insulator 224. Therefore, the proportion of oxygen contained in the sputtering gas should be 70% or more, preferably 80% or more, and more preferably 100%.

[0257] When the oxide film 230B is formed by a sputtering method, an oxygen-excessive oxide semiconductor is formed when the proportion of oxygen contained in the sputtering gas is set to more than 30% and less than or equal to 100%, preferably 70% to 100%. A transistor using an oxygen-excessive oxide semiconductor for a channel formation region can have relatively high reliability. However, one embodiment of the present invention is not limited thereto. When the oxide film 230B is formed by a sputtering method, an oxygen-deficient oxide semiconductor is formed when the proportion of oxygen contained in the sputtering gas is set to 1% to 30%, preferably 5% to 20%. A transistor using an oxygen-deficient oxide semiconductor for a channel formation region can have relatively high field-effect mobility. Furthermore, the crystallinity of the oxide film can be improved by forming the oxide film while heating the substrate.

[0258] In this embodiment, oxide film 230A is formed by sputtering using an oxide target with an atomic ratio of In:Ga:Zn=1:3:4. Oxide film 230B is formed by sputtering using an oxide target with an atomic ratio of In:Ga:Zn=4:2:4.1. Each oxide film can be formed according to the desired characteristics of oxide 230a and oxide 230b by appropriately selecting the film formation conditions and atomic ratio.

[0259] Next, an oxide film 243A is formed on the oxide film 230B (see FIGS. 9A to 9D). The oxide film 243A can be formed by sputtering, CVD, MBE, PLD, ALD, or the like. The atomic ratio of Ga to In in the oxide film 243A is preferably greater than the atomic ratio of Ga to In in the oxide film 230B. In this embodiment, the oxide film 243A is formed by sputtering using an oxide target with an atomic ratio of In:Ga:Zn=1:3:4.

[0260] It is preferable to form the insulator 222, the insulator 224, the oxide film 230A, the oxide film 230B, and the oxide film 243A by sputtering without exposing them to the atmosphere. For example, a multi-chamber film formation apparatus may be used. This allows the insulator 222, the insulator 224, the oxide film 230A, the oxide film 230B, and the oxide film 243A to be formed with reduced hydrogen content, and further reduces the incorporation of hydrogen into the films between film formation steps.

[0261] Next, heat treatment is preferably performed. The heat treatment may be performed within a temperature range in which the oxide film 230A, the oxide film 230B, and the oxide film 243A do not polycrystallize, i.e., 250°C to 650°C, preferably 400°C to 600°C. The heat treatment is performed in a nitrogen gas or inert gas atmosphere, or an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more. For example, when the heat treatment is performed in a mixed atmosphere of nitrogen gas and oxygen gas, the oxygen gas concentration may be approximately 20%. The heat treatment may also be performed under reduced pressure. Alternatively, the heat treatment may be performed in a nitrogen gas or inert gas atmosphere, followed by an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more to replenish the desorbed oxygen.

[0262] Furthermore, it is preferable that the gas used in the heat treatment be highly purified. For example, the moisture content of the gas used in the heat treatment should be 1 ppb or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less. By performing the heat treatment using a highly purified gas, it is possible to prevent moisture and other substances from being absorbed into oxide film 230A, oxide film 230B, oxide film 243A, and the like as much as possible.

[0263] In this embodiment, the heat treatment is performed in a nitrogen atmosphere at 550°C for one hour, followed by another heat treatment in an oxygen atmosphere at 550°C for one hour. This heat treatment can remove impurities such as water and hydrogen from the oxide film 230A, the oxide film 230B, and the oxide film 243A. Furthermore, this heat treatment can improve the crystallinity of the oxide film 230B, resulting in a denser, more compact structure. This reduces the diffusion of oxygen or impurities in the oxide film 230B.

[0264] Next, a conductive film 242A is formed on the oxide film 243A (see FIGS. 9A to 9D). The conductive film 242A can be formed by sputtering, CVD, MBE, PLD, ALD, or the like. For example, tantalum nitride may be formed as the conductive film 242A by sputtering. Note that heat treatment may be performed before the formation of the conductive film 242A. The heat treatment may be performed under reduced pressure, and the conductive film 242A may be formed successively without exposure to the air. By performing such treatment, moisture and hydrogen adsorbed on the surface of the oxide film 243A can be removed, and the moisture and hydrogen concentrations in the oxide film 230A, the oxide film 230B, and the oxide film 243A can be further reduced. The temperature of the heat treatment is preferably 100° C. or higher and 400° C. or lower. In this embodiment, the temperature of the heat treatment is 200° C.

[0265] Next, an insulating film 271A is formed on the conductive film 242A (see FIGS. 9A to 9D). The insulating film 271A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The insulating film 271A is preferably an insulating film that has a function of suppressing oxygen permeation. For example, the insulating film 271A may be formed by sputtering aluminum oxide or silicon nitride.

[0266] Next, an insulating film 273A is formed on the insulating film 271A (see FIGS. 9A to 9D). The insulating film 273A can be formed by sputtering, CVD, MBE, PLD, ALD, or the like. For example, the insulating film 273A may be formed by sputtering silicon nitride or silicon oxide.

[0267] Note that the conductive film 242A, the insulating film 271A, and the insulating film 273A are preferably formed by sputtering without exposure to the atmosphere. For example, a multi-chamber film formation apparatus may be used. This allows the conductive film 242A, the insulating film 271A, and the insulating film 273A to be formed with reduced hydrogen content and also reduces the amount of hydrogen mixed into the films between film formation steps. Furthermore, when a hard mask is provided on the insulating film 273A, the film that becomes the hard mask may also be formed continuously without exposure to the atmosphere.

[0268] Next, the oxide film 230A, the oxide film 230B, the oxide film 243A, the conductive film 242A, the insulating film 271A, and the insulating film 273A are processed into island shapes using lithography to form the oxide 230a, the oxide 230b, the oxide layer 243B, the conductive layer 242B, the insulating layer 271B, and the insulating layer 273B (see FIGS. 10A to 10D). This processing can be performed using dry etching or wet etching. Dry etching is suitable for microfabrication. The oxide film 230A, the oxide film 230B, the oxide film 243A, the conductive film 242A, the insulating film 271A, and the insulating layer 271B may be processed under different conditions. During this process, the thickness of the insulator 224 in the region not overlapping with the oxide 230a may be reduced. In this step, the insulator 224 may be processed into an island shape by overlapping with the oxide 230a.

[0269] In lithography, a resist is first exposed through a mask. The exposed area is then removed or left using a developer to form a resist mask. A conductor, semiconductor, or insulator can then be processed into a desired shape by etching through the resist mask. For example, a resist mask can be formed by exposing the resist to KrF excimer laser light, ArF excimer laser light, or EUV (Extreme Ultraviolet) light. An immersion technique can also be used, in which a liquid (e.g., water) is filled between the substrate and the projection lens for exposure. An electron beam or an ion beam can also be used instead of the light described above. When an electron beam or an ion beam is used, a mask is not required. The resist mask can be removed by dry etching such as ashing, wet etching, dry etching followed by wet etching, or wet etching followed by dry etching.

[0270] Furthermore, a hard mask made of an insulator or a conductor may be used under the resist mask. When using a hard mask, an insulating film or a conductive film serving as a hard mask material is formed on the conductive film 242A, a resist mask is formed thereon, and the hard mask material is etched to form a hard mask with a desired shape. Etching of the conductive film 242A and the like may be performed after removing the resist mask or may be performed while the resist mask is left in place. In the latter case, the resist mask may be lost during etching. The hard mask may be removed by etching after etching the conductive film 242A and the like. On the other hand, if the hard mask material does not affect subsequent processes or can be used in subsequent processes, it is not necessary to remove the hard mask. In this embodiment, the insulating layer 271B and the insulating layer 273B are used as hard masks. On the other hand, if the insulating layer 271B functions sufficiently as a hard mask, the insulating layer 273B is not necessarily required. In this case, the insulating film 273A does not need to be formed. Furthermore, when the insulating layer 273B is not provided and the insulating layer 271B is used as a hard mask, it is preferable to appropriately adjust the film thickness of the insulating layer 271B to prevent the insulating layer 271B from disappearing during etching of the conductive film 242A and the like.

[0271] Here, since the insulating layers 271B and 273B function as masks for the conductive layer 242B, the conductive layer 242B does not have a curved surface between its side surface and top surface, as shown in FIGS. 10B to 10D. As a result, the conductors 242a and 242b shown in FIGS. 1B and 1D have angular ends where their side surfaces and top surfaces intersect. Because the angular ends where the side surfaces and top surfaces of the conductor 242 intersect are angular, the cross-sectional area of ​​the conductor 242 is larger than when the ends have a curved surface. This reduces the resistance of the conductor 242, thereby increasing the on-current of the transistor 200.

[0272] The oxide 230a, the oxide 230b, the oxide layer 243B, the conductive layer 242B, the insulating layer 271B, and the insulating layer 273B are formed so that at least a portion of each overlaps with the conductor 205. Preferably, the side surfaces of the oxide 230a, the oxide 230b, the oxide layer 243B, the conductive layer 242B, the insulating layer 271B, and the insulating layer 273B are approximately perpendicular to the top surface of the insulator 222. When the side surfaces of the oxide 230a, the oxide 230b, the oxide layer 243B, the conductive layer 242B, the insulating layer 271B, and the insulating layer 273B are approximately perpendicular to the top surface of the insulator 222, a smaller area and higher density can be achieved when providing multiple transistors 200. Alternatively, the angle formed by the side surfaces of the oxide 230a, the oxide 230b, the oxide layer 243B, the conductive layer 242B, the insulating layer 271B, and the insulating layer 273B and the upper surface of the insulator 222 may be low. In this case, the angle formed by the side surfaces of the oxide 230a, the oxide 230b, the oxide layer 243B, the conductive layer 242B, the insulating layer 271B, and the insulating layer 273B and the upper surface of the insulator 222 is preferably 60 degrees or more and less than 70 degrees. By adopting such a shape, the coverage of the insulator 275 and the like can be improved in subsequent processes, and defects such as voids can be reduced.

[0273] Furthermore, by-products generated in the etching process may form layers on the side surfaces of the oxide 230a, the oxide 230b, the oxide layer 243B, the conductive layer 242B, the insulating layer 271B, and the insulating layer 273B. In this case, the layered by-products are formed on the oxide 230a, the oxide 230b, the oxide 243, the conductor 242, the insulator 271, and between the insulators 273 and 272. Similarly, layered by-products may be formed on the insulator 224. Even if the insulator 275 is formed with the layered by-products formed on the insulator 224, the layered by-products would prevent oxygen from being added to the insulator 224. Therefore, it is preferable to remove the layered by-products formed in contact with the upper surface of the insulator 224.

[0274] Next, an insulating film that becomes the insulator 272 is formed on the insulator 224, the oxide 230a, the oxide 230b, the oxide layer 243B, the conductive layer 242B, the insulating layer 271B, and the insulating layer 273B. The insulating film that becomes the insulator 272 can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, a silicon nitride film is formed by a sputtering method as the insulating film that becomes the insulator 272.

[0275] Next, the insulating film that will become the insulator 272 is anisotropically etched to remove the insulating film on the insulating layer 273B and the insulating film on the insulator 224 (see FIGS. 11A to 11D). Furthermore, if any layer-like by-products remain in the step shown in FIG. 10, they can be removed by the anisotropic etching. As a result, the insulating layer 272A is formed in contact with the side surfaces of the oxide 230a, the oxide 230b, the oxide layer 243B, the conductive layer 242B, the insulating layer 271B, and the insulating layer 273B.

[0276] In this way, the oxide 230a, the oxide 230b, the oxide layer 243B, and the conductive layer 242B can be covered with the insulating layer 272A and the insulating layer 271B, which have the function of suppressing oxygen diffusion. This makes it possible to reduce the diffusion of oxygen into the oxide 230a, the oxide 230b, the oxide layer 243B, and the conductive layer 242B during the subsequent process of forming the insulator 275.

[0277] Next, the insulator 275 is formed over the insulator 224, the insulating layer 272A, and the insulating layer 273B (see FIGS. 11A to 11D). The insulator 275 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The insulator 275 is preferably an insulating film that has the function of suppressing oxygen permeation. For example, the insulator 275 may be formed by a sputtering method using aluminum oxide.

[0278] The insulator 275 is preferably formed by sputtering. By forming the insulator 275 by sputtering, oxygen can be added to the insulator 224 and the insulating layer 273B. In this case, since the insulating layer 271B is provided in contact with the top surface of the conductive layer 242B and the insulating layer 272A is provided in contact with the side surface of the conductive layer 242B, oxidation of the conductive layer 242B can be reduced.

[0279] Next, an insulating film to be the insulator 280 is formed on the insulator 275. The insulating film can be formed by sputtering, CVD, MBE, PLD, ALD, or the like. For example, a silicon oxide film can be formed by sputtering. The insulating film to be the insulator 280 can be formed by sputtering in an oxygen-containing atmosphere, thereby forming the insulator 280 containing excess oxygen. Furthermore, the hydrogen concentration in the insulator 280 can be reduced by using a sputtering method that does not require hydrogen as a deposition gas. Heat treatment may be performed before the formation of the insulating film. The heat treatment may be performed under reduced pressure, and the insulating film may be formed successively without exposure to the atmosphere. By performing such treatment, moisture and hydrogen adsorbed on the surface of the insulator 275 can be removed, and the moisture and hydrogen concentrations in the oxide 230a, the oxide 230b, the oxide layer 243B, and the insulator 224 can be reduced. The heat treatment conditions described above can be used for the heat treatment.

[0280] Next, the insulating film that will become the insulator 280 is subjected to CMP processing to form the insulator 280 with a flat upper surface (see FIGS. 11A to 11D). Alternatively, a silicon nitride film may be formed on the insulator 280 by, for example, a sputtering method, and the CMP processing may be performed until the silicon nitride reaches the insulator 280.

[0281] Next, a portion of the insulator 280, a portion of the insulator 275, a portion of the insulating layer 273B, a portion of the insulating layer 271B, a portion of the insulating layer 272A, a portion of the conductive layer 242B, a portion of the oxide layer 243B, and a portion of the oxide 230b are processed to form an opening that reaches the oxide 230b. The opening is preferably formed so as to overlap the conductor 205. By forming the opening, the insulator 273a, the insulator 273b, the insulator 271a, the insulator 271b, the insulator 272a, the insulator 272b, the conductor 242a, the conductor 242b, the oxide 243a, and the oxide 243b are formed (see FIGS. 12A to 12D).

[0282] When forming the opening, the upper portion of the oxide 230b is removed. By removing a portion of the oxide 230b, a groove is formed in the oxide 230b. Depending on the depth of the groove, the groove may be formed in the process of forming the opening, or may be formed in a process different from the process of forming the opening.

[0283] Furthermore, dry etching or wet etching can be used to process a portion of the insulator 280, a portion of the insulator 275, a portion of the insulating layer 273B, a portion of the insulating layer 271B, a portion of the insulating layer 272A, a portion of the conductive layer 242B, a portion of the oxide layer 243B, and a portion of the oxide 230b. Dry etching is suitable for fine processing. The processing may be performed under different conditions. For example, a portion of the insulator 280 may be processed by dry etching, a portion of the insulator 275, a portion of the insulating layer 273B, a portion of the insulating layer 271B, and a portion of the insulating layer 272A may be processed by wet etching, and a portion of the oxide layer 243B, a portion of the conductive layer 242B, and a portion of the oxide 230b may be processed by dry etching. Furthermore, the processing of a portion of the oxide layer 243B and a portion of the conductive layer 242B may be performed under different conditions from the processing of a portion of the oxide 230b.

[0284] Here, it is preferable to remove impurities attached to the surfaces of or diffused into the oxides 230a and 230b. It is also preferable to remove damaged regions formed on the surface of the oxide 230b by the dry etching. Examples of such impurities include those derived from components contained in the insulator 280, the insulator 275, part of the insulating layer 273B, part of the insulating layer 271B, part of the insulating layer 272A, and the conductive layer 242B, components contained in the materials used in the device used to form the openings, and components contained in the gas or liquid used in etching. Examples of such impurities include aluminum, silicon, tantalum, fluorine, and chlorine.

[0285] In particular, impurities such as aluminum or silicon inhibit the formation of a CAAC-OS oxide 230b. Therefore, it is preferable to reduce or eliminate impurity elements such as aluminum or silicon that inhibit the formation of a CAAC-OS oxide. For example, the concentration of aluminum atoms in and around the oxide 230b may be 5.0 atomic % or less, preferably 2.0 atomic % or less, more preferably 1.5 atomic % or less, even more preferably 1.0 atomic % or less, and even more preferably less than 0.3 atomic %.

[0286] Note that the region of the metal oxide where the CAAC-OS transformation is inhibited by impurities such as aluminum or silicon and becomes an amorphous-like oxide semiconductor (a-like OS) is sometimes called a non-CAAC region. In the non-CAAC region, the density of the crystal structure is reduced, so V O A large amount of H is formed, which makes the transistor more likely to be normally on. Therefore, it is preferable that the non-CAAC region of the oxide 230b be reduced or eliminated.

[0287] In contrast, it is preferable that the oxide 230b has a layered CAAC structure. In particular, it is preferable that the oxide 230b has the CAAC structure up to the bottom edge of the drain. Here, in the transistor 200, the conductor 242a or the conductor 242b and its vicinity function as the drain. In other words, it is preferable that the oxide 230b near the bottom edge of the conductor 242a (conductor 242b) has the CAAC structure. In this way, even at the drain edge, which significantly affects the drain breakdown voltage, the damaged region of the oxide 230b is removed, and by having the CAAC structure, fluctuations in the electrical characteristics of the transistor 200 can be further suppressed. Furthermore, the reliability of the transistor 200 can be improved.

[0288] In order to remove the above-mentioned impurities, a cleaning process is performed. The cleaning method includes wet cleaning using a cleaning solution, plasma treatment using plasma, and cleaning by heat treatment, and the above cleaning methods may be combined as appropriate. Note that the cleaning process may deepen the grooves.

[0289] For wet cleaning, cleaning treatment may be performed using an aqueous solution of ammonia water, oxalic acid, phosphoric acid, hydrofluoric acid, or the like diluted with carbonated water or pure water, pure water, carbonated water, or the like. Alternatively, ultrasonic cleaning may be performed using these aqueous solutions, pure water, or carbonated water. Alternatively, these cleaning methods may be used in combination as appropriate.

[0290] In this specification, an aqueous solution obtained by diluting commercially available hydrofluoric acid with pure water may be referred to as "diluted hydrofluoric acid," and an aqueous solution obtained by diluting commercially available ammonia water with pure water may be referred to as "diluted ammonia water." The concentration, temperature, and other parameters of the aqueous solution may be adjusted appropriately depending on the impurities to be removed and the configuration of the semiconductor device to be cleaned. The ammonia concentration of the diluted ammonia water may be set to 0.01% or more and 5% or less, preferably 0.1% or more and 0.5% or less. The hydrogen fluoride concentration of the diluted hydrofluoric acid may be set to 0.01 ppm or more and 100 ppm or less, preferably 0.1 ppm or more and 10 ppm or less.

[0291] It is preferable to use a frequency of 200 kHz or more, and more preferably 900 kHz or more, for ultrasonic cleaning, as this frequency can reduce damage to the oxide 230b and the like.

[0292] The cleaning process may be repeated multiple times, and the cleaning solution may be changed for each cleaning process. For example, the first cleaning process may be performed using diluted hydrofluoric acid or diluted ammonia water, and the second cleaning process may be performed using pure water or carbonated water.

[0293] In this embodiment, the cleaning process involves wet cleaning using diluted hydrofluoric acid, followed by wet cleaning using pure water or carbonated water. By performing this cleaning process, impurities attached to the surfaces of or diffused into the oxides 230a and 230b can be removed. Furthermore, the crystallinity of the oxide 230b can be improved.

[0294] In the past, processes such as dry etching or the above-mentioned cleaning process may result in the thickness of the insulator 224 in the area that overlaps the opening but does not overlap with the oxide 230b being thinner than the thickness of the insulator 224 in the area that overlaps with the oxide 230b.

[0295] After the etching or cleaning, a heat treatment may be performed. The heat treatment may be performed at a temperature of 100°C or higher and 450°C or lower, preferably 350°C or higher and 400°C or lower. The heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing 10 ppm or higher, 1% or higher, or 10% or higher of an oxidizing gas. For example, the heat treatment is preferably performed in an oxygen atmosphere. This supplies oxygen to the oxide 230a and the oxide 230b, thereby reducing the oxygen vacancy V. O The heat treatment can reduce the amount of oxide 230b. In addition, by performing such heat treatment, the crystallinity of the oxide 230b can be improved. The heat treatment may be performed under reduced pressure. Alternatively, after the heat treatment in an oxygen atmosphere, the heat treatment may be performed in a nitrogen atmosphere without exposure to the air.

[0296] Next, the insulating film 250A is formed (see FIGS. 13A to 13D). Heat treatment may be performed before the formation of the insulating film 250A. The heat treatment may be performed under reduced pressure, and the insulating film 250A may be formed immediately after the formation of the insulating film 250A without exposure to the atmosphere. The heat treatment is preferably performed in an oxygen-containing atmosphere. By performing such treatment, moisture and hydrogen adsorbed on the surface of the oxide 230b can be removed, and the moisture and hydrogen concentrations in the oxide 230a and the oxide 230b can be further reduced. The temperature of the heat treatment is preferably 100°C or higher and 400°C or lower.

[0297] The insulating film 250A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The insulating film 250A is preferably formed by a film formation method using a gas in which hydrogen atoms are reduced or removed. This reduces the hydrogen concentration in the insulating film 250A. The insulating film 250A will become the insulator 250 that contacts the oxide 230b in a later process, so it is preferable that the hydrogen concentration be reduced in this way.

[0298] Furthermore, the insulating film 250A is preferably formed using the ALD method. The insulator 250, which functions as the gate insulating film of the miniaturized transistor 200, must be extremely thin (e.g., between 5 nm and 30 nm) and have minimal variation in thickness. In contrast, the ALD method is a film formation method in which a precursor and a reactant (oxidizer) are alternately introduced. The thickness can be adjusted by the number of times this cycle is repeated, allowing for precise film thickness adjustment. This allows for the precision of the gate insulating film required by the miniaturized transistor 200 to be achieved. Furthermore, as shown in FIGS. 13B and 13C , the insulating film 250A must be formed with good coverage on the bottom and side surfaces of the opening formed by the insulator 280, etc. Because atomic layers can be deposited one by one on the bottom and side surfaces of the opening, the insulating film 250A can be formed with good coverage on the opening.

[0299] Furthermore, when the insulating film 250A is formed by using the PECVD method, the film forming gas containing hydrogen is decomposed in the plasma, generating a large amount of hydrogen radicals. The reduction reaction of the hydrogen radicals extracts oxygen from the oxide 230b, forming V. O When H is formed, the hydrogen concentration in the oxide 230b increases. However, when the insulating film 250A is formed using the ALD method, the generation of hydrogen radicals can be suppressed both when introducing the precursor and when introducing the reactant. Therefore, by forming the insulating film 250A using the ALD method, the hydrogen concentration in the oxide 230b can be prevented from increasing.

[0300] Although the insulating film 250A is illustrated as a single layer in FIGS. 13B, 13C, and 13D, it may have a stacked structure of two or more layers. When the insulating film 250A has a stacked structure of two layers, it is preferable that the lower layer of the insulating film 250A is formed using an insulator that releases oxygen when heated, and the upper layer of the insulating film 250A is formed using an insulator that has the function of suppressing oxygen diffusion. This configuration can suppress the diffusion of oxygen contained in the lower layer of the insulator 250 into the conductor 260. In other words, it can suppress a decrease in the amount of oxygen supplied to the oxide 230. It can also suppress oxidation of the conductor 260 due to oxygen contained in the lower layer of the insulator 250. For example, the lower layer of the insulating film 250A can be formed using a material that can be used for the insulator 250 described above, and the upper layer of the insulating film 250A can be formed using a material similar to that of the insulator 222.

[0301] Specifically, the upper layer of the insulating film 250A can be made of a metal oxide containing one or more elements selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, etc., or a metal oxide that can be used as the oxide 230. In particular, it is preferable to use an insulator containing an oxide of one or both of aluminum and hafnium.

[0302] In this embodiment, the insulating film 250A has a two-layer laminate structure, with a lower layer of silicon oxide formed by the PEALD method and an upper layer of hafnium oxide formed by the thermal ALD method.

[0303] When insulating film 250A has a two-layer laminated structure, it is preferable that the insulating film that forms the lower layer of insulating film 250A and the insulating film that forms the upper layer of insulating film 250A are successively formed without exposure to the atmospheric environment. By forming the films without exposure to the atmosphere, it is possible to prevent impurities such as hydrogen or moisture from the atmospheric environment from adhering to the insulating film that forms the lower layer of insulating film 250A and the insulating film that forms the upper layer of insulating film 250A, and it is possible to keep the vicinity of the interface between the insulating film that forms the lower layer of insulating film 250A and the insulating film that forms the upper layer of insulating film 250A clean.

[0304] Next, microwave treatment is performed in an oxygen-containing atmosphere (see FIGS. 13A to 13D). The dotted lines in FIGS. 13B, 13C, and 13D indicate microwaves, high-frequency waves such as RF, oxygen plasma, or oxygen radicals. For the microwave treatment, a microwave treatment device having a power source for generating high-density plasma using microwaves is preferably used. The microwave treatment device may also have a power source for applying RF to the substrate side. High-density plasma can be used to generate high-density oxygen radicals. Applying RF to the substrate side can efficiently introduce oxygen ions generated by high-density plasma into the oxide 230b. The microwave treatment is preferably performed under reduced pressure, with a pressure of 60 Pa or higher, preferably 133 Pa or higher, more preferably 200 Pa or higher, and even more preferably 400 Pa or higher. The oxygen flow ratio (O2 / O2+Ar) is preferably 50% or lower, and more preferably 10% to 30%. The treatment temperature may be 750° C. or less, preferably 500° C. or less, for example, about 400° C. After the oxygen plasma treatment, a heat treatment may be performed successively without exposure to the outside air.

[0305] As shown in Figures 13B, 13C, and 13D, microwave processing is performed in an atmosphere containing oxygen, whereby oxygen gas is converted into plasma using microwaves or high-frequency waves such as RF, and the oxygen plasma can be applied to the region between the conductors 242a and 242b of the oxide 230b. At this time, microwaves or high-frequency waves such as RF can also be irradiated onto the region 230bc. In other words, microwaves, high-frequency waves such as RF, oxygen plasma, etc. can be applied to the region 230bc shown in Figure 2. The action of the plasma, microwaves, etc., can increase the V of the region 230bc. O H can be split off and hydrogen H can be removed from the region 230bc. O H → H + V O " occurs, and the hydrogen concentration in the region 230bc can be reduced. Therefore, oxygen vacancies and V O By supplying oxygen radicals generated by the oxygen plasma or oxygen contained in the insulator 250 to the oxygen vacancies formed in the region 230bc, the oxygen vacancies in the region 230bc can be further reduced, and the carrier concentration can be lowered.

[0306] On the other hand, conductors 242a and 242b are provided on regions 230ba and 230bb shown in Fig. 2. As shown in Figs. 13B, 13C, and 13D, conductors 242a and 242b shield the effects of microwaves, high frequency waves such as RF, oxygen plasma, and the like, so that these effects do not reach regions 230ba and 230bb. As a result, V O Since there is no reduction in H and no excessive supply of oxygen, it is possible to prevent a decrease in the carrier concentration.

[0307] In this way, oxygen vacancies and V are selectively formed in the oxide semiconductor region 230bc. OBy removing H, the region 230bc can be made i-type or substantially i-type. Furthermore, the supply of excess oxygen to the regions 230ba and 230bb, which function as source and drain regions, can be prevented, maintaining the n-type conductivity. This prevents fluctuations in the electrical characteristics of the transistor 200 and prevents the electrical characteristics of the transistor 200 from varying across the substrate.

[0308] Therefore, it is possible to provide a semiconductor device with less variation in transistor characteristics, a highly reliable semiconductor device, and a semiconductor device with good electrical characteristics.

[0309] 13, the microwave treatment is performed after the insulating film 250A is formed, but the present invention is not limited to this. For example, the microwave treatment may be performed before the insulating film 250A is formed, or may be performed both before and after the insulating film 250A is formed.

[0310] For example, when the insulating film 250A has the above-mentioned two-layer structure, microwave processing is performed, and then the lower layer of the insulating film 250A, silicon oxide, is deposited by PEALD, and the upper layer of the insulating film 250A, hafnium oxide, is deposited by thermal ALD. Here, the microwave processing, PEALD deposition of the silicon oxide, and thermal ALD deposition of the hafnium oxide are preferably performed consecutively without exposure to the atmosphere. For example, a multi-chamber processing device may be used. Alternatively, the microwave processing may be replaced by processing using a plasma-excited reactant (oxidant) in a PEALD device. Here, oxygen gas may be used as the reactant (oxidant).

[0311] Alternatively, a heat treatment may be performed while maintaining the reduced pressure after the microwave treatment. By performing such a treatment, hydrogen in the insulating film 250A, the oxide 230b, and the oxide 230a can be efficiently removed. Some of the hydrogen may be gettered to the conductor 242 (the conductor 242a and the conductor 242b). Alternatively, a heat treatment step may be repeated multiple times while maintaining the reduced pressure after the microwave treatment. Repeated heat treatments can more efficiently remove hydrogen from the insulating film 250A, the oxide 230b, and the oxide 230a. The heat treatment temperature is preferably 300°C or higher and 500°C or lower.

[0312] Furthermore, by modifying the film quality of the insulating film 250A by microwave treatment, it is possible to suppress the diffusion of hydrogen, water, impurities, etc. Therefore, it is possible to suppress the diffusion of hydrogen, water, impurities, etc. into the oxide 230b, the oxide 230a, etc. via the insulator 250 in a post-process such as film formation of a conductive film that becomes the conductor 260, or in a post-treatment such as heat treatment.

[0313] Next, a conductive film that will become the conductor 260a and a conductive film that will become the conductor 260b are formed in this order. The conductive film that will become the conductor 260a and the conductive film that will become the conductor 260b can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, the conductive film that will become the conductor 260a is formed using an ALD method, and the conductive film that will become the conductor 260b is formed using a CVD method.

[0314] Next, the insulating film 250A, the conductive film that will become the conductor 260a, and the conductive film that will become the conductor 260b are polished by CMP until the insulator 280 is exposed, thereby forming the insulator 250 and the conductor 260 (the conductor 260a and the conductor 260b) (see FIGS. 14A to 14D). As a result, the insulator 250 is arranged to cover the opening that reaches the oxide 230b and the inner walls (side walls and bottom surface) of the groove in the oxide 230b. The conductor 260 is also arranged to fill the opening and the groove via the insulator 250.

[0315] Next, heat treatment may be performed under the same conditions as the above heat treatment. In this embodiment, the treatment is performed in a nitrogen atmosphere at 400° C. for 1 hour. The heat treatment can reduce the moisture and hydrogen concentrations in the insulators 250 and 280. Note that after the heat treatment, the next step of forming the insulator 282 may be performed without exposure to the air.

[0316] Next, the insulator 282 is formed over the insulator 250, the conductor 260, and the insulator 280 (see FIGS. 15A to 15D). The insulator 282 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The insulator 282 is preferably formed by a sputtering method. By using a sputtering method that does not require the use of hydrogen as a deposition gas, the hydrogen concentration in the insulator 282 can be reduced. Furthermore, by forming the insulator 282 by a sputtering method in an atmosphere containing oxygen, oxygen can be added to the insulator 280 during deposition. This allows the insulator 280 to contain excess oxygen. At this time, the insulator 282 is preferably formed while heating the substrate.

[0317] In this embodiment, an aluminum oxide film is formed by pulse DC sputtering using an aluminum target in an atmosphere containing oxygen gas as the insulator 282. By using the pulse DC sputtering method, the film thickness distribution can be made more uniform, and the sputtering rate and film quality can be improved.

[0318] Next, the insulator 283 is formed over the insulator 282 (see FIGS. 16A to 16D). The insulator 283 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The insulator 283 is preferably formed by a sputtering method. The sputtering method, which does not require hydrogen as a deposition gas, can reduce the hydrogen concentration in the insulator 283. The insulator 283 may also have a multilayer structure. For example, a silicon nitride film may be formed by a sputtering method, and then a silicon nitride film may be formed on the silicon nitride by a CVD method. The insulator 283 and the insulator 212, which have high barrier properties, surround the transistor 200, thereby preventing moisture and hydrogen from entering from the outside.

[0319] Next, heat treatment may be performed. In this embodiment, the treatment is performed in a nitrogen atmosphere at 400° C. for 1 hour. As shown in FIG. 2, this heat treatment allows oxygen added by the formation of the insulator 282 to diffuse into the insulators 280 and 250 and to be selectively supplied to the channel formation region of the oxide 230. Note that this heat treatment may be performed not only after the formation of the insulator 283 but also after the formation of the insulator 282.

[0320] Next, openings are formed in the insulators 271, 273, 275, 280, 282, and 283, reaching the conductor 242 (see FIGS. 16A to 16D). The openings may be formed using lithography. Note that although the shape of the openings is circular in top view in FIG. 16A, the shape is not limited to this. For example, the openings may be substantially circular such as oval, polygonal such as square, or polygonal such as square with rounded corners in top view.

[0321] Next, an insulating film that will become the insulator 241 is formed, and the insulating film is anisotropically etched to form the insulator 241 (see FIGS. 16A to 16D). The insulating film that will become the insulator 241 can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. It is preferable to use an insulating film that has the function of suppressing oxygen permeation as the insulating film that will become the insulator 241. For example, it is preferable to form a film of aluminum oxide using the ALD method. Alternatively, it is preferable to form a film of silicon nitride using the PEALD method. Silicon nitride is preferable because it has a high barrier property against hydrogen.

[0322] Furthermore, dry etching, for example, may be used for anisotropic etching of the insulating film that will become the insulator 241. By providing the insulator 241 on the sidewall of the opening, it is possible to suppress the permeation of oxygen from the outside and prevent oxidation of the conductors 240a and 240b that will be formed next. It is also possible to prevent impurities such as water and hydrogen from diffusing to the outside from the conductors 240a and 240b.

[0323] Next, a conductive film that will become the conductor 240a and the conductor 240b is formed. The conductive film that will become the conductor 240a and the conductor 240b preferably has a layered structure including a conductor that has the function of suppressing the permeation of impurities such as water and hydrogen. For example, it can be a layered structure of tantalum nitride, titanium nitride, or the like, and tungsten, molybdenum, copper, or the like. The conductive film that will become the conductor 240 can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0324] Next, CMP processing is performed to remove portions of the conductive film that will become the conductors 240a and 240b, thereby exposing the upper surface of the insulator 283. As a result, the conductive film remains only in the openings, thereby forming the conductors 240a and 240b with flat upper surfaces (see FIGS. 16A to 16D). Note that the CMP processing may remove portions of the upper surfaces of the insulators 283 and 274.

[0325] Next, a conductive film is formed to become the conductor 246. The conductive film to become the conductor 246 can be formed by sputtering, CVD, MBE, PLD, ALD, or the like.

[0326] Next, the conductive film that will become the conductor 246 is processed by lithography to form the conductor 246a that contacts the upper surface of the conductor 240a and the conductor 246b that contacts the upper surface of the conductor 240b (see FIGS. 1A to 1D). At this time, a part of the insulator 283 may be removed in a region where the conductor 246a and the conductor 246b do not overlap with the insulator 283.

[0327] Next, an insulator 286 is formed on the conductor 246 and the insulator 283 (see FIGS. 1A to 1D). The insulator 286 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The insulator 286 may also be a multilayer structure. For example, a silicon nitride film may be formed by a sputtering method, and another silicon nitride film may be formed on the silicon nitride by a CVD method.

[0328] 1A to 1D can be manufactured. As shown in FIGS. 4A to 16A, 4B to 16B, 4C to 16C, and 4D to 16D, the transistor 200 can be manufactured by the method for manufacturing a semiconductor device described in this embodiment.

[0329] <Microwave processing equipment> A microwave processing apparatus that can be used in the method for manufacturing the semiconductor device will be described below.

[0330] First, the configuration of a manufacturing apparatus that minimizes the inclusion of impurities during the manufacture of semiconductor devices and the like will be described with reference to FIGS.

[0331] 17 is a schematic top view of a single-wafer processing multi-chamber manufacturing apparatus 2700. The manufacturing apparatus 2700 has an atmosphere-side substrate supply chamber 2701 equipped with a cassette port 2761 for accommodating substrates and an alignment port 2762 for aligning the substrates, an atmosphere-side substrate transfer chamber 2702 for transferring substrates from the atmosphere-side substrate supply chamber 2701, a load lock chamber 2703a for loading substrates and for switching the pressure inside the chamber from atmospheric pressure to reduced pressure or from reduced pressure to atmospheric pressure, an unload lock chamber 2703b for unloading substrates and for switching the pressure inside the chamber from reduced pressure to atmospheric pressure or from atmospheric pressure to reduced pressure, a transfer chamber 2704 for transferring substrates in a vacuum, chambers 2706a, 2706b, 2706c, and 2706d.

[0332] The atmospheric side substrate transfer chamber 2702 is connected to a load lock chamber 2703a and an unload lock chamber 2703b, the load lock chamber 2703a and the unload lock chamber 2703b are connected to a transfer chamber 2704, and the transfer chamber 2704 is connected to chambers 2706a, 2706b, 2706c and 2706d.

[0333] A gate valve GV is provided at the connection between each chamber, and each chamber can be independently maintained in a vacuum state, except for the atmosphere-side substrate supply chamber 2701 and the atmosphere-side substrate transfer chamber 2702. A transfer robot 2763a is provided in the atmosphere-side substrate transfer chamber 2702, and a transfer robot 2763b is provided in the transfer chamber 2704. Substrates can be transferred within the manufacturing apparatus 2700 by the transfer robots 2763a and 2763b.

[0334] The back pressure (total pressure) of the transfer chamber 2704 and each chamber is, for example, 1×10 -4 Pa or less, preferably 3×10 -5 Pa or less, more preferably 1×10 -5 The partial pressure of gas molecules (atoms) with a mass-to-charge ratio (m / z) of 18 in the transfer chamber 2704 and each chamber is, for example, 3×10 -5Pa or less, preferably 1×10 -5 Pa or less, more preferably 3×10 -6 The partial pressure of gas molecules (atoms) with m / z of 28 in the transfer chamber 2704 and each chamber is, for example, 3×10 -5 Pa or less, preferably 1×10 -5 Pa or less, more preferably 3×10 -6 The partial pressure of gas molecules (atoms) with m / z of 44 in the transfer chamber 2704 and each chamber is, for example, 3×10 -5 Pa or less, preferably 1×10 -5 Pa or less, more preferably 3×10 -6 Pa or less.

[0335] The total pressure and partial pressure in the transfer chamber 2704 and each chamber can be measured using a mass spectrometer, for example, a quadrupole mass spectrometer (also called Q-mass) Qulee CGM-051 manufactured by ULVAC, Inc.

[0336] It is also desirable that the transfer chamber 2704 and each chamber have a configuration with little external or internal leakage. For example, the leak rate of the transfer chamber 2704 and each chamber is 3×10 -6 Pa·m 3 / s or less, preferably 1 × 10 -6 Pa·m 3 / s or less. For example, if the leak rate of a gas molecule (atom) with m / z of 18 is 1×10 -7 Pa·m 3 / s or less, preferably 3 × 10 -8 Pa·m 3 / s or less. For example, if the leak rate of a gas molecule (atom) with m / z of 28 is 1×10 -5 Pa·m 3 / s or less, preferably 1 × 10 -6 Pa·m 3 / s or less. For example, the leak rate of a gas molecule (atom) with m / z 44 is 3 × 10 -6 Pa·m 3 / s or less, preferably 1 × 10 -6Pa·m 3 / s or less.

[0337] The leak rate can be derived from the total pressure and partial pressure measured using the mass spectrometer mentioned above. The leak rate depends on external and internal leaks. External leaks are caused by gases entering from outside the vacuum system due to tiny holes or poor seals. Internal leaks are caused by leaks from partitions such as valves within the vacuum system or gases released from internal components. In order to keep the leak rate below the above-mentioned values, measures must be taken to prevent both external and internal leaks.

[0338] For example, it is advisable to seal the opening and closing portions of the transfer chamber 2704 and each chamber with a metal gasket. It is preferable to use a metal gasket coated with iron fluoride, aluminum oxide, or chromium oxide. Metal gaskets have higher adhesion than O-rings and can reduce external leakage. Furthermore, by using a passivated metal coated with iron fluoride, aluminum oxide, chromium oxide, or the like, the release of gas containing impurities from the metal gasket can be suppressed, thereby reducing internal leakage.

[0339] Furthermore, aluminum, chromium, titanium, zirconium, nickel, or vanadium, which contain impurities and emit little gas, are used as components constituting the manufacturing apparatus 2700. The aforementioned components may also be coated with an alloy containing iron, chromium, nickel, or the like. Alloys containing iron, chromium, nickel, or the like are rigid, heat-resistant, and suitable for processing. Here, reducing the surface roughness of the components by polishing or the like to reduce the surface area can reduce the amount of emitted gas.

[0340] Alternatively, the components of the manufacturing apparatus 2700 may be coated with iron fluoride, aluminum oxide, chromium oxide, or the like.

[0341] It is preferable that the components of the manufacturing apparatus 2700 be constructed solely from metal as much as possible, and even if a viewing window made of quartz or the like is installed, it is advisable to thinly coat the surface with iron fluoride, aluminum oxide, chromium oxide, or the like to suppress gas emissions.

[0342] The adsorbed matter present in the transfer chamber 2704 and each chamber is adsorbed to the inner walls and does not affect the pressure of the transfer chamber 2704 or each chamber. However, it can cause gas emissions when the transfer chamber 2704 or each chamber is evacuated. Therefore, although there is no correlation between the leak rate and the evacuation speed, it is important to use a pump with high evacuation capacity to desorb as much adsorbed matter as possible from the transfer chamber 2704 and each chamber and evacuate them in advance. To promote the desorption of adsorbed matter, the transfer chamber 2704 and each chamber may be baked. Baking can increase the desorption rate of adsorbed matter by approximately 10 times. Baking can be performed at temperatures between 100°C and 450°C. In this case, introducing an inert gas into the transfer chamber 2704 and each chamber while removing adsorbed matter can further increase the desorption rate of water and other substances that are difficult to desorb by evacuation alone. Heating the introduced inert gas to the same temperature as the baking temperature can further increase the desorption rate of adsorbed matter. A rare gas is preferably used as the inert gas.

[0343] Alternatively, it is preferable to increase the pressure in the transfer chamber 2704 and each chamber by introducing an inert gas such as a heated rare gas or oxygen, and then evacuating the transfer chamber 2704 and each chamber again after a certain period of time has elapsed. The introduction of heated gas can desorb adsorbed substances from the transfer chamber 2704 and each chamber, thereby reducing impurities present in the transfer chamber 2704 and each chamber. It is effective to repeat this process two to 30 times, preferably five to 15 times. Specifically, by introducing an inert gas or oxygen at a temperature of 40°C to 400°C, preferably 50°C to 200°C, the pressure in the transfer chamber 2704 and each chamber can be adjusted to 0.1 Pa to 10 kPa, preferably 1 Pa to 1 kPa, and more preferably 5 Pa to 100 Pa. The pressure can be maintained for a period of 1 minute to 300 minutes, preferably 5 minutes to 120 minutes. Thereafter, the transfer chamber 2704 and each chamber are evacuated for a period of 5 minutes to 300 minutes, preferably 10 minutes to 120 minutes.

[0344] Next, chamber 2706b and chamber 2706c will be described with reference to the cross-sectional schematic diagram shown in FIG.

[0345] Chamber 2706b and chamber 2706c are chambers capable of, for example, performing microwave processing on an object to be processed. Note that chamber 2706b and chamber 2706c differ only in the atmosphere during microwave processing. Since the other configurations are common, they will be described together below.

[0346] Chamber 2706b and chamber 2706c have a slot antenna plate 2808, a dielectric plate 2809, a substrate holder 2812, and an exhaust port 2819. Also provided outside chamber 2706b and chamber 2706c are a gas supply source 2801, a valve 2802, a high-frequency generator 2803, a waveguide 2804, a mode converter 2805, a gas pipe 2806, a waveguide 2807, a matching box 2815, a high-frequency power supply 2816, a vacuum pump 2817, and a valve 2818.

[0347] The high-frequency generator 2803 is connected to a mode converter 2805 via a waveguide 2804. The mode converter 2805 is connected to a slot antenna plate 2808 via a waveguide 2807. The slot antenna plate 2808 is disposed in contact with a dielectric plate 2809. The gas supply source 2801 is connected to the mode converter 2805 via a valve 2802. Gas is delivered to chambers 2706b and 2706c via a gas pipe 2806 that passes through the mode converter 2805, the waveguide 2807, and the dielectric plate 2809. The vacuum pump 2817 evacuates gases and other gases from chambers 2706b and 2706c via a valve 2818 and an exhaust port 2819. The high-frequency power supply 2816 is connected to a substrate holder 2812 via a matching box 2815.

[0348] The substrate holder 2812 has a function of holding the substrate 2811. For example, it has a function of electrostatically or mechanically chucking the substrate 2811. It also has a function as an electrode to which power is supplied from a high-frequency power supply 2816. It also has an internal heating mechanism 2813 and has a function of heating the substrate 2811.

[0349] For example, a dry pump, a mechanical booster pump, an ion pump, a titanium sublimation pump, a cryopump, or a turbomolecular pump can be used as the vacuum pump 2817. A cryotrap may also be used in addition to the vacuum pump 2817. The use of a cryopump or a cryotrap is particularly preferable because it allows water to be efficiently pumped out.

[0350] The heating mechanism 2813 may be, for example, a heating mechanism that uses a resistance heating element or the like for heating. Alternatively, it may be a heating mechanism that uses heat conduction or heat radiation from a medium such as a heated gas for heating. For example, RTA (Rapid Thermal Annealing) such as GRTA (Gas Rapid Thermal Annealing) or LRTA (Lamp Rapid Thermal Annealing) can be used. GRTA performs heating processing using high-temperature gas. An inert gas is used as the gas.

[0351] The gas supply source 2801 may be connected to a refiner via a mass flow controller. The gas used preferably has a dew point of -80°C or lower, preferably -100°C or lower. For example, oxygen gas, nitrogen gas, and rare gas (such as argon gas) may be used.

[0352] The dielectric plate 2809 may be made of, for example, silicon oxide (quartz), aluminum oxide (alumina), or yttrium oxide (yttria). Furthermore, another protective layer may be formed on the surface of the dielectric plate 2809. The protective layer may be made of, for example, magnesium oxide, titanium oxide, chromium oxide, zirconium oxide, hafnium oxide, tantalum oxide, silicon oxide, aluminum oxide, or yttrium oxide. Because the dielectric plate 2809 is exposed to a particularly high-density region of the high-density plasma 2810 (described later), providing a protective layer can mitigate damage. As a result, an increase in particles during processing can be suppressed.

[0353] The high-frequency generator 2803 has the function of generating microwaves in the range of, for example, 0.3 GHz to 3.0 GHz, 0.7 GHz to 1.1 GHz, or 2.2 GHz to 2.8 GHz. The microwaves generated by the high-frequency generator 2803 are transmitted to a mode converter 2805 via a waveguide 2804. The mode converter 2805 converts the microwaves transmitted in TE mode to TEM mode. The microwaves are then transmitted to a slot antenna plate 2808 via a waveguide 2807. The slot antenna plate 2808 has multiple slot holes, and the microwaves pass through the slot holes and a dielectric plate 2809. An electric field is then generated below the dielectric plate 2809, generating a high-density plasma 2810. The high-density plasma 2810 contains ions and radicals depending on the gas species supplied from the gas supply source 2801. For example, oxygen radicals are present.

[0354] At this time, the ions and radicals generated by the high-density plasma 2810 can modify the film or the like on the substrate 2811. It may be preferable to apply a bias to the substrate 2811 side using a high-frequency power supply 2816. For example, an RF power supply with a frequency of 13.56 MHz or 27.12 MHz may be used as the high-frequency power supply 2816. By applying a bias to the substrate side, ions in the high-density plasma 2810 can be efficiently delivered to the depths of openings in the film or the like on the substrate 2811.

[0355] For example, oxygen radical treatment using high density plasma 2810 can be performed in chamber 2706b or chamber 2706c by introducing oxygen from gas supply source 2801.

[0356] Next, chamber 2706a and chamber 2706d will be described with reference to the schematic cross-sectional view shown in FIG.

[0357] Chamber 2706a and chamber 2706d are chambers capable of irradiating an object to be treated with electromagnetic waves, for example. Chamber 2706a and chamber 2706d differ only in the type of electromagnetic waves. Since the other configurations are largely common, they will be described together below.

[0358] Chamber 2706a and chamber 2706d each have one or more lamps 2820, a substrate holder 2825, a gas inlet 2823, and an exhaust port 2830. Also, outside chamber 2706a and chamber 2706d, a gas supply source 2821, a valve 2822, a vacuum pump 2828, and a valve 2829 are provided.

[0359] The gas supply source 2821 is connected to a gas inlet 2823 via a valve 2822. The vacuum pump 2828 is connected to an exhaust port 2830 via a valve 2829. The lamp 2820 is disposed opposite a substrate holder 2825. The substrate holder 2825 has a function of holding a substrate 2824. The substrate holder 2825 also has an internal heating mechanism 2826 that has a function of heating the substrate 2824.

[0360] A light source capable of emitting electromagnetic waves such as visible light or ultraviolet light may be used as the lamp 2820. For example, a light source capable of emitting electromagnetic waves having a peak wavelength of 10 nm to 2500 nm, 500 nm to 2000 nm, or 40 nm to 340 nm may be used.

[0361] For example, the lamp 2820 may be a light source such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high-pressure sodium lamp, or a high-pressure mercury lamp.

[0362] For example, the electromagnetic waves emitted from the lamps 2820 can be partially or completely absorbed by the substrate 2824, thereby modifying the film on the substrate 2824. For example, defects can be generated or reduced, or impurities can be removed. Note that if the process is performed while the substrate 2824 is heated, defects can be generated or reduced, or impurities can be removed efficiently.

[0363] Alternatively, for example, the substrate holder 2825 may be heated by electromagnetic waves emitted from the lamp 2820, thereby heating the substrate 2824. In this case, the substrate holder 2825 does not need to have the heating mechanism 2826 inside.

[0364] For the vacuum pump 2828, refer to the description of the vacuum pump 2817. For the heating mechanism 2826, refer to the description of the heating mechanism 2813. For the gas supply source 2821, refer to the description of the gas supply source 2801.

[0365] By using the above manufacturing apparatus, it is possible to modify the film while suppressing the inclusion of impurities in the processed object.

[0366] <Modification of Semiconductor Device> An example of a semiconductor device according to one embodiment of the present invention will be described below with reference to FIGS. 20A to 20D and 21A to 21D.

[0367] Each figure A shows a top view of the semiconductor device. Each figure B is a cross-sectional view corresponding to the portion indicated by the dashed line A1-A2 in each figure A. Each figure C is a cross-sectional view corresponding to the portion indicated by the dashed line A3-A4 in each figure A. Each figure D is a cross-sectional view corresponding to the portion indicated by the dashed line A5-A6 in each figure A. In the top view of each figure A, some elements are omitted for clarity.

[0368] In the semiconductor devices shown in each of Figures A to D, the same reference numerals are used to designate structures having the same functions as those constituting the semiconductor device shown in <Configuration Examples of Semiconductor Device>. In this section, the materials described in detail in <Configuration Examples of Semiconductor Device> can also be used as the constituent materials of the semiconductor device.

[0369] <Semiconductor Device Modification 1> The semiconductor device shown in Figures 20A to 20D is a modified example of the semiconductor device shown in Figures 1A to 1D. The semiconductor device shown in Figures 20A to 20D differs from the semiconductor device shown in Figures 1A to 1D in the shape of the insulator 283. Also, it differs in that it has an insulator 284 and an insulator 274.

[0370] 20A to 20D, insulator 214, insulator 216, insulator 222, insulator 224, insulator 275, insulator 280, and insulator 282 are patterned. Furthermore, insulator 284 is structured to cover insulators 212, insulator 214, insulator 216, insulator 222, insulator 224, insulator 275, insulator 280, and insulator 282. That is, insulator 284 contacts the top surface of insulator 282, the side surfaces of insulators 214, insulator 216, insulator 222, insulator 224, insulator 275, and insulator 280, and the top surface of insulator 212. Furthermore, insulator 284 is disposed to cover insulator 284. As a result, insulators 214, 216, 222, 224, 280, and 282, including oxide 230, are isolated from the outside by insulators 283, 284, and 212. In other words, transistor 200 is disposed within an area sealed by insulators 284 and 212.

[0371] For example, the insulators 214, 271, 275, 282, and 284 may be formed using a material capable of capturing and fixing hydrogen. Note that the insulator 284 may be formed using an insulator similar to that of the insulator 282. The insulators 212 and 283 may be formed using a material capable of suppressing the diffusion of hydrogen and oxygen. The insulators 214, 271, 275, 282, and 284 may be formed using a metal oxide having an amorphous structure, such as aluminum oxide. Typically, the insulators 212 and 283 may be formed using silicon nitride. In particular, using aluminum oxide having an amorphous structure or aluminum oxide having an amorphous structure as the insulator 284 is preferable because it may be possible to more effectively capture or fix hydrogen. This enables the manufacture of a highly reliable transistor 200 and semiconductor device with favorable characteristics.

[0372] With this configuration, it is possible to prevent hydrogen contained outside the sealed region from being mixed into the sealed region.

[0373] 20A to 20D show a structure in which the insulator 212 and the insulator 283 are provided as a single layer, but the present invention is not limited to this. For example, each of the insulator 212 and the insulator 283 may have a stacked structure of two or more layers.

[0374] The insulator 274 is provided to cover the insulator 283 and functions as an interlayer film. The insulator 274 preferably has a lower dielectric constant than the insulator 214. By using a material with a low dielectric constant as the interlayer film, parasitic capacitance generated between wirings can be reduced. The insulator 274 can be provided using, for example, a material similar to that of the insulator 280.

[0375] <Modification 2 of Semiconductor Device> 21A to 21D are modifications of the semiconductor device shown in FIGS. 20A to 20D. The semiconductor device shown in FIGS. 21A to 21D differs from the semiconductor device shown in FIGS. 20A to 20D in that it includes oxide 230c and oxide 230d. It also differs in that it includes insulator 287. It also differs in that it does not include insulator 271, insulator 272, insulator 273, or insulator 284.

[0376] 21A to 21D further includes an oxide 230c on the oxide 230b and an oxide 230d on the oxide 230c. The oxide 230c and the oxide 230d are provided in openings formed in the insulator 280 and the insulator 275. The oxide 230c is in contact with the side of the oxide 243a, the side of the oxide 243b, the side of the conductor 242a, the side of the conductor 242b, and the side of the insulator 275. The top surface of the oxide 230c and the top surface of the oxide 230d are in contact with the insulator 282.

[0377] By disposing the oxide 230d on the oxide 230c, it is possible to suppress the diffusion of impurities from structures formed above the oxide 230d to the oxide 230b or the oxide 230c. In addition, by disposing the oxide 230d on the oxide 230c, it is possible to suppress the upward diffusion of oxygen from the oxide 230b or the oxide 230c.

[0378] Furthermore, in a cross-sectional view of the transistor in the channel length direction, a groove is preferably formed in the oxide 230b, and the oxide 230c is preferably embedded in the groove. In this case, the oxide 230c is disposed so as to cover the inner wall (sidewall and bottom surface) of the groove. The thickness of the oxide 230c is preferably approximately the same as the depth of the groove. With this configuration, even if a damaged region is formed on the surface of the oxide 230b at the bottom of the opening when forming an opening for embedding the conductor 260 or the like, the damaged region can be removed. This can suppress poor electrical characteristics of the transistor 200 due to the damaged region.

[0379] Here, it is preferable that the atomic ratio of In to element M in the metal oxide used for oxide 230c is greater than the atomic ratio of In to element M in the metal oxide used for oxide 230a or oxide 230d.

[0380] When the oxide 230c is used as the main carrier path, the atomic ratio of indium to the main metal element in the oxide 230c is preferably greater than the atomic ratio of indium to the main metal element in the oxide 230b. Furthermore, the atomic ratio of In to the element M in the oxide 230c is preferably greater than the atomic ratio of In to the element M in the oxide 230b. Using a metal oxide with a high indium content for the channel formation region can increase the on-state current of the transistor. Therefore, by increasing the atomic ratio of indium to the main metal element in the oxide 230c compared to the atomic ratio of indium to the main metal element in the oxide 230b, the oxide 230c can be used as the main carrier path. Furthermore, the conduction band minimum of the oxide 230c is preferably farther from the vacuum level than the conduction band minimums of the oxides 230a and 230b. In other words, the electron affinity of the oxide 230c is preferably greater than the electron affinity of the oxide 230a and the oxide 230b, and in this case, the main path of carriers is the oxide 230c.

[0381] Specifically, the oxide 230c may be a metal oxide or indium oxide having a composition of In:M:Zn=4:2:3 (atomic ratio) or a composition close thereto, In:M:Zn=5:1:3 (atomic ratio) or a composition close thereto, or In:M:Zn=10:1:3 (atomic ratio) or a composition close thereto.

[0382] The oxide 230c is preferably a CAAC-OS, and the c-axis of the crystal of the oxide 230c is preferably oriented in a direction substantially perpendicular to the surface on which the oxide 230c is formed or the top surface of the oxide 230c. The CAAC-OS has the property of easily transferring oxygen in a direction perpendicular to the c-axis. Therefore, oxygen contained in the oxide 230c can be efficiently supplied to the oxide 230b.

[0383] Furthermore, the oxide 230d preferably contains at least one of the metal elements constituting the metal oxide used in the oxide 230c, and more preferably contains all of the metal elements. For example, the oxide 230c may be an In-M-Zn oxide, an In-Zn oxide, or an indium oxide, and the oxide 230d may be an In-M-Zn oxide, an M-Zn oxide, or an oxide of element M. This can reduce the defect state density at the interface between the oxide 230c and the oxide 230d.

[0384] Furthermore, the conduction band minimum of the oxide 230d is preferably closer to the vacuum level than the conduction band minimum of the oxide 230c. In other words, the electron affinity of the oxide 230d is preferably smaller than that of the oxide 230c. In this case, the oxide 230d is preferably made of a metal oxide that can be used for the oxide 230a or the oxide 230b. In this case, the main carrier path is the oxide 230c.

[0385] Specifically, the oxide 230c may be a metal oxide or indium oxide having an atomic ratio of In:M:Zn=4:2:3 or a similar composition, an atomic ratio of In:M:Zn=5:1:3 or a similar composition, or an atomic ratio of In:M:Zn=10:1:3 or a similar composition. The oxide 230d may be a metal oxide or an oxide of element M having an atomic ratio of In:M:Zn=1:3:4 or a similar composition, an atomic ratio of M:Zn=2:1 or a similar composition, or an atomic ratio of M:Zn=2:5 or a similar composition. Note that a similar composition includes a range of ±30% of the desired atomic ratio. Gallium is preferably used as the element M.

[0386] Furthermore, the oxide 230d is preferably a metal oxide that suppresses the diffusion or permeation of oxygen more than the oxide 230c. By providing the oxide 230d between the insulator 250 and the oxide 230c, oxygen can be efficiently supplied to the oxide 230b via the oxide 230c.

[0387] Furthermore, by making the atomic ratio of In to the main component metal element in the metal oxide used for the oxide 230d smaller than the atomic ratio of In to the main component metal element in the metal oxide used for the oxide 230c, it is possible to suppress diffusion of In toward the insulator 250. For example, the atomic ratio of In to the element M in the oxide 230d may be made smaller than the atomic ratio of In to the element M in the oxide 230c. Because the insulator 250 functions as a gate insulator, if In is mixed into the insulator 250, etc., the transistor characteristics will be poor. Therefore, by providing the oxide 230d between the oxide 230c and the insulator 250, it is possible to provide a highly reliable semiconductor device.

[0388] Note that the oxide 230c may be provided for each transistor 200. That is, the oxide 230c of one transistor 200 and the oxide 230c of another transistor 200 adjacent to the transistor 200 may not be in contact with each other. Alternatively, the oxide 230c of one transistor 200 and the oxide 230c of another transistor 200 adjacent to the transistor 200 may be separated from each other. In other words, the oxide 230c may not be disposed between the transistor 200 and the transistor 200 adjacent to the transistor 200.

[0389] In a semiconductor device in which multiple transistors 200 are arranged side by side in the channel width direction, the above structure allows the oxide 230c to be independently provided in each transistor 200. This prevents a parasitic transistor from being formed between a transistor 200 and a transistor 200 adjacent to the transistor 200, thereby preventing the leakage path from being formed. This makes it possible to provide a semiconductor device that has favorable electrical characteristics and can be miniaturized or highly integrated.

[0390] Note that the insulator 287 can be an insulator similar to the insulator 282 or the insulator 284. After the insulator 284 shown in Fig. 20 is formed, anisotropic etching can be performed using a dry etching method to form the insulator 287 that contacts the side surfaces of the insulators 214, 216, 222, 224, 275, 280, and 282 shown in Fig. 21.

[0391] Furthermore, as shown in FIG. 21 , in a configuration in which the insulators 271 and 273 are not provided, a curved surface may exist between the side surface of the conductor 242 and the top surface of the conductor 242. In other words, the end of the side surface and the end of the top surface may be curved. The curved surface may have a radius of curvature of 3 nm or more and 10 nm or less, preferably 5 nm or more and 6 nm or less, at the end of the conductor 242. The lack of corners at the end improves film coverage in subsequent film formation processes. Note that the present invention is not limited to this, and the configuration shown in FIG. 21 may further include the insulators 271, 272, and 273.

[0392] <Semiconductor Device Modification 3> The semiconductor device shown in Figures 22A to 22D is a modified example of the semiconductor device shown in Figures 20A to 20D. The semiconductor device shown in Figures 22A to 22D differs from the semiconductor device shown in Figures 20A to 20D in the shape of the insulator 214. Also, the semiconductor device shown in Figures 22A to 22D differs from the semiconductor device shown in Figures 20A to 20D in that it does not have an insulator 272. Also, the semiconductor device shown in Figures 22A to 22D differs in the structure of the insulator 275.

[0393] 22A to 22D, the insulators 214, 271, 275a, 282, and 284 each preferably contain a metal oxide having an amorphous structure. For example, the insulators 214, 271, 275a, 282, and 284 each preferably contain aluminum oxide having an amorphous structure or aluminum oxide having an amorphous structure. When the insulators 214, 271, 275a, 282, and 284 each contain a metal oxide having an amorphous structure, hydrogen contained in the transistor 200 or hydrogen present around the transistor 200 can be captured or fixed. In particular, it is preferable that hydrogen contained in the channel formation region of the transistor 200 be captured or fixed.

[0394] 22A to 22C, the insulator 250 functioning as a gate insulating film has a stacked structure of an insulator 250a and an insulator 250b. For example, silicon oxide can be used as the insulator 250a, and hafnium oxide can be used as the insulator 250b.

[0395] 22B to 22D , the insulator 214 is also present in a region other than the region overlapping with the insulator 222. In addition, in the region where the insulator 214 does not overlap with the insulator 222, the top surface of the insulator 214 is in contact with the bottom surface of the insulator 284. Furthermore, the insulator 212 is provided below the insulator 214, and the insulator 283 is provided above the insulator 284. Therefore, the transistor 200 is sealed with the insulators 214 and 284, and further sealed with the insulators 212 and 283. In other words, the transistor 200 is sealed with the insulators 214 and 284 that capture or fix hydrogen, and further sealed with the insulators 212 and 283 that suppress diffusion of hydrogen and oxygen. With such a structure, a highly reliable transistor 200 and a highly reliable semiconductor device can be manufactured.

[0396] In the semiconductor device of this modification, the insulator 275 has a stacked-layer structure of insulators 275a and 275b. For example, aluminum oxide having an amorphous structure can be used as the insulator 275a, and silicon nitride can be used as the insulator 275b. The semiconductor device of this modification does not include the insulator 272, so the insulator 275a is in contact with the side surfaces of the oxide 230a, the oxide 230b, the oxide 243, the conductor 242, and the insulator 271. Therefore, the insulator 275a can capture or fix hydrogen contained in the oxide 230a, the oxide 230b, the oxide 243, and the like. It is particularly preferable that the insulator 275a capture or fix hydrogen contained in the channel formation region of the transistor 200.

[0397] <Modification 4 of the semiconductor device> The semiconductor device shown in Figures 23A to 23D is a modified example of the semiconductor device shown in Figures 22A to 22D. The semiconductor device shown in Figures 23A to 23D differs from the semiconductor device shown in Figures 22A to 22D in the shape of the insulator 271. Also, the semiconductor device shown in Figures 23A to 23D differs in that it does not have an insulator 273.

[0398] As shown in FIG. 23B, since the insulator 273 is not provided, the insulator 275a is provided so as to contact the upper surface of the insulator 271.

[0399] The insulator 271 is used as a hard mask in the manufacturing process of the transistor 200. In this modification, the insulator 273, which can function as a hard mask like the insulator 271, is not provided. Therefore, it is preferable to adjust the thickness of the insulator 271 to suppress loss of the insulator 271 in the manufacturing process of the transistor 200. Specifically, it is preferable to form the insulator 271 in this modification thicker than the insulator 271 in the semiconductor device described above or in Modifications 1 to 3.

[0400] <Application examples of semiconductor devices> 24A and 24B will be used to describe an example of a semiconductor device including a transistor 200 according to one embodiment of the present invention, which is different from those described in the above <Structural Example of Semiconductor Device> and the above <Modified Example of Semiconductor Device>. In the semiconductor device shown in FIGS. 24A and 24B, structures having the same functions as those of the semiconductor device described in <<Modified Example of Semiconductor Device>> (see FIGS. 20A to 20D) are denoted by the same reference numerals. In this section, the transistor 200 can be made of materials described in detail in the <Structural Example of Semiconductor Device> and the <Modified Example of Semiconductor Device>.

[0401] 24A and 24B show a configuration in which a plurality of transistors 200_1 to 200_n are encapsulated by an insulator 283 and an insulator 212. Note that although the transistors 200_1 to 200_n appear to be aligned in the channel length direction in FIGS. 24A and 24B, this is not a limitation. The transistors 200_1 to 200_n may be aligned in the channel width direction or may be arranged in a matrix. Furthermore, the transistors 200_1 to 200_n may be arranged without any regularity depending on the design.

[0402] 24A, a portion where the insulator 283 and the insulator 212 contact each other (hereinafter, may be referred to as a sealing portion 265) is formed outside the plurality of transistors 200_1 to 200_n. The sealing portion 265 is formed so as to surround the plurality of transistors 200_1 to 200_n. With this structure, the plurality of transistors 200_1 to 200_n can be enclosed by the insulator 283 and the insulator 212. Therefore, a plurality of transistors surrounded by the sealing portion 265 are provided on the substrate.

[0403] Also, dicing lines (sometimes called scribe lines, division lines, or cutting lines) may be provided overlapping the sealing portion 265. The substrate is divided along the dicing lines, so that a group of transistors surrounded by the sealing portion 265 is extracted as one chip.

[0404] 24A shows an example in which the plurality of transistors 200_1 to 200_n are surrounded by one sealing portion 265, but the present invention is not limited to this. As shown in Fig. 24B, the plurality of transistors 200_1 to 200_n may be surrounded by a plurality of sealing portions. In Fig. 24B, the plurality of transistors 200_1 to 200_n are surrounded by a sealing portion 265a and further surrounded by an outer sealing portion 265b.

[0405] In this manner, by using a structure in which the plurality of transistors 200_1 to 200_n are surrounded by a plurality of sealing portions, the area in which the insulator 283 and the insulator 212 are in contact with each other increases, thereby further improving the adhesion between the insulator 283 and the insulator 212. This makes it possible to more reliably seal the plurality of transistors 200_1 to 200_n.

[0406] In this case, a dicing line may be provided overlapping the sealing portion 265a or the sealing portion 265b, or may be provided between the sealing portion 265a and the sealing portion 265b.

[0407] 24A and 24B, unlike the transistor 200 shown in FIG. 20, the upper surface of the insulator 274 is substantially flush with the upper surface of the insulator 283. Also, the insulator 284 is not provided. However, the present invention is not limited to this. For example, the insulator 274 may cover the insulator 283, or the insulator 284 may be provided.

[0408] According to one embodiment of the present invention, a semiconductor device with little variation in transistor characteristics can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with high reliability can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with good electrical characteristics can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with high on-state current can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with low power consumption can be provided.

[0409] As described above, the structures and methods described in this embodiment can be used in appropriate combination with other structures and methods described in this embodiment, structures and methods described in other embodiments, or structures and methods described in examples.

[0410] (Embodiment 2) In this embodiment mode, one mode of a semiconductor device will be described with reference to FIGS.

[0411] [Storage device 1] 25 illustrates an example of a semiconductor device (memory device) according to one embodiment of the present invention. In the semiconductor device according to one embodiment of the present invention, a transistor 200 is provided above a transistor 300, and a capacitor 100 is provided above the transistors 300 and 200. Note that the transistor 200 described in the above embodiment can be used as the transistor 200.

[0412] The transistor 200 is a transistor in which a channel is formed in a semiconductor layer containing an oxide semiconductor. The transistor 200 has a low off-state current; therefore, when used in a memory device, the stored data can be retained for a long time. That is, a refresh operation is not required or the frequency of the refresh operation is extremely low; therefore, the power consumption of the memory device can be sufficiently reduced.

[0413] 25, a wiring 1001 is electrically connected to the source of a transistor 300, and a wiring 1002 is electrically connected to the drain of the transistor 300. A wiring 1003 is electrically connected to one of the source and drain of a transistor 200, a wiring 1004 is electrically connected to a first gate of the transistor 200, and a wiring 1006 is electrically connected to a second gate of the transistor 200. The gate of the transistor 300 and the other of the source and drain of the transistor 200 are electrically connected to one electrode of a capacitor 100, and a wiring 1005 is electrically connected to the other electrode of the capacitor 100.

[0414] Moreover, the memory device shown in FIG. 25 can be arranged in a matrix to form a memory cell array.

[0415] <Transistor 300> The transistor 300 is provided on a substrate 311 and includes a conductor 316 functioning as a gate, an insulator 315 functioning as a gate insulator, a semiconductor region 313 formed of part of the substrate 311, and low-resistance regions 314a and 314b functioning as source and drain regions. The transistor 300 may be either a p-channel type or an n-channel type.

[0416] Here, in the transistor 300 shown in FIG. 25, a semiconductor region 313 (a part of a substrate 311) where a channel is formed has a convex shape. In addition, a conductor 316 is provided to cover the side and top surfaces of the semiconductor region 313 with an insulator 315 interposed therebetween. Note that the conductor 316 may be made of a material that adjusts the work function. Such a transistor 300 is also called a FIN-type transistor because it utilizes the convex portion of the semiconductor substrate. Note that an insulator may be provided in contact with the top of the convex portion and function as a mask for forming the convex portion. In addition, although the case where the convex portion is formed by processing a part of the semiconductor substrate has been shown, a semiconductor film having a convex shape may also be formed by processing an SOI substrate.

[0417] Note that the transistor 300 shown in FIG. 25 is just an example, and the structure is not limited to this, and an appropriate transistor may be used depending on the circuit configuration and driving method.

[0418] <Capacitor element 100> The capacitor 100 is provided above the transistor 200. The capacitor 100 includes a conductor 110 functioning as a first electrode, a conductor 120 functioning as a second electrode, and an insulator 130 functioning as a dielectric. Here, the insulator 130 is preferably the same as the insulator 286 described in the above embodiment.

[0419] For example, the conductor 112 and the conductor 110 can be formed simultaneously over the conductor 240. The conductor 112 functions as a plug or a wiring electrically connected to the capacitor 100, the transistor 200, or the transistor 300. The conductor 112 and the conductor 110 correspond to the conductor 246 in the above embodiment.

[0420] 25, the conductor 112 and the conductor 110 are shown as having a single layer structure, but are not limited to this configuration and may have a laminated structure of two or more layers. For example, a conductor having barrier properties and a conductor having high adhesion to the conductor having high conductivity may be formed between a conductor having barrier properties and a conductor having high conductivity.

[0421] The insulator 130 can be made of, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium nitride oxide, hafnium nitride, or the like, and can be formed as a stacked layer or a single layer.

[0422] For example, it is preferable to use a layered structure of a material with high dielectric strength, such as silicon oxynitride, and a high dielectric constant (high-k) material for the insulator 130. With this configuration, the capacitor 100 can ensure sufficient capacitance by having an insulator with high dielectric constant (high-k), and the capacitor 100 can improve its dielectric strength by having an insulator with high dielectric strength, thereby preventing electrostatic breakdown of the capacitor 100.

[0423] Examples of high-dielectric-constant (high-k) materials (materials with a high relative dielectric constant) insulators include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0424] On the other hand, materials with high dielectric strength (materials with low dielectric constant) include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with fluorine added, silicon oxide with carbon added, silicon oxide with carbon and nitrogen added, silicon oxide or resin with pores, etc.

[0425] <Wiring layer> Between each structure, a wiring layer provided with an interlayer film, wiring, plugs, etc. may be provided. Furthermore, multiple wiring layers may be provided depending on the design. Here, for a conductor functioning as a plug or wiring, the same reference numeral may be used to refer to multiple structures. Furthermore, in this specification and the like, the wiring and the plug electrically connected to the wiring may be integrated. That is, there are cases where a part of the conductor functions as the wiring, and cases where a part of the conductor functions as the plug.

[0426] For example, an insulator 320, an insulator 322, an insulator 324, and an insulator 326 are stacked in this order as an interlayer film over the transistor 300. Conductors 328 and 330 electrically connected to the capacitor 100 or the transistor 200 are embedded in the insulators 320, 322, 324, and 326. The conductors 328 and 330 function as plugs or wirings.

[0427] The insulator functioning as an interlayer film may also function as a planarizing film that covers the underlying unevenness. For example, the top surface of the insulator 322 may be planarized by a planarization process using a chemical mechanical polishing (CMP) method or the like to enhance flatness.

[0428] A wiring layer may be provided on the insulator 326 and the conductor 330. For example, in FIG. 25, an insulator 350, an insulator 352, and an insulator 354 are stacked in this order. Furthermore, a conductor 356 is formed in the insulator 350, the insulator 352, and the insulator 354. The conductor 356 functions as a plug or a wiring.

[0429] Similarly, a conductor 218 and a conductor (conductor 205) constituting the transistor 200 are embedded in the insulators 210, 212, 214, and 216. Note that the conductor 218 functions as a plug or wiring electrically connected to the capacitor 100 or the transistor 300. Furthermore, an insulator 150 is provided over the conductor 120 and the insulator 130.

[0430] Here, similar to the insulator 241 described in the above embodiment, the insulator 217 is provided in contact with the side surface of the conductor 218 that functions as a plug. The insulator 217 is provided in contact with the inner wall of the opening formed in the insulators 210, 212, 214, and 216. In other words, the insulator 217 is provided between the conductor 218 and the insulators 210, 212, 214, and 216. Note that the conductor 205 can be formed in parallel with the conductor 218, and therefore the insulator 217 may be formed in contact with the side surface of the conductor 205.

[0431] The insulator 217 may be, for example, an insulator such as silicon nitride, aluminum oxide, or silicon nitride oxide. The insulator 217 is provided in contact with the insulators 210, 212, 214, and 222, and therefore can prevent impurities such as water or hydrogen from the insulator 210 or the insulator 216 from mixing into the oxide 230 through the conductor 218. Silicon nitride is particularly suitable because it has a high barrier property against hydrogen. In addition, the insulator 217 can prevent oxygen contained in the insulator 210 or the insulator 216 from being absorbed by the conductor 218.

[0432] The insulator 217 can be formed by a method similar to that of the insulator 241. For example, a silicon nitride film is formed by a PEALD method, and an opening reaching the conductor 356 is formed by anisotropic etching.

[0433] Examples of insulators that can be used as the interlayer film include insulating oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, and metal nitride oxides.

[0434] For example, by using a material with a low dielectric constant for the insulator that functions as an interlayer film, the parasitic capacitance that occurs between wirings can be reduced. Therefore, it is advisable to select a material depending on the function of the insulator.

[0435] For example, insulators 150, 210, 352, and 354 preferably have an insulator with a low dielectric constant. For example, the insulator preferably includes silicon nitride oxide, silicon nitride, fluorine-doped silicon oxide, carbon-doped silicon oxide, carbon- and nitrogen-doped silicon oxide, pore-containing silicon oxide, or resin. Alternatively, the insulator preferably has a layered structure of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, fluorine-doped silicon oxide, carbon-doped silicon oxide, carbon- and nitrogen-doped silicon oxide, or pore-containing silicon oxide, and resin. Silicon oxide and silicon oxynitride are thermally stable, and therefore can be combined with resin to form a thermally stable layered structure with a low dielectric constant. Examples of resins include polyester, polyolefin, polyamide (e.g., nylon, aramid), polyimide, polycarbonate, and acrylic.

[0436] Furthermore, the electrical characteristics of a transistor including an oxide semiconductor can be stabilized by surrounding the transistor with an insulator that has a function of suppressing the permeation of oxygen and impurities such as hydrogen. Therefore, the insulators 214, 212, and 350 can be formed using insulators that have a function of suppressing the permeation of oxygen and impurities such as hydrogen.

[0437] Examples of insulators that can suppress the permeation of impurities such as hydrogen and oxygen include insulators containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum, and can be used in a single layer or a stacked layer. Specifically, examples of insulators that can suppress the permeation of impurities such as hydrogen and oxygen include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, silicon nitride oxide, and silicon nitride.

[0438] Conductors that can be used for wiring and plugs include materials containing one or more metal elements selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, etc. Also usable are semiconductors with high electrical conductivity, typified by polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicide.

[0439] For example, the conductors 328, 330, 356, conductor 218, and conductor 112 can be formed using a single layer or a stack of conductive materials such as metal materials, alloy materials, metal nitride materials, or metal oxide materials formed from the above materials. High-melting-point materials such as tungsten and molybdenum, which have both heat resistance and conductivity, are preferably used, and tungsten is preferred. Alternatively, they are preferably formed using low-resistance conductive materials such as aluminum and copper. Using a low-resistance conductive material can reduce wiring resistance.

[0440] <Wiring or plug in layer provided with oxide semiconductor> When an oxide semiconductor is used for the transistor 200, an insulator having an excess oxygen region may be provided near the oxide semiconductor. In that case, an insulator having a barrier property is preferably provided between the insulator having the excess oxygen region and a conductor provided in the insulator having the excess oxygen region.

[0441] 25, for example, an insulator 241 may be provided between the insulator 224 and the insulator 280 containing excess oxygen and the conductor 240. By providing the insulator 241 in contact with the insulator 222, the insulator 275, the insulator 282, and the insulator 283, the insulator 224 and the transistor 200 can be sealed with an insulator having barrier properties.

[0442] That is, the insulator 241 can prevent excess oxygen contained in the insulator 224 and the insulator 280 from being absorbed by the conductor 240. Furthermore, the insulator 241 can prevent hydrogen, which is an impurity, from diffusing into the transistor 200 through the conductor 240.

[0443] The insulator 241 may be an insulating material that has the function of suppressing the diffusion of impurities such as water or hydrogen, and oxygen. For example, it is preferable to use silicon nitride, silicon nitride oxide, aluminum oxide, or hafnium oxide. Silicon nitride is particularly preferable because it has a high barrier property against hydrogen. Other examples that can be used include metal oxides such as magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, and tantalum oxide.

[0444] As described in the above embodiment, the transistor 200 may be sealed with the insulators 212, 214, 282, and 283. Such a structure can reduce the intrusion of hydrogen contained in the insulators 274, 150, and the like into the insulator 280 and the like.

[0445] Here, the conductor 240 penetrates the insulators 283 and 282, and the conductor 218 penetrates the insulators 214 and 212. As described above, the insulator 241 is provided in contact with the conductor 240, and the insulator 217 is provided in contact with the conductor 218. This makes it possible to reduce hydrogen that gets mixed into the inside of the insulators 212, 214, 282, and 283 via the conductors 240 and 218. In this way, the transistor 200 is sealed with the insulators 212, 214, 282, 283, 241, and 217, making it possible to reduce the intrusion of impurities such as hydrogen contained in the insulator 274 from the outside.

[0446] <Dicing line> The following describes dicing lines (sometimes called scribe lines, dividing lines, or cutting lines) that are provided when dividing a large-area substrate into individual semiconductor elements to extract multiple semiconductor devices in chip form. As a dividing method, for example, first, grooves (dicing lines) for dividing the semiconductor elements are formed in the substrate, and then the substrate is cut along the dicing lines to divide (divide) the multiple semiconductor devices.

[0447] 25, for example, it is preferable to design the insulator 282, the insulator 280, the insulator 275, the insulator 224, the insulator 222, the insulator 216, and the insulator 214 so that the area where the insulator 283 and the insulator 212 contact each other overlaps with the dicing line. That is, openings are provided in the insulators 282, 280, 275, 224, 222, 216, and 214 near the area that will become the dicing line provided on the outer edge of the memory cell having multiple transistors 200.

[0448] That is, the insulators 212 and 283 are in contact with each other through openings formed in the insulators 282, 280, 275, 224, 222, 216, and 214. For example, the insulators 212 and 283 may be formed using the same material and the same method. Providing the insulators 212 and 283 using the same material and the same method can improve adhesion. For example, it is preferable to use silicon nitride.

[0449] With this structure, the transistor 200 can be surrounded by the insulator 212, the insulator 214, the insulator 282, and the insulator 283. At least one of the insulators 212, 214, 282, and 283 has a function of suppressing diffusion of oxygen, hydrogen, and water. Therefore, even when the substrate is divided into a plurality of chips by dividing the substrate into each circuit region in which the semiconductor element described in this embodiment is formed, impurities such as hydrogen or water can be prevented from entering from the side surface of the divided substrate and diffusing into the transistor 200.

[0450] Furthermore, this structure can prevent excess oxygen in the insulator 280 and the insulator 224 from diffusing to the outside. Therefore, the excess oxygen in the insulator 280 and the insulator 224 is efficiently supplied to the oxide in which a channel is formed in the transistor 200. The oxygen can reduce oxygen vacancies in the oxide in which a channel is formed in the transistor 200. This allows the oxide in which a channel is formed in the transistor 200 to be an oxide semiconductor with a low density of defect states and stable characteristics. That is, fluctuations in the electrical characteristics of the transistor 200 can be suppressed and reliability can be improved.

[0451] 25, the shape of the capacitor 100 is a planar type, but the shape of the memory device described in this embodiment is not limited to this. For example, as shown in FIG. 26, the shape of the capacitor 100 may be a cylindrical type. Note that the memory device shown in FIG. 26 has the same configuration below the insulator 150 as the semiconductor device shown in FIG. 25.

[0452] 26 includes an insulator 150 on an insulator 130, an insulator 142 on the insulator 150, a conductor 115 disposed in an opening formed in the insulator 150 and the insulator 142, an insulator 145 on the conductor 115 and the insulator 142, a conductor 125 on the insulator 145, and an insulator 152 on the conductor 125 and the insulator 145. At least a portion of the conductor 115, the insulator 145, and the conductor 125 are disposed in the openings formed in the insulator 150 and the insulator 142. An insulator 154 is disposed on the insulator 152, and a conductor 153 and an insulator 156 are disposed on the insulator 154. The conductor 140 is disposed in an opening formed in the insulator 130, the insulator 150, the insulator 142, the insulator 145, the insulator 152, and the insulator 154.

[0453] The conductor 115 functions as the lower electrode of the capacitor 100, the conductor 125 functions as the upper electrode of the capacitor 100, and the insulator 145 functions as the dielectric of the capacitor 100. The capacitor 100 has a configuration in which the upper electrode and the lower electrode face each other across the dielectric not only on the bottom surface but also on the side surfaces of the openings in the insulators 150 and 142, allowing for a larger capacitance per unit area. Therefore, the deeper the openings, the larger the capacitance of the capacitor 100 can be. Increasing the capacitance per unit area of ​​the capacitor 100 in this way can promote miniaturization or high integration of semiconductor devices.

[0454] The insulator 152 may be an insulator that can be used for the insulator 280. The insulator 142 preferably functions as an etching stopper when forming an opening in the insulator 150, and may be an insulator that can be used for the insulator 214.

[0455] The shape of the openings formed in the insulator 150 and the insulator 142 when viewed from above may be rectangular, a polygonal shape other than a rectangular, a polygonal shape with curved corners, or a circular shape including an ellipse. Here, it is preferable that the area over which the openings and the transistor 200 overlap in the top view is large. With such a configuration, the area occupied by a semiconductor device including the capacitor 100 and the transistor 200 can be reduced.

[0456] The conductor 115 is disposed in contact with the insulator 142 and an opening formed in the insulator 150. The upper surface of the conductor 115 preferably substantially coincides with the upper surface of the insulator 142. The lower surface of the conductor 115 is in contact with the conductor 110 through the opening in the insulator 130. The conductor 115 is preferably formed by an ALD method, a CVD method, or the like, and may be formed using, for example, a conductor that can be used for the conductor 205.

[0457] The insulator 145 is disposed to cover the conductor 115 and the insulator 142. For example, the insulator 145 is preferably formed by an ALD method, a CVD method, or the like. The insulator 145 may be formed using, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, zirconium oxide, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium nitride oxide, hafnium nitride, or the like, and can be provided as a stacked layer or a single layer. For example, the insulator 145 can be an insulating film in which zirconium oxide, aluminum oxide, and zirconium oxide are stacked in this order.

[0458] Furthermore, it is preferable to use a material with high dielectric strength, such as silicon oxynitride, or a high dielectric constant (high-k) material for the insulator 145. Alternatively, a laminated structure of a material with high dielectric strength and a high dielectric constant (high-k) material may be used.

[0459] Examples of high-dielectric-constant (high-k) insulators include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium. Using such high-k materials ensures sufficient capacitance of the capacitor 100 even when the insulator 145 is thick. By thickening the insulator 145, leakage current between the conductor 115 and the conductor 125 can be suppressed.

[0460] On the other hand, materials with high dielectric strength include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with fluorine added, silicon oxide with carbon added, silicon oxide with carbon and nitrogen added, silicon oxide with vacancies, and resin. For example, silicon nitride (SiN) formed using the ALD method is x ), silicon oxide (SiO x ), silicon nitride (SiN x ) can be used. By using such an insulator with high dielectric strength, the dielectric strength is improved, and electrostatic breakdown of the capacitor element 100 can be suppressed.

[0461] The conductor 125 is arranged to fill the openings formed in the insulator 142 and the insulator 150. The conductor 125 is electrically connected to the wiring 1005 via the conductor 140 and the conductor 153. The conductor 125 is preferably formed by an ALD method, a CVD method, or the like, and may be formed using, for example, a conductor that can be used for the conductor 205.

[0462] The conductor 153 is provided over the insulator 154 and is covered with the insulator 156. The conductor 153 may be any conductor that can be used for the conductor 112, and the insulator 156 may be any insulator that can be used for the insulator 152. Here, the conductor 153 is in contact with the top surface of the conductor 140 and functions as a terminal of the capacitor 100, the transistor 200, or the transistor 300.

[0463] [Storage device 2] An example of a semiconductor device (memory device) according to one embodiment of the present invention is illustrated in FIGS. 27A and 27B.

[0464] <Memory device configuration example 1> 27A is a cross-sectional view of a semiconductor device including a memory device 290. The memory device 290 shown in Fig. 27A includes a capacitor device 292 in addition to the transistor 200 shown in Fig. 1A to Fig. 1D. Fig. 27A corresponds to a cross-sectional view of the transistor 200 in the channel length direction.

[0465] The capacitor 292 includes a conductor 242b, an insulator 271b and an insulator 273b provided on the conductor 242b, an insulator 272b provided in contact with a side surface of the conductor 242b, an insulator 275 provided to cover the insulator 273b and the insulator 272b, and a conductor 294 on the insulator 275. That is, the capacitor 292 constitutes a metal-insulator-metal (MIM) capacitor. Note that one of a pair of electrodes included in the capacitor 292, i.e., the conductor 242b, can also serve as a source electrode of a transistor. Furthermore, a dielectric layer included in the capacitor 292 can also serve as a protective layer provided in the transistor, i.e., the insulators 271, 272, and 275. Therefore, part of the manufacturing process of the transistor can be used in the manufacturing process of the capacitor 292, resulting in a highly productive semiconductor device. Furthermore, one of the pair of electrodes of the capacitor 292, that is, the conductor 242b, also serves as the source electrode of the transistor, so that the area in which the transistor and the capacitor are arranged can be reduced.

[0466] The conductor 294 may be made of, for example, a material that can be used for the conductor 242.

[0467] <Memory device configuration example 2> FIG. 27B is a cross-sectional view of a semiconductor device having a memory device 290, which has a structure different from that shown in FIG. 27A. The memory device 290 shown in FIG. 27B includes a capacitor device 292 in addition to the transistor 200 shown in FIGS. 22A to 22D. Unlike the capacitor device 292 shown in FIG. 27A, a portion of the capacitor device 292 shown in FIG. 27B is provided in openings formed in the insulator 280, the insulator 275, the insulator 273b, and the insulator 271b. Note that FIG. 27B corresponds to a cross-sectional view of the transistor 200 in the channel length direction.

[0468] The capacitance device 292 includes a conductor 242b, an insulator 293 disposed on the conductor 242b, and a conductor 294 disposed on the insulator 293. The insulator 293 and the conductor 294 are disposed in openings formed in the insulators 280, 275, 273b, and 271b. The insulator 293 is disposed in contact with the bottom and side walls of the openings. That is, the insulator 293 is in contact with the top surface of the conductor 242b, the side surfaces of the insulators 271b, 273b, 275a, 275b, and 280. The insulator 293 is disposed so as to form a recess along the shape of the opening. The conductor 294 is disposed in contact with the top surface and side surfaces of the insulator 293 so as to fill the recesses. The height of the upper surfaces of the insulator 293 and the conductor 294 may be approximately the same as the height of the upper surfaces of the insulator 280, the insulator 250, and the conductor 260.

[0469] Here, the conductor 242b functions as the lower electrode of the capacitor 292, the conductor 294 functions as the upper electrode of the capacitor 292, and the insulator 293 functions as the dielectric of the capacitor 292. Thus, the capacitor 292 constitutes an MIM capacitor. One of the pair of electrodes of the capacitor 292, i.e., the conductor 242b, can also serve as the source electrode of a transistor. Therefore, part of the manufacturing process of the transistor can be used in the manufacturing process of the capacitor 292, resulting in a highly productive semiconductor device. Furthermore, since the insulator 293 can be provided separately from the structure of the transistor 200, the structure and material of the insulator 293 can be appropriately selected according to the performance required of the capacitor 292. Furthermore, since one of the pair of electrodes of the capacitor 292, i.e., the conductor 242b, also serves as the source electrode of the transistor, the area in which the transistor and the capacitor are arranged can be reduced.

[0470] The insulator 293 is preferably made of a high-dielectric-constant (high-k) material. Examples of high-dielectric-constant (high-k) insulators (materials with a high relative dielectric constant) include gallium oxide, hafnium oxide, zirconium oxide, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium nitride oxide, hafnium nitride, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium. The insulator 293 may also be made of a stack of films made of these high-dielectric-constant materials. For example, the insulator 293 may be made of an insulating film stacked in this order of zirconium oxide, aluminum oxide, and zirconium oxide.

[0471] The conductor 294 may be made of, for example, a material that can be used for the conductor 260. The conductor 294 may have a layered structure similar to the conductor 260.

[0472] 15, the insulator 293 and the conductor 294 can be formed before the insulator 282 is formed, that is, before the process shown in FIG. The insulator 293 and the conductor 294 can be formed in a manner similar to that used to form the insulator 250 and the conductor 260. That is, openings are formed in the insulator 280, the insulator 275, the insulator 273b, and the insulator 271b, and a laminated film that will become the insulator 293 and the conductor 294 is formed to fill the openings, and a portion of the laminated film is removed using CMP processing to form the insulator 293 and the conductor 294.

[0473] <Modifications of memory devices> Hereinafter, an example of a semiconductor device including a transistor 200 and a capacitor device 292 according to one embodiment of the present invention, which is different from the semiconductor device shown in the previous <Configuration Example 1 of Memory Device>, will be described with reference to FIGS. 28A , 28B , 29 , and 30 . In the semiconductor devices shown in FIGS. 28A , 28B , 29 , and 30 , the same reference numerals are used to designate structures having the same functions as those in the semiconductor device shown in the previous embodiment and <Configuration Example 1 of Memory Device> (see FIG. 27A ). In this section, the transistor 200 and the capacitor device 292 can be made of materials described in detail in the previous embodiment and <Configuration Example 1 of Memory Device>. Although the memory device shown in FIG. 27A is used as the memory device in FIGS. 28A , 28B , 29 , and 30 , the present invention is not limited thereto. For example, the memory device shown in FIG. 27B may also be used.

[0474] <<Memory Device Variation 1>> An example of a semiconductor device 600 including a transistor 200a, a transistor 200b, a capacitor 292a, and a capacitor 292b according to one embodiment of the present invention will be described below with reference to FIG. 28A.

[0475] 28A is a cross-sectional view in the channel length direction of a semiconductor device 600 including a transistor 200a, a transistor 200b, a capacitor 292a, and a capacitor 292b. The capacitor 292a includes a conductor 242a, an insulator 271a provided on the conductor 242a, an insulator 272a provided in contact with a side surface of the conductor 242a, and a conductor 294a provided to cover the insulator 271a and the insulator 272a. The capacitor 292b includes a conductor 242b, an insulator 271b provided on the conductor 242b, an insulator 272b provided in contact with a side surface of the conductor 242b, and a conductor 294b provided to cover the insulator 271b and the insulator 272b.

[0476] As shown in FIG. 28A , the semiconductor device 600 has a symmetrical configuration with the dashed line A3-A4 as the axis of symmetry. Conductor 242c serves as both the source electrode or drain electrode of transistor 200a and the source electrode or drain electrode of transistor 200b. An insulator 271c is provided on conductor 242c, and an insulator 273c is provided on insulator 271c. Conductor 246, which functions as wiring, and transistors 200a and 200b are also connected by conductor 240, which functions as a plug. By configuring the two transistors, two capacitance devices, and the connections between the wiring and plugs as described above, a semiconductor device that can be miniaturized or highly integrated can be provided.

[0477] The configuration examples of the semiconductor device shown in FIGS. 1A to 1D and 27A can be referred to for the configurations and effects of the transistor 200a, the transistor 200b, the capacitor device 292a, and the capacitor device 292b.

[0478] <<Memory Device Variation 2>> In the above, the transistor 200a, the transistor 200b, the capacitance device 292a, and the capacitance device 292b are given as examples of the configuration of the semiconductor device, but the semiconductor device described in this embodiment is not limited to this. For example, as shown in FIG. 28B , a configuration may be adopted in which a semiconductor device 600 and a semiconductor device having a configuration similar to that of the semiconductor device 600 are connected via a capacitance unit. In this specification, a semiconductor device including the transistor 200a, the transistor 200b, the capacitance device 292a, and the capacitance device 292b is referred to as a cell. For the configurations of the transistor 200a, the transistor 200b, the capacitance device 292a, and the capacitance device 292b, the above descriptions of the transistor 200a, the transistor 200b, the capacitance device 292a, and the capacitance device 292b can be referred to.

[0479] FIG. 28B is a cross-sectional view of a semiconductor device 600 having a transistor 200a, a transistor 200b, a capacitance device 292a, and a capacitance device 292b, and a cell having a configuration similar to that of the semiconductor device 600, connected via a capacitance section.

[0480] As shown in FIG. 28B, the conductor 294b, which functions as one electrode of the capacitance device 292b of the semiconductor device 600, also serves as one electrode of the capacitance device of a semiconductor device 601 having a similar configuration to the semiconductor device 600. Although not shown, the conductor 294a, which functions as one electrode of the capacitance device 292a of the semiconductor device 600, also serves as one electrode of the capacitance device of the semiconductor device adjacent to the left side of the semiconductor device 600, i.e., in the A1 direction in FIG. 28B. The same configuration is also true for the cells on the right side of the semiconductor device 601, i.e., in the A2 direction in FIG. 28B. In other words, a cell array (also referred to as a memory device layer) can be configured. This cell array configuration reduces the spacing between adjacent cells, thereby reducing the projected area of ​​the cell array and enabling higher integration. Furthermore, by arranging the cell array configuration shown in FIG. 28B in a matrix, a matrix cell array can be configured.

[0481] As described above, by forming the transistor 200a, the transistor 200b, the capacitance device 292a, and the capacitance device 292b in the configuration shown in this embodiment, the cell area can be reduced, and miniaturization or high integration of a semiconductor device having a cell array can be achieved.

[0482] Furthermore, the cell array may be configured not only in a plane but also in a stacked configuration. Fig. 29 shows a cross-sectional view of a configuration in which cell arrays 610 are stacked in n layers. As shown in Fig. 29, by stacking multiple cell arrays (cell arrays 610_1 to 610_n), cells can be integrated and arranged without increasing the occupied area of ​​the cell array. In other words, a 3D cell array can be configured.

[0483] <Memory Device Modification Example 3> FIG. 30 shows an example in which a memory unit 470 includes a transistor layer 413 having a transistor 200T and four memory device layers 415 (memory device layers 415_1 to 415_4).

[0484] Each of the memory device layers 415_1 to 415_4 includes a plurality of memory devices 420.

[0485] The memory device 420 is electrically connected to the memory device 420 in a different memory device layer 415 and the transistor 200T in the transistor layer 413 via the conductor 424 and the conductor 205.

[0486] The memory unit 470 is sealed by the insulators 212, 214, 282, and 283 (hereinafter referred to as a sealing structure for convenience). The insulator 274 is provided around the insulator 283. The insulators 274, 283, and 212 are provided with conductors 440, which are electrically connected to the element layer 411.

[0487] Furthermore, an insulator 280 is provided inside the sealing structure. The insulator 280 has a function of releasing oxygen when heated. Alternatively, the insulator 280 has an excess oxygen region.

[0488] Note that the insulators 212 and 283 are preferably made of a material having a high barrier property against hydrogen, and the insulators 214 and 282 are preferably made of a material having a function of capturing or fixing hydrogen.

[0489] For example, examples of materials having a high barrier property against hydrogen include silicon nitride and silicon nitride oxide, while examples of materials having a function of capturing or fixing hydrogen include aluminum oxide, hafnium oxide, and oxides containing aluminum and hafnium (hafnium aluminate).

[0490] Note that the crystal structure of the materials used for the insulators 212, 214, 282, and 283 is not particularly limited, and may be amorphous or crystalline. For example, an amorphous aluminum oxide film is preferably used as a material capable of capturing or fixing hydrogen. Amorphous aluminum oxide may be able to capture and fix a larger amount of hydrogen than aluminum oxide with high crystallinity.

[0491] Insulators 282 and 214 are preferably provided between the transistor layer 413 and the memory device layer 415 or between the memory device layers 415. Insulators 296 are preferably provided between the insulators 282 and 214. The insulator 296 can be made of a material similar to that of the insulator 283. Alternatively, silicon oxide or silicon oxynitride can be used. Alternatively, a known insulating material can be used.

[0492] Here, the excess oxygen in the insulator 280 can be considered as follows for the diffusion of hydrogen in the oxide semiconductor in contact with the insulator 280.

[0493] Hydrogen present in the oxide semiconductor diffuses to other structures through the insulator 280 in contact with the oxide semiconductor. Due to the diffusion of hydrogen, excess oxygen in the insulator 280 reacts with hydrogen in the oxide semiconductor to form an OH bond, which then diffuses through the insulator 280. When the hydrogen atom having the OH bond reaches a material (typically, the insulator 282) that has the function of capturing or fixing hydrogen, the hydrogen atom reacts with an oxygen atom that is bonded to an atom (e.g., a metal atom) in the insulator 282, and is captured or fixed in the insulator 282. Meanwhile, the oxygen atom of the excess oxygen that had the OH bond is presumably left as excess oxygen in the insulator 280. In other words, the excess oxygen in the insulator 280 is highly likely to play a bridging role in the diffusion of hydrogen.

[0494] In order to satisfy the above model, the manufacturing process of the semiconductor device is one of the important factors.

[0495] For example, the insulator 280 containing excess oxygen is formed over an oxide semiconductor, and then the insulator 282 is formed. After that, heat treatment is preferably performed. Specifically, the heat treatment is performed in an atmosphere containing oxygen, an atmosphere containing nitrogen, or a mixed atmosphere of oxygen and nitrogen at a temperature of 350° C. or higher, preferably 400° C. or higher. The heat treatment time is 1 hour or longer, preferably 4 hours or longer, and further preferably 8 hours or longer.

[0496] By the above heat treatment, hydrogen in the oxide semiconductor can diffuse outward through the insulator 280 and the insulator 282. That is, the absolute amount of hydrogen present in and around the oxide semiconductor can be reduced.

[0497] After the heat treatment, the insulator 283 is formed. The insulator 283 is a material having a high barrier property against hydrogen, and therefore can prevent hydrogen diffused to the outside or hydrogen present outside from entering the inside, specifically, the oxide semiconductor or the insulator 280 side.

[0498] Note that the heat treatment described above is performed after the insulator 282 is formed, but is not limited thereto. For example, the heat treatment may be performed after the transistor layer 413 is formed or after the memory device layers 415_1 to 415_3 are formed. When hydrogen is diffused outward by the heat treatment, the hydrogen diffuses upward or laterally in the transistor layer 413. Similarly, when the heat treatment is performed after the memory device layers 415_1 to 415_3 are formed, the hydrogen diffuses upward or laterally.

[0499] By using the above manufacturing process, the insulator 212 and the insulator 283 are bonded to each other, thereby forming the above-described sealing structure.

[0500] As described above, by using the above structure and manufacturing process, a semiconductor device including an oxide semiconductor with a reduced hydrogen concentration can be provided. Therefore, a semiconductor device with high reliability can be provided. Furthermore, according to one embodiment of the present invention, a semiconductor device with good electrical characteristics can be provided.

[0501] As described above, the structures and methods described in this embodiment can be used in appropriate combination with other structures and methods described in this embodiment, structures and methods described in other embodiments, or structures and methods described in examples.

[0502] (Embodiment 3) In this embodiment, a transistor including an oxide as a semiconductor (hereinafter also referred to as an OS transistor) and a memory device including a capacitor (hereinafter also referred to as an OS memory device) according to one embodiment of the present invention will be described with reference to FIGS. 31A, 31B, and 32A to 32H. The OS memory device is a memory device including at least a capacitor and an OS transistor that controls charging and discharging of the capacitor. The off-state current of the OS transistor is extremely small, so the OS memory device has excellent retention characteristics and can function as a nonvolatile memory.

[0503] <Storage device configuration example> 31A shows an example of the configuration of an OS memory device. The memory device 1400 has a peripheral circuit 1411 and a memory cell array 1470. The peripheral circuit 1411 has a row circuit 1420, a column circuit 1430, an output circuit 1440, and a control logic circuit 1460.

[0504] The column circuit 1430 includes, for example, a column decoder, a precharge circuit, a sense amplifier, a write circuit, etc. The precharge circuit has a function of precharging the wiring. The sense amplifier has a function of amplifying a data signal read from a memory cell. Note that the above wiring is connected to a memory cell in the memory cell array 1470, and will be described in detail later. The amplified data signal is output to the outside of the memory device 1400 as a data signal RDATA via the output circuit 1440. The row circuit 1420 also includes, for example, a row decoder, a word line driver circuit, etc., and can select a row to access.

[0505] The memory device 1400 is supplied with a low power supply voltage (VSS) from the outside as power supply voltages, a high power supply voltage (VDD) for the peripheral circuit 1411, and a high power supply voltage (VIL) for the memory cell array 1470. Control signals (CE, WE, RE), an address signal ADDR, and a data signal WDATA are also input from the outside to the memory device 1400. The address signal ADDR is input to a row decoder and a column decoder, and the data signal WDATA is input to a write circuit.

[0506] The control logic circuit 1460 processes control signals (CE, WE, RE) input from the outside to generate control signals for the row decoder and column decoder. The control signal CE is a chip enable signal, the control signal WE is a write enable signal, and the control signal RE is a read enable signal. The signals processed by the control logic circuit 1460 are not limited to these, and other control signals may be input as needed.

[0507] The memory cell array 1470 has a plurality of memory cells MC arranged in a matrix and a plurality of wirings. The number of wirings connecting the memory cell array 1470 and the row circuit 1420 is determined by the configuration of the memory cells MC, the number of memory cells MC in one column, etc. The number of wirings connecting the memory cell array 1470 and the column circuit 1430 is determined by the configuration of the memory cells MC, the number of memory cells MC in one row, etc.

[0508] 31A shows an example in which the peripheral circuit 1411 and the memory cell array 1470 are formed on the same plane, but the present embodiment is not limited to this. For example, as shown in FIG. 31B, the memory cell array 1470 may be provided so as to overlap a part of the peripheral circuit 1411. For example, a sense amplifier may be provided so as to overlap the memory cell array 1470 below.

[0509] 32A to 32H will be used to explain examples of the configuration of a memory cell that can be applied to the above-described memory cell MC.

[0510] [DOSRAM] 32A to 32C show circuit configuration examples of a DRAM memory cell. In this specification and the like, a DRAM using a memory cell with one OS transistor and one capacitor may be referred to as a DOSRAM (Dynamic Oxide Semiconductor Random Access Memory). The memory cell 1471 shown in FIG. 32A includes a transistor M1 and a capacitor CA. The transistor M1 includes a gate (sometimes referred to as a top gate) and a back gate.

[0511] The first terminal of the transistor M1 is connected to the first terminal of the capacitance element CA, the second terminal of the transistor M1 is connected to the wiring BIL, the gate of the transistor M1 is connected to the wiring WOL, the back gate of the transistor M1 is connected to the wiring BGL, and the second terminal of the capacitance element CA is connected to the wiring CAL.

[0512] The wiring BIL functions as a bit line, and the wiring WOL functions as a word line. The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitor CA. When writing and reading data, it is preferable to apply a low-level potential to the wiring CAL. The wiring BGL functions as a wiring for applying a potential to the back gate of the transistor M1. The threshold voltage of the transistor M1 can be increased or decreased by applying an arbitrary potential to the wiring BGL.

[0513] 32A corresponds to the memory device shown in FIG 27. That is, the transistor M1 corresponds to the transistor 200, and the capacitance element CA corresponds to the capacitance device 292.

[0514] Furthermore, the memory cell MC is not limited to the memory cell 1471, and the circuit configuration can be changed. For example, the memory cell MC may be configured such that the back gate of the transistor M1 is connected to the wiring WOL instead of the wiring BGL, as in the memory cell 1472 shown in FIG. 32B. Furthermore, for example, the memory cell MC may be configured as a memory cell including a single-gate transistor, that is, a transistor M1 without a back gate, as in the memory cell 1473 shown in FIG. 32C.

[0515] When the semiconductor device described in the above embodiment is used for the memory cell 1471 or the like, the transistor 200 can be used as the transistor M1 and the capacitor 100 can be used as the capacitor CA. By using an OS transistor as the transistor M1, the leakage current of the transistor M1 can be made very small. That is, written data can be held by the transistor M1 for a long time, so that the frequency of refreshing the memory cell can be reduced. Furthermore, the refresh operation of the memory cell can be made unnecessary. Furthermore, because the leakage current is very small, multilevel data or analog data can be held in the memory cell 1471, the memory cell 1472, and the memory cell 1473.

[0516] Furthermore, in the DOSRAM, if the sense amplifier is configured to overlap under the memory cell array 1470 as described above, the bit line can be shortened, which reduces the bit line capacitance and the storage capacitance of the memory cell.

[0517] [NOSRAM] 32D to 32G show circuit configuration examples of a gain cell type memory cell with two transistors and one capacitor. The memory cell 1474 shown in FIG. 32D includes a transistor M2, a transistor M3, and a capacitor CB. The transistor M2 has a top gate (sometimes simply referred to as a gate) and a back gate. In this specification and the like, a memory device having a gain cell type memory cell using an OS transistor as the transistor M2 may be referred to as a nonvolatile oxide semiconductor RAM (NOSRAM).

[0518] The first terminal of transistor M2 is connected to the first terminal of capacitor CB, the second terminal of transistor M2 is connected to wiring WBL, the gate of transistor M2 is connected to wiring WOL, and the back gate of transistor M2 is connected to wiring BGL. The second terminal of capacitor CB is connected to wiring CAL. The first terminal of transistor M3 is connected to wiring RBL, the second terminal of transistor M3 is connected to wiring SL, and the gate of transistor M3 is connected to the first terminal of capacitor CB.

[0519] The wiring WBL functions as a write bit line, the wiring RBL functions as a read bit line, and the wiring WOL functions as a word line. The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitance element CB. When writing data, while retaining data, and when reading data, it is preferable to apply a low-level potential to the wiring CAL. The wiring BGL functions as a wiring for applying a potential to the back gate of the transistor M2. By applying an arbitrary potential to the wiring BGL, the threshold voltage of the transistor M2 can be increased or decreased.

[0520] 32D corresponds to the memory device shown in Fig. 25. That is, the transistor M2 corresponds to the transistor 200, the capacitor CB corresponds to the capacitor 100, the transistor M3 corresponds to the transistor 300, the wiring WBL corresponds to the wiring 1003, the wiring WOL corresponds to the wiring 1004, the wiring BGL corresponds to the wiring 1006, the wiring CAL corresponds to the wiring 1005, the wiring RBL corresponds to the wiring 1002, and the wiring SL corresponds to the wiring 1001.

[0521] Furthermore, the memory cell MC is not limited to the memory cell 1474, and the circuit configuration can be changed as appropriate. For example, the memory cell MC may be configured such that the back gate of the transistor M2 is connected to the wiring WOL instead of the wiring BGL, as in the memory cell 1475 shown in FIG. 32E. Furthermore, for example, the memory cell MC may be configured as a memory cell having a single gate structure, that is, a memory cell including a transistor M2 without a back gate, as in the memory cell 1476 shown in FIG. 32F. Furthermore, for example, the memory cell MC may be configured such that the wiring WBL and the wiring RBL are combined into a single wiring BIL, as in the memory cell 1477 shown in FIG. 32G.

[0522] When the semiconductor device described in the above embodiment is used for the memory cell 1474 or the like, the transistor 200 can be used as the transistor M2, the transistor 300 can be used as the transistor M3, and the capacitor CB can be used as the capacitor CB. By using an OS transistor as the transistor M2, the leakage current of the transistor M2 can be significantly reduced. This allows written data to be held by the transistor M2 for a long time, thereby reducing the frequency of refreshing the memory cell. Furthermore, the refresh operation of the memory cell can be eliminated. Furthermore, since the leakage current is extremely small, multilevel data or analog data can be held in the memory cell 1474. The same applies to the memory cells 1475 to 1477.

[0523] Note that the transistor M3 may be a transistor having silicon in a channel formation region (hereinafter, may be referred to as a Si transistor). The conductivity type of the Si transistor may be either an n-channel type or a p-channel type. The Si transistor may have higher field-effect mobility than an OS transistor. Therefore, a Si transistor may be used as the transistor M3 functioning as a read transistor. Furthermore, by using a Si transistor as the transistor M3, the transistor M2 can be stacked on top of the transistor M3, thereby reducing the area occupied by the memory cell and achieving higher integration of the memory device.

[0524] Furthermore, the transistor M3 may be an OS transistor. When OS transistors are used for the transistors M2 and M3, the memory cell array 1470 can be configured as a circuit using only n-type transistors.

[0525] FIG. 32H shows an example of a gain cell type memory cell with three transistors and one capacitor. The memory cell 1478 shown in FIG. 32H includes transistors M4 to M6 and a capacitor CC. The capacitor CC is provided as appropriate. The memory cell 1478 is electrically connected to wirings BIL, RWL, WWL, BGL, and GNDL. The GNDL wiring is a wiring that applies a low-level potential. Note that the memory cell 1478 may be electrically connected to wirings RBL and WBL instead of wiring BIL.

[0526] The transistor M4 is an OS transistor having a back gate, and the back gate is electrically connected to the wiring BGL. Note that the back gate and the gate of the transistor M4 may be electrically connected to each other. Alternatively, the transistor M4 does not necessarily have a back gate.

[0527] Note that the transistors M5 and M6 may be n-channel Si transistors or p-channel Si transistors, or the transistors M4 to M6 may be OS transistors. In this case, the memory cell array 1470 can be configured as a circuit using only n-channel transistors.

[0528] When the semiconductor device described in the above embodiment is used in the memory cell 1478, the transistor 200 can be used as the transistor M4, the transistors M5 and M6 can be used as the transistors M5 and M6, and the capacitor 100 can be used as the capacitor CC. By using an OS transistor as the transistor M4, the leakage current of the transistor M4 can be made extremely small.

[0529] Note that the configurations of the peripheral circuit 1411, the memory cell array 1470, and the like shown in this embodiment are not limited to those described above. The arrangement or functions of these circuits, and wirings, circuit elements, and the like connected to the circuits may be changed, deleted, or added as necessary.

[0530] Generally, various storage devices (memories) are used in semiconductor devices such as computers depending on the application. Figure 33 shows various storage devices by layer. The higher the layer, the faster the access speed required, while the lower the layer, the larger the storage capacity and recording density required. Figure 33 shows, from the top layer, memories integrated as registers in arithmetic processing units such as CPUs, SRAM (Static Random Access Memory), DRAM (Dynamic Random Access Memory), and 3D NAND memory.

[0531] The memory embedded as a register in a CPU or other processing unit is frequently accessed by the processing unit because it is used to temporarily store the results of calculations. Therefore, a faster operating speed is required than a larger memory capacity. Registers also have the function of storing setting information for the processing unit.

[0532] SRAM is used, for example, in caches. Caches have the function of storing a copy of the information stored in main memory. By storing copies of frequently used data in the cache, access speed to the data can be increased.

[0533] DRAM is used, for example, as main memory. Main memory has the function of storing programs and data read from storage. The recording density of DRAM is approximately 0.1 to 0.3 Gbit / mm 2 is.

[0534] 3D NAND memory is used, for example, in storage. Storage has the function of storing data that requires long-term storage and various programs used by processing units. Therefore, storage requires a large memory capacity and high recording density rather than an operating speed. The recording density of memory devices used in storage is approximately 0.6 to 6.0 Gbit / mm 2 is.

[0535] A storage device according to one embodiment of the present invention has a high operating speed and can retain data for a long period of time. The storage device according to one embodiment of the present invention can be suitably used as a storage device located in a boundary area 901 that includes both a tier where a cache is located and a tier where a main memory is located. The storage device according to one embodiment of the present invention can also be suitably used as a storage device located in a boundary area 902 that includes both a tier where a main memory is located and a tier where a storage is located.

[0536] As described above, the structures and methods described in this embodiment can be used in appropriate combination with other structures and methods described in this embodiment, structures and methods described in other embodiments, or structures and methods described in examples.

[0537] (Fourth embodiment) In this embodiment, an example of a chip 1200 on which a semiconductor device of the present invention is mounted is shown using Figures 34A and 34B. A plurality of circuits (systems) are mounted on the chip 1200. A technology for integrating a plurality of circuits (systems) on a single chip in this way is sometimes called a system on chip (SoC).

[0538] As shown in FIG. 34A, the chip 1200 includes a CPU 1211, a GPU 1212, one or more analog arithmetic units 1213, one or more memory controllers 1214, one or more interfaces 1215, one or more network circuits 1216, and the like.

[0539] Chip 1200 is provided with bumps (not shown), which are connected to a first surface of a printed circuit board (PCB) 1201, as shown in Fig. 34B. In addition, a plurality of bumps 1202 are provided on the backside of the first surface of PCB 1201, which is connected to a motherboard 1203.

[0540] The motherboard 1203 may be provided with storage devices such as a DRAM 1221 and a flash memory 1222. For example, the DOSRAM described in the previous embodiment may be used as the DRAM 1221. Also, for example, the NOSRAM described in the previous embodiment may be used as the flash memory 1222.

[0541] The CPU 1211 preferably has multiple CPU cores. The GPU 1212 preferably has multiple GPU cores. The CPU 1211 and the GPU 1212 may each have a memory for temporarily storing data. Alternatively, a memory common to the CPU 1211 and the GPU 1212 may be provided on the chip 1200. The memory may be the NOSRAM or DOSRAM described above. The GPU 1212 is suitable for parallel calculation of a large amount of data and can be used for image processing and multiply-and-accumulate operations. By providing the GPU 1212 with an image processing circuit or a multiply-and-accumulate circuit using the oxide semiconductor of the present invention, it becomes possible to perform image processing and multiply-and-accumulate operations with low power consumption.

[0542] Furthermore, by providing the CPU 1211 and GPU 1212 on the same chip, the wiring between the CPU 1211 and GPU 1212 can be shortened, enabling high-speed data transfer from the CPU 1211 to the GPU 1212, data transfer between the memories of the CPU 1211 and GPU 1212, and transfer of the calculation results from the GPU 1212 to the CPU 1211 after calculation in the GPU 1212.

[0543] The analog calculation unit 1213 has one or both of an A / D (analog / digital) conversion circuit and a D / A (digital / analog) conversion circuit. The analog calculation unit 1213 may also be provided with the above-mentioned product-sum calculation circuit.

[0544] The memory controller 1214 has a circuit that functions as a controller for the DRAM 1221 and a circuit that functions as an interface for the flash memory 1222 .

[0545] The interface 1215 has an interface circuit with externally connected devices such as a display device, speaker, microphone, camera, and controller. Controllers include a mouse, keyboard, game controller, etc. As such an interface, a USB (Universal Serial Bus), HDMI (registered trademark) (High-Definition Multimedia Interface), etc. can be used.

[0546] The network circuit 1216 has a function of controlling connections with a LAN (Local Area Network), etc. It may also have a circuit for network security.

[0547] The above circuits (systems) can be formed in the same manufacturing process on the chip 1200. Therefore, even if the number of circuits required for the chip 1200 increases, there is no need to increase the manufacturing process, and the chip 1200 can be manufactured at low cost.

[0548] A PCB 1201 on which a chip 1200 having a GPU 1212 is provided, a motherboard 1203 on which a DRAM 1221 and a flash memory 1222 are provided can be called a GPU module 1204.

[0549] The GPU module 1204 includes the chip 1200 using SoC technology, allowing for a small size. Furthermore, due to its superior image processing capabilities, it is suitable for use in portable electronic devices such as smartphones, tablet devices, laptop PCs, and portable (portable) game consoles. Furthermore, a multiply-and-accumulate circuit using the GPU 1212 can execute techniques such as deep neural networks (DNNs), convolutional neural networks (CNNs), recurrent neural networks (RNNs), autoencoders, deep Boltzmann machines (DBMs), and deep belief networks (DBNs). Therefore, the chip 1200 can be used as an AI chip, and the GPU module 1204 can be used as an AI system module.

[0550] As described above, the structures and methods described in this embodiment can be used in appropriate combination with other structures and methods described in this embodiment, structures and methods described in other embodiments, or structures and methods described in examples.

[0551] (Embodiment 5) This embodiment mode will describe examples of electronic com...

Claims

1. An oxide semiconductor; a first conductor and a second conductor having a region disposed above the oxide semiconductor; a first insulator in contact with an upper surface of the first conductor; a second insulator in contact with an upper surface of the second conductor; a third insulator covering the first insulator and the second insulator, the third insulator having an opening formed therein and overlapping a region between the first conductor and the second conductor; a fourth insulator disposed above the third insulator, the fourth insulator having an opening formed therein and overlapping a region between the first conductor and the second conductor; a fifth insulator disposed above the oxide semiconductor and in a region between the first conductor and the second conductor; a third conductor on the fifth insulator; and a first nitride insulator disposed between the first insulator and the third insulator; a second nitride insulator disposed between the second insulator and the third insulator; the first insulator, the second insulator, and the third insulator are metal oxides having an amorphous structure; The semiconductor device, wherein the first nitride insulator and the second nitride insulator are silicon nitride.

2. In claim 1, a sixth insulator below the oxide semiconductor; and a seventh insulator in contact with an upper surface of the fourth insulator and the third conductor; The semiconductor device, wherein the sixth insulator and the seventh insulator are metal oxides having an amorphous structure.

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