Semiconductor device and manufacturing method thereof

Abstract

To ensure the reliability of a semiconductor device and to improve the performance of the semiconductor device.SOLUTION: A semiconductor device includes an n-type semiconductor substrate, a trench TR, a gate electrode GE1 formed inside the trench TR via a gate insulating film, a p-type base region PB formed on the semiconductor substrate, and an n-type emitter region NE formed in the base region PB, and the trench TR extends in the Y direction in plan view. The plurality of emitter regions NE are formed at a distance L1 from each other along the Y direction. The distance L1 is wider than one-fifth of the width W1 of the emitter region NE in the Y direction, and narrower than the width W1.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having a gate electrode formed inside a trench and a manufacturing method thereof. [Background technology]

[0002] Trench gate IGBTs (Insulated Gate Bipolar Transistors) are widely used as IGBTs with low on-resistance.

[0003] For example, Patent Document 1 discloses an IGBT with a GGEE structure. In such an IGBT, a trench is formed in an n-type semiconductor substrate, and a gate electrode is embedded in the trench with a gate insulating film interposed therebetween. A p-type base region is also formed in the semiconductor substrate, and an n-type emitter region is formed above the base region. The base region and the emitter region are formed by ion implantation in a state where an insulating film separate from the gate insulating film is formed on the semiconductor substrate. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2013-140885 Summary of the Invention [Problem to be solved by the invention]

[0005] Conventionally, a gate insulating film is formed inside the trench and on the semiconductor substrate, a polycrystalline silicon film is deposited on the gate insulating film, and the polycrystalline silicon film is then dry-etched. As a result, the polycrystalline silicon film on the semiconductor substrate is removed, and the polycrystalline silicon film is embedded inside the trench as a gate electrode. When ion implantation is performed on the semiconductor substrate, the gate insulating film on the semiconductor substrate is used as a through film to reduce damage to the semiconductor substrate.

[0006] However, because the gate insulating film is relatively thick, variations in thickness are likely to occur during the formation of the gate insulating film and during the dry etching process of the polycrystalline silicon film. Therefore, as in Patent Document 1, it is effective to remove the gate insulating film on the semiconductor substrate and perform a re-oxidation process to form a new silicon oxide film. Ion implantation is performed using this new silicon oxide film as a through film to form the base region and emitter region. The re-oxidation process is a thermal oxidation process using oxygen gas, known as dry oxidation.

[0007] The inventors of this application have found that reoxidation treatment increases the interface state density and generates hydrogen ions in the gate insulating film, degrading PBTI (Positive Bias Temperature Instability). Degradation of PBTI leads to a problem of threshold voltage fluctuation over time, which reduces the reliability of the semiconductor device.

[0008] On the other hand, for semiconductor devices, load short circuit withstand capability (the time it takes for a semiconductor device to be destroyed by latch-up when current is allowed to flow until the collector current is saturated) is used as one of the indicators for product evaluation. To improve performance, it is necessary to increase current, but this reduces load short circuit withstand capability. In this case, the spacing between each emitter region becomes narrower and the area of ​​each emitter region along the gate electrode becomes larger, which causes the problem of significant PBTI degradation.

[0009] The main objective of the present application is to achieve both suppression of threshold voltage fluctuation due to PBTI degradation and improvement of load short circuit tolerance. This ensures the reliability of the semiconductor device and improves the performance of the semiconductor device. Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0010] A brief summary of a representative embodiment of the present invention will be given below.

[0011] According to one embodiment, a semiconductor device includes a semiconductor substrate of a first conductivity type, a first trench formed in the semiconductor substrate, a first gate insulating film formed inside the first trench, a first gate electrode formed on the first gate insulating film so as to fill the first trench, a base region of a second conductivity type opposite to the first conductivity type formed in the semiconductor substrate such that a bottom of the base region is shallower than a bottom of the first trench, and a plurality of emitter regions of the first conductivity type formed in the base region, wherein the first trench extends in a first direction in a plan view, the plurality of emitter regions are spaced apart from each other by a first distance along the first direction, each of the plurality of emitter regions has a first width in the first direction, the first distance being greater than one-fifth of the first width and less than the first width.

[0012] A method for manufacturing a semiconductor device according to one embodiment includes: (a) preparing a semiconductor substrate of a first conductivity type; (b) forming a first trench in the semiconductor substrate after the step (a); (c) forming a first gate insulating film inside the first trench and on the semiconductor substrate after the step (b); (d) forming a first conductive film on the first gate insulating film so as to fill the inside of the first trench after the step (c); and (e) removing the first conductive film formed outside the trench after the step (d), thereby forming a first conductive film inside the first trench. (f) after step (e), removing the first gate insulating film formed on the semiconductor substrate, (g) after step (f), forming a first insulating film on the semiconductor substrate, (h) after step (g), forming a base region of a second conductivity type opposite to the first conductivity type in the semiconductor substrate by ion implantation so that the bottom of the base region is shallower than the bottom of the first trench, and (i) after step (h), forming a plurality of emitter regions of the first conductivity type in the base region by ion implantation, wherein the first trench extends in a first direction in a plan view, and in step (i), the plurality of emitter regions are formed along the first direction to be spaced apart by a first distance, each of the plurality of emitter regions having a first width in the first direction, the first distance being greater than one-fifth of the first width and less than the first width. [Effects of the Invention]

[0013] According to one embodiment, the reliability of the semiconductor device can be ensured and the performance of the semiconductor device can be improved. [Brief explanation of the drawings]

[0014] [Figure 1] 1 is a plan view showing a semiconductor device according to a first embodiment. [Figure 2] 1 is a plan view of a main part of a semiconductor device according to a first embodiment. [Figure 3] 1 is a cross-sectional view showing a semiconductor device in a first embodiment. [Figure 4] 2A to 2C are cross-sectional views showing a manufacturing process of the semiconductor device in the first embodiment. [Figure 5] 5 is a cross-sectional view showing a manufacturing process following FIG. 4. [Figure 6] FIG. 6 is a cross-sectional view showing a manufacturing process following FIG. 5. [Figure 7] 7A to 7C are cross-sectional views showing a manufacturing process following FIG. 6. [Figure 8] 8 is a cross-sectional view showing a manufacturing process following FIG. 7. [Figure 9] 9 is a cross-sectional view showing a manufacturing process following FIG. 8. [Figure 10] 7 is an enlarged cross-sectional view showing the details of the manufacturing process of FIG. 6. [Figure 11] FIG. 11 is an enlarged cross-sectional view showing a manufacturing step subsequent to FIG. [Figure 12] FIG. 12 is an enlarged cross-sectional view showing a manufacturing step subsequent to FIG. [Figure 13] FIG. 13 is an enlarged cross-sectional view showing a manufacturing step subsequent to FIG. [Figure 14] 14 is an enlarged cross-sectional view showing the manufacturing process subsequent to FIG. 13 and the depth relationship of each component. [Figure 15] FIG. 2 is an enlarged cross-sectional view showing the depth relationship of each component. [Figure 16] 10 is a graph showing the results of analyzing PBTI degradation. [Figure 17] FIG. 1 is an enlarged cross-sectional view showing a model of PBTI degradation. [Figure 18] 10 is a graph showing the results of analyzing the distance between each emitter region and the variation in threshold voltage. [Figure 19] FIG. 19 is a cross-sectional view showing a model for the analysis of FIG. 18. [Figure 20] FIG. 19 is a cross-sectional view showing a model for the analysis of FIG. 18. [Figure 21] FIG. 19 is a cross-sectional view showing a model for the analysis of FIG. 18. [Figure 22] FIG. 19 is a cross-sectional view showing a model for the analysis of FIG. 18. [Figure 23] FIG. 10 is an enlarged cross-sectional view showing a model of PBTI degradation of a semiconductor device in a second embodiment. [Figure 24] 10 is a graph showing the results of analyzing PBTI degradation. [Figure 25] FIG. 10 is an enlarged cross-sectional view showing the depth relationship of each component in the second embodiment. [Figure 26] FIG. 10 is an enlarged cross-sectional view showing the depth relationship of each component in the second embodiment. [Figure 27] FIG. 11 is a cross-sectional view showing a semiconductor device according to a third embodiment. [Figure 28] FIG. 10 is a plan view of a main part of a semiconductor device according to a first modified example. [Figure 29] FIG. 10 is a plan view of a main part of a semiconductor device according to a second modification. [Figure 30] FIG. 10 is a cross-sectional view showing a semiconductor device according to a second modification. DETAILED DESCRIPTION OF THE INVENTION

[0015] Hereinafter, embodiments will be described in detail with reference to the drawings. In all drawings for explaining the embodiments, components having the same functions are designated by the same reference numerals, and repeated explanations thereof will be omitted. In the following embodiments, explanations of the same or similar parts will not be repeated unless particularly necessary.

[0016] The X, Y, and Z directions described herein intersect and are perpendicular to one another. In this application, the Z direction is described as the vertical, height, or thickness direction of a structure. In addition, expressions such as "plan view" and "planar view" used in this application mean that the surface formed by the X and Y directions is a "plane," and that this "plane" is viewed from the Z direction.

[0017] (Embodiment 1) <Structure of semiconductor device> The structure of the semiconductor device 100 according to the first embodiment will be described below with reference to FIGS. 1 to 3. The main feature of the first embodiment is the structure of the emitter region NE formed along the gate electrode GE1. Such a feature will be described in detail later with reference to FIGS. 18 to 22. Before that, the overall structure of the semiconductor device 100 and a manufacturing method thereof will be described.

[0018] Fig. 1 is a plan view showing a semiconductor chip that is a semiconductor device 100. As shown in Fig. 1, most of the semiconductor device 100 is covered with an emitter electrode EE. A gate wiring GW is formed on the outer periphery of the emitter electrode EE.

[0019] A portion of each of the emitter electrode EE and the gate wiring GW is covered with a protective film (not shown). The areas exposed from this protective film serve as the emitter pad EP and the gate pad GP. External connection members such as wire bonding or clips (copper plates) are connected to the emitter pad EP and the gate pad GP, thereby electrically connecting the semiconductor device 100 to another semiconductor chip or a wiring board.

[0020] Fig. 2 is a plan view of a main part corresponding to the cell region 1A shown in Fig. 1. A semiconductor element such as an IGBT is formed in the cell region 1A. The IGBT shown in Fig. 2 is an IGBT with a GGEE structure, and is an IE type IGBT that can utilize the IE (Injection Enhancement) effect.

[0021] The IE effect is a technology that increases the concentration of charges accumulated in the drift region NV by making it difficult for holes to be discharged from the emitter electrode EE when the IGBT is in the on state. Therefore, the semiconductor device 100 has an active cell AC that performs the main operation of the IGBT and an inactive cell IAC other than the active cell AC. The gate electrode GE1 of the active cell AC is electrically connected to the gate wiring GW, and a gate potential is supplied to the active cell AC when the IGBT is in operation. The gate electrode GE2 of the inactive cell IAC is electrically connected to the emitter electrode EE, and an emitter potential is supplied to the active cell AC when the IGBT is in operation.

[0022] 3 is a cross-sectional view taken along line AA in FIG. 2. The semiconductor device 100 includes a semiconductor substrate SUB having a low-concentration n-type drift region NV. Here, the n-type semiconductor substrate SUB itself constitutes the drift region NV. The drift region NV may be a stacked structure of an n-type silicon substrate and a semiconductor layer grown on the silicon substrate by epitaxial growth while introducing phosphorus (P). In the present application, such a stacked structure will also be described as the semiconductor substrate SUB.

[0023] An n-type field stop region (impurity region) NS is formed in the semiconductor substrate SUB on the back surface side thereof. The field stop region NS is provided to prevent a depletion layer extending from the pn junction on the front surface TS side of the semiconductor substrate SUB from reaching the p-type collector region PC when the IGBT is turned off.

[0024] A p-type collector region (impurity region) PC is formed on the back surface of the semiconductor substrate SUB, The collector region PC is located below the field stop region NS.

[0025] A collector electrode CE is formed on the rear surface of the semiconductor substrate SUB. The collector electrode CE is electrically connected to the collector region PC and supplies a collector potential to the collector region PC. The collector electrode CE is made of a metal film such as an AlSi film, a Ti film, a NiV film, or an Au film.

[0026] A trench TR is formed in the semiconductor substrate SUB on the front surface side of the semiconductor substrate SUB. The trench TR penetrates an emitter region NE and a base region PB, which will be described later, and reaches the semiconductor substrate SUB. The depth of the trench TR is, for example, not less than 2 μm and not more than 3 μm.

[0027] A gate insulating film GI is formed inside the trench TR. Gate electrodes GE1 and GE2 are formed on the gate insulating film GI so as to fill the trench TR. The gate insulating film GI is, for example, a silicon oxide film, and the gate electrodes GE1 and GE2 are, for example, polycrystalline silicon films doped with n-type impurities. The thickness of the gate insulating film GI is, for example, 100 nm.

[0028] In the active cell AC, a hole barrier region (impurity region) NHB is formed in the semiconductor substrate SUB between a pair of trenches TR (a pair of gate electrodes GE1). A p-type base region (impurity region) PB is formed in the hole barrier region NHB. An n-type emitter region (impurity region) NE is formed in the p-type base region PB. The bottom of the base region PB is shallower than the bottom of the trench TR, and the bottom of the emitter region NE is shallower than the bottom of the base region PB.

[0029] In the inactive cell IAC, a hole barrier region NHB is formed in the semiconductor substrate SUB between the pair of trenches TR (the pair of gate electrodes GE2). A p-type floating region (impurity region) PF is formed in the semiconductor substrate SUB between the gate electrodes GE1 and GE2. A p-type base region PB is formed in the hole barrier region NHB and the floating region PF. To enhance high-voltage resistance characteristics, the floating region PF is preferably formed deeper than the bottom of the trench TR, and more preferably formed to cover the bottom of the trench TR.

[0030] An interlayer insulating film IL is formed on the semiconductor substrate SUB. The interlayer insulating film IL includes an insulating film IF1 formed on the semiconductor substrate SUB and an insulating film IF2 formed on the insulating film IF1. The insulating film IF1 is a silicon oxide film. The insulating film IF2 is a silicon oxide film containing boron and phosphorus, and is a BPSG (Boro Phospho Silicate Glass) film. The thickness of the insulating film IF1 is, for example, not less than 20 nm and not more than 50 nm.

[0031] In the active cell AC, the contact hole CH penetrates the interlayer insulating film IL and the emitter region NE and reaches the base region PB. The contact hole CH is formed so as to be in contact with the emitter region NE and the base region PB.

[0032] The interlayer insulating film IL is recessed above the contact hole CH. As a result, part of the upper surface of the emitter region NE is exposed from the interlayer insulating film IL. Therefore, inside the contact hole CH, the emitter electrode EE is in contact not only with the side surface of the emitter region NE but also with part of the upper surface of the emitter region NE. This reduces the contact resistance between the emitter electrode EE and the emitter region NE.

[0033] The structure of the contact hole CH in the inactive cell IAC is almost the same as that of the active cell AC, except that it does not have an emitter region NE. In both the active cell AC and the inactive cell IAC, a p-type high-concentration diffusion region (impurity region) PR is formed around the bottom of the contact hole CH. The high-concentration diffusion region PR is provided to reduce contact resistance with the emitter electrode EE and to prevent latch-up.

[0034] Although not shown here, the contact holes CH are also formed on parts of the gate electrodes GE1 and GE2.

[0035] An emitter electrode EE is formed on the interlayer insulating film IL so as to fill the contact hole CH. The emitter electrode EE is electrically connected to the emitter region NE, the base region PB, the heavily doped diffusion region PR, and the gate electrode GE2, and supplies an emitter potential to these regions.

[0036] Although not shown here, a gate wiring GW is also formed on the interlayer insulating film IL in the same process as the emitter electrode EE. The gate wiring GW is embedded inside the contact hole CH on the gate electrode GE1, electrically connected to the gate electrode GE1, and supplies a gate potential to the gate electrode GE1. The emitter electrode EE and gate wiring GW are made of, for example, a TiW film and an aluminum film formed on the TiW film. The aluminum film is the main conductor film of the emitter electrode EE and gate wiring GW and is sufficiently thicker than the TiW film.

[0037] The emitter electrode EE and the gate wiring GW may also include the TiW film and the aluminum film, and may be composed of a wiring portion formed on the interlayer insulating film IL and a plug formed inside the contact hole CH. In this case, the plug is composed of a laminated film of a barrier metal film and a conductive film. The barrier metal film is composed of, for example, a laminated film of a titanium film and a titanium nitride film formed on the titanium film. The conductive film is composed of, for example, a tungsten film.

[0038] The impurity concentration of each impurity region is shown below. The impurity concentration of the drift region NV is 1×10 13 cm -3 Above 2 x 10 14 cm -3 The impurity concentration of the field stop region NS is higher than that of the drift region NV, and is 5×10 16 cm -3 Above and up to 5 x 10 17 cm -3 The impurity concentration of the hole barrier region NHB is higher than that of the drift region NV, and is 1×10 16 cm -3 Above 1×10 17 cm -3 The impurity concentration of the emitter region NE is higher than that of the hole barrier region NHB, and is 1×10 18 cm -3 Above 1×10 21 cm -3 The impurity concentration of the collector region PC is 1×10 17 cm -3 Above and up to 1×10 21 cm -3 The impurity concentration of the floating region PF is 1×10 15 cm -3 Above 1×10 16 Less than cm -3 The impurity concentration of the base region PB is higher than that of the floating region PF, and is 1×10 16 cm -3 Above 1×10 18 cm -3 The impurity concentration of the high-concentration diffusion region PR is higher than the impurity concentration of the base region PB, and is 1×10 18 cm -3 Above 1×10 21 cm -3 The following is the result.

[0039] <Method of manufacturing a semiconductor device> A method for manufacturing the semiconductor device 100 according to the first embodiment will be described below with reference to FIGS.

[0040] 4, first, a semiconductor substrate SUB having an n-type drift region NV is prepared. Next, an n-type hole barrier region NHB and a p-type floating region PF are formed in the semiconductor substrate SUB by photolithography and ion implantation.

[0041] Next, a trench TR is formed in the semiconductor substrate SUB. First, an insulating film made of, for example, a silicon oxide film is formed on the semiconductor substrate SUB, and the insulating film is patterned by photolithography and dry etching to form a hard mask. Next, an anisotropic etching process is performed on the semiconductor substrate SUB using the hard mask as a mask, thereby forming a trench TR in the semiconductor substrate SUB. Thereafter, the hard mask is removed by wet etching or the like.

[0042] 5, first, the impurities contained in the hole barrier region NHB and the floating region PF are diffused by subjecting the semiconductor substrate SUB to a heat treatment at, for example, a temperature of 1000° C. or higher and 1200° C. or lower. This heat treatment causes the hole barrier region NHB to diffuse to near the bottom of the trench TR, and the floating region PF to diffuse to a position deeper than the bottom of the trench TR so as to cover the bottom of the trench TR.

[0043] Next, a gate insulating film GI is formed inside the trench TR and on the semiconductor substrate SUB. The gate insulating film GI is formed by thermal oxidation treatment (wet oxidation treatment) using water vapor in an atmosphere at 950°C. The thickness of the gate insulating film GI is, for example, 100 nm. Next, a conductive film PL, such as a polycrystalline silicon film doped with n-type impurities, is formed on the gate insulating film GI by, for example, a CVD method so as to fill the inside of the trench TR.

[0044] 6, first, the conductive film PL formed outside the trench TR is removed by dry etching. The conductive film PL formed inside the trench TR is left as gate electrodes GE1 and GE2. Next, the gate insulating film GI formed outside the trench TR is removed by anisotropic etching and isotropic etching.

[0045] 7, an insulating film IF1 made of a silicon oxide film is formed on a semiconductor substrate SUB. The insulating film IF1 is formed by thermal oxidation treatment (dry oxidation treatment) using oxygen gas in an atmosphere at 950° C. The thickness of the insulating film IF1 is, for example, not less than 20 nm and not more than 50 nm.

[0046] Next, using the insulating film IF1 as a through film, a p-type base region PB is formed in the semiconductor substrate SUB (floating region PF and hole barrier region NHB) by photolithography and ion implantation. Next, an n-type emitter region NE is formed in the base region PB of the active cell AC by photolithography and ion implantation.

[0047] Next, an insulating film IF2 is formed on the insulating film IF1 by, for example, a CVD method. The insulating film IF2 is a silicon oxide film containing boron and phosphorus, and is a BPSG film. The insulating films IF1 and IF2 each constitute a part of the interlayer insulating film IL. The thickness of the insulating film IF2 is thicker than the thickness of the insulating film IF1, for example, 1000 nm. Next, the insulating film IF2 is subjected to a heat treatment (reflow treatment) at, for example, 950°C for 30 minutes. This reflow treatment softens the insulating film IF2, and the upper surface of the insulating film IF2 is flattened.

[0048] 8, a contact hole CH is formed in the insulating film IF2, the insulating film IF1, the emitter region NE, and the base region PB by photolithography and dry etching. The bottom of the contact hole CH is located in the base region PB.

[0049] Next, p-type high concentration diffusion regions PR are formed at the bottom of the contact holes CH by photolithography and ion implantation, followed by heat treatment at 950° C. for 30 seconds to activate the impurities contained in each impurity region.

[0050] 9, the insulating films IF2 and IF1 are recessed by isotropic etching. For example, an aqueous solution containing hydrofluoric acid is used for this isotropic etching. As a result, the opening width of the contact hole CH located on the semiconductor substrate SUB becomes larger than the opening width of the contact hole CH located inside the semiconductor substrate SUB. The recession amount of the insulating films IF2 and IF1 due to the isotropic etching is about 130 nm.

[0051] Next, an emitter electrode EE is formed on the interlayer insulating film IL so as to fill the contact hole CH. First, a TiW film is formed on the interlayer insulating film IL by, for example, sputtering, and then an aluminum film is formed on the TiW film by, for example, sputtering. Next, the TiW film and the aluminum film are patterned by photolithography and dry etching to form the emitter electrode EE. Although not shown here, the gate wiring GW is also formed in the same process as the process of forming the emitter electrode EE.

[0052] After the TiW film is formed by the sputtering method, a hydrogen annealing process is performed to form a metal alloy, for example, at 400° C. to 600° C. in a hydrogen atmosphere for 30 minutes.

[0053] The structure shown in Figure 3 is then obtained through the following manufacturing steps. First, ions are implanted from the backside of the semiconductor substrate SUB to form an n-type field stop region NS and a p-type collector region PC. After these ion implantations, laser annealing is performed to activate the impurities contained in the field stop region NS and the collector region PC. Next, a metal film such as an AlSi film, Ti film, NiV film, or Au film is formed by, for example, sputtering on the collector region PC exposed on the backside of the semiconductor substrate SUB. This metal film becomes the collector electrode CE.

[0054] <Study by the inventors of the present application> As described above, since the thickness of the gate insulating film GI is relatively thick, variations in the thickness of the gate insulating film GI are likely to occur during the formation of the gate insulating film GI and during the dry etching process of the conductive film PL. Therefore, in the first embodiment, the insulating film IF1 is re-formed to have a uniform and thin thickness, and the insulating film IF1 is used as a through film for ion implantation.

[0055] Furthermore, wet oxidation is used to form the gate insulating film GI, while dry oxidation is used to form the insulating film IF1. In wet oxidation, the solubility of water vapor is high and the diffusion rate of H2O molecules is high, resulting in a faster oxidation rate than in dry oxidation. Although the oxidation rate is slow in dry oxidation, dry oxidation is suitable for forming the insulating film IF1 in terms of forming a film of uniform thickness.

[0056] 6 and subsequent manufacturing steps will be described in detail below with reference to Figures 10 to 15. Figure 10 shows a state in which, after the gate insulating film GI and the conductive film PL are formed, the conductive film PL formed outside the trench TR is removed and the gate electrode GE1 is formed.

[0057] 10, in order to repair etching damage to the upper surface of the gate electrode GE1, a thin silicon oxide film may be formed on the upper surface of the gate electrode GE1 by performing a thermal oxidation process (dry oxidation process) using oxygen gas in an atmosphere at 950° C. In FIG. 10, such a silicon oxide film is illustrated as being integrated with the gate insulating film GI.

[0058] Although the periphery of the gate electrode GE1 will be described here, the same manufacturing steps are also carried out around the gate electrode GE2, except for the formation of the emitter region NE.

[0059] As shown in Figure 11, an anisotropic etching process is performed to reduce the thickness of the gate insulating film GI. If an attempt is made to remove all of the gate insulating film GI on the semiconductor substrate SUB by the anisotropic etching process, over-etching will result in etching damage to the semiconductor substrate SUB. Therefore, most of the gate insulating film GI is removed by the anisotropic etching process, but part of the gate insulating film GI is left outside the trench TR.

[0060] As shown in FIG. 12, an isotropic etching process is performed to remove the gate insulating film GI formed outside the trench TR. At this time, since the etching also progresses from the upper surface side of the gate electrode GE1, a part of the gate insulating film GI that is in contact with the side surface of the gate electrode GE1 inside the trench TR is also removed. As a result, a part of the side surface of the gate electrode GE1 is exposed. In other words, the upper part of the gate electrode GE1 is exposed.

[0061] 13, an insulating film IF1 made of a silicon oxide film is formed on a semiconductor substrate SUB. The insulating film IF1 is formed by thermal oxidation treatment (dry oxidation treatment) using oxygen gas in an atmosphere at 950° C. The thickness of the insulating film IF1 formed on the semiconductor substrate SUB is thinner than the thickness of the gate insulating film GI formed on the semiconductor substrate SUB in FIG. 5, is half or less of the thickness of the gate insulating film GI, and is, for example, 20 nm or more and 50 nm or less.

[0062] By the dry oxidation process, the insulating film IF1 is also formed between the side surface of the trench TR and the gate insulating film GI, like a bird's beak. The insulating film IF1 is also formed on a part of the exposed side surface of the gate electrode GE1. That is, the upper part of the gate electrode GE1 is oxidized, and the corner formed by the upper surface of the gate electrode GE1 and the side surface of the gate electrode GE1 is oxidized. Although the gate insulating film GI and the insulating film IF1 are integrated, they are illustrated separately here for ease of understanding.

[0063] Next, as shown in FIG. 14, a base region PB is formed in the semiconductor substrate SUB by photolithography and ion implantation, and an emitter region NE is formed in the base region PB. These ion implantations are performed using the insulating film IF1 as a through film. The ion implantation of the base region PB is performed using boron with an energy of 110 keV and a dose of 1×10 13 cm 2 Above 2 x 10 13 cm 2 The ion implantation of the emitter region NE is performed using arsenic, with an energy of 100 keV and a dose of 1×10 15 cm 2 Above 5 x 10 15 cm 2 It is carried out under the following conditions:

[0064] In the first embodiment, the boundary 10 between the base region PB and the emitter region NE is located, for example, at a position not less than 100 nm and not more than 200 nm from the upper surface of the semiconductor substrate SUB.

[0065] Reference symbol D1 indicates the depth position of the insulating film IF1 formed between the side surface of the trench TR and the gate insulating film GI. Reference symbol D2 indicates the depth position of the insulating film IF1 formed on a part of the side surface of the gate electrode GE1. The boundary 10 is located at a position shallower than the depths D1 and D2 of these insulating films IF1. As shown in FIG. 15, the boundary 10 is located at a position shallower than the part (depth D3) of the side surface of the gate electrode GE1 exposed in FIG. 12. The depth D3 is approximately the same as the depth D2.

[0066] According to the research of the present inventors, it has been found that dry oxidation treatment increases the interface state, forms hydrogen ions, and deteriorates PBTI. Originally, the interface state is in a state where the SiH junction at the interface is broken. Because wet oxidation treatment is performed in an HO atmosphere, the interface state re-bonds with hydrogen in the HO, making it easier to regenerate the SiH junction. Therefore, it is presumed that wet oxidation treatment is easy to reduce the interface state. On the other hand, dry oxidation treatment is performed in an oxygen gas atmosphere, making it difficult to regenerate the SiH junction. Therefore, it is presumed that dry oxidation treatment is difficult to reduce the interface state.

[0067] Fig. 16 is a graph showing the results of an analysis of PBTI degradation by the present inventors. Fig. 17 is a cross-sectional view showing a model of PBTI degradation according to the first embodiment.

[0068] FIG. 16 shows the study example (circle) and the first embodiment (circle). In the study example (circle), the gate insulating film GI was not removed and the insulating film IF1 was not formed by dry oxidation treatment. Instead, the gate insulating film GI was used as a through film for ion implantation. In the first embodiment (circle), the threshold voltage (Vth) fluctuated over time due to PBTI degradation. Using a component separation method, the inventors of the present application have clarified that PBTI degradation includes an interface state component and a trap component due to hydrogen ions in the gate insulating film. Hydrogen ions diffused by PBTI stress terminate the interface state, resulting in a decrease in the threshold voltage. On the other hand, when positively charged hydrogen ions approach the interface between the gate insulating film GI and the base region PB, the hydrogen ions act as traps in the film, presumably reducing the threshold voltage.

[0069] That is, as shown in FIG. 17, if a portion where there is an interface state and a portion where hydrogen ions are distributed is used as a channel region, a fluctuation (ΔVth) in the threshold voltage occurs.

[0070] <Main features of the first embodiment> The semiconductor device 100 according to the first embodiment will be described below with reference to FIG. 2 and FIGS.

[0071] 2, the trench TR, the gate electrode GE1, the gate electrode GE2, and the contact hole CH extend in the Y direction. The emitter regions NE are formed between a pair of trenches TR (a pair of gate electrodes GE1) and are spaced apart from each other by a distance L1 along the Y direction. The base region PB located below the emitter region NE adjacent to the gate electrode GE1 is used as a channel region.

[0072] 2, the width of each of the multiple emitter regions NE in the Y direction is indicated as width W1. Width W1 is the effective gate width, and the sum of the multiple widths W1 is the overall gate width of one active cell AC.

[0073] Fig. 18 is a graph showing the results of an experiment conducted by the inventors, illustrating the relationship between the distance L1 and the change in threshold voltage (ΔVth) due to the PBTI degradation described above. Figs. 19 to 22 are cross-sectional views taken along line BB in Fig. 2, and each diagrammatically illustrates cases 1 to 4 shown in Fig. 18.

[0074] 19 to 22, the emitter region NE includes a high-concentration region NEa and a low-concentration region NEb having an impurity concentration lower than that of the high-concentration region NEa. The low-concentration region NEb is a region into which the impurities constituting the high-concentration region NEa are diffused from the high-concentration region NEa by heat treatment. The low-concentration region NEb is not a region with a uniform impurity concentration, but in fact, the impurity concentration decreases with increasing distance from the high-concentration region NEa.

[0075] Therefore, more specifically, the width W1 is the sum of the width W1a of the high-concentration region NEa in the Y direction and twice the width W1b of the low-concentration region NEb diffused from the high-concentration region NEa. The distance L1 is the distance by which the low-concentration regions NEb are spaced apart from one another in the Y direction.

[0076] 18, the inventors' study revealed that the fluctuation of the threshold voltage changes depending on the value of the distance L1. For example, in Cases 1 and 4, the fluctuation of the threshold voltage can be kept to a minimum. However, in Cases 2 and 3, the fluctuation of the threshold voltage becomes very large.

[0077] As shown in Figure 19, if the distance L1 is sufficiently large and adjacent emitter regions NE (low concentration regions NEb) are not in contact with each other, no current flows through the base region PB located between the two emitter regions NE, and therefore the fluctuation in threshold voltage is small.

[0078] However, as shown in FIGS. 20 and 21, when the distance L1 becomes equal to or less than zero and the adjacent low-concentration regions NEb come into contact, current also begins to flow in the base region PB located around the contact point. That is, the base region PB located around the contact point begins to function as a parasitic channel region. This parasitic channel region has a larger exposed area of ​​the base region PB than the base region PB located below the high-concentration region NEa, so the impact of PBTI degradation is greater. In other words, referring to FIG. 17, at the contact point, the position of the boundary 10 can be considered to be close to the upper surface of the semiconductor substrate SUB, so the impact of PBTI degradation is greater.

[0079] 22, if the two emitter regions NE are brought closer together so that their high-concentration regions NEa overlap, the fluctuation in threshold voltage can be suppressed to the same extent as in Case 1. In other words, if the areas that are significantly affected by PBTI degradation are covered with the high-concentration regions NEa, the only difference between Case 1 and Case 4 is the gate width (width W1 of the emitter region NE).

[0080] In this way, by setting the width W1 wide and increasing the effective gate width, the amount of current obtained can be increased. At the same time, by setting the distance L1 to an appropriate value, it is possible to minimize the fluctuation in threshold voltage due to PBTI degradation. In other words, it is possible to suppress the fluctuation in threshold voltage and improve the load short circuit resistance at the same time. This ensures the reliability of the semiconductor device 100 and improves the performance of the semiconductor device 100.

[0081] In the first embodiment, the width W1a is, for example, 1.0 μm, the width W1b is, for example, 0.2 μm, and the width W1 is, for example, 1.4 μm. From the viewpoint of minimizing the influence of PBTI degradation, it is preferable that the distance L1 be wider than one-fifth of the width W1. Furthermore, taking into consideration a margin for mask misalignment and the diffusion coefficient of the low concentration region NEb, it is preferable that the distance L1 be 0.2 μm or more.

[0082] On the other hand, if the distance L1 is set too wide, the proportion of the total gate width in the active cell AC decreases, resulting in a decrease in the amount of current obtained. Therefore, it is preferable that the distance L1 is narrower than the width W1. That is, in the first embodiment, it is preferable that the relationship "width W1 / 5<distance L1<width W1" is satisfied. It is also preferable that the lower limit of the distance L1 is 0.2 μm or more.

[0083] (Embodiment 2) 23 to 26, the semiconductor device 100 according to the second embodiment will be described below. In the following description, differences from the first embodiment will be mainly described, and descriptions of points that overlap with the first embodiment will be omitted.

[0084] In the second embodiment, the emitter region NE is formed deeper than in the first embodiment. For this reason, the ion implantation of the emitter region NE is performed in two steps. The first ion implantation is performed using arsenic, with an energy of 100 keV and a dose of 1×10 15 cm 2 Above 5 x 10 15 cm 2 The second ion implantation is performed using phosphorus, with an energy of 70 keV and a dose of 1×10 14 cm 2 Above 1×10 15 cm 2 It is carried out under the following conditions:

[0085] 23, in the second embodiment, the boundary 10 between the base region PB and the emitter region NE is located at a position 300 nm to 500 nm from the top surface of the semiconductor substrate SUB. By positioning the boundary 10 deeper in this way, a portion where threshold voltage fluctuations due to PBTI degradation are likely to occur can be avoided from being used as the channel region, and a portion where PBTI degradation is less likely to occur can be used as the channel region.

[0086] 24 is a graph showing the variation in threshold voltage in the first embodiment and the second embodiment. It can be seen that the variation in threshold voltage is suppressed in the second embodiment (◯) compared to the first embodiment (□). Therefore, the reliability of the semiconductor device 100 can be further improved.

[0087] 25, in the second embodiment, the boundary 10 is located at a position deeper than the depths D1 and D2 of the insulating film IF1. Also, as shown in FIG. 26, the boundary 10 is located at a position deeper than a part (depth D3) of the side surface of the gate electrode GE1 exposed in FIG.

[0088] The fact that the boundary 10 is located at a position deeper than the insulating film IF1 can also be expressed as follows: As shown in FIGS. 25 and 26 , the dry oxidation process results in a distance L2 between the gate electrode GE1 and the emitter region NE above the boundary 10 being wider than a distance L3 between the gate electrode GE1 and the base region PB below the boundary 10. Furthermore, the distance L2 increases with increasing distance to the upper surface of the gate electrode GE1. In other words, above the boundary 10, the width of the gate electrode GE1 decreases with increasing distance to the upper surface of the gate electrode GE1. The difference between the distance L2 and the distance L3 at the position of the upper surface of the gate electrode GE1 is 30 nm or more and 100 nm or less.

[0089] (Embodiment 3) A semiconductor device 100 according to the third embodiment will be described below with reference to Fig. 27. In the following description, differences from the first embodiment will be mainly described, and explanation of points that overlap with the first embodiment will be omitted. Fig. 27 is a cross-sectional view taken along line BB shown in Fig. 2.

[0090] 27, in the third embodiment, counter-doped regions PD are formed between a plurality of emitter regions NE. The counter-doped regions PD are p-type impurity regions or intrinsic semiconductor regions having a lower impurity concentration than the base regions PB. The counter-doped regions PD are formed to be shallower than the base regions PB and deeper than the heavily doped regions NEa.

[0091] Such a counter-doped region PD is formed by introducing a p-type impurity, such as boron, into the base region PB by ion implantation after the step of forming the base region PB or the step of forming the emitter region NE. The impurity concentration of the counter-doped region PD is set to such an extent that the region that was the low-concentration region NEb in the first embodiment is inverted to p-type or the impurity concentration of the low-concentration region NEb is canceled out.

[0092] The presence of the counter-doped region PD reduces the possibility of multiple emitter regions NE coming into contact with each other. This makes it easier to suppress fluctuations in threshold voltage due to PBTI degradation. Furthermore, since it is no longer necessary to consider the width W1b of the low-concentration region NEb in the Y direction, the emitter regions NE can be placed closer to each other by the width W1b.

[0093] Furthermore, the technology described in the third embodiment may be combined with the technology described in the second embodiment.

[0094] (Variation 1) The semiconductor device 100 according to the first modification of the first embodiment will be described below with reference to FIG.

[0095] In Modification 1, the width of the emitter region NE in the Y direction is width W2. The distance that the multiple emitter regions NE are spaced apart from one another in the Y direction is distance L4. Width W2 is about three times width W1 in Embodiment 1, and distance L4 is about three times distance L1 in Embodiment 1.

[0096] In this way, even if the width W2 and the distance L4 are increased by the same proportion, the total gate width of the active cell AC remains the same as in the first embodiment, and the amount of current obtained remains unchanged. Therefore, even in the first modification, it is possible to suppress the threshold voltage due to PBTI degradation and improve the load short circuit resistance at the same time.

[0097] Furthermore, the technology described in the first modification may be applied in combination with the technology described in the second and third embodiments.

[0098] (Variation 2) 29 and 30, a semiconductor device 100 according to the second modification of the first embodiment will be described below. Fig. 30 is a cross-sectional view taken along the line CC shown in Fig. 29.

[0099] Although the IGBT with the GGEE structure has been described in the first embodiment, the technology of the present application can also be applied to IGBTs with other structures. In the second modification, an IGBT with the GE structure will be described.

[0100] 29 and 30 , in Modification 2, the trench TR and gate electrode GE2 of the inactive cell IAC are adjacent to the trench TR and gate electrode GE1 of the active cell AC in the X direction. The base region PB, multiple emitter regions NE, and heavily doped diffusion region PR of the active cell AC are formed between these trenches TR.

[0101] The contact hole CH penetrates the interlayer insulating film IL and the emitter region NE and reaches the base region PB. The contact hole CH is also formed to reach a part of the gate electrode GE2. Therefore, the emitter electrode EE is not only connected to the emitter region NE, the base region PB, and the heavily doped diffusion region PR, but is also electrically connected to the gate electrode GE2 and supplies an emitter potential to these regions.

[0102] In the second modification, the relationship "width W1 / 5<distance L1<width W1" is also satisfied. The lower limit of the distance L1 is preferably 0.2 μm or more. This makes it possible to suppress fluctuations in the threshold voltage and improve the load short circuit resistance.

[0103] Furthermore, the technology described in the second modification may be applied in combination with the technology described in the second embodiment, the third embodiment, and the first modification.

[0104] The present invention has been specifically described above based on the embodiments, but the present invention is not limited to these embodiments and can be modified in various ways without departing from the spirit of the present invention. [Explanation of symbols]

[0105] 10 boundaries 100 Semiconductor device 1A cell area AC active cell CE collector electrode CH contact hole EE emitter electrode EP Emitter Pad GE1, GE2 gate electrodes GI gate insulating film GP Gate Pad GW Gate wiring IAC Inactive Cell IF1, IF2 insulating film IL Interlayer insulating film NE emitter region NEa high concentration area NEb low concentration area NHB hole barrier region NS field stop region NV drift region PB Base Area PC Collector Area PD counter-doped region PF floating area PL conductive film PR high concentration diffusion region SUB Semiconductor substrate TR Trench

Claims

1. a semiconductor substrate of a first conductivity type; a first trench formed in the semiconductor substrate; a first gate insulating film formed inside the first trench; a first gate electrode formed on the first gate insulating film so as to fill the first trench; a base region of a second conductivity type opposite to the first conductivity type, the base region being formed in the semiconductor substrate such that the bottom of the base region is shallower than the bottom of the first trench; a plurality of emitter regions of the first conductivity type formed in the base region; Equipped with the first trench extends in a first direction in a plan view, the plurality of emitter regions are spaced apart from one another by a first distance along the first direction; Each of the plurality of emitter regions has a first width in the first direction; the first distance is greater than one-fifth of the first width and less than the first width; further comprising a counter-doped region formed between the plurality of emitter regions; The counter-doped region is an impurity region of the second conductivity type having a lower impurity concentration than the base region, or an intrinsic semiconductor region.

2. 2. The semiconductor device according to claim 1, The semiconductor device, wherein the first distance is 0.2 μm or more.

3. 2. The semiconductor device according to claim 1, a second distance between the first gate electrode and each of the plurality of emitter regions above a boundary between the base region and each of the plurality of emitter regions is wider than a third distance between the first gate electrode and the base region below the boundary; the second distance increases as it approaches the top surface of the first gate electrode, a difference between the second distance and the third distance at the position of the upper surface of the first gate electrode is 30 nm or more and 100 nm or less.

4. 4. The semiconductor device according to claim 3, The semiconductor device, wherein the plurality of emitter regions contain both arsenic and phosphorus.

5. 2. The semiconductor device according to claim 1, a second trench formed in the semiconductor substrate; a second gate insulating film formed inside the second trench; a second gate electrode formed on the second gate insulating film so as to fill the second trench; Further provided with the second trench extends in the first direction and is adjacent to the first trench in a second direction perpendicular to the first direction in a plan view; the base region and the plurality of emitter regions are formed between the first trench and the second trench; a gate potential is supplied to the first gate electrode and the second gate electrode, The semiconductor device is configured such that an emitter potential is supplied to the base region and the plurality of emitter regions, respectively.

6. 2. The semiconductor device according to claim 1, a second trench formed in the semiconductor substrate; a second gate insulating film formed inside the second trench; a second gate electrode formed on the second gate insulating film so as to fill the second trench; Further provided with the second trench extends in the first direction and is adjacent to the first trench in a second direction perpendicular to the first direction in a plan view; the base region and the plurality of emitter regions are formed between the first trench and the second trench; a gate potential is supplied to the first gate electrode; an emitter potential is supplied to the base region, the plurality of emitter regions, and the second gate electrode, respectively.

7. (a) providing a semiconductor substrate of a first conductivity type; (b) after the step (a), forming a first trench in the semiconductor substrate; (c) after the step (b), forming a first gate insulating film inside the first trench and on the semiconductor substrate; (d) after the step (c), forming a first conductive film on the first gate insulating film so as to fill the inside of the first trench; (e) after the step (d), removing the first conductive film formed outside the first trench to form a first gate electrode made of the first conductive film inside the first trench; (f) after the step (e), removing the first gate insulating film formed on the semiconductor substrate; (g) after the step (f), forming a first insulating film on the semiconductor substrate; (h) after the step (g), forming a base region of a second conductivity type, which is opposite to the first conductivity type, in the semiconductor substrate by ion implantation so that the bottom of the base region is shallower than the bottom of the first trench; (i) after the step (h), forming a plurality of emitter regions of the first conductivity type in the base region by ion implantation; (j) after the step (h) or the step (i), introducing the second conductivity type impurity into the base region by ion implantation to form an impurity region of the second conductivity type having an impurity concentration lower than that of the base region, or a counter-doped region which is an intrinsic semiconductor region, between the plurality of emitter regions; Equipped with the first trench extends in a first direction in a plan view, In the step (i), the plurality of emitter regions are formed to be spaced apart from each other by a first distance along the first direction, Each of the plurality of emitter regions has a first width in the first direction; A method for manufacturing a semiconductor device, wherein the first distance is greater than one-fifth of the first width and is narrower than the first width.

8. 8. The method for manufacturing a semiconductor device according to claim 7, The method for manufacturing a semiconductor device, wherein the first distance is 0.2 μm or more.

9. 8. The method for manufacturing a semiconductor device according to claim 7, In the step (c), the first gate insulating film is formed by a thermal oxidation treatment using water vapor; In the step (g), the first insulating film is formed by thermal oxidation using oxygen gas.

10. 10. The method for manufacturing a semiconductor device according to claim 9, a thickness of the first insulating film formed on the semiconductor substrate in the step (g) being thinner than a thickness of the first gate insulating film formed on the semiconductor substrate in the step (c).

11. 8. The method for manufacturing a semiconductor device according to claim 7, In the step (g), the first insulating film is also formed between the side surface of the first trench and the first gate insulating film; a boundary between the base region and the emitter region located at a position deeper than the first insulating film formed between the side surface of the first trench and the first gate insulating film;

12. 12. The method for manufacturing a semiconductor device according to claim 11, In the step (f), a portion of the first gate insulating film in contact with a side surface of the first gate electrode inside the first trench is also removed, thereby exposing a portion of the side surface of the first gate electrode; In the step (g), the first insulating film is also formed on a part of the exposed side surface of the first gate electrode; the boundary is located at a position deeper than the part of the side surface of the first gate electrode exposed in the step (f).

13. 13. The method for manufacturing a semiconductor device according to claim 12, In the step (i), the plurality of emitter regions are formed by ion implantation of both arsenic and phosphorus.

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