Semiconductor device and manufacturing method thereof

Abstract

To provide a method for manufacturing a semiconductor device.SOLUTION: A method for manufacturing a semiconductor device includes forming an epitaxial layer on a substrate, forming a well region and a source region in the epitaxial layer, forming a first trench in the epitaxial layer, the first trench having a fillet protruding toward the well region at a corner portion, forming a second trench in the epitaxial layer, the second trench having a bottom portion higher than the bottom portion of the first trench and a width greater than the width of the first trench, and forming a gate structure in the first trench and the second trench.SELECTED DRAWING: Figure 6

Description

[Technical Field]

[0001] Some embodiments of the present disclosure relate to a semiconductor device and a manufacturing method thereof. [Background technology]

[0002] To improve the channel density of a metal oxide semiconductor field effect transistor (MOSFET), the MOSFET can have a gate trench structure and a vertical channel. However, the on-resistance of the MOSFET may be too high due to excessive electric field concentration at the corners of the gate trench structure. Summary of the Invention [Means for solving the problem]

[0003] Some embodiments of the present disclosure provide a method for manufacturing a semiconductor device, including forming an epitaxial layer on a substrate; forming a well region and a source region in the epitaxial layer; forming a first trench in the epitaxial layer having a fillet at a corner thereof that protrudes toward the well region; forming a second trench in the epitaxial layer, the second trench having a bottom higher than the bottom of the first trench and a width greater than the width of the first trench; and forming a gate structure in the first trench and the second trench.

[0004] In some embodiments, forming the first trench in the epitaxial layer includes forming vertical sidewalls of the first trench in the epitaxial layer and exposing a drift region of the epitaxial layer at a bottom of the first trench; and performing a selective etching process to form fillets at corners of the first trench that protrude toward the well region, and to etch the well region at a rate greater than the drift region by the selective etching process.

[0005] In some embodiments, when the second trench is formed in the epitaxial layer, a well region is exposed at the bottom of the second trench.

[0006] In some embodiments, when the second trench is formed in the epitaxial layer, the bottom of the second trench is higher than the bottom of the source region.

[0007] In some embodiments, the gate structure comprises a gate dielectric layer having a width in the second trench that is greater than the width in the first trench, and a gate layer surrounded by the gate dielectric layer.

[0008] Some embodiments of the present disclosure provide a semiconductor device including: a substrate; an epitaxial layer overlying the substrate; a gate structure in the epitaxial layer having, from bottom to top, a first portion, a second portion, and a third portion, the width of the third portion being greater than the width of the second portion, and the width of the first portion being greater than the width of the second portion; a source electrode overlying the epitaxial layer; and a drain electrode underlying the substrate.

[0009] In some embodiments, the epitaxial layer comprises a source region adjacent to the third portion of the gate structure and having a bottom lower than a bottom of the third portion of the gate structure, and a well region adjacent to the source region and the gate structure.

[0010] In some embodiments, the epitaxial layer comprises a source region adjacent to a third portion of the gate structure and a well region adjacent to the source region and the gate structure, the third portion of the gate structure contacting the well region and the source region.

[0011] In some embodiments, the gate structure comprises a gate dielectric layer, wherein a width of the gate dielectric layer in a third portion of the gate structure is greater than a width of the gate dielectric layer in a first portion of the gate structure, and a gate layer surrounded by the gate dielectric layer.

[0012] In some embodiments, the width of the gate dielectric layer in the first portion of the gate structure is greater than the width of the gate dielectric layer in the second portion of the gate structure. [Brief explanation of the drawings]

[0013] [Figure 1] 1A-1D are cross-sectional views of forming a semiconductor device according to some embodiments of the present disclosure. [Figure 2] 1A-1D are cross-sectional views of forming a semiconductor device according to some embodiments of the present disclosure. [Figure 3] 1A-1D are cross-sectional views of forming a semiconductor device according to some embodiments of the present disclosure. [Figure 4] 1A-1D are cross-sectional views of forming a semiconductor device according to some embodiments of the present disclosure. [Figure 5] 1A-1D are cross-sectional views of forming a semiconductor device according to some embodiments of the present disclosure. [Figure 6] 1A-1D are cross-sectional views of forming a semiconductor device according to some embodiments of the present disclosure. [Figure 7] 10A and 10B are cross-sectional views illustrating semiconductor devices according to some other embodiments of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0014] Some embodiments of the present disclosure relate to a semiconductor device, and the gate structure of the semiconductor device has, from bottom to top, a first portion, a second portion, and a third portion. The width of the third portion is greater than the width of the first portion, and the width of the first portion is greater than the width of the second portion. The first portion of the gate structure can be used to avoid electric field concentration at corners of the gate structure, thereby reducing the on-resistance of the semiconductor device.

[0015] 1-6 are cross-sectional views of forming a semiconductor device according to some embodiments of the present disclosure. Referring to FIG. 1, an epitaxial layer 120 is formed on a substrate 110. The substrate 110 and the epitaxial layer 120 may be fabricated from semiconductor materials such as silicon, silicon carbide, analogs, or combinations thereof. The substrate 110 and the epitaxial layer 120 may have a first conductivity type, and the substrate 110 may be a heavily doped region and the epitaxial layer 120 may be a lightly doped region. In some embodiments, the substrate 110 may be a heavily doped N-type substrate and the epitaxial layer 120 may be a lightly doped N-type region. In some embodiments, the doped region of the first conductivity type may include N-type dopants such as nitrogen, arsenic, and phosphorus.

[0016] Subsequently, well regions 122 and source regions 124 are formed in the epitaxial layer 120. In some embodiments, a thermal oxidation process may first be performed on the epitaxial layer 120 to form a silicon oxide layer on the surface of the epitaxial layer 120. A first patterned photoresist layer may then be formed on the epitaxial layer 120, and an ion implantation process may be performed to implant ions of a second conductivity type into the epitaxial layer 120 to form the well region 122. The location of the well region 122 is defined by the first patterned photoresist layer. Subsequently, the first patterned photoresist layer is removed, and a second patterned photoresist layer is formed on the epitaxial layer 120. An ion implantation process is performed to implant ions of the first conductivity type into the epitaxial layer 120 to form the source region 124. The location of the source region 124 is defined by the second patterned photoresist layer. After forming the source region 124 and the well region 122, the second patterned photoresist layer and the silicon oxide layer can be removed using a wet etching process. In some embodiments, one side of the source region 124 can be substantially aligned with one side of the well region 122, and the source region 124 does not completely cover the well region 122. That is, a portion of the top of the well region 122 is still exposed. Also, the bottom of the well region 122 is lower than the bottom of the source region 124. The well region 122 can have a second conductivity type, the source region 124 can have a first conductivity type, and the well region 122 can be a lightly or moderately doped region, and the source region 124 can be a heavily doped region. In some embodiments, the well region 122 can be a lightly or moderately doped region of P type, and the source region 124 can be a heavily doped region of N type. After forming the well region 122 and the source region 124, the remaining portion not occupied by the well region 122 and the source region 124 is the drift region 126, and the drift region 126 is a lightly doped region having a first conductivity type, for example, an N-type lightly doped region.In some embodiments, the doped regions of the first conductivity type can include N-type dopants such as, for example, nitrogen, arsenic, and phosphorus, while the doped regions of the second conductivity type can include P-type dopants such as, for example, boron, aluminum, and gallium.

[0017] Referring to FIG. 2 , a trench T1 is formed in the epitaxial layer 120. Specifically, a hard mask layer HM1 can be formed on the epitaxial layer 120, with the hard mask layer HM1 exposing a portion of the drift region 126 between adjacent source regions 124. In some embodiments, the hard mask layer HM1 may be formed of a dielectric material, such as silicon nitride, silicon oxide, the like, or a combination thereof. Subsequently, a trench T1 is formed in the epitaxial layer 120 using the hard mask layer HM1 as an etching mask. The trench T1 can be formed by a dry etching process. The trench T1 has vertical sidewalls (e.g., sidewalls substantially perpendicular to the bottom of the substrate 110), exposing the drift region 126 of the epitaxial layer 120 at the bottom of the trench T1, and the bottom of the trench T1 is substantially flush with the well region 122, exposing the well region 122 and the source region 124 at the sidewalls of the trench T1. Thus, drift region 126 and well region 122 are simultaneously exposed near the corners of trench T1. In some embodiments, trench T1 may have a width W1 between 0.8 microns and 1.1 microns. In some embodiments, trench T1 may have a depth between 2.2 microns and 2.5 microns.

[0018] Referring to FIG. 3 , a selective etching process is performed to form fillets C at the corners of trench T1 that protrude toward well region 122. Specifically, near the corners of trench T1, drift region 126 and well region 122, which have different conductivity type dopants, are simultaneously exposed. When the same material is doped with different types of dopants, it is selective to a particular etching process. For example, a selective etching process may have a high etching rate for P-type doped regions but a low etching rate for N-type doped regions. Therefore, an appropriate etching process may be selected to form fillets C at the corners of trench T1 that protrude toward well region 122. Specifically, the etching rate of the selective etching process for well region 122 (e.g., P-type doped regions) is higher than the etching rate for drift region 126 (e.g., N-type doped regions), so fillets C can be formed in well region 122. Thus far, a trench T1 can be formed in the epitaxial layer 120, with the trench T1 having vertical sidewalls and a fillet C protruding into the well region, and the width of the bottom of the trench T1 being greater than the width of the top of the trench T1. In some embodiments, the maximum width W2 of the trench T1 (the width of the portion of the trench T1 having the fillet C) may be between 1.2 microns and 1.5 microns. From another perspective, the outer edge of the fillet C extends beyond the sidewall of the trench T1, and the bottom of the fillet C is lower than the bottom surface of the trench T1.

[0019] Referring to FIG. 4 , after forming the fillet C of the trench T1, a shield region 128 is formed at the bottom of the trench T1. Specifically, using the hard mask layer HM1 (see FIG. 3 ) as a mask, an ion implantation process can be performed to implant ions of a second conductivity type into the epitaxial layer 120 to form the shield region 128. The shield region 128 can have the second conductivity type, and the shield region 128 can be a heavily doped region. In some embodiments, the shield region 128 can be a heavily doped region, and the doping concentration of the shield region 128 is greater than the doping concentration of the well region 122. After forming the shield region 128, the hard mask layer HM1 is removed. In some embodiments, the doped region of the second conductivity type can include a P-type dopant, such as boron, aluminum, and gallium.

[0020] A hard mask layer HM2 can then be formed on the epitaxial layer 120, exposing the trench T1 and a portion of the source region 124. In some embodiments, the hard mask layer HM2 may be formed of a dielectric material such as silicon nitride, silicon oxide, the like, or a combination thereof. A trench T2 is then formed in the epitaxial layer 120 using the hard mask layer HM2 as an etch mask. The bottom of the trench T2 is higher than the bottom of the trench T1, and the width of the trench T2 is greater than the width of the trench T1. In some embodiments, the width W3 of the trench T2 may be between 1.6 microns and 1.8 microns. In some embodiments, because the bottom of the trench T2 is higher than the bottom of the source region 124, the trench T2 does not expose the well region 122. In some embodiments, after forming the trench T2, the vertical sidewall length L of the trench T1 is between 1.0 microns and 1.2 microns.

[0021] 5, the hard mask layer HM2 is removed using a wet etching process. Subsequently, a source electrode 130 is formed on the well region 122 and the source region 124, and a drain electrode 140 is formed under the substrate 110. In some embodiments, the source electrode 130 and the drain electrode 140 may be fabricated from a conductive material such as a metal.

[0022] Referring to FIG. 6 , a gate structure 150 is formed in trenches T1 and T2. The gate structure 150 includes a gate dielectric layer 152 and a gate layer 154. The gate layer 154 is surrounded by the gate dielectric layer 152. The width W4 of the gate dielectric layer 152 in trench T2 is greater than the widths W5 and W6 of the gate dielectric layer 152 in trench T1. Specifically, trenches T1 and T2 may first be filled with a dielectric material, and trenches may then be formed in the dielectric material. A gate material layer may then be formed in the trenches in the dielectric material. Thus, the gate dielectric layer 152 and gate layer 154 of the gate structure 150 may be formed in trenches T1 and T2. Because the sidewalls of the gate layer 154 of the gate structure 150 are substantially perpendicular to the surface of the substrate 110, a width W6 of the gate dielectric layer 152 surrounded by the fillet C of the trench T1 is greater than a width W5 of the gate dielectric layer 152 surrounded by the vertical sidewalls of the trench T1. In some embodiments, the gate dielectric layer 152 may be made of silicon oxide, silicon nitride, or the like. The gate layer 154 may be made of a semiconductor or conductive material, such as polycrystalline silicon or a metal.

[0023] The resulting semiconductor device is shown in FIG. 6. The semiconductor device includes a substrate 110, an epitaxial layer 120, a gate structure 150, a source electrode 130, and a drain electrode 140. The epitaxial layer 120 is on the substrate 110. The gate structure 150 is formed in trenches T1 and T2 in the epitaxial layer 120. Therefore, the gate structure 150 has the structure described above for trenches T1 and T2, and relevant details will not be repeated. In other respects, the gate structure 150 has, from bottom to top, a first portion 150A, a second portion 150B, and a third portion 150C. The width of the third portion 150C is greater than the width of the second portion 150B, and the width of the first portion 150A is greater than the width of the second portion 150B. The first portion 150A of the gate structure 150 has an outwardly protruding fillet C. In some embodiments, the width of third portion 150C is also greater than the width of first portion 150A. Source electrode 130 is on epitaxial layer 120. Drain electrode 140 is below substrate 110. Epitaxial layer 120 includes source region 124, well region 122, drift region 126, and shield region 128. Source region 124 is adjacent to third portion 150C of gate structure 150, the bottom of which is higher than the bottom of source region 124, and first portion 150A of gate structure 150 contacts well region 122. Well region 122 is adjacent to source region 124 and gate structure 150. Shield region 128 is at the bottom of gate structure 150. In some embodiments, the source region 124 and the drift region 126 have a first conductivity type, and the well region 122 and the shield region 128 have a second conductivity type, and the second conductivity type is different from the first conductivity type.

[0024] The gate structure 150 of the semiconductor device according to some embodiments of the present disclosure includes a gate dielectric layer 152 and a gate layer 154. The gate layer 154 is surrounded by the gate dielectric layer 152. The width of the gate dielectric layer 152 in the third portion 150C of the gate structure 150 is greater than the width of the gate dielectric layer 152 in the first portion 150A of the gate structure 150, which in turn is greater than the width of the gate dielectric layer 152 in the second portion 150B of the gate structure 150. The gate dielectric layer 152 in the first portion 150A of the gate structure 150 can be used to direct the current path away from the corners of the gate layer 154 of the gate structure 150, so that the current path is not affected by the strong electric field at the corners of the gate layer 154 of the gate structure 150. This can result in a low on-resistance of the semiconductor device. A current path can flow from the drain electrode 140 through the drift region 126 , through the boundary between the well region 122 and the gate structure 150 , through the boundary between the well region 122 and the source region 124 , and to the source electrode 130 .

[0025] Furthermore, the semiconductor device of the present disclosure can reduce the capacitance between the source region 124 and the gate layer 154. Specifically, the capacitance between the source region 124 and the gate layer 154 can be determined by the gate dielectric layer 152 having vertical sidewalls therebetween (e.g., portion M in FIG. 6 , i.e., the portion of the gate dielectric layer 152 in the second portion 150B of the gate structure 150 that overlaps with the source region 124). When the gate structure 150 has the third portion 150C and the third portion 150C overlaps with the source region 124, the portion of the gate dielectric layer 152 in the second portion 150B of the gate structure 150 that overlaps with the source region 124 is reduced, and therefore the portion of the gate dielectric layer 152 in the second portion 150B of the gate structure 150 that overlaps with the source region 124 is also reduced. In this way, reducing the capacitance between the source region 124 and the gate layer 154 can reduce the effect of this capacitance on the semiconductor device.

[0026] FIG. 7 is a cross-sectional view illustrating a semiconductor device according to some other embodiments of the present disclosure. The semiconductor device of FIG. 7 is similar to the semiconductor device of FIG. 6 , except that when forming the semiconductor device of FIG. 7 , the well region 122 is exposed at the bottom of the trench T2 when the trench T2 is formed in the epitaxial layer 120 (see the step of FIG. 4 ). Therefore, the third portion 150C of the gate structure 150 of the semiconductor device contacts the well region 122 and the source region 124. When the third portion 150C of the gate structure 150 contacts the well region 122, the area of ​​the channel region (the boundary between the well region 122 and the gate structure 150) of the semiconductor device can be increased. However, this also increases the resistance of the semiconductor device. Therefore, the resistance of the semiconductor device can be controlled by controlling the proportion of the third portion 150C of the gate structure 150 that contacts the well region 122.

[0027] As described above, some embodiments of the present disclosure relate to a semiconductor device, and the gate structure of the semiconductor device includes, from bottom to top, a first portion, a second portion, and a third portion. The width of the third portion is greater than the width of the first portion, and the width of the first portion is greater than the width of the second portion. The first portion of the gate structure can be used to avoid electric field concentration at corners of the gate structure, thereby reducing the on-resistance of the semiconductor device. The third portion of the gate structure can be used to reduce the overlap of the second portion of the gate structure with the source region, thereby reducing capacitance between the source region and the gate layer, thereby reducing the effect of this capacitance on the semiconductor device.

[0028] The above are only some embodiments of the present disclosure, not all embodiments, and any equivalent changes made by those skilled in the art to the technical solutions of the present disclosure after reading the specification of the present disclosure will fall within the scope of the claims of the present disclosure. [Explanation of symbols]

[0029] 110: Substrate 120: Epitaxial layer 122: Well area 124: Source area 126: Drift region 128: Shield area 130: Source electrode 140: Drain electrode 150: Gate structure 150A: 1st part 150B: 2nd part 150C: 3rd part 152: Gate dielectric layer 154: Gate layer C: Fillet HM1, HM2: hard mask layers L: Length M: Partial T1, T2: Trench W1, W2, W3, W4, W5, W6: Width

Claims

1. forming an epitaxial layer on a substrate; forming a well region and a source region in the epitaxial layer; forming a first trench in the epitaxial layer having a fillet at a corner thereof projecting toward the well region; forming a second trench in the epitaxial layer, the second trench having a bottom higher than a bottom of the first trench and a width greater than a width of the first trench; forming a gate structure in the first trench and the second trench; A method for manufacturing a semiconductor device comprising:

2. Forming the first trench in the epitaxial layer includes: forming vertical sidewalls of the first trench in the epitaxial layer and exposing a drift region of the epitaxial layer at a bottom of the first trench; 2. The method of claim 1, further comprising: performing a selective etching process to form the fillet at the corner of the first trench, the fillet projecting toward the well region, and causing the selective etching process to etch the well region at a rate greater than the etch rate of the drift region.

3. 2. The method of claim 1, wherein the well region is exposed at the bottom of the second trench when the second trench is formed in the epitaxial layer.

4. 2. The method of claim 1, wherein when the second trench is formed in the epitaxial layer, the bottom of the second trench is higher than the bottom of the source region.

5. The gate structure comprises: a gate dielectric layer having a width in the second trench that is greater than a width in the first trench; a gate layer surrounded by the gate dielectric layer; The method of claim 1 , comprising:

6. A substrate; an epitaxial layer on the substrate; a gate structure in the epitaxial layer having, from bottom to top, a first portion, a second portion, and a third portion, the third portion having a width greater than a width of the second portion and the first portion having a width greater than a width of the second portion; a gate structure comprising: a gate dielectric layer, the width of the gate dielectric layer in the third portion of the gate structure being greater than a width of the gate dielectric layer in the first portion of the gate structure; and a gate structure surrounded by the gate dielectric layer; a source electrode on the epitaxial layer; a drain electrode underlying the substrate; A semiconductor device comprising:

7. The epitaxial layer is a source region adjacent to the third portion of the gate structure and having a bottom lower than a bottom of the third portion of the gate structure; a well region adjacent to the source region and the gate structure; The semiconductor device according to claim 6 , comprising:

8. The epitaxial layer is a source region adjacent the third portion of the gate structure; a well region adjacent to the source region and the gate structure; Equipped with The semiconductor device according to claim 6 , wherein the third portion of the gate structure contacts the well region and the source region.

9. 7. The semiconductor device of claim 6, wherein a width of the gate dielectric layer in the first portion of the gate structure is greater than a width of the gate dielectric layer in the second portion of the gate structure.

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