Semiconductor device and manufacturing method thereof

Abstract

To provide a semiconductor device that further reduces the ON resistance of a power MOS field-effect transistor, and a method of manufacturing the same.SOLUTION: A first power MOS field effect transistor TMT1 is formed in a first region FRE defined on a semiconductor substrate SUB which has a first principal surface FMS and a second principal surface SMS opposed each other and comprises a substrate body SBY and an epitaxial layer NEL, and a second power MOS field effect transistor TMT2 is formed in a second region SRE. A thickness TK1 of the epitaxial layer NEL located in the first region FRE between a first principal surface first part FMS1 and a second principal surface first part SMS1 is less than a thickness TK2 of the epitaxial layer NEL located in the second region SRE between a first principal surface second part FMS2 and a second principal surface second part SMS2.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device and a manufacturing method thereof, and is suitable for use in, for example, an in-vehicle semiconductor device having a power MOSFET as a switching element. [Background technology]

[0002] In recent years, switches that use power metal oxide semiconductor field effect transistors (MOS) as semiconductor elements have been used in in-vehicle semiconductor devices. One such switch is a switch that supplies or cuts off power from a battery to components that require power, such as headlamps or power windows.

[0003] When performing maintenance such as inspecting or replacing a battery, the cable connected to the battery may need to be disconnected, and after the maintenance is completed, the disconnected cable will be connected to the battery. At this time, it is expected that the cable will be connected in the opposite polarity (reverse connection) from its original polarity.

[0004] If the cable is connected to the battery in reverse, current will flow through the parasitic diode of a power MOS field effect transistor even when the switch is off. In other words, current will flow in the reverse direction even when the switch is off.

[0005] In order to prevent such a reverse current flow, a semiconductor device has been proposed in which two power MOS field effect transistors are connected in series (anti-series connection) on one semiconductor chip with their drains connected to each other (Patent Document 1).Furthermore, in order to reduce the on-resistance when a current flows through two power MOS field effect transistors connected in series (anti-series connection), a semiconductor device with a column structure has been proposed (Patent Document 2). [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Japanese Patent Application Laid-Open No. 2002-368219 [Patent Document 2] Japanese Patent Application Laid-Open No. 2016-207716 Summary of the Invention [Problem to be solved by the invention]

[0007] In a semiconductor device that uses a power MOS field effect transistor as a switch, there is a demand for further reduction in the on-resistance when a current flows through the power MOS field effect transistor.

[0008] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0009] A semiconductor device according to one embodiment includes: a lead frame or backside metal; a semiconductor substrate, a first region and a second region, and a first switching element; Second Switching Element and, an interlayer insulating film, a first plug, a second plug, a first source electrode, and a second source electrode; The semiconductor substrate comprises: Mounted on a lead frame or backside metal, The semiconductor substrate has a first main surface and a second main surface, the first region and the second region being defined in the semiconductor substrate, and the first switching element is formed in the first region and conducts current between the first main surface and the second main surface. The second switching element is formed in the second region and is connected in anti-series with the first switching element. The interlayer insulating film is formed to cover the first main surface of the semiconductor substrate. The first plug is formed in the first region to penetrate the interlayer insulating film. The second plug is formed in the second region to penetrate the interlayer insulating film. The first source electrode is formed in the first region to cover the interlayer insulating film. The second source electrode is formed in the second region to cover the interlayer insulating film. The semiconductor substrate is N-type The board body and N type and a semiconductor layer. The N-type substrate body is formed so as to contact the lead frame or the backside metal in the first region and the second region, and has a second main surface. The semiconductor layer is formed so as to be in contact with the substrate body and has a first main surface. The first switching element includes a first electrode, a P-type first impurity region (first portion), and an N-type second impurity region (first portion). The first electrode is formed in a first trench formed in the semiconductor layer with a first insulating film interposed therebetween. The P-type first impurity region (first portion) is formed in the semiconductor layer from the first main surface to a position shallower than a bottom of the first electrode, in contact with the first insulating film. The N-type second impurity region (first portion) is formed in the first impurity region (first portion) from the first main surface to a position shallower than a bottom of the first impurity region (first portion). The second switching element includes a second electrode, a P-type first impurity region (second portion), and an N-type second impurity region (second portion). The second electrode is formed in a second trench formed in the semiconductor layer with a second insulating film interposed therebetween. The P-type first impurity region (second portion) is formed in the semiconductor layer from the first main surface to a position shallower than a bottom of the second electrode, in contact with the second insulating film. The N-type second impurity region second portion is formed in the first impurity region second portion from the first major surface to a position shallower than the bottom of the first impurity region second portion. The first source electrode is electrically connected to the second impurity region first portion via the first plug and is connected to the battery. The second source electrode is electrically connected to the second impurity region second portion via the second plug and is connected to the load. The thickness of the semiconductor layer in the portion located in the first region and through which current is conducted by the first switching element is the first thickness. Second Switching ElementThe thickness of the semiconductor layer at the portion where the current is conducted is the second thickness. The first thickness is thinner than the second thickness.

[0010] A method for manufacturing a semiconductor device according to another embodiment includes the following steps: forming a semiconductor device having a first main surface and a second main surface facing each other, a first region and a second region defined therein, and the second main surface; N type a substrate body and a substrate having a first main surface and formed so as to be in contact with the substrate body; N type a first switching element for conducting a current between a first main surface and a second main surface of the semiconductor substrate; a second switching element connected in anti-series with the first switching element; a first thickness of the semiconductor layer in a portion located in the first region and through which a current is conducted for the first switching element is formed in the second region of the semiconductor substrate; Second Switching Element The thickness of the semiconductor layer is set to be thinner than the second thickness of the portion where the current is conducted. An interlayer insulating film is formed so as to cover the first main surface of the semiconductor substrate. A first plug is formed in the first region and a second plug is formed in the second region so as to penetrate the interlayer insulating film. A first source electrode is formed in the first region and a second source electrode is formed in the second region so as to cover the interlayer insulating film. A lead frame or backside metal is prepared, and the semiconductor substrate is mounted in a state in which the second main surface is in contact with the lead frame or backside metal. The step of forming a first switching element includes the following steps: A first electrode is formed in a first trench formed in the semiconductor layer with a first insulating film interposed therebetween. No. A P-type first impurity region first portion is formed in the semiconductor layer, extending from the first main surface to a position shallower than the bottom of the first electrode, in a manner that the first insulating film is in contact with the first impurity region. An N-type second impurity region first portion is formed in the first impurity region first portion, extending from the first main surface to a position shallower than the bottom of the first impurity region first portion. The step of forming a second switching element includes the following steps: forming a second electrode in a second trench formed in the semiconductor layer, with a second insulating film interposed therebetween; forming a P-type first impurity region second portion in the semiconductor layer, extending from the first main surface to a position shallower than the bottom of the second electrode, in a manner that the first insulating film is in contact with the second insulating film; forming an N-type second impurity region second portion in the first impurity region second portion, extending from the first main surface to a position shallower than the bottom of the first impurity region second portion. The step of forming a first source electrode includes a step of electrically connecting the first impurity region first portion to the second impurity region via the first plug and connecting it to the battery. The step of forming the second source electrode includes the step of electrically connecting the second source electrode to the second portion of the second impurity region via the second plug and connecting the second source electrode to the load. [Effects of the Invention]

[0011] According to the semiconductor device of the embodiment, the on-resistance can be further reduced.

[0012] According to the method for manufacturing a semiconductor device according to another embodiment, a semiconductor device capable of further reducing the on-resistance can be manufactured. [Brief explanation of the drawings]

[0013] [Figure 1] FIG. 1 is a circuit diagram showing an example of a circuit including the semiconductor device according to the first to third embodiments. [Figure 2] 1 is a plan view showing an example of a plane pattern of a semiconductor device according to a first embodiment. [Figure 3] FIG. 3 is a cross-sectional view taken along line III-III in FIG. 2 in the embodiment. [Figure 4] FIG. 2 is a cross-sectional view showing an example of a step of a method for manufacturing a semiconductor device in the embodiment. [Figure 5] 5 is a cross-sectional view showing a step performed after the step shown in FIG. 4 in the embodiment. [Figure 6] FIG. 5 is a cross-sectional view showing another example of the step shown in FIG. 4 in the embodiment. [Figure 7] 7 is a cross-sectional view showing a step performed after the step shown in FIG. 5 or 6 in the embodiment. FIG. [Figure 8] 8 is a cross-sectional view showing a step performed after the step shown in FIG. 7 in the embodiment. [Figure 9] 9 is a cross-sectional view showing a step performed after the step shown in FIG. 8 in the embodiment. [Figure 10] 10 is a cross-sectional view showing a step performed after the step shown in FIG. 9 in the embodiment. [Figure 11] 11 is a cross-sectional view showing a step performed after the step shown in FIG. 10 in the embodiment. [Figure 12] 12 is a cross-sectional view showing a step performed after the step shown in FIG. 11 in the embodiment. [Figure 13] 13 is a cross-sectional view showing a step performed after the step shown in FIG. 12 in the embodiment. [Figure 14] 14 is a cross-sectional view showing a step performed after the step shown in FIG. 13 in the embodiment. [Figure 15] FIG. 10 is a cross-sectional view illustrating an operation of the semiconductor device when the battery is properly connected in the embodiment. [Figure 16] FIG. 10 is a circuit diagram for explaining the operation of the semiconductor device when the battery is properly connected in the embodiment. [Figure 17] 10 is a cross-sectional view illustrating an operation of the semiconductor device when the battery is connected in reverse in the embodiment. FIG. [Figure 18] FIG. 10 is a circuit diagram for explaining the operation of the semiconductor device in the case where the battery is connected in reverse in the embodiment. [Figure 19] FIG. 10 is a cross-sectional view showing a semiconductor device according to a second embodiment. [Figure 20] 2 is a cross-sectional view showing one step of a method for manufacturing a semiconductor device in the embodiment. FIG. [Figure 21] 21 is a cross-sectional view showing a step performed after the step shown in FIG. 20 in the embodiment. [Figure 22] 22 is a cross-sectional view showing a step performed after the step shown in FIG. 21 in the embodiment. [Figure 23] 10A and 10B are cross-sectional views illustrating the operation of the semiconductor device in the case where the battery is properly connected and the case where the battery is reversely connected in the embodiment. [Figure 24] FIG. 10 is a cross-sectional view showing a semiconductor device according to a third embodiment. [Figure 25] 2 is a cross-sectional view showing one step of a method for manufacturing a semiconductor device in the embodiment. FIG. [Figure 26] 26 is a cross-sectional view showing a step performed after the step shown in FIG. 25 in the embodiment. [Figure 27] 10A and 10B are cross-sectional views illustrating the operation of the semiconductor device in the case where the battery is properly connected and the case where the battery is reversely connected in the embodiment. [Figure 28] FIG. 10 is a cross-sectional view showing a semiconductor device according to a fourth embodiment. [Figure 29] 2 is a cross-sectional view showing one step of a method for manufacturing a semiconductor device in the embodiment. FIG. [Figure 30] FIG. 30 is a cross-sectional view showing a step performed after the step shown in FIG. 29 in this embodiment. [Figure 31] FIG. 2 is a cross-sectional view illustrating an operation of the semiconductor device in the embodiment. [Figure 32] FIG. 10 is a cross-sectional view showing a semiconductor device according to a fifth embodiment. [Figure 33] 2 is a cross-sectional view showing one step of a method for manufacturing a semiconductor device in the embodiment. FIG. [Figure 34] FIG. 34 is a cross-sectional view showing a step performed after the step shown in FIG. 33 in this embodiment. [Figure 35]FIG. 2 is a cross-sectional view illustrating an operation of the semiconductor device in the embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0014] First, a circuit will be described in which a semiconductor device is applied in which two power MOS field effect transistors serving as switches are connected in series in opposite directions (anti-series connection). Note that the "anti-series connection" here refers to the connection relationship on the circuit shown in Figure 1, i.e., the electrical connection relationship.

[0015] As shown in Fig. 1, a first power MOS field effect transistor TMT1 and a second power MOS field effect transistor TMT2 are electrically connected in series (anti-series connection) via a common drain region CDN. The positive electrode of a battery BA is electrically connected to the source S1 of the first power MOS field effect transistor TMT1, and the negative electrode of the battery BA is electrically connected to the source S2 of the second power MOS field effect transistor TMT2 (appropriate connection). A load LAD, such as a headlamp, is electrically connected between the source S2 and the battery BA. The structure of the semiconductor device will be specifically described below.

[0016] (Embodiment 1) Here, a first example of a semiconductor device SDV in which two power MOS field effect transistors are connected in series in the opposite directions (anti-series connection) will be described.

[0017] 2 and 3, the first power MOS field effect transistor TMT1 (first switching element) and the second power MOS field effect transistor TMT2 (second switching element) are formed on the same semiconductor substrate SUB. The first power MOS field effect transistor TMT1 has a columnless structure that does not include a column. The second power MOS field effect transistor TMT2 has a superjunction structure (SJ structure) that includes a column CLM.

[0018] The semiconductor substrate SUB has a first main surface FMS and a second main surface SMS facing each other. The semiconductor substrate SUB includes an N-type substrate body SBY having the second main surface SMS, and an N-type epitaxial layer NEL (semiconductor layer) having the first main surface FMS. The N-epitaxial layer NEL is formed so as to be in contact with the substrate body SBY. The N-type impurity concentration of the substrate body SBY is set to be higher than the N-type impurity concentration of the epitaxial layer NEL, for example, by about two orders of magnitude.

[0019] A first region FRE and a second region SRE are defined in the semiconductor substrate SUB. The first power MOS field effect transistor TMT1 is formed in the first region FRE. The second power MOS field effect transistor TMT2 is formed in the second region SRE. A first main surface FHS of the semiconductor substrate SUB includes a first main surface first portion FMS1 located in the first region FRE and a first main surface second portion FMS2 located in the second region SRE.

[0020] The second main surface SMS includes a second main surface first portion SMS1 located in the first region FRE and a second main surface second portion SMS2 located in the second region SRE. The second main surface first portion SMS1 and the second main surface second portion SMS2 are located on the same plane. The first main surface first portion FMS1 is located closer to the second main surface SMS than the first main surface second portion FMS2.

[0021] Here, in the epitaxial layer NEL located in the first region FRE and between the first main surface first portion FMS1 and the second main surface first portion SMS1, the thickness of the portion that becomes the channel region where current conduction occurs is defined as thickness TK1. Also, in the epitaxial layer NEL located in the second region SRE and between the first main surface second portion FMS2 and the second main surface second portion SMS2, the thickness of the portion that becomes the channel region where current conduction occurs is defined as thickness TK2. In this case, thickness TK1 is thinner than thickness TK2.

[0022] Next, the structures of the first power MOS field effect transistor TMT1 and the second power MOS field effect transistor TMT2 will be described in more detail.

[0023] In the first region FRE in which the first power MOS field effect transistor TMT1 is formed, a gate electrode GEL1 (first electrode) is formed in the trench TRC1 (see FIG. 8) with a gate oxide film GZ1 (first insulating film) interposed therebetween. A P- region PM1 (first impurity region first portion) is formed from the surface of the first main surface first portion FMS1 (epitaxial layer NEL) of the semiconductor substrate SUB to a position shallower than the bottom of the gate electrode GEL1, in a manner to be in contact with the gate oxide film GZ1. An N+ region SN1 (second impurity region first portion) is formed from the surface of the first main surface first portion FMS1 (epitaxial layer NEL) of the semiconductor substrate SUB to a position shallower than the bottom of the P- region PM1. The N+ region SN1 serves as the source region of the first power MOS field effect transistor TMT1.

[0024] In the second region SRE in which the second power MOS field effect transistor TMT2 is formed, a gate electrode GEL2 (second electrode) is formed in the trench TRC2 (see FIG. 8) with a gate oxide film GZ2 (second insulating film) interposed therebetween. A P-region PM2 (first impurity region second portion) is formed from the surface of the first main surface second portion FMS2 (epitaxial layer NEL) of the semiconductor substrate SUB to a position shallower than the bottom of the gate electrode GEL2, in a manner that the P-region PM2 is in contact with the gate oxide film GZ2.

[0025] P-type columns CLM (first pillars) are formed to extend from the bottom of the P- region PM2 toward the substrate body SBY. The columns CLM are arranged at intervals from one another along the direction in which the gate electrode GEL2 extends (the direction perpendicular to the paper surface). An N+ region SN2 (second impurity region second part) is formed from the surface of the first main surface second part FMS2 (epitaxial layer NEL) of the semiconductor substrate SUB to a position shallower than the bottom of the P- region PM2. The N+ region SN2 serves as the source region of the second power MOS field effect transistor TMT2.

[0026] An interlayer insulating film ILF is formed so as to cover the first main surface FMS of the semiconductor substrate SUB. In the first region FRE, a plug PLG1 is formed so as to penetrate the interlayer insulating film ILF. In the second region SRE, a plug PLG2 is formed so as to penetrate the interlayer insulating film ILF. In the first region FRE, a source electrode SEL1 is formed so as to cover the interlayer insulating film ILF. In the second region SRE, a source electrode SEL2 is formed so as to cover the interlayer insulating film ILF.

[0027] In the first region FRE, the source electrode SEL1 and the N+ region SN1 are electrically connected via a plug PLG1. In the second region SRE, the source electrode SEL2 and the N+ region SN2 are electrically connected via a plug PLG2. The plugs PLG1 (PLG2) may be formed in a stripe shape along the direction in which the gate electrode GEL1 (GEL2) extends (the direction perpendicular to the paper surface), or may be formed at intervals from each other.

[0028] 2, in the first region FRE, a gate G1 electrically connected to the gate electrode GEL1 of the first power MOS field effect transistor TMT1 is arranged on the side of the source electrode SEL1, and in the second region SRE, a gate G2 electrically connected to the gate electrode GEL2 of the second power MOS field effect transistor TMT2 is arranged on the side of the source electrode SEL2.

[0029] In the semiconductor substrate SUB, a periphery region TMR is defined so as to surround each of the first region FRE and the second region SRE. Fig. 2 shows the periphery region TMR located between the first region FRE and the second region SRE. A periphery structure portion TS that prevents current leakage is formed in the periphery region TMR.

[0030] The semiconductor substrate SUB is mounted on a lead frame LEF. The lead frame LEF is arranged so as to be in contact with the second main surface SMC of the substrate body SBY (semiconductor substrate SUB). The substrate body SBY and the lead frame LEF form a common drain region CDN (drain electrode) of the first power MOS field effect transistor TMT1 and the second power MOS field effect transistor TMT2. Note that, instead of the lead frame LEF, for example, a backside metal BME may be formed.

[0031] As will be described later, when the battery BA is properly connected, the withstand voltage is ensured by the second power MOS field effect transistor TMT2, whereas when the polarity of the battery BA is reversed, the withstand voltage is ensured by the first power MOS field effect transistor TMT1.

[0032] Next, an example of a method for manufacturing the above-mentioned semiconductor device SDV will be described. As shown in Fig. 4, a semiconductor substrate SUB is prepared by growing an N-type epitaxial layer NEL on one surface of a substrate body SBY by epitaxial growth. Next, a silicon oxide film SOF is formed by, for example, CVD (Chemical Vapor Deposition) so as to cover a first main surface FMS of the semiconductor substrate SUB (epitaxial layer NEL).

[0033] Next, by performing photolithography and etching, the portion of the silicon oxide film SOF located in the first region FRE is removed while leaving the portion of the silicon oxide film SOF located in the second region SRE, thereby exposing the surface of the epitaxial layer NEL.

[0034] Next, as shown in FIG. 5, the exposed epitaxial layer NEL is subjected to, for example, a TMAH (TetraMethylAmmonium Hydroxide) etching process using the silicon oxide film SOF as an etching mask. As a result, etching proceeds along the plane orientation (111) of the epitaxial layer NEL (silicon), and the position of the first portion FMS1 of the first main surface recedes toward the substrate body SBY relative to the position of the second portion FMS2 of the first main surface. The thickness TK1 (see FIG. 3) of the epitaxial layer NEL in the first region FRE is adjusted by the etching amount. Thereafter, the silicon oxide film SOF is removed, and the entire surface of the epitaxial layer NEL is exposed as shown in FIG. 7.

[0035] Note that the TMAH etching process hardly damages the surface of the epitaxial layer NEL compared to, for example, a dry etching process, and thus does not affect the operation of the power MOS field-effect transistor formed subsequently. In addition to the TMAH etching process, a method of forming a thick oxide film and then removing the oxide film may be applied in this step. As shown in FIG. 6, a silicon nitride film SNF is formed to cover the first main surface FMS of the semiconductor substrate SUB, and then photolithography and etching are performed to remove the portion of the silicon nitride film SNF located in the first region FRE, thereby exposing the surface of the epitaxial layer NEL.

[0036] Next, a relatively thick silicon oxide film SIF is formed by oxidizing the exposed surface of the epitaxial layer NEL by thermal oxidation. Next, the silicon oxide film SIF is removed, so that the position of the first portion FMS1 of the first main surface is recessed toward the substrate body SBY relative to the position of the second portion FMS2 of the first main surface. The thickness TK1 (see FIG. 3) of the epitaxial layer NEL in the first region FRE is adjusted by the film thickness of the silicon oxide film SIF. Thereafter, the silicon nitride film SNF is removed, and the entire surface of the epitaxial layer NEL is exposed, as shown in FIG. 7.

[0037] Next, photolithography and etching are performed to form trenches TRC1 and TRC2 in the epitaxial layer NEL (see FIG. 8). As a result, a trench TRC1 is formed in the first region FRE, as shown in FIG. 8. A trench TRC2 is formed in the second region SRE.

[0038] Next, an implantation mask for forming the columns is formed. A silicon oxide film IMF is formed by, for example, a CVD method so as to cover the first main surface FMS of the semiconductor substrate SUB (epitaxial layer NEL) (see FIG. 9). Next, as shown in FIG. 9, the silicon oxide film IMF is subjected to photolithography and etching to remove portions of the silicon oxide film IMF located in regions where the columns will be formed, thereby exposing the surface of the epitaxial layer NEL.

[0039] Next, columns CLM are formed in the epitaxial layer NEL by implanting P-type impurities using the silicon oxide film IMF as an implantation mass. The silicon oxide film IMF is then removed. Next, as shown in FIG. 10, a gate electrode GEL1 is formed in the first region FRE with a gate oxide film GZ1 interposed in the trench TRC1 by a typical technique. A gate electrode GEL2 is formed in the second region SRE with a gate oxide film GZ2 interposed in the trench TRC2.

[0040] Next, a photoresist pattern (not shown) for forming a P-region is formed by performing a predetermined photolithography process. Next, P-type impurities are implanted using the photoresist pattern as an implantation mass. As a result, a P-region PM1 is formed in the first region FRE, as shown in FIG. 11. The P-region PM1 is formed from the first portion FMS1 of the first main surface to a position shallower than the bottom of the gate electrode GEL1. A P-region PM2 is formed in the second region SRE. The P-region PM2 is formed from the first portion FMS2 of the first main surface to a position shallower than the bottom of the gate electrode GEL2. The P-region PM2 is also formed so as to be connected to the column CLM. Thereafter, the photoresist pattern is removed.

[0041] Next, a photoresist pattern (not shown) for forming an N+ region is formed by performing a predetermined photolithography process. Next, N-type impurities are implanted using the photoresist pattern as an implantation mask. As a result, an N+ region SN1 is formed in the first region FRE, as shown in FIG. 11. The N+ region SN1 is formed from the first portion FMS1 of the first main surface to a position shallower than the bottom of the P- region PM1. An N+ region SN2 is formed in the second region SRE. The N+ region SN2 is formed from the second portion FMS2 of the first main surface to a position shallower than the bottom of the P- region PM2. Thereafter, the photoresist pattern is removed.

[0042] 12, an interlayer insulating film ILF is formed so as to cover the first main surface FMS of the semiconductor substrate SUB. Next, a photoresist pattern (not shown) for forming contact openings is formed by performing a predetermined photolithography process. Next, the interlayer insulating film ILF is etched using the photoresist pattern as an etching mask.

[0043] 13, a contact opening CH1 is formed in the first region FRE. The contact opening CH1 is formed to penetrate the interlayer insulating film ILF and the N+ region SN1 and reach the P- region PM1. A contact opening CH2 is formed in the second region SRE. The contact opening CH2 is formed to penetrate the interlayer insulating film ILF and the N+ region SN2 and reach the P- region PM2.

[0044] Next, a metal film such as aluminum is formed by, for example, sputtering so as to fill the contact openings CH1 and CH2. As a result, a plug PLG1 is formed in the contact opening CH1 in the first region FRE, as shown in Fig. 14. A plug PLG2 is formed in the contact opening CH2 in the second region SRE.

[0045] Furthermore, a metal film such as an aluminum film is formed to cover the interlayer insulating film ILF, and predetermined photolithography and etching processes are performed. As a result, a source electrode SEL1 and a gate G1 are formed in the first region FRE (see FIG. 2). A source electrode SEL2 and a gate G2 are formed in the second region SRE (see FIG. 2).

[0046] Thereafter, the semiconductor substrate SUB is diced, and the semiconductor substrate SUB on which the first power MOS field effect transistor TMT1 and the second power MOS field effect transistor TMT2 are formed is extracted as a single chip. The semiconductor substrate SUB extracted as a chip undergoes a process of being mounted on a lead frame LEF, and is completed as a semiconductor device SDV, as shown in FIG.

[0047] Next, the operation of the semiconductor device SDV described above will be described. First, a case where the battery BA is properly connected will be described as shown in Fig. 1. In this case, by applying a voltage equal to or greater than the threshold value to each of the gate electrode GEL1 of the first power MOS field effect transistor TMT1 and the gate electrode GEL2 of the second power MOS field effect transistor TMT2, the first power MOS field effect transistor TMT1 and the second power MOS field effect transistor TMT2 are turned on.

[0048] As a result, as shown in FIGS. 1 and 15, a current flows from the battery BA through the first power MOS field effect transistor TMT1 and the second power MOS field effect transistor TMT2, and power is supplied to the load LAD.

[0049] Next, the gate electrode GEL2 is electrically short-circuited to the source S2, thereby turning off the second power MOS field-effect transistor TMT2. Here, as shown in Figure 16, regardless of the state (on or off) of the first power MOS field-effect transistor TMT1, a current flows through the parasitic diode PDD1, causing the potential of the common drain region CDN to rise. At this time, the second power MOS field-effect transistor TMT2, which has a breakdown voltage several times higher than the voltage of the battery BA, maintains its breakdown voltage and prevents current from flowing through the circuit.

[0050] Next, we will explain the case where the battery BA is reverse-connected. In this case, the first power MOS field-effect transistor TMT1 is turned off. Here, as shown in FIGS. 17 and 18, regardless of the state (on or off) of the second power MOS field-effect transistor TMT2, current flows through the parasitic diode PDD2, and the potential of the common drain region CDN rises. At this time, the withstand voltage is maintained by the first power MOS field-effect transistor TMT1, which has a withstand voltage slightly higher than the voltage of the battery BA. This makes it possible to prevent current from flowing backward in the circuit.

[0051] In this way, in the semiconductor device SDV described above, it is possible to prevent current from flowing through the circuit (see FIG. 1) both when the battery BA is properly connected to the semiconductor device SDV and when the battery BA is reversely connected to the semiconductor device SDV.

[0052] Furthermore, in the semiconductor device SDV described above, the on-resistance can be reduced. This will be explained.

[0053] First, in the semiconductor device SDV, the withstand voltage of the first power MOS field effect transistor TMT1 only needs to be approximately the maximum rated voltage of the battery BA, while the withstand voltage of the second power MOS field effect transistor TMT2 is required to be a voltage that takes into account surges and the like during normal operation, for example, a voltage several times the voltage of the battery BA.

[0054] To ensure the breakdown voltage of the second power MOS field-effect transistor TMT2, the thickness of the epitaxial layer NEL must be increased. Increasing the thickness of the epitaxial layer NEL also increases the breakdown voltage of the first power MOS field-effect transistor TMT1 more than necessary.

[0055] Therefore, in normal operation, the on-resistance of the first power MOS field effect transistor TMT1 increases as the thickness of the epitaxial layer NEL increases, which may deteriorate the characteristics of the semiconductor device SDV.

[0056] In the semiconductor device SDV described above, the first main surface first portion FMS1 in the first region FRE is located closer to the second main surface SMS than the first main surface second portion FSM2 in the second region SRE. That is, a structure is formed in which the thickness TK1 of the epitaxial layer NEL in the first region FRE is selectively thinner than the thickness TK2 of the epitaxial layer NEL in the second region SRE.

[0057] As a result, the thickness TK2 of the epitaxial layer NEL is set to an optimum value for ensuring the breakdown voltage of the second power MOS field-effect transistor TMT2, while the thickness TK1 of the epitaxial layer NEL in the first region FRE is selectively thinned, thereby reducing the on-resistance. In other words, by selectively adjusting (thinning) the thickness TK1 of the epitaxial layer NEL in the first region FRE while ensuring the breakdown voltage (thickness TK2 of the epitaxial layer NEL) of the second power MOS field-effect transistor TMT2, the on-resistance of the semiconductor device SDV can be easily optimized.

[0058] The inventors estimated the effect of reducing the on-resistance. The influence of the thickness (unit thickness) of the epitaxial layer NEL on the resistance value per unit area of ​​the first power MOS field-effect transistor TMT1 was approximately 1.2 mΩmm. 2 Here, the area of ​​the first region FRE is set to several mm2 The area of ​​the second region SRE is assumed to be several tens of mm 2 Assuming this, it was estimated that the on-resistance could be reduced by 0.2 mΩ per 1.0 μm of epitaxial layer NEL thickness. It was found that this had a reduction effect of approximately 10% to 20% compared to the target on-resistance.

[0059] (Embodiment 2) In the semiconductor device described above, the second power MOS field effect transistor TMT2 has been exemplified as a second power MOS field effect transistor TMT2 having an SJ structure equipped with a column CLM. Here, a semiconductor device including a second power MOS field effect transistor TMT2 without a column will be described as a second example of a semiconductor device SDV in which two power MOS field effect transistors are connected in series in opposite directions (anti-series connection).

[0060] 19, the first power MOS field effect transistor TMT1 has a columnless structure that does not include a column, and the second power MOS field effect transistor TMT2 also has a columnless structure that does not include a column. In order to ensure that the second power MOS field effect transistor TMT2 with a columnless structure has the same withstand voltage as the second power MOS field effect transistor TMT2 with a columnar structure, it is necessary to set the thickness TK4 of the portion of the epitaxial layer NEL that becomes the channel region where current conducts to be thicker.

[0061] Therefore, the thickness TK4 of the epitaxial layer NEL in the second region SRE in which the second power MOS field effect transistor TMT2 is formed is set to be thicker than the thickness TK2 of the epitaxial layer NEL in the second region SRE shown in FIG.

[0062] However, if the thickness of the epitaxial layer NEL in the first region FRE where the first power MOS field effect transistor TMT1 is formed also becomes thicker in accordance with the thickness of the epitaxial layer NEL in the second region SRE, the on-resistance will increase. Therefore, in the second region SRE, the thickness of the epitaxial layer NEL is set thick to ensure a desired breakdown voltage, while in the first region FRE, the thickness of the portion of the epitaxial layer NEL that becomes a channel region where current conducts needs to be thinned to achieve a desired on-resistance.

[0063] Therefore, the difference (step) between the thickness TK4 of the epitaxial layer NEL in the second region SRE and the thickness TK3 of the epitaxial layer NEL in the first region FRE is larger than the difference (step) between the thickness TK2 and the thickness TK1 shown in Fig. 3. Note that the other configurations are similar to those of the semiconductor device SDV shown in Fig. 3 etc., and therefore the same members are denoted by the same reference numerals, and the description thereof will not be repeated unless necessary.

[0064] Next, an example of a method for manufacturing the semiconductor device SDV described above will be described. First, for example, by performing an etching process on the epitaxial layer NEL in the same manner as in the steps shown in Figures 4 and 5 described above, the position of the first main surface first portion FMS1 is set back toward the substrate body SBY with respect to the position of the first main surface second portion FMS2, as shown in Figure 20.

[0065] At this time, the thickness TK4 of the epitaxial layer NEL that ensures the desired breakdown voltage becomes thicker, and accordingly, the amount of etching of the epitaxial layer NEL in the first region FRE until the thickness TK3 of the epitaxial layer NEL that provides the desired on-resistance increases. Therefore, the difference (step) between the position (height) of the first portion FMS1 of the first main surface and the position (height) of the second portion FMS2 of the first main surface becomes larger than the step in the process shown in FIG.

[0066] Next, the epitaxial layer NEL is subjected to photolithography and etching processes to form a trench TRC1 in the first region FRE and a trench TRC2 in the second region SRE (see FIG. 21). Here, there is a large difference (step) between the position (height) of the first main surface first portion FMS1 and the position (height) of the first main surface second portion FMS2. Therefore, to avoid defocusing, the photolithography process and the like may be performed in two separate steps.

[0067] 21, a gate electrode GEL1 is formed in the first region FRE with a gate oxide film GZ1 interposed in the trench TRC1 by a general method, and a gate electrode GEL2 is formed in the second region SRE with a gate oxide film GZ2 interposed in the trench TRC2.

[0068] 11 to 14, a plug PLG1 is formed in the contact opening CH1 in the first region FRE as shown in Fig. 22. A plug PLG2 is formed in the contact opening CH2 in the second region SRE. After that, source electrodes SEL1, SEL2, etc. are formed, the semiconductor substrate SUB is diced, and the semiconductor substrate SUB is mounted on a lead frame LEF, completing the semiconductor device SDV as shown in Fig. 19.

[0069] Next, the operation of the semiconductor device SDV described above will be explained. As with the semiconductor device SDV described above, first, in the on state when the battery BA (see FIG. 1) is properly connected, a current flows through the first power MOS field effect transistor TMT1 and then through the second power MOS field effect transistor TMT2 (see the thick dotted arrow) as shown in FIG. 23. At this time, the thickness TK3 of the epitaxial layer NEL (first power MOS field effect transistor TMT1) in the first region FRE is selectively set thin, thereby reducing the on-resistance.

[0070] On the other hand, in the OFF state, the withstand voltage is ensured by the epitaxial layer NEL (second power MOS field effect transistor TMT2) having a thickness TK4 set to have a withstand voltage several times the voltage of the battery BA.

[0071] Next, when the battery BA (see FIG. 1) is reverse-connected, the withstand voltage is maintained by the first power MOS field-effect transistor TMT1, which has a withstand voltage slightly higher than the voltage of the battery BA.

[0072] The semiconductor device SDV described above does not include columns, and the process of forming the columns is omitted, which contributes to reducing manufacturing costs. Furthermore, by increasing the thickness TK4 of the epitaxial layer NEL to compensate for the absence of columns, the breakdown voltage of the second power MOS field-effect transistor TMT2 can be ensured.

[0073] Furthermore, by etching the epitaxial layer NEL in the first region FRE to a greater extent until it reaches the thickness TK3 in proportion to the increase in thickness TK4, the effect on the on-resistance caused by the increase in the thickness of the epitaxial layer NEL is minimized, and a desired on-resistance can be obtained. Moreover, by selectively adjusting (thinning) the thickness TK3 of the epitaxial layer NEL in the first region FRE, the on-resistance of the semiconductor device SDV can be easily optimized.

[0074] (Embodiment 3) Here, as a third example of the semiconductor device SDV in which two power MOS field effect transistors are connected in series in the opposite directions (anti-series connection), a semiconductor device SDV in which the substrate body is processed will be described.

[0075] 24, in the epitaxial layer NEL in the first region FRE, a thickness TK1 of a portion that becomes a channel region where current conduction occurs is thinner than a thickness TK2 of a portion that becomes a channel region where current conduction occurs in the epitaxial layer NEL in the second region SRE. The first main surface first portion FMS1 and the first main surface second portion FMS2 are located on the same plane. The second main surface first portion SMS1 is located closer to the first main surface FMS than the second main surface second portion SMS2.

[0076] A backside metal BME or the like is formed so as to contact the second main surface SMS including the second main surface first portion SMS1. Note that the other configurations are similar to those of the semiconductor device SDV shown in FIG. 3 and the like, and therefore the same components are denoted by the same reference numerals, and the description thereof will not be repeated unless necessary.

[0077] Next, an example of a method for manufacturing the above-mentioned semiconductor device SDV will be described. First, a semiconductor substrate SUB is prepared, and the semiconductor substrate SUB is subjected to the same processes as those shown in Figures 8 to 14 without receding the surface (first main surface first portion FMS1) of the epitaxial layer NEL located in the first region FRE. Next, as shown in Figure 25, a source electrode SEL1 is formed in the first region FRE, and a source electrode SEL2 is formed in the second region SRE.

[0078] Next, an etching process is performed on the substrate body SBY of the semiconductor substrate SUB. As shown in FIG. 26, for example, a TMAH etching process is performed on the substrate body SBY located in the first region FRE. As a result, etching proceeds along the plane orientation (111) of the substrate body SBY, and the epitaxial layer NEL is exposed. Furthermore, etching proceeds along the plane orientation (111) of the exposed epitaxial layer NEL, and the position of the second main surface first portion SMS1 recedes toward the first main surface FMS relative to the position of the second main surface second portion SMS2.

[0079] Next, for example, a back surface metal BME is formed so as to be in contact with the second main surface SMS including the second main surface first portion SMS1. After that, the semiconductor substrate SUB is diced, and the semiconductor device SDV is completed as shown in FIG.

[0080] Next, the operation of the semiconductor device SDV described above will be explained. As with the semiconductor device SDV described in the first embodiment, first, in the on state when the battery BA (see FIG. 1) is properly connected, a current flows through the first power MOS field effect transistor TMT1 and then through the second power MOS field effect transistor TMT2 (see the thick dotted arrow) as shown in FIG. 27. At this time, the thickness TK1 of the epitaxial layer NEL (first power MOS field effect transistor TMT1) in the first region FRE is selectively set to be thin, thereby reducing the on-resistance.

[0081] On the other hand, in the OFF state, the withstand voltage is ensured by the epitaxial layer NEL (second power MOS field effect transistor TMT2) having a thickness TK2 set to have a withstand voltage several times the voltage of the battery BA.

[0082] Next, when the battery BA (see FIG. 1) is reverse-connected, the withstand voltage is maintained by the first power MOS field-effect transistor TMT1, which has a withstand voltage slightly higher than the voltage of the battery BA.

[0083] In the above-described semiconductor device SDV, the first portion SMS1 of the second main surface in the first region FRE is located closer to the first main surface FMS than the second portion SMS2 of the second main surface in the second region SRE. That is, a structure is formed in which the thickness TK1 of the epitaxial layer NEL in the first region FRE is selectively thinner than the thickness TK2 of the epitaxial layer NEL in the second region SRE.

[0084] This makes it possible to easily optimize the on-resistance of the semiconductor device SDV by selectively adjusting (thinning) the thickness TK1 of the epitaxial layer NEL in the first region FRE while ensuring the breakdown voltage (thickness TK2 of the epitaxial layer NEL) of the second power MOS field effect transistor TMT2.

[0085] (Fourth embodiment) Here, a first example of a semiconductor device SDV including one power MOS field effect transistor and one logic / analog transistor will be described.

[0086] As shown in Figure 28, a power MOS field-effect transistor TMT and a logic-analog transistor LAT are formed on the same semiconductor substrate SUB. The power MOS field-effect transistor TMT has a superjunction structure (SJ structure) equipped with a column TCLM. The logic-analog transistor LAT controls the operation (on / off) of the power MOS field-effect transistor TMT.

[0087] The power MOS field-effect transistor TMT is formed in the first region FRE. The logic-analog transistor LAT is formed in the second region SRE. The second main surface first portion SMS1 and the second main surface second portion SMS2 are located on the same plane. The first main surface first portion FMS1 is located closer to the second main surface SMS than the first main surface second portion FMS2. In the epitaxial layer NEL in the first region FRE, a thickness TK1 of a portion that becomes a channel region where current conducts is thinner than a thickness TK2 of a portion that becomes a channel region where current conducts is thinner in the epitaxial layer NEL in the second region SRE.

[0088] The structures of the power MOS field-effect transistor TMT and the logic-analog transistor LAT will be explained in more detail.

[0089] In the first region FRE in which the power MOS field-effect transistor TMT is formed, a gate electrode TGE (first electrode) is formed in the trench TRC (see FIG. 30) with a gate oxide film TGZ (first insulating film) interposed therebetween. A P-region TPM (first impurity region first portion) is formed from the surface of the first main surface first portion FMS1 (epitaxial layer NEL) of the semiconductor substrate SUB to a position shallower than the bottom of the gate electrode TGE in a manner that the P-region TPM is in contact with the gate oxide film TGZ.

[0090] An N+ region TSN (first second impurity region) is formed from the surface of the first main surface first portion FMS1 (epitaxial layer NEL) of the semiconductor substrate SUB to a position shallower than the bottom of the P- region TPM. The N+ region TSN serves as the source region of the power MOS field-effect transistor TMT. A P-type column TCLM (second columnar body) is formed so as to extend from the bottom of the P- region LPM2 toward the substrate body SBY.

[0091] In the second region SRE in which the logic-analog transistor LAT is formed, a P-region LPM (first impurity region third portion) is formed from the surface of the first main surface second portion FMS2 (epitaxial layer NEL) to a predetermined depth. In the P-region LPM, a source region LSN and a drain region LDN (a pair of second impurity region third portions) are formed from the surface (surface of the P-region LPM) of the first main surface first portion FMS1 (epitaxial layer NEL) to a position shallower than the bottom of the P-region LPM. The source region LSN and the drain region LDN are formed at a distance from each other. A gate electrode LGE (third electrode) is formed on the P-region LPM sandwiched between the source region LSN and the drain region LDN, with a gate oxide film LGZ (third insulating film) interposed therebetween.

[0092] An interlayer insulating film ILF is formed so as to cover the first main surface FMS of the semiconductor substrate SUB. In the first region FRE, a plug TPG is formed so as to penetrate the interlayer insulating film ILF. In the second region SRE, a plug LPG is formed so as to penetrate the interlayer insulating film ILF. In the first region FRE, a source electrode TSE is formed so as to cover the interlayer insulating film ILF. In the second region SRE, a source electrode LSE and a drain electrode LDE are formed so as to contact the interlayer insulating film ILF.

[0093] In the first region FRE, the source electrode TSE and the N+ region TSN are electrically connected via a plug TPG. In the second region SRE, the source electrode LSE and the source region LSN are electrically connected via a plug LPG. The drain electrode LDE and the drain region LDN are electrically connected via a plug LPG.

[0094] The semiconductor substrate SUB is mounted on a lead frame LEF. The lead frame LEF is arranged so as to contact the second main surface SMC of the substrate body SBY (semiconductor substrate SUB). In addition to the lead frame LEF, a backside metal BME may be formed. Note that the other configurations are similar to those of the semiconductor device SDV shown in FIG. 3 and the like, and therefore the same components are designated by the same reference numerals, and their description will not be repeated unless necessary.

[0095] Next, an example of a method for manufacturing the above-mentioned semiconductor device SDV will be described. First, for example, by performing an etching process on the epitaxial layer NEL in the same manner as in the steps shown in Figures 4 and 5, the position of the first main surface first portion FMS1 is set back toward the substrate body SBY with respect to the position of the first main surface second portion FMS2, as shown in Figure 29.

[0096] Next, a trench TRC is formed in the first region FRE by performing photolithography and etching on the epitaxial layer NEL (see FIG. 30). Next, as shown in FIG. 30, a column TCLM is formed in the first region FRE by a process similar to the process shown in FIG. 9. Next, a gate electrode TGE is formed in the trench TRC with a gate oxide film TGZ interposed therebetween. In the second region SRE, a gate electrode TGE is formed on the epitaxial layer NEL with a gate oxide film LGZ interposed therebetween.

[0097] Here, by separating the process of forming the gate oxide film TGZ from the process of forming the gate oxide film LGZ, it is possible to form the gate oxide film TGZ and the gate oxide film LGZ having appropriate film thicknesses according to the performance of the power MOS field effect transistor TMT and the performance of the logic-analog transistor LAT.

[0098] 12 to 14 are then applied to the semiconductor substrate SUB. Next, a source electrode TSE is formed in the first region FRE, and a source electrode LSE and a drain electrode LDE are formed in the second region SRE (see FIG. 28). After that, the semiconductor substrate SUB is diced and mounted on a lead frame LEF, and the semiconductor device SDV is completed as shown in FIG.

[0099] Next, an example of the operation of the semiconductor device SDV described above will be described. The on / off operation of the power MOS field-effect transistor TMT formed in the first region FRE is controlled by the logic-analog transistor LAT formed in the second region SRE. As shown in Figure 31, when the power MOS field-effect transistor TMT is in the on state, a current flows from the lead frame LEF (backside metal BME) to the source electrode TSE (see the dotted arrow).

[0100] The above-described semiconductor device SDV has the following advantages: Usually, a semiconductor device including a power MOS field-effect transistor TMT and a logic-analog transistor LAT is designed so that the breakdown voltage of the logic-analog transistor LAT is higher than the breakdown voltage of the power MOS field-effect transistor TMT.

[0101] To ensure the breakdown voltage of the logic-analog transistor LAT, it is necessary to set the thickness of the epitaxial layer NEL in the second region SRE to a desired thickness. On the other hand, if the thickness of the epitaxial layer NEL in the first region FRE where the power MOS field-effect transistor TMT is formed is set to the same thickness as the thickness of the epitaxial layer NEL in the second region SRE, the on-resistance when current flows through the power MOS field-effect transistor TMT will increase.

[0102] In the semiconductor device SDV described above, the thickness TK1 of the epitaxial layer NEL in the first region FRE is thinner than the thickness TK2 of the epitaxial layer NEL in the second region SRE, thereby reducing the on-resistance when a current flows through the power MOS field-effect transistor TMT.

[0103] Furthermore, because the thickness TK1 of the epitaxial layer NEL in the first region FRE is thinner than the thickness TK2 of the epitaxial layer NEL in the second region SRE, the breakdown voltage of the power MOS field-effect transistor TMT is lower than the breakdown voltage of the logic-analog transistor LAT. As a result, assuming a situation in which breakdown occurs in the semiconductor device SDV, the power MOS field-effect transistor TMT will break down first, thereby preventing the logic-analog transistor LAT from being destroyed by the breakdown.

[0104] In this way, in the semiconductor device SDV described above, the breakdown voltage of the logic-analog transistor LAT can be ensured, thereby preventing destruction due to breakdown, and the on-resistance of the power MOS field-effect transistor TMT can be reduced.

[0105] (Embodiment 5) Here, as a second example of the semiconductor device SDV including one power MOS field effect transistor and one logic / analog transistor, a semiconductor device SDV in which processing is performed on the substrate body will be described.

[0106] 32, in the epitaxial layer NEL in the first region FRE, a thickness TK1 of a portion that becomes a channel region where current conduction occurs is thinner than a thickness TK2 of a portion that becomes a channel region where current conduction occurs in the epitaxial layer NEL in the second region SRE. The first main surface first portion FMS1 and the first main surface second portion FMS2 are located on the same plane. The second main surface first portion SMS1 is located closer to the first main surface FMS than the second main surface second portion SMS2.

[0107] A backside metal BME or the like is formed so as to contact the second main surface SMS including the second main surface first portion SMS1. Note that the other configurations are similar to the configuration of the semiconductor device SDV shown in Fig. 28, and therefore the same components are denoted by the same reference numerals, and the description thereof will not be repeated unless necessary.

[0108] Next, an example of a manufacturing method of the above-mentioned semiconductor device SDV will be described. First, a semiconductor substrate SUB is prepared, and the semiconductor substrate SUB is subjected to the same processes as those shown in Figures 30 and 31 without receding the surface (first main surface first portion FMS1) of the epitaxial layer NEL located in the first region FRE. As a result, a source electrode TSE is formed in the first region FRE, as shown in Figure 33. A source electrode LSE and a drain electrode LDE are formed in the second region SRE.

[0109] Next, an etching process is performed on the substrate body SBY of the semiconductor substrate SUB. As shown in FIG. 34, for example, a TMAH etching process is performed on the substrate body SBY located in the first region FRE. As a result, etching proceeds along the plane orientation (111) of the substrate body SBY, and the epitaxial layer NEL is exposed. Furthermore, etching proceeds along the plane orientation (111) of the exposed epitaxial layer NEL, and the position of the second main surface first portion SMS1 recedes toward the first main surface FMS relative to the position of the second main surface second portion SMS2.

[0110] Next, for example, a back surface metal BME is formed so as to be in contact with the second main surface SMS including the second main surface first portion SMS1. After that, the semiconductor substrate SUB is diced, and the semiconductor device SDV is completed as shown in FIG.

[0111] Next, an example of the operation of the semiconductor device SDV described above will be described. The on / off operation of the power MOS field-effect transistor TMT formed in the first region FRE is controlled by the logic-analog transistor LAT formed in the second region SRE. As shown in Figure 35, when the power MOS field-effect transistor TMT is in the on state, a current flows from the lead frame LEF (backside metal BME) to the source electrode TSE (see the dotted arrow).

[0112] In the semiconductor device SDV described above, similarly to the semiconductor device SDV described above, the thickness TK1 of the epitaxial layer NEL in the first region FRE is thinner than the thickness TK2 of the epitaxial layer NEL in the second region SRE, thereby making it possible to reduce the on-resistance when a current flows through the power MOS field-effect transistor TMT.

[0113] Furthermore, because the thickness TK1 of the epitaxial layer NEL in the first region FRE is thinner than the thickness TK2 of the epitaxial layer NEL in the second region SRE, the breakdown voltage of the power MOS field-effect transistor TMT is lower than the breakdown voltage of the logic-analog transistor LAT. As a result, assuming a situation in which breakdown occurs in the semiconductor device SDV, the power MOS field-effect transistor TMT will break down first, thereby preventing the logic-analog transistor LAT from being destroyed by the breakdown.

[0114] In this way, in the semiconductor device SDV described above, the breakdown voltage of the logic-analog transistor LAT can be ensured, thereby preventing destruction due to breakdown, and the on-resistance of the power MOS field-effect transistor TMT can be reduced.

[0115] In the semiconductor device SDV described above, the power MOS field effect transistor TMT having an SJ structure is mentioned, but also in the semiconductor devices SDV described in the first to third embodiments, the first power MOS field effect transistor TMT1 may be a first power MOS field effect transistor TMT1 having an SJ structure provided with a column, as necessary. The semiconductor devices described in each embodiment can be variously combined as necessary.

[0116] The invention made by the inventor has been specifically described above based on an embodiment, but it goes without saying that the present invention is not limited to the above embodiment and can be modified in various ways without departing from the gist of the invention. [Explanation of symbols]

[0117] TMT1 first power MOS field-effect transistor, PDD1 parasitic diode, G1 gate, GEL1 gate electrode, GZ1 gate oxide, SEL1 source electrode, PLG1 plug, S1 source, SN1 N+ region, PM1 P- region, TMT2 second power MOS field-effect transistor, PDD2 parasitic diode, G2 gate, GEL2 gate electrode, GZ2 gate oxide, SEL2 source electrode, PLG2 plug, S2 source, SN2 N+ region, PM2 P- region, CLM column, CDN drain region, TMT MOS field-effect transistor, TGE gate electrode, TGZ gate oxide, TSE source electrode, TPG plug, TSN N+ region, TPM P- region, TCLM column, LAT logic-analog transistor, LGE gate electrode, LGZ gate oxide, LSE source electrode, LDE drain electrode, LSN source region, LDN drain region, LPM P- region, LPG plug, SDV Semiconductor device, SUB semiconductor substrate, SBY substrate body, NEL epitaxial layer, FMS first main surface, SMS second main surface, FRE first region, FMS1 first part of first main surface, SMS1 first part of second main surface, SRE second region, FMS2 second part of first main surface, SMS2 second part of second main surface, LEF lead frame, BME backside metal, ILF interlayer insulating film, BA battery, LAD load, TMR peripheral region, TS peripheral structure portion, SOF, SIF, IMF silicon oxide film, SNF silicon nitride film, TRC1, TRC2, TRC trench, CH1, CH2 contact opening.

Claims

1. A lead frame or backside metal, a semiconductor substrate mounted on the lead frame or the back surface metal and having a first main surface and a second main surface; a first region and a second region each defined in the semiconductor substrate; a first switching element formed in the first region and conducting current between the first main surface and the second main surface; a second switching element formed in the second region and connected in anti-series with the first switching element; an interlayer insulating film formed to cover the first main surface of the semiconductor substrate; a first plug formed in the first region so as to penetrate the interlayer insulating film; a second plug formed in the second region so as to penetrate the interlayer insulating film; a first source electrode formed in the first region so as to cover the interlayer insulating film; a second source electrode formed in the second region so as to cover the interlayer insulating film; Equipped with The semiconductor substrate is an N-type substrate body formed so as to contact the lead frame or the back surface metal in the first region and the second region and having the second main surface; an N-type semiconductor layer formed in contact with the substrate body and having the first main surface; Including, The first switching element is a first electrode formed in a first trench formed in the semiconductor layer with a first insulating film interposed therebetween; a P-type first impurity region first portion formed in the semiconductor layer from the first main surface to a position shallower than a bottom of the first electrode in a manner to contact the first insulating film; an N-type second impurity region first portion formed in the first impurity region first portion from the first main surface to a position shallower than a bottom of the first impurity region first portion; Including, The second switching element is a second electrode formed in a second trench formed in the semiconductor layer with a second insulating film interposed therebetween; a P-type first impurity region second portion formed in the semiconductor layer from the first main surface to a position shallower than a bottom of the second electrode in a manner to contact the second insulating film; an N-type second impurity region second part formed in the first impurity region second part from the first main surface to a position shallower than a bottom of the first impurity region second part; Including, the first source electrode is electrically connected to the first portion of the second impurity region through the first plug and is connected to a battery; the second source electrode is electrically connected to the second portion of the second impurity region via the second plug and is connected to a load; a thickness of the semiconductor layer in a portion located in the first region and through which the current related to the first switching element is conducted is a first thickness; a thickness of the semiconductor layer in a portion located in the second region and through which a current related to the second switching element is conducted is a second thickness; The semiconductor device, wherein the first thickness is less than the second thickness.

2. The first main surface of the semiconductor substrate is a first portion of a first main surface located in the first region; a first main surface second portion located in the second region; Including, The semiconductor device according to claim 1 , wherein said first main surface first portion is located closer to said second main surface than said first main surface second portion.

3. The second main surface of the semiconductor substrate is a first portion of the second main surface located in the first region; a second portion of a second main surface located in the second region; Including, The semiconductor device according to claim 1 , wherein said second main surface first portion is located closer to said first main surface than said second main surface second portion.

4. 2. The semiconductor device according to claim 1, wherein said first switching element includes a P-type first columnar body extending from said first portion of said first impurity region toward said substrate body.

5. 2. The semiconductor device according to claim 1, wherein said second switching element includes a P-type second columnar body extending from said first impurity region second portion toward said substrate body.

6. A semiconductor device described in any one of claims 1 to 5, wherein the impurity concentration of the N-type substrate body is higher than the impurity concentration of the N-type semiconductor layer.

7. a step of preparing a semiconductor substrate having a first main surface and a second main surface, in which a first region and a second region are respectively defined, the semiconductor substrate including an N-type substrate body having the second main surface, and an N-type semiconductor layer formed in contact with the substrate body and having the first main surface; forming a first switching element in the first region of the semiconductor substrate, the first switching element conducting a current between the first main surface and the second main surface, and forming a second switching element in the second region of the semiconductor substrate, the second switching element being connected in anti-series to the first switching element; making a first thickness of the semiconductor layer in a portion located in the first region and through which the current related to the first switching element is conducted thinner than a second thickness of the semiconductor layer in a portion located in the second region and through which the current related to the second switching element is conducted; forming an interlayer insulating film so as to cover the first main surface of the semiconductor substrate; forming a first plug in the first region and a second plug in the second region so as to penetrate the interlayer insulating film; forming a first source electrode in the first region and a second source electrode in the second region so as to cover the interlayer insulating film; preparing a lead frame or a back surface metal, and mounting the semiconductor substrate on the lead frame or the back surface metal in a manner that the second main surface is in contact with the lead frame or the back surface metal; Equipped with The step of forming the first switching element includes: forming a first electrode in a first trench formed in the semiconductor layer with a first insulating film interposed therebetween; forming a P-type first impurity region (first part) in the semiconductor layer from the first main surface to a position shallower than a bottom of the first electrode in a manner to be in contact with the first insulating film; forming an N-type second impurity region first portion in the first impurity region first portion, extending from the first main surface to a position shallower than a bottom of the first impurity region first portion; Including, The step of forming the second switching element includes: forming a second electrode in a second trench formed in the semiconductor layer with a second insulating film interposed therebetween; forming a P-type first impurity region second part in the semiconductor layer from the first main surface to a position shallower than a bottom of the second electrode in a manner to be in contact with the second insulating film; forming an N-type second impurity region second part in the first impurity region second part, extending from the first main surface to a position shallower than a bottom of the first impurity region second part; Including, the step of forming the first source electrode includes the step of electrically connecting the first source electrode to the first portion of the second impurity region through the first plug and connecting the first source electrode to a battery; a second source electrode formed on the first portion of the second impurity region through the second plug and connected to a load;

8. In the step of preparing the semiconductor substrate, a first region of the first main surface defines a first main surface first portion; The second region of the first main surface defines a first main surface second portion, 8. The method for manufacturing a semiconductor device according to claim 7, wherein in the step of making the first thickness thinner than the second thickness, the first portion of the first main surface is brought closer to the second main surface than the second portion of the first main surface by performing an etching process on the first portion of the first main surface.

9. In the step of preparing the semiconductor substrate, a second major surface first portion is defined in the first region of the second major surface; a second region of the second main surface defines a second main surface second portion; 8. The method for manufacturing a semiconductor device according to claim 7, wherein in the step of making the first thickness thinner than the second thickness, the second main surface first portion is brought closer to the first main surface relative to the second main surface second portion by performing an etching process on the second main surface first portion.

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