Semiconductor device and manufacturing method thereof

Abstract

To provide a semiconductor device with high reliability and a method for manufacturing the same.SOLUTION: A semiconductor substrate SUB includes a first surface FS, a second surface SS facing the first surface FS, and a groove TR extending from the second surface SS toward the first surface FS. A gate electrode GE is arranged in the groove TR, and includes a lower end LE located in a bottom of the groove TR and an upper end UE facing the lower end LE. The upper end UE is located closer to the first surface FS side than the second surface SS. An n-type source region SR includes a first region S1 having a first concentration and a second region S2 having a second concentration higher than the first concentration. The first region S1 includes a portion located closer to the first surface FS side than the upper end UE of the gate electrode GE. The second region S2 is located closer to the second surface SS side than the upper end UE of the gate electrode GE.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device and a manufacturing method thereof, and can be suitably used, for example, in a semiconductor device having a trench gate field effect transistor and a manufacturing method thereof. [Background technology]

[0002] A conventional semiconductor device having a trench-gate field-effect transistor is disclosed, for example, in Japanese Patent Laid-Open No. 2016-35996 (Patent Document 1). In Patent Document 1, the trench-gate field-effect transistor has a trench and a gate electrode formed in the trench with a gate insulating film interposed therebetween. A sidewall insulating film is formed on the gate electrode and on the sidewall of the trench. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2016-35996 Summary of the Invention [Problem to be solved by the invention]

[0004] It is desired to improve the reliability even more than that of the semiconductor device having the configuration described in Patent Document 1.

[0005] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0006] According to one embodiment of the semiconductor device, the semiconductor substrate has a first surface, a second surface opposite the first surface, and a trench extending from the second surface toward the first surface. The gate electrode is disposed in the trench and has a lower end located at the bottom of the trench and an upper end opposite the lower end, the upper end being located closer to the first surface than the second surface. The source region has a first region having a first concentration and a second region having a second concentration higher than the first concentration. The first region has a portion located closer to the first surface than the upper end of the gate electrode. The second region is located closer to the second surface than the upper end of the gate electrode.

[0007] According to one embodiment of a method for manufacturing a semiconductor device, a semiconductor substrate is prepared, the semiconductor substrate having a first surface, a second surface opposite the first surface, and a trench extending from the second surface toward the first surface. A gate electrode is formed in the trench with a gate insulating film interposed therebetween, the gate electrode having a lower end located at the bottom of the trench and an upper end opposite the lower end and located closer to the first surface than the second surface. A source region is formed in the semiconductor substrate. The step of forming the source region includes the steps of forming a first region having a first concentration, the first region having a portion located closer to the first surface than the upper end of the gate electrode, and forming a second region located closer to the second surface than the upper end of the gate electrode and having a second concentration higher than the first concentration. [Effects of the Invention]

[0008] According to the above embodiment, it is possible to realize a highly reliable semiconductor device and a method for manufacturing the same. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a cross-sectional view showing the configuration of a semiconductor device according to a first embodiment. [Figure 2] 2 is an enlarged cross-sectional view showing the periphery of a groove in FIG. 1. FIG. [Figure 3] 2A is an enlarged cross-sectional view showing a part of the source region in FIG. 1, and FIG. 2B is a diagram showing the impurity concentration distribution in the depth direction of the source region. [Figure 4] 2 is a cross-sectional view showing a first step of the method for manufacturing the semiconductor device according to the first embodiment. [Figure 5]4 is a cross-sectional view showing a second step in the method for manufacturing the semiconductor device according to the first embodiment. FIG. [Figure 6] 4 is a cross-sectional view showing a third step of the method for manufacturing the semiconductor device according to the first embodiment. FIG. [Figure 7] 4 is a cross-sectional view showing a fourth step of the method for manufacturing the semiconductor device according to the first embodiment. FIG. [Figure 8] 5 is a cross-sectional view showing a fifth step of the method for manufacturing the semiconductor device according to the first embodiment. FIG. [Figure 9] 10 is a cross-sectional view showing a sixth step of the method for manufacturing the semiconductor device according to the first embodiment. FIG. [Figure 10] 10 is a cross-sectional view showing a seventh step of the method for manufacturing the semiconductor device according to the first embodiment. FIG. [Figure 11] 10 is a cross-sectional view showing an eighth step of the method for manufacturing the semiconductor device according to the first embodiment. FIG. [Figure 12] 10 is a cross-sectional view showing a ninth step of the method for manufacturing the semiconductor device according to the first embodiment. FIG. [Figure 13] 10 is a cross-sectional view showing a tenth step of the method for manufacturing the semiconductor device according to the first embodiment. FIG. [Figure 14] 10 is a cross-sectional view showing an eleventh step of the method for manufacturing the semiconductor device according to the first embodiment. FIG. [Figure 15] FIG. 1 is a cross-sectional view showing the configuration of Comparative Example 1. [Figure 16] FIG. 10 is a cross-sectional view showing the configuration of Comparative Example 2. [Figure 17] FIG. 10 is a cross-sectional view showing the configuration of Comparative Example 3. [Figure 18] FIG. 10 is a diagram showing the relationship between the applied voltage and the lifetime when ion implantation is performed at a low dose and a high dose. [Figure 19] FIG. 10 is a cross-sectional view showing the configuration of a semiconductor device according to a second embodiment. [Figure 20] 10 is a cross-sectional view showing a first step of a method for manufacturing a semiconductor device according to a second embodiment. [Figure 21] 10 is a cross-sectional view showing a second step in the method for manufacturing a semiconductor device according to the second embodiment. [Figure 22] FIG. 10 is a cross-sectional view showing a configuration of a semiconductor device according to a modified example. DETAILED DESCRIPTION OF THE INVENTION

[0010] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. In the specification and drawings, identical or corresponding components are designated by the same reference numerals, and redundant descriptions will not be repeated. For the sake of convenience, configurations may be omitted or simplified in the drawings. At least some of the embodiments and modified examples may be combined with each other in any desired manner.

[0011] The semiconductor device in the embodiments described below is not limited to a semiconductor chip, but may be a semiconductor wafer before being divided into semiconductor chips, or a semiconductor package in which semiconductor chips are sealed with resin. Furthermore, in this specification, a plan view refers to a viewpoint seen from a direction perpendicular to the surface of a semiconductor substrate.

[0012] (Embodiment 1) <Configuration of semiconductor device> First, the configuration of the semiconductor device according to the first embodiment will be described with reference to FIGS.

[0013] 1, the semiconductor device according to the first embodiment includes a semiconductor substrate SUB and a vertical trench-gate field-effect transistor. The field-effect transistor is, for example, a MISFET (Metal Insulator Semiconductor Field Effect Transistor), and more specifically, a power MOS (Metal Oxide Semiconductor) transistor. The field-effect transistor is formed on the semiconductor substrate SUB.

[0014] The material of the gate insulating film GI used in this field-effect transistor is not limited to silicon oxide film, and may be other materials such as silicon nitride film. In addition, although an n-channel field-effect transistor will be described below, the transistor to which the present disclosure is applied may also be a p-channel field-effect transistor.

[0015] The semiconductor substrate SUB has a first surface FS and a second surface SS. The first surface FS and the second surface SS face each other. The semiconductor substrate SUB is made of, for example, single crystal silicon. A trench TR is provided in the semiconductor substrate SUB. The trench TR extends from the second surface SS of the semiconductor substrate SUB toward the first surface FS.

[0016] The insulated gate field effect transistor is a vertical transistor that passes a current between the first surface FS and the second surface SS of the semiconductor substrate SUB. + The semiconductor device has a drain region DR, an n-type drift region DRI, a p-type base region BR, an n-type source region SR, a gate insulating film GI, and a gate electrode GE. + The drain region DR, the n-type drift region DRI, the p-type base region BR, and the n-type source region SR are each disposed in the semiconductor substrate.

[0017] n + The drain region DR is disposed on the first surface FS of the semiconductor substrate SUB. The n-type drift region DRI is + It is arranged on the second surface SS side with respect to the drain region DR, and n + The n-type drift region DRI is in contact with the drain region DR. + The n-type impurity concentration is lower than that of the drain region DR.

[0018] The p-type base region BR is disposed on the second surface SS side of the n-type drift region DRI and forms a pn junction with the n-type drift region DRI. The n-type source region SR is disposed on the second surface SS side of the p-type base region BR and forms a pn junction with the p-type base region BR. The n-type source region SR is disposed on the second surface SS of the semiconductor substrate SUB.

[0019] The trenches TR extend from the second surface SS through the n-type source regions SR and the p-type base regions BR to the n-type drift regions DRI. A gate insulating film GI is disposed along the wall surfaces of the trenches TR. The gate insulating film GI is made of, for example, a silicon oxide film, but is not limited to this.

[0020] The gate electrode GE is arranged in the trench TR with a gate insulating film GI interposed therebetween. The gate electrode GE is made of, for example, polycrystalline silicon (doped polysilicon) into which impurities have been introduced. The gate electrode GE faces the p-type base region BR with the gate insulating film GI interposed therebetween. A sidewall insulating film SW is arranged on the gate electrode GE so as to cover the sidewall of the trench TR.

[0021] An interlayer insulating layer IL is disposed on the second surface SS of the semiconductor substrate SUB. The interlayer insulating layer IL is made of, for example, a silicon oxide film. The interlayer insulating layer IL has, for example, a boro-phosphosilicate glass (BPSG) film formed using tetra ethyl orthosilicate (TEOS) as a raw material.

[0022] A contact hole CH is provided in the interlayer insulating layer IL. The contact hole CH penetrates the interlayer insulating layer IL and reaches the semiconductor substrate SUB. The contact hole CH reaches the n-type source region SR. Although not shown, the interlayer insulating layer IL also has a contact hole that reaches the gate electrode GE.

[0023] A conductive layer PL is buried in the contact hole CH. The conductive layer PL is connected to the n-type source region SR. The conductive layer PL includes a barrier metal layer and a buried conductive layer. The barrier metal layer is formed along the wall surface of the contact hole CH and is made of, for example, a stacked film of titanium (Ti) and titanium nitride (TiN). The buried conductive layer fills the inside of the contact hole CH and is made of, for example, tungsten (W).

[0024] A source electrode SE is disposed on the interlayer insulating layer IL. The source electrode SE is electrically connected to the n-type source region SR via a conductive layer PL. An insulating film PF is disposed on the interlayer insulating layer IL so as to cover a portion of the source electrode SE. The insulating film PF is a passivation film made of, for example, a polyimide-based resin. An opening OP is provided in the insulating film PF. A portion of the source electrode SE is exposed from the opening OP. The portion of the source electrode SE exposed from the opening OP forms a source bonding pad.

[0025] A drain electrode DE is disposed on the first surface FS of the semiconductor substrate SUB. + By contacting the drain region DR, + It is electrically connected to the drain region DR.

[0026] 2, the gate electrode GE has a lower end LE located at the bottom of the trench TR and an upper end UE facing the lower end LE. The upper end UE of the gate electrode GE is located closer to the first surface FS (FIG. 1) than the second surface SS of the semiconductor substrate SUB.

[0027] The gate insulating film GI has a first insulating film G1 and a second insulating film G2. The first insulating film G1 is arranged along the bottom wall of the trench TR and the lower side of the sidewall of the trench TR (on the first surface FS side). The end of the first insulating film G1 on the second surface SS side is located closer to the first surface FS than the position of the upper surface of the gate electrode GE.

[0028] The second insulating film G2 is located above the first insulating film G1 (on the second surface SS side) and is disposed along the sidewall of the trench TR. The second insulating film G2 is connected to the end of the first insulating film G1 on the second surface SS side. The thickness of the second insulating film G2 (the thickness in the direction perpendicular to the direction from the second surface SS toward the first surface FS) is thinner than the thickness of the first insulating film G1.

[0029] A recess is formed between the gate electrode GE and the gate insulating film GI. The bottom wall of this recess is formed by the upper surface (the end surface on the second surface SS side) of the first insulating film G1. One side wall of this recess is formed by the side wall of the gate electrode GE, and the other side wall of this recess is formed by the side wall of the second insulating film G2.

[0030] The first insulating film G1 and the second insulating film G2 are made of the same material, for example, silicon oxide film, but are not limited to this material.

[0031] A sidewall insulating film SW is arranged closer to the second surface SS than the gate insulating film GI. Specifically, the sidewall insulating film SW is arranged closer to the second surface SS than the first insulating film G1. The sidewall insulating film SW is arranged along the sidewall of the trench TR. The sidewall insulating film SW is made of, for example, a silicon oxide film, but is not limited to this material. A second insulating film G2 of the gate insulating film GI is located between the sidewall insulating film SW and the sidewall of the trench TR.

[0032] The sidewall insulating film SW covers a part of the upper surface of the gate electrode GE and fills the recess between the gate electrode GE and the sidewall insulating film SW. An interlayer insulating layer IL is disposed on the sidewall insulating film SW. The sidewall insulating film SW is in contact with the interlayer insulating layer IL.

[0033] The n-type source region SR has a first region S1 and a second region S2. The first region S1 forms a pn junction with the p-type base region BR. The second region S2 is located on the second surface SS side of the first region S1 and is connected to the first region S1. The n-type impurity concentration of the second region S2 is higher than the n-type impurity concentration of the first region S1.

[0034] The first region S1 has a portion located closer to the first plane FS than the upper end UE of the gate electrode GE. The pn junction between the first region S1 and the p-type base region BR is located closer to the first plane FS than the upper end UE of the gate electrode GE. For example, a portion PN1 of the pn junction between the first region S1 and the p-type base region BR, which is in contact with the sidewall of the trench TR, is located closer to the first plane FS than a portion UE1 of the upper end UE of the gate electrode GE that is closest to the portion PN1.

[0035] The second region S2 is located closer to the second surface SS than the upper end UE of the gate electrode GE. The junction between the first region S1 and the second region S2 (indicated by the dashed line in the figure) is located closer to the second surface SS than the upper end UE of the gate electrode GE. For example, a portion CN1 of the junction between the first region S1 and the second region S2 that contacts the sidewall of the trench TR is located closer to the second surface SS than a portion UE1 of the upper end UE of the gate electrode GE that is closest to the portion CN1.

[0036] 3, the n-type impurity concentration distribution in the first region S1 has a concentration peak on the first surface side of the second surface SS. The n-type impurity in the first region S1 is, for example, phosphorus (P), but is not limited to this.

[0037] The n-type impurity concentration distribution in the second region S2 has a concentration peak at a position closer to the second surface SS than the concentration peak position in the first region S1. The n-type impurity in the second region S2 is, for example, arsenic (As), but is not limited to this.

[0038] The concentration peak in the first region S1 is, for example, 1×10 19 cm -3 The concentration peak in the second region S2 is, for example, 1×10 20 cm -3 The n-type impurity concentration at the concentration peak in the second region S2 is higher than the n-type impurity concentration at the concentration peak in the first region S1. The n-type impurity concentration at the concentration peak in the second region S2 may be, for example, 10 times or more higher than the n-type impurity concentration at the concentration peak in the first region S1.

[0039] At the pn junction between the first region S1 and the p-type base region BR, the n-type impurity concentration in the first region S1 is approximately the same as the p-type impurity concentration in the p-type base region BR. At the junction between the first region S1 and the second region S2, the n-type impurity concentration in the first region S1 is approximately the same as the n-type impurity concentration in the second region S2.

[0040] <Method of manufacturing a semiconductor device> Next, a method for manufacturing the semiconductor device according to the first embodiment will be described with reference to FIGS.

[0041] As shown in Figure 4, a semiconductor substrate SUB is prepared having a first surface FS (Figure 1) and a second surface SS facing each other. At least an n-type drift region DRI is formed in the semiconductor substrate SUB. A trench TR is formed in the second surface SS of the semiconductor substrate SUB by photolithography and etching techniques. The trench TR is formed so as to extend from the second surface SS toward the first surface FS. As a result of the above, a semiconductor substrate SUB is prepared having the first surface FS, the second surface SS facing the first surface FS, and the trench TR extending from the second surface SS toward the first surface FS.

[0042] 5, the second surface SS of the semiconductor substrate SUB and the inner walls (side walls and bottom walls) of the trenches TR are oxidized. As a result, a first insulating film G1 made of a silicon oxide film is formed on the second surface SS of the semiconductor substrate SUB and the inner walls of the trenches TR.

[0043] 6, a conductive layer GE made of doped polysilicon for the gate electrode is formed on the first insulating film G1 so as to fill the trench TR. The conductive layer GE may be formed by forming polycrystalline silicon on the second surface SS and then doping the polycrystalline silicon with impurities. Alternatively, the conductive layer GE may be formed by depositing polycrystalline silicon doped with impurities on the second surface SS.

[0044] As shown in FIG. 7, the conductive layer GE is removed by etching until at least the surface of the first insulating film G1 is exposed. This leaves the conductive layer GE in the trench TR. The conductive layer GE remaining in the trench TR forms a gate electrode GE. The gate electrode GE is formed to have a lower end LE located at the bottom of the trench TR and an upper end UE opposing the lower end LE. By the above etching, the conductive layer GE is etched away so that the upper end UE of the gate electrode GE is located closer to the first surface FS than the second surface SS of the semiconductor substrate SUB.

[0045] 8, the first insulating film G1 is removed by wet etching at least until the second surface SS of the semiconductor substrate SUB is exposed. At this time, the first insulating film G1 is etched away so that the upper end (the end on the second surface SS side) of the first insulating film G1 is located closer to the first surface FS than the upper end UE of the gate electrode GE.

[0046] As shown in FIG. 9, the second surface SS of the semiconductor substrate SUB and the sidewalls of the trenches TR are oxidized. As a result, a second insulating film G2 made of a silicon oxide film is formed on the second surface SS of the semiconductor substrate SUB and the sidewalls of the trenches TR. Although not shown, the upper surface and side surfaces of the gate electrode GE may also be oxidized during this oxidation. The second insulating film G2 is formed so as to connect to the upper end (the end on the second surface SS side) of the first insulating film G1. A recess is also formed between the gate electrode GE and the second insulating film G2.

[0047] 10, p-type impurities (e.g., boron (B)) are implanted into the semiconductor substrate SUB from the second surface SS side of the semiconductor substrate SUB by ion implantation. As a result, a p-type base region BR is formed in the second surface SS of the semiconductor substrate SUB. The p-type base region BR is formed so as to be located on the second surface SS side of the n-type drift region DRI and to form a pn junction with the n-type drift region DRI.

[0048] As shown in FIG. 11, an insulating film SWI is formed on the second insulating film G2 so as to fill the trench TR. The insulating film SWI is made of, for example, a silicon oxide film. Thereafter, the insulating films SWI and G2 are anisotropically etched. This anisotropic etching is performed until the second surface SS of the semiconductor substrate SUB and the upper surface of the gate electrode GE are exposed.

[0049] 12, the second insulating film G2 on the second surface SS is removed by the above-described anisotropic etching, but the second insulating film G2 along the sidewall of the trench TR remains. The remaining second insulating film G2 forms the gate insulating film GI together with the first insulating film G1.

[0050] Furthermore, by the above-mentioned anisotropic etching, a sidewall insulating film SW is formed from the insulating film SWI. The sidewall insulating film SW is formed so as to sandwich the second insulating film G2 between itself and the sidewall of the trench TR. The sidewall insulating film SW is formed so as to follow the sidewall of the trench TR on the second surface SS side of the gate insulating film GI relative to the first insulating film G1. The sidewall insulating film SW is also formed so as to cover a part of the upper surface of the gate electrode GE and to fill the recess between the gate electrode GE and the gate insulating film GI.

[0051] 13, n-type impurities (for example, phosphorus) are ion-implanted into the semiconductor substrate SUB from the second surface SS side of the semiconductor substrate SUB. This ion implantation is performed with an implantation energy of 50 keV or more and 100 keV or less, and a fluence of 1.0×10 14 atoms / cm 2 The ion implantation is performed under the following dose conditions: Moreover, this ion implantation is performed in a state where the sidewall insulating film SW is located closer to the second surface SS than the first insulating film G1 of the gate insulating film GI.

[0052] This ion implantation forms a first region S1 in the second surface SS of the semiconductor substrate SUB. The first region S1 is formed so as to be located on the second surface SS side with respect to the p-type base region BR and to form a pn junction with the p-type base region BR.

[0053] The first region S1 is formed to have a portion located closer to the first plane FS than the upper end UE of the gate electrode GE. The first region S1 is formed so that the pn junction between the first region S1 and the p-type base region BR is located closer to the first plane FS than the upper end UE of the gate electrode GE. For example, the first region S1 is formed so that a portion PN1 of the pn junction between the first region S1 and the p-type base region BR, which is in contact with the sidewall of the trench TR, is located closer to the first plane FS than a portion UE1 of the upper end UE of the gate electrode GE that is closest to the portion PN1.

[0054] 14, n-type impurities (e.g., arsenic) are ion-implanted into the semiconductor substrate SUB from the second surface SS side of the semiconductor substrate SUB. This ion implantation is performed under conditions that are lower than the implantation energy of the impurity ions for forming the first region S1 and are higher than the dose of the impurity ions for forming the first region S1. This ion implantation is performed, for example, with an implantation energy of 10 keV or more and 40 keV or less, and a dose of 1.0×10 16 atoms / cm 2 Moreover, this ion implantation is performed in a state where the sidewall insulating film SW is located closer to the second surface SS than the first insulating film G1 of the gate insulating film GI.

[0055] As a result, a second region S2 is formed on the second surface SS of the semiconductor substrate SUB. The second region S2 is formed so as to be located on the second surface SS side with respect to the first region S1 and so as to be joined to the first region S1.

[0056] The second region S2 is formed so as to be located closer to the second surface SS than the upper end UE of the gate electrode GE. The second region S2 is formed so as to have a higher n-type impurity concentration than the n-type impurity concentration of the first region S1. The second region S2 is formed so that the junction between the first region S1 and the second region S2 is located closer to the second surface SS than the upper end UE of the gate electrode GE. For example, the second region S2 is formed so that a portion CN1 of the junction between the first region S1 and the second region S2, which is in contact with the sidewall of the trench TR, is located closer to the second surface SS than a portion UE1 of the upper end UE of the gate electrode GE that is closest to portion CN1.

[0057] Thereafter, as shown in FIG. 1, an interlayer insulating layer IL, a conductive layer PL, a source electrode SE, a drain electrode DE, an insulating film PF, etc. are formed, thereby manufacturing the semiconductor device of this embodiment.

[0058] <Effects> Next, the effects of this embodiment will be described in comparison with Comparative Examples 1 to 3.

[0059] As shown in FIG. 15, in Comparative Example 1, high-dose ion implantation is performed to form the n-type source region SR without forming a sidewall insulating film. In this case, impurity ions are implanted not only into the semiconductor substrate SUB but also into the gate insulating film GI at the upper end of the trench TR. The region indicated by scattered hatching in the figure indicates a region in the gate insulating film GI where a high dose of impurity ions has been implanted. The gate insulating film GI into which the high dose of impurity ions has been implanted is deteriorated by implantation damage. This causes a leakage current, as indicated by the arrow in the figure, during use, reducing the reliability of the gate insulating film GI.

[0060] 16, a sidewall insulating film SW is disposed on the gate electrode GE and the gate insulating film GI. In this state, ion implantation is performed at a high dose to form the n-type source region SR. Therefore, when the n-type source region SR is formed shallow from the second surface SS, the presence of the sidewall insulating film SW suppresses the implantation of impurity ions into the gate insulating film GI located between the gate electrode GE and the semiconductor substrate SUB.

[0061] In this case, however, an offset OFS occurs between the upper end of the gate electrode GE and the lower end of the n-type source region SR. When the offset OFS occurs, the threshold voltage of the field-effect transistor increases sharply, and the offset OFS becomes a factor causing variations.

[0062] 17, it is necessary to form the n-type source region SR deep from the second surface SS so as to prevent the occurrence of the offset OFS. However, in this case, even if the sidewall insulating film SW is arranged, impurity ions are implanted at a high dose into the gate insulating film GI between the gate electrode GE and the semiconductor substrate SUB. Therefore, as in the above, the gate insulating film GI into which the impurity ions are implanted at a high dose is deteriorated by implantation damage, and the reliability of the gate insulating film GI is reduced.

[0063] In Comparative Example 3, it is also possible to implant impurity ions at a low dose so as not to affect the reliability of the gate insulating film GI. However, in this case, the impurity concentration in the n-type source region SR becomes low, and the contact between the n-type source region SR and the conductive layer deteriorates.

[0064] 1 and 2, the n-type source region SR has a first region S1 having a first concentration and a second region S2 having a second concentration higher than the first concentration. The first region S1 has a portion located closer to the first surface FS than the upper end UE of the gate electrode GE, and the second region S2 is located closer to the second surface SS than the upper end UE of the gate electrode GE.

[0065] This prevents a high dose of impurity ions for forming the second region S2 from being implanted into the gate insulating film GI between the gate electrode GE and the semiconductor substrate SUB, thereby making the gate insulating film GI less susceptible to damage caused by the implantation of a high dose of impurity ions, and improving the reliability of the gate insulating film GI.

[0066] Furthermore, since the second region S2 has a higher n-type impurity concentration than the first region S1, it is possible to prevent the contact between the second region S2 and the conductive layer PL from deteriorating.

[0067] Furthermore, since the first region S1 has a portion located closer to the first face FS than the upper end UE of the gate electrode GE, it is possible to prevent an offset from occurring between the n-type source region SR and the gate electrode GE, thereby preventing variations such as a sudden increase in the threshold voltage of the field-effect transistor.

[0068] Since the first region S1 has a portion located closer to the first surface FS than the upper end UE of the gate electrode GE, a low dose of impurity ions for forming the first region S1 is implanted into the gate insulating film GI between the gate electrode GE and the semiconductor substrate SUB. However, the present inventors have confirmed that even if such a low dose of impurity ions is implanted into the gate insulating film GI, the lifetime of the gate insulating film GI is not significantly reduced. The results of the inventors' investigation are shown in FIG. 18 below.

[0069] Fig. 18 is a diagram showing the relationship between applied voltage and lifetime when ions are implanted at a low dose and a high dose. In Fig. 18, the horizontal axis shows the indexed applied voltage, and the vertical axis shows the lifetime of the gate insulating film. The lifetime is longer at the top of the vertical axis, and shorter at the bottom. The white circles in the graph represent values ​​of 2.0 x 10 15 atoms / cm 2 The black diamond indicates a low dose of 9.0×10 15 atoms / cm 2 This shows a high dose of .

[0070] As is clear from the results in Figure 18, the lifetime of the gate insulating film is longer when the dose is low than when the dose is high. Furthermore, at an applied voltage of 6.0 V, which is the assumed operating condition, the lifetime of the gate insulating film when the dose is low is more than two orders of magnitude longer than that when the dose is high.

[0071] This shows that in the semiconductor device of this embodiment, the gate insulating film GI can maintain a long life.

[0072] In this embodiment, a sidewall insulating film SW is provided as shown in Fig. 2. This makes it difficult for impurity ions to be implanted into the gate insulating film GI between the gate electrode GE and the semiconductor substrate SUB during the high-dose ion implantation shown in Fig. 14. This further improves the reliability of the gate insulating film GI.

[0073] (Embodiment 2) <Configuration of semiconductor device> Next, the configuration of the semiconductor device according to the second embodiment will be described with reference to FIG.

[0074] 19, the semiconductor device of this embodiment differs from that of Embodiment 1 in the configuration of the n-type source region SR. The n-type source region SR in this embodiment has a first region S1 and a second region S2. The second region S2 has an n-type impurity concentration higher than the n-type impurity concentration of the first region S1.

[0075] The first region S1 has a first portion S1a and a second portion S1b. The first portion S1a is located away from the trench TR. The second portion S1b is connected to the first portion S1a and extends along the sidewall of the trench TR toward the first face FS beyond the first portion S1a. The first portion S1a and the second portion S1b have the same n-type impurity concentration.

[0076] An end EP of the second portion S1b on the first surface FS side is located closer to the first surface FS than an upper end UE of the gate electrode GE. For example, the first portion S1a is formed so that the pn junction between the end EP of the second portion S1b and the p-type base region BR is located closer to the first surface FS than a portion UE1 of the upper end UE of the gate electrode GE that is closest to the sidewall of the trench TR.

[0077] The pn junction between the first portion S1a and the p-type base region BR is located closer to the second surface SS than the upper end UE of the gate electrode GE. For example, the first portion S1a is formed so that the pn junction between the first portion S1a and the p-type base region BR is located closer to the second surface SS than a portion UE1 of the upper end UE of the gate electrode GE that is closest to the sidewall of the trench TR.

[0078] The pn junction between the first portion S1a and the p-type base region BR may be located closer to the first face FS than the upper end UE of the gate electrode GE.

[0079] The configuration of this embodiment other than the above is almost the same as the configuration of embodiment 1, so the same elements are given the same reference numerals and the description thereof will not be repeated.

[0080] <Method of manufacturing a semiconductor device> Next, a method for manufacturing a semiconductor device according to the second embodiment will be described with reference to FIGS.

[0081] The method for manufacturing a semiconductor device according to this embodiment first goes through the same steps as in the first embodiment shown in Fig. 4 to Fig. 10. After that, as shown in Fig. 20, before the sidewall insulating film SW is formed, ions of an n-type impurity (for example, phosphorus) are obliquely implanted into the semiconductor substrate SUB from the second surface SS side of the semiconductor substrate SUB. This oblique implantation is carried out at a rate of, for example, 1.0 × 10 14 atoms / cm 2 The oblique implantation is performed under the following dose conditions: Oblique implantation is implanting impurity ions into the semiconductor substrate SUB at an angle oblique to the second surface SS of the semiconductor substrate SUB. The oblique implantation is, for example, oblique rotation ion implantation.

[0082] This oblique implantation forms a first region S1 on the second surface SS of the semiconductor substrate SUB. The first region S1 is formed to have the first portion S1a and the second portion S1b as described above.

[0083] 11 and 12. Then, as shown in FIG. 21, n-type impurities (e.g., arsenic) are ion-implanted into the semiconductor substrate SUB from the second surface SS side of the semiconductor substrate SUB. This ion implantation is performed under conditions where the dose of impurity ions is greater than that for forming the first region S1. This ion implantation is performed, for example, with an implantation energy of 10 keV or more and 40 keV or less, and a dose of 1.0×10 16 atoms / cm 2 Moreover, this ion implantation is performed in a state where the sidewall insulating film SW is located closer to the second surface SS than the first insulating film G1 of the gate insulating film GI.

[0084] As a result, a second region S2 is formed on the second surface SS of the semiconductor substrate SUB. The second region S2 is formed so as to be located on the second surface SS side with respect to the first region S1 and so as to be joined to the first region S1.

[0085] The second region S2 is formed so as to be located closer to the second surface SS than the upper end UE of the gate electrode GE. The second region S2 is formed so as to have a higher n-type impurity concentration than the n-type impurity concentration of the first region S1. The second region S2 is formed so that the junction between the first region S1 and the second region S2 is located closer to the second surface SS than the upper end UE of the gate electrode GE. For example, the second region S2 is formed so that a portion CN1 of the junction between the first region S1 and the second region S2, which is in contact with the sidewall of the trench TR, is located closer to the second surface SS than a portion UE1 of the upper end UE of the gate electrode GE that is closest to portion CN1.

[0086] Thereafter, similarly to the first embodiment, an interlayer insulating layer IL, a conductive layer PL, a source electrode SE, a drain electrode DE, an insulating film PF, etc. are formed, thereby manufacturing the semiconductor device of this embodiment.

[0087] <Effects> Next, the effects of this embodiment will be described.

[0088] 19, in this embodiment, the second portion S1b extends along the sidewall of the trench TR toward the first face FS more than the first portion S1a. This suppresses the occurrence of an offset between the n-type source region SR and the gate electrode GE. This makes it possible to prevent variations such as a sudden increase in the threshold voltage of the field-effect transistor.

[0089] 20, in this embodiment, the first region S1 is formed along the sidewall of the trench TR by obliquely implanting impurity ions before forming the sidewall insulating film SW. This makes it possible to form the first region S1 to a deep position on the first surface FS side with low implantation energy. This makes it possible to suppress implantation variations during ion implantation.

[0090] (Variation) Next, the configuration of a semiconductor device according to a modified example will be described with reference to FIG.

[0091] 22, a tapered portion TP may be provided on the sidewall of the trench TR at a connection portion with the second surface SS. The tapered portion TP is inclined so as to increase the opening dimension of the trench TR. The tapered portion TP is covered with the second insulating film G2 of the gate insulating film GI. The tapered portion TP is also covered with the sidewall insulating film SW with the second insulating film G2 interposed therebetween.

[0092] The configuration of the modified example other than that described above is almost the same as that of the first embodiment, so the same elements are given the same reference numerals and the description thereof will not be repeated.

[0093] Also in the second embodiment, the tapered portion TP may be provided similarly to the above-described modified example.

[0094] The invention made by the inventor has been specifically described above based on an embodiment, but it goes without saying that the present invention is not limited to the above embodiment and can be modified in various ways without departing from the gist of the invention. [Explanation of symbols]

[0095] BR p-type base region, CH contact hole, CN1, PN1, UE1 part, DE drain electrode, DR n + Drain region, DRI n-type drift region, EP edge, FS first surface, G1 first insulating film, G2 second insulating film, PL conductive layer, GE gate electrode, GI gate insulating film, IL interlayer insulating layer, LE bottom edge, OP opening, PF, SWI insulating films, S1 first region, S1a first part, S1b second part, S2 second region, SE source electrode, SR n-type source region, SS second surface, SUB semiconductor substrate, SW sidewall insulating film, TP tapered part, TR trench, UE top edge.

Claims

1. a semiconductor substrate having a first surface, a second surface opposite to the first surface, and a trench extending from the second surface toward the first surface; a gate electrode disposed in the trench with a gate insulating film interposed therebetween; a source region disposed within the semiconductor substrate; the gate electrode has a lower end located at a bottom of the trench and an upper end opposite to the lower end, the upper end being located closer to the first surface than the second surface; the source region has a first region having a first concentration and a second region having a second concentration higher than the first concentration; the first region has a portion located closer to the first surface than the upper end of the gate electrode, the second region is located on the second surface side of the upper end of the gate electrode, the first region has a first portion located away from the groove and a second portion extending along a sidewall of the groove toward the first surface beyond the first portion, A semiconductor device, wherein a depth of the second portion from a junction between the first region and the second region to a bottom surface of the second portion is greater than a depth of the first portion from the junction between the first region and the second region to a bottom surface of the first portion.

2. The semiconductor device according to claim 1 , further comprising a sidewall insulating film disposed along a sidewall of said trench on said second surface side of said gate insulating film.

3. 2. The semiconductor device according to claim 1, wherein an end of said second portion on said first surface side is located closer to said first surface than said upper end of said gate electrode.

4. A semiconductor device as described in claim 1, wherein the first region is bonded to the entire bottom surface of the second region.

5. providing a semiconductor substrate having a first surface, a second surface opposite to the first surface, and a trench extending from the second surface toward the first surface; forming a gate electrode in the trench with a gate insulating film interposed therebetween, the gate electrode having a lower end located at the bottom of the trench and an upper end facing the lower end and located closer to the first surface than the second surface; forming a first region of a source region by obliquely implanting impurity ions into the semiconductor substrate; forming a sidewall insulating film along a sidewall of the trench on the second surface side of the gate insulating film after the step of forming the first region; after the step of forming the sidewall insulating film, implanting impurity ions into the semiconductor substrate in a direction perpendicular to the second surface with the sidewall insulating film in place to form a second region of the source region, the first region has a portion located closer to the first surface than the upper end of the gate electrode and has a first concentration; The second region is located on the second surface side of the upper end of the gate electrode and has a second concentration higher than the first concentration.

6. 6. The method for manufacturing a semiconductor device according to claim 5, wherein the step of forming the first region includes the step of implanting impurity ions into the semiconductor substrate with the sidewall insulating film in place.

7. an implantation energy of the impurity ions for forming the second region is lower than an implantation energy of the impurity ions for forming the first region; 7. The method for manufacturing a semiconductor device according to claim 6, wherein a dose of impurity ions for forming said second region is greater than a dose of impurity ions for forming said first region.

8. 6. The method for manufacturing a semiconductor device according to claim 5, wherein a dose of impurity ions for forming said second region is greater than a dose of impurity ions for forming said first region.

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