Semiconductor device manufacturing method

Abstract

To provide a manufacturing method for semiconductor device that prevents what is called glue remaining of an adhesive on a semiconductor wafer when an adhesive tape covering an outer peripheral end edge of the semiconductor wafer is peeled off after a plating growth process.SOLUTION: A manufacturing method for semiconductor device comprises:a stage of forming a first electrode layer on a wafer top surface; a stage of injecting heavy ions of elements of the third period or above in an outer peripheral region on the wafer top surface; a stage of forming an oxide film in the outer peripheral region where the heavy ions are injected; and a process of forming a second electrode layer on the first electrode layer by plating. The dosage of the heavy ions is 1E15 cm-2 or larger, the injection flying depth of the heavy ions into the wafer is 0.02 μm or larger, and the heavy ions are As, P or Ar ions.SELECTED DRAWING: Figure 4B

Description

[Technical Field]

[0001] The present invention relates to a method for manufacturing a semiconductor device. [Background technology]

[0002] Patent Document 1 describes that the outer peripheral edge of a semiconductor wafer is covered to provide electrical insulation, thereby creating an insulating portion necessary for electroless nickel plating. [Prior art document] [Patent documents] [Patent Document 1] JP 2011-219503 A Summary of the Invention [Problem to be solved by the invention]

[0003] Thus, when the adhesive tape covering the outer peripheral edge of the semiconductor wafer is peeled off after the plating growth step, there is a problem that the adhesive remains on the semiconductor wafer (so-called "adhesive residue"). [Means for solving the problem]

[0004] In a first aspect of the present invention, a method for manufacturing a semiconductor device includes the steps of forming a first electrode layer on a front surface of a wafer, implanting heavy ions of elements of the third period or higher into a peripheral region of the front surface of the wafer, forming an oxide film in the peripheral region into which the heavy ions have been implanted, and forming a second electrode layer on the first electrode layer by plating. step The present invention provides a method for manufacturing a semiconductor device comprising the steps of:

[0005] heavy The ion dose is 1E15cm -2 It may be more than that.

[0006] The implantation depth of the heavy ions into the wafer may be 0.02 μm or greater.

[0007] The heavy ions may be As, P or Ar ions.

[0008] The thickness of the oxide film may be 8 nm or more and 50 nm or less.

[0009] The step of forming the oxide film may include the step of irradiating the front surface of the wafer with plasma, where irradiating the front surface of the wafer with plasma includes exposing the front surface of the wafer to plasma.

[0010] The manufacturing method may further include a step of forming a resist on the first electrode layer before the step of forming the oxide film, and the resist may be removed by irradiating with plasma.

[0011] The upper surface of the first electrode layer exposed by removing the resist may be subjected to descum treatment by irradiating with plasma.

[0012] The resist may have a thickness of 2 μm or more.

[0013] The manufacturing method may further include a step of forming a passivation film on the first electrode layer before the step of forming the resist, and the resist may be formed on the front surface of the wafer inside the passivation film.

[0014] The manufacturing method involves forming the second electrode layer by plating. step Before the step of (2), a step of attaching a protective tape to the back surface of the wafer may be further included.

[0015] The diameter of the protective tape may be larger than the diameter of the wafer.

[0016] The manufacturing method involves forming the second electrode layer by plating. step The method may further comprise a step of covering the outer peripheral region with a protective tape before the step (a).

[0017] The second electrode layer is formed by plating. step In the step, the wafer may be immersed in the plating solution with the outer peripheral region exposed.

[0018] The first electrode layer may be Al—Si and the second electrode layer may be Ni / Au.

[0019] The above summary of the invention does not list all of the features of the present invention, and subcombinations of these features may also be inventions. [Brief explanation of the drawings]

[0020] [Figure 1] 1 is a cross-sectional view showing an example of a semiconductor device 100 manufactured by a semiconductor device manufacturing method according to an embodiment. [Figure 2] 1A and 1B are a schematic view and a cross-sectional view of an example of a wafer to which a semiconductor device manufacturing method according to an embodiment is applied, taken along the radial direction of the wafer in an outer peripheral region 6. FIG. [Figure 3A] 3A to 3C are cross-sectional views illustrating an example of a wafer in each step of a method for manufacturing a semiconductor device according to an embodiment. [Figure 3B] 3A to 3C are cross-sectional views illustrating an example of a wafer in each step of a method for manufacturing a semiconductor device according to an embodiment. [Figure 3C] 3A to 3C are cross-sectional views illustrating an example of a wafer in each step of a method for manufacturing a semiconductor device according to an embodiment. [Figure 3D] 3A to 3C are cross-sectional views illustrating an example of a wafer in each step of a method for manufacturing a semiconductor device according to an embodiment. [Figure 3E] 3A to 3C are cross-sectional views illustrating an example of a wafer in each step of a method for manufacturing a semiconductor device according to an embodiment. [Figure 3F] 3A to 3C are cross-sectional views illustrating an example of a wafer in each step of a method for manufacturing a semiconductor device according to an embodiment. [Figure 3G] 3A to 3C are cross-sectional views illustrating an example of a wafer in each step of a method for manufacturing a semiconductor device according to an embodiment. [Figure 3H] 3A to 3C are cross-sectional views illustrating an example of a wafer in each step of a method for manufacturing a semiconductor device according to an embodiment. [Figure 3I] 3A to 3C are cross-sectional views illustrating an example of a wafer in each step of a method for manufacturing a semiconductor device according to an embodiment. [Figure 3J] 3A to 3C are cross-sectional views illustrating an example of a wafer in each step of a method for manufacturing a semiconductor device according to an embodiment. [Figure 4A]FIG. 10 is a flow chart showing an example of a method for manufacturing a semiconductor device according to a comparative example. [Figure 4B] FIG. 1 is a flow chart showing an example of a method for manufacturing a semiconductor device according to an embodiment. [Figure 5] FIG. 10 is a diagram comparing adhesive residue occurrence rates in the peripheral region of a wafer. DETAILED DESCRIPTION OF THE INVENTION

[0021] The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the scope of the invention according to the claims. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0022] FIG. 1 is a cross-sectional view showing an example of a semiconductor device 100 manufactured by a semiconductor device manufacturing method according to an embodiment. The semiconductor device 100 may be an insulated gate field effect transistor (MOSFET: Metal Oxide Semiconductor Field Effect Transistor), an insulated gate bipolar transistor (IGBT: Insulated Gate Bipolar Transistor), a free wheel diode (FWD: Free Wheel Diode), a reverse conducting insulated gate bipolar transistor (RC-IGBT: Reverse Conducting IGBT) having all of these functions, or the like. As an example, the semiconductor device 100 shown in FIG. 1 is an RC-IGBT. The semiconductor device 100 includes a semiconductor substrate having a transistor section 70 including an IGBT as a transistor element and a diode section 80 including an FWD as a diode element.

[0023] 1 is a cross section in the trench arrangement direction passing through the emitter region 12, the base region 14, the gate trench portion 40, and the dummy trench portion 30. In the cross section shown in FIG. 1, the semiconductor device 100 of this example has a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, and a collector electrode 24.

[0024] The interlayer insulating film 38 is provided on the front surface 21 of the semiconductor substrate 10. The interlayer insulating film 38 is an insulating film such as silicate glass doped with impurities such as boron or phosphorus. The interlayer insulating film 38 may be in contact with the front surface 21, or another film such as an oxide film may be provided between the interlayer insulating film 38 and the front surface 21. A contact hole 54 is provided to penetrate the interlayer insulating film 38.

[0025] The emitter electrode 52 is provided on the front surface 21 of the semiconductor substrate 10 and on the upper surface of the interlayer insulating film 38. The emitter electrode 52 is electrically connected to the front surface 21 through a contact hole 54 in the interlayer insulating film 38. A plug (not shown) made of tungsten (W) or the like may be embedded inside the contact hole 54 via a barrier metal film.

[0026] The collector electrode 24 is provided on the rear surface 23 of the semiconductor substrate 10. The emitter electrode 52 and the collector electrode 24 are formed of a material containing a metal or a laminated film thereof.

[0027] The semiconductor substrate 10 may be a silicon substrate, a silicon carbide substrate, a nitride semiconductor substrate such as gallium nitride, etc. The semiconductor substrate 10 in this example is a silicon substrate.

[0028] The semiconductor substrate 10 has a drift region 18 of a first conductivity type. In this example, the drift region 18 is N-type. The drift region 18 may be a remaining region of the semiconductor substrate 10 without other doped regions being provided therein.

[0029] One or more accumulation regions 16 may be provided in the Z-axis direction above the drift region 18. The accumulation region 16 is a region in which the same dopant as the drift region 18 accumulates at a higher concentration than the drift region 18. The doping concentration of the accumulation region 16 is higher than the doping concentration of the drift region 18.

[0030] The accumulation region 16 in this example is N-type. The accumulation region 16 may be provided only in the transistor section 70, or may be provided in both the transistor section 70 and the diode section 80. By providing the accumulation region 16, the carrier injection enhancement effect (IE effect) can be enhanced, and the on-voltage can be reduced.

[0031] In the transistor section 70, an emitter region 12 is provided above the base region 14 in contact with the front surface 21. The emitter region 12 is provided in contact with the gate trench section 40. The doping concentration of the emitter region 12 is higher than the doping concentration of the drift region 18. Examples of dopants for the emitter region 12 include arsenic (As), phosphorus (P), and antimony (Sb).

[0032] The diode section 80 is provided with a base region 14 exposed on the front surface 21. The base region 14 of the diode section 80 operates as an anode.

[0033] A buffer region 20 of the first conductivity type may be provided below the drift region 18. In this example, the buffer region 20 is N-type. The doping concentration of the buffer region 20 is higher than the doping concentration of the drift region 18. The buffer region 20 may function as a field stop layer that prevents a depletion layer extending from the lower surface side of the base region 14 from reaching the collector region 22 and the cathode region 82.

[0034] In the transistor section 70, a collector region 22 is provided below the buffer region 20. The collector region 22 may be provided in contact with the cathode region 82 on the back surface 23.

[0035] In the diode section 80, a cathode region 82 is provided below the buffer region 20. The cathode region 82 may be provided at the same depth as the collector region 22 of the transistor section 70. The diode section 80 may function as a freewheeling diode (FWD) that conducts a freewheeling current in the reverse direction when the transistor section 70 is turned off.

[0036] The semiconductor substrate 10 is provided with a gate trench portion 40 and a dummy trench portion 30. The gate trench portion 40 and the dummy trench portion 30 are provided so as to pass from the front surface 21 through the base region 14 and the accumulation region 16 to reach the drift region 18. The trench portion passing through the doped region is not limited to a case where the trench portion is formed after the doped region is formed. A case where the doped region is formed between the trench portions after the trench portions are formed is also included in the case where the trench portion passes through the doped region.

[0037] The gate trench portion 40 has a gate trench provided on the front surface 21, a gate insulating film 42, and a gate conductive portion 44. The gate insulating film 42 is provided to cover the inner wall of the gate trench. The gate insulating film 42 may be formed of an oxide film or a nitride film. The gate conductive portion 44 is provided so as to fill the inside of the gate trench more inward than the gate insulating film 42. The upper surface of the gate conductive portion 44 may be in the same plane as the front surface 21. The gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is formed of impurity-doped polysilicon or the like.

[0038] The gate conductive portion 44 may be provided to be longer in the depth direction than the base region 14. The gate trench portion 40 is covered on the front surface 21 with an interlayer insulating film 38. When a predetermined voltage is applied to the gate conductive portion 44, a channel is formed by an electron inversion layer in the surface layer of the base region 14 at the interface that contacts the gate trench.

[0039] The dummy trench portion 30 may have the same structure as the gate trench portion 40 in a cross section in the trench arrangement direction. The dummy trench portion 30 has a dummy trench, a dummy insulating film 32, and a dummy conductive portion 34 provided on the front surface 21. The dummy insulating film 32 is provided to cover the inner wall of the dummy trench. The dummy insulating film 32 may be formed of an oxide film or a nitride film. The dummy conductive portion 34 is provided so as to fill the inside of the dummy trench further inside than the dummy insulating film 32. The upper surface of the dummy conductive portion 34 may be located in the same XY plane as the front surface 21. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The dummy conductive portion 34 may be formed of the same material as the gate conductive portion 44.

[0040] In this example, the gate trench portion 40 and the dummy trench portion 30 are covered on the front surface 21 with an interlayer insulating film 38. The bottoms of the dummy trench portion 30 and the gate trench portion 40 may have a downwardly convex curved shape (a curved shape in cross section).

[0041] In the trench arrangement direction, mesa portions are provided between the trench portions. The mesa portion refers to a region sandwiched between the trench portions inside the semiconductor substrate 10. As an example, the depth position of the mesa portion is from the front surface 21 of the semiconductor substrate 10 to the bottom end of the trench portion.

[0042] The mesa portion in this example is sandwiched between adjacent trench portions in the trench arrangement direction, and is provided on the front surface 21 of the semiconductor substrate 10, extending in the extension direction (Y-axis direction) along the trench portions. In this example, the transistor portion 70 is provided with a mesa portion 60, and the diode portion 80 is provided with a mesa portion 61. In this specification, the mesa portion simply referred to as a mesa portion refers to both the mesa portion 60 and the mesa portion 61.

[0043] Each mesa portion is provided with a base region 14. In each mesa portion, at least one of a first conductivity type emitter region 12 and a second conductivity type contact region (not shown) may be provided in a region sandwiched between the base regions 14 in a top view. In this example, the emitter region 12 is N+ type, and the contact region is P+ type. The emitter region 12 and the contact region may be provided between the base region 14 and the front surface 21 of the semiconductor substrate 10 in the depth direction.

[0044] The mesa portion of the transistor section 70 has an emitter region 12 exposed on the front surface 21 of the semiconductor substrate 10. The emitter region 12 is provided in contact with the gate trench portion 40. The mesa portion in contact with the gate trench portion 40 has a contact region exposed on the front surface 21 of the semiconductor substrate 10.

[0045] The contact regions and emitter regions 12 in the mesa portion are each provided from one trench portion to the other trench portion in the trench arrangement direction. As an example, the contact regions and emitter regions 12 in the mesa portion are alternately arranged along the trench extension direction.

[0046] In another example, the contact region and emitter region 12 of the mesa portion may be provided in a stripe pattern along the trench extension direction. For example, the emitter region 12 is provided in a region in contact with the trench portion, and the contact region is provided in a region sandwiched between the emitter regions 12.

[0047] The mesa portion of the diode portion 80 does not have an emitter region 12. A base region 14 may be provided on the upper surface of the mesa portion of the diode portion 80. The base region 14 may be disposed over the entire mesa portion of the diode portion 80.

[0048] A contact hole 54 is provided above each mesa portion. The contact holes 54 are arranged in a region sandwiched between the base regions 14 in the extension direction. In this example, the contact holes 54 are provided above the contact regions, the base regions 14, and the emitter regions 12. The contact holes 54 may be arranged in the center in the arrangement direction of the mesa portions.

[0049] In the diode section 80, an N+ type cathode region 82 is provided in a region adjacent to the back surface 23 of the semiconductor substrate 10. A P+ type collector region 22 may be provided in a region of the back surface 23 of the semiconductor substrate 10 where the cathode region 82 is not provided. In FIG. 1, the boundary between the cathode region 82 and the collector region 22 is indicated by a dotted line.

[0050] FIG. 2 is a schematic diagram showing an example of a wafer to which a semiconductor device manufacturing method according to an embodiment of the present invention is applied, and a cross-sectional view of an outer peripheral region 6 along the wafer radial direction. The wafer 1 of this example has a central region 2 having an element structure provided on its front surface 21, and an outer peripheral region 6 surrounding the central region 2. The element structure provided in the central region 2 constitutes the semiconductor device 100 described in FIG. 1. Therefore, the wafer 1 corresponds to the semiconductor substrate 10 of FIG. 1. Elements of the wafer 1 of this example that are common to elements of the semiconductor device 100 will be described using the same reference numerals. However, structures such as the emitter region 12, base region 14, and gate trench portion 40 provided inside the semiconductor substrate 10 (wafer 1) are omitted in FIG. 2.

[0051] In the central region 2, a first electrode layer 3 is provided on the front surface 21, and a second electrode layer 4 is formed on the first electrode layer 3 by plating. The first electrode layer 3 is made of Al, Al-Si, Al-Si-Cu, Al-Cu, or the like. In this example, the first electrode layer 3 is Al-Si. The first electrode layer 3 has a thickness of 1.0 μm to 6.0 μm.

[0052] The second electrode layer 4 is formed of a solder bonding material and bonds the first electrode layer 3 to an external connection terminal. In this example, the second electrode layer 4 is Ni / Au, in which an Au layer is stacked on a Ni layer. The second electrode layer 4 may be formed by electroless plating. The first electrode layer 3 and the second electrode layer 4 constitute an emitter electrode 52 of the semiconductor device 100.

[0053] The passivation film 5 is provided on the front surface 21 of the wafer 1 and the first electrode layer 3 in the central region 2. The passivation film 5 may be any insulating film that adheres closely to the wafer 1 and the first electrode layer 3, and in one example is made of SiN, SiO2, polyimide, or the like. In this example, the passivation film 5 is a polyimide film. The passivation film 5 has a thickness of 5 μm to 10 μm.

[0054] The passivation film 5 has an opening that exposes the second electrode layer 4. Furthermore, the passivation film 5 provided above an element structure is separated from the passivation film 5 provided above an adjacent element structure. In this example, the outermost periphery of the passivation film 5 when viewed from above the wafer 1 is set as the boundary between the central region 2 and the peripheral region 6.

[0055] The peripheral region 6 is the region between the central region 2 and the edge 7. The edge 7 is the boundary between the front surface 21 and the back surface 23 of the wafer 1, and extends circularly along the periphery of the wafer 1. In the peripheral region 6, an oxide film 8 is provided on the front surface 21 of the wafer 1. In this example, the oxide film 8 is formed by performing plasma processing on the ion-implanted wafer 1. The heavy ions implanted to form the oxide film 8 in this example are heavy ions of elements in the third period or higher, and in one example, are As, P, or Ar ions. The thickness of the oxide film 8 in this example is 8 nm or more and 50 nm or less.

[0056] A collector electrode 24 is provided on the back surface 23 of the wafer 1. In this example, the collector electrode 24 has a laminated structure of Al / Ti / Ni / Au, in this order from the back surface 23 side. Alternatively, the collector electrode 24 may have a laminated structure of Al-Si / Ti / Ni / Au, Ti / Ni / Au, Al / Ti / Ni / Ag, Al-Si / Ti / Ni / Ag, Al / Ti / NiV / Au, Al-Si / Ti / NiV / Au, Al / Ti / NiV / Ag, Al-Si / Ti / NiV / Ag, Ti / NiV / Ag, or the like, in this order from the back surface 23 side. In this example, the collector electrode 24 is provided over substantially the entire back surface 23, but it may also be provided only in the region corresponding to the element structure, i.e., the central region 2.

[0057] 3A to 3J are cross-sectional views showing an example of a wafer at each step of a manufacturing method of a semiconductor device according to an embodiment. Similar to FIG. 2, FIGS. 3A to 3J show cross-sectional views along the wafer radial direction of the outer circumferential region 6. Here, the description will focus on the step of forming an oxide film 8 in the outer circumferential region 6 on the front surface 21 of the wafer 1 and the step of forming a second electrode layer 4 by plating on the first electrode layer 3 in the central region 2.

[0058] 3A shows wafer 1 that has undergone the steps of forming first electrode layer 3 on front surface 21 of wafer 1 and forming passivation film 5 on first electrode layer 3. First electrode layer 3 is formed by depositing Al-Si to a thickness of 1.0 μm to 6.0 μm.

[0059] In one example, the process of forming the passivation film 5 includes the steps of applying polyimide to the front surface 21 of the wafer 1, removing the polyimide that has spread to the peripheral region 6 and the back surface 23 by edge rinsing, and curing the polyimide applied to the central region 2. The edge rinsing may be performed in a range 2.5 mm wide along the edge 7. The passivation film 5 may be formed to extend beyond the element structure in a top view of the wafer 1, to the extent that the applied polyimide does not spread to the back surface 23.

[0060] Here, since the passivation film 5 is not formed in the peripheral region 6, the silicon of the wafer 1 is exposed on the front surface 21 of the wafer 1. The step of forming the collector electrode 24 on the back surface 23 of the wafer 1 may be performed before or after the step of forming the first electrode layer 3 and the passivation film 5.

[0061] 3B shows the wafer 1 after a step of forming a resist 9 on the first electrode layer 3. In one example, the resist 9 is formed by dropping and spin-coating a resist onto the front surface 21 of the wafer 1, and then dissolving and removing the resist in areas where the resist 9 is not to be formed by edge rinsing with an organic solvent. Alternatively, the resist 9 may be formed by exposing or not exposing a photosensitive resist spin-coated onto the front surface 21 of the wafer 1, and then removing the resist in areas where the resist 9 is not to be formed with a developer.

[0062] In this example, the resist 9 may be formed over the entire central region 2 of the wafer 1 in a top view, i.e., in the same range as the passivation film 5, or may be formed in a range inside the outer periphery of the passivation film 5. In other words, the resist 9 is not formed in the outer periphery region 6. This is because, if the resist 9 is formed on the front surface 21 of the wafer 1 in the outer periphery region 6, the formation of the oxide film 8 in that region will be hindered in the oxide film formation step described below.

[0063] The resist 9 in this example has a thickness that is five times or more the depth of the range of ions implanted into the resist 9 in the ion implantation step described below. In one example, the thickness of the resist 9 is 2 μm or more. This prevents the implanted ions from penetrating through the resist 9 in the ion implantation step described below.

[0064] FIG. 3C shows wafer 1 after undergoing a step of implanting heavy ions of elements of the third period or higher into peripheral region 6. In one example, the heavy ions are As, P, or Ar ions. In this example, As ions are implanted. The As ions may be implanted over the entire front surface 21 of wafer 1, or may be implanted only into peripheral region 6. The implantation of ionized impurity elements forms crystal defects in the silicon of wafer 1 exposed in peripheral region 6, but by implanting heavy ions with a large mass, an oxide film 8 with a uniform thickness is formed in the oxide film formation step described below.

[0065] In this example, the dose of heavy ions is 1E15 cm -2 This is the end. As a result, crystal defects are reliably formed even in the edge portion 7 where ions are difficult to implant. The implantation range depth of the heavy ions into the wafer 1 may be 0.02 μm or more, and the acceleration energy may be 20 keV to 30 keV. As a result, the implanted ions do not penetrate the resist 9 in the central region 2, and crystal defects are formed in the silicon of the wafer 1 in the peripheral region 6.

[0066] 3D and 3E show wafer 1 undergoing a plasma treatment process on front surface 21. In this example, by irradiating front surface 21 of wafer 1 with O radicals, the peripheral region 6 into which heavy ions have been implanted is selectively plasma oxidized, as shown in FIG. 3D, and an oxide film 8 grows. In this example, the thickness of oxide film 8 is 8 nm or more and 50 nm or less.

[0067] On the other hand, by irradiating the front surface 21 of the wafer 1 with O radicals, the resist 9 is ashed (ashed) and disappears in the central region 2, as shown in Fig. 3E. In other words, the process of forming the oxide film 8 by the plasma treatment in this example also serves as ashing of the resist 9.

[0068] The upper surface of the first electrode layer 3 exposed by removing the resist 9 may be subjected to a descum treatment by irradiating it with plasma. The descum treatment is a treatment for removing residues such as carbon before the plating growth step described below. In other words, the step of forming the oxide film 8 by plasma treatment in this example may also serve as a descum treatment for the first electrode layer 3.

[0069] FIG. 3F shows the wafer 1 after a step of attaching a protective tape 90 to the back surface 23 of the wafer 1. The protective tape 90 protects the collector electrode 24 provided on the back surface 23 of the wafer 1 from the plating solution in the plating growth step described below. In one example, the protective tape 90 has a structure in which a base material 91 and an adhesive 92 are laminated. The diameter of the protective tape 90 is larger than the diameter of the wafer 1. The protective tape 90 may cover the entire back surface 23 of the wafer 1. In this example, the next plating growth step is performed with the outer circumferential region 6 of the front surface 21 exposed and not covered by the protective tape 90.

[0070] 3G to 3H show wafer 1 undergoing a plating growth process. Wafer 1, with protective tape 90 attached to rear surface 23, is immersed in plating solution 95. In the actual plating growth process, wafer 1 is immersed in multiple plating tanks for pre-treatment and post-treatment, but for simplicity, only one plating tank is shown in FIGS. 3G to 3H.

[0071] A Ni film is formed on the first electrode layer 3 by electroless plating. Then, the wafer 1 is immersed in a post-treatment bath, and an Au film is grown by immersion to prevent oxidation of the Ni film. This results in the formation of a Ni / Au second electrode layer 4, as shown in FIG. 3H. The plating growth step, the protective tape application step performed before the plating growth step, and the protective tape peeling step (described below) performed after the plating growth step may be collectively referred to as the plating process.

[0072] In the plating growth process, a small amount of plating metal is formed on the conductive material due to the reduction reaction of the plating solution 95. Therefore, if the silicon of the wafer is exposed, plating metal is formed in that area. Such unintentionally generated plating metal has low adhesion to the substrate, so it peels off and remains in the plating solution 95, causing localized plating failure or re-adhering to the wafer and causing device malfunction.

[0073] In the present example, the wafer 1 has an oxide film 8 on the front surface 21 in the peripheral region 6, so that the silicon of the wafer 1 is not exposed even in the peripheral region 6 where the passivation film 5 is not provided. In this way, it is possible to prevent unintended formation of plated metal in the peripheral region 6.

[0074] 3I shows wafer 1 removed from plating solution 95, and FIG. 3J shows wafer 1 after the step of removing protective tape 90. Adhesive 92 of protective tape 90 has a stronger adhesive strength to substrate 91 than to metals and oxides. Therefore, when protective tape 90 covering collector electrode 24 is removed, adhesive 92 peels off from collector electrode 24 while remaining in close contact with substrate 91.

[0075] However, the adhesive 92 of the protective tape 90 has a stronger adhesive force to silicon than to the substrate 91. Therefore, if the protective tape 90 is applied to an area of ​​the wafer where the silicon is exposed, peeling the protective tape 90 will cause the adhesive 92 to peel off from the substrate 91 and remain in contact with the silicon, resulting in so-called adhesive residue. This adhesive residue may cause problems in subsequent steps of the plating process, such as the wafer sticking to a stage, a transfer arm, or the like.

[0076] In the present example, the wafer 1 has an oxide film 8 provided in the outer peripheral region 6 of the front surface 21, and therefore there is no need to cover the outer peripheral region 6 with protective tape 90 to protect it from the plating solution 95. Alternatively, the outer peripheral region 6 of the front surface 21 may be covered with protective tape 90 before the plating growth step is performed on the wafer 1. Even if the protective tape 90 is attached to the outer peripheral region 6 of the front surface 21, the oxide film 8 is provided in the outer peripheral region 6, and the adhesive force of the adhesive 92 to the oxide film 8 is low, so there is no risk of adhesive residue remaining after the protective tape 90 is peeled off.

[0077] 4A is a flow diagram showing an example of a method for manufacturing a semiconductor device according to a comparative example. Here, the plating process for forming a second electrode layer 4 on a first electrode layer 3 will be mainly described. The wafer used in the comparative example differs from wafer 1 according to the example in that it does not have an oxide film 8. However, since the wafer used in the comparative example has a structure similar to wafer 1 according to the example in other respects, elements common to wafer 1 will be described as having the same elements with the same reference numerals. In step S100, front surface 21 of the wafer that has undergone the previous process is descummed by irradiating it with O2 plasma.

[0078] In step S110, protective tape 90 is applied to the back surface 23 of the wafer, and in step S120, protective tape 90 is further applied to the edge 7 of the wafer. The protective tape 90 applied to the edge 7 covers the front surface 21 and the outer circumferential region 6 of the back surface 23, with the edge 7 of the wafer as the center. In other words, the protective tape 90 applied to the edge 7 covers the silicon of the wafer exposed in the outer circumferential region 6 of the front surface 21, thereby protecting the outer circumferential region 6 from the plating solution 95 in the subsequent plating growth step. Note that the order of steps S110 and S120 may be reversed, and the protective tape 90 covering the edge 7 may be superimposed on the protective tape 90 covering the back surface 23, or vice versa.

[0079] In step S130, the wafer is immersed in plating solution 95 and subjected to a plating growth process. In step S140, protective tape 90 is peeled off from edge 7 of the wafer, and in step S150, protective tape 90 is peeled off from back surface 23 of the wafer. Because peripheral region 6 and back surface 23 of the wafer were protected by protective tape 90 during the plating growth process, Ni plating does not grow in these areas, and second electrode layer 4 is formed only on first electrode layer 3. The wafer that has undergone the plating process undergoes the next process to form the final semiconductor device 100.

[0080] 4B is a flow diagram showing an example of a method for manufacturing a semiconductor device according to an embodiment. As with the comparative example described in FIG. 4A, differences from the comparative example will be mainly described in relation to the plating process. In step S200, a resist 9 is formed on the front surface 21 of the wafer 1 that has undergone the previous process. The resist 9 is formed on the first electrode layer 3 provided in the central region 2 of the front surface 21.

[0081] In step S210, heavy ions of an element of the third period or higher are implanted into the peripheral region 6 of the front surface 21 of the wafer 1. In one example, the heavy ions are As, P, or Ar ions, and in this example, As ions are implanted. The dose of the heavy ions is 1E15 cm -2 The implantation range depth of the heavy ions into the wafer 1 may be 0.02 μm or more, and the acceleration energy may be 20 keV to 30 keV.

[0082] In step S220, a plasma treatment process is performed on front surface 21 of wafer 1. In this example, by irradiating front surface 21 of wafer 1 with O radicals, the peripheral region 6 into which heavy ions have been implanted is selectively oxidized to grow an oxide film 8, and the resist 9 provided in central region 2 is removed by ashing, thereby performing a descum treatment on first electrode layer 3. The thickness of oxide film 8 formed here is equal to or greater than 8 nm and equal to or less than 50 nm.

[0083] That is, in the comparative example, the plasma treatment step is performed only for the descum treatment before the plating process (step S100), but in the embodiment, the plasma treatment step not only performs the descum treatment but also simultaneously performs the step of growing the oxide film 8 and the step of ashing and removing the resist 9. In this way, according to the embodiment, the process can be made more efficient.

[0084] In step S230, protective tape 90 is applied to the back surface 23 of the wafer. In step S240, the wafer 1 is immersed in a plating solution 95, and a plating growth process is performed. In step S250, protective tape 90 is peeled off from the back surface 23 of the wafer. After the plating process, the wafer is subjected to the next process to form the final semiconductor device 100.

[0085] Unlike the comparative example, the example does not include a step of attaching protective tape 90 to edge 7 before the plating growth step. That is, in the example, the plating growth step is performed on wafer 1 with outer periphery region 6 of front surface 21 exposed. In the example, since oxide film 8 is provided on outer periphery region 6 of front surface 21 of wafer 1, it is not necessary to protect with protective tape 90 during the plating growth step, and the step of attaching protective tape 90 to edge 7 (step S120) and the peeling step (step S140) in the comparative example can be omitted.

[0086] Alternatively, in the embodiment, a step of attaching protective tape 90 to edge 7 (step S120) and a peeling step (step S140) may be performed. In this case, protective tape 90 covers oxide film 8 in outer peripheral region 6 of front surface 21 of wafer 1. That is, in the comparative example, adhesive 92 of protective tape 90 adheres to the silicon of the wafer in outer peripheral region 6 of front surface 21 of wafer 1, whereas in the embodiment, adhesive 92 of protective tape 90 adheres to oxide film 8.

[0087] The adhesive 92 of the protective tape 90 has a stronger adhesive force to the silicon than to the substrate 91. Therefore, in the comparative example, when the protective tape 90 is peeled off (step S140), there is a risk that the adhesive 92 will peel off from the substrate 91 and remain adhered to the silicon, resulting in adhesive residue. On the other hand The adhesive 92 of the protective tape 90 has a stronger adhesive strength to the substrate 91 than to the metal and oxide. Therefore, in the embodiment, when the protective tape 90 covering the oxide film 8 is peeled off, the adhesive 92 peels off from the oxide film 8 while remaining in close contact with the substrate 91, and no adhesive residue is left. Thus, according to the embodiment, there is no risk of adhesive residue causing the wafer to stick to a stage, a transfer arm, or the like in subsequent steps of the plating process.

[0088] Figure 5 is a graph comparing the incidence of adhesive residue in the peripheral region of a wafer. Here, the incidence of adhesive residue in the peripheral region 6 of the front surface 21 is compared between a wafer subjected to the plating process according to the comparative example shown in Figure 4A and a wafer 1 subjected to the plating process according to the example shown in Figure 4B (including cases where protective tape application and peeling processes for the edge 7 were performed and where they were not performed). The incidence of adhesive residue is the percentage of wafers on which adhesive residue was confirmed after the plating process relative to the total number of wafers processed in the same process.

[0089] In the comparative example, the adhesive residue occurrence rate exceeded 70%, whereas in the example, the adhesive residue occurrence rate was 0%. Thus, according to the example, the occurrence of adhesive residue was prevented, and there was no risk of the wafer sticking to the stage, transfer arm, etc. in the subsequent steps of the plating process.

[0090] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the claims that such modifications and improvements can also be included within the technical scope of the present invention.

[0091] It should be noted that the execution order of each process, such as operations, procedures, steps, and stages, in the devices, systems, programs, and methods shown in the claims, specifications, and drawings is not specifically stated as "before," "prior to," etc., and that the processes can be performed in any order unless the output of a previous process is used in a subsequent process. Even if the operational flow in the claims, specifications, and drawings is described using "first," "next," etc. for convenience, this does not mean that the processes must be performed in this order. [Explanation of symbols]

[0092] REFERENCE SIGNS LIST 1 wafer, 2 central region, 3 first electrode layer, 4 second electrode layer, 5 passivation film, 6 peripheral region, 7 edge, 8 oxide film, 9 resist, 10 semiconductor substrate, 12 emitter region, 14 base region, 16 accumulation region, 18 drift region, 20 buffer region, 21 front surface, 22 collector region, 23 back surface, 24 collector electrode, 30 dummy transistor a contact hole; a mesa portion; a contact hole; a contact hole formed on the contact hole; a contact hole formed on the contact hole; a contact hole formed on the contact hole; a contact hole formed on the contact hole; a contact hole formed on the contact hole; a contact hole formed on the contact hole; a contact hole formed on the contact hole; a contact hole formed on the contact hole;

Claims

1. forming a first electrode layer on a front surface of the wafer; implanting heavy ions of elements from the third period or higher of the periodic table of the elements into an outer peripheral region of the front surface of the wafer; forming an oxide film on the outer peripheral region where the heavy ions are implanted; forming a second electrode layer on the first electrode layer by plating; A method for manufacturing a semiconductor device comprising:

2. The dose of the heavy ions is 1E15 cm －２ That's all The method for manufacturing a semiconductor device according to claim 1 .

3. The implantation depth of the heavy ions into the wafer is 0.02 μm or more.

3. The method for manufacturing a semiconductor device according to claim 1.

4. The heavy ions are As, P or Ar ions. The method for manufacturing a semiconductor device according to claim 1 .

5. The thickness of the oxide film is 8 nm or more and 50 nm or less. The method for manufacturing a semiconductor device according to claim 1 .

6. The step of forming the oxide film includes the step of irradiating plasma onto the front surface of the wafer. The method for manufacturing a semiconductor device according to claim 1 .

7. and forming a resist on the first electrode layer before forming the oxide film. The resist is removed by irradiation with the plasma. The method for manufacturing a semiconductor device according to claim 6 .

8. The upper surface of the first electrode layer exposed by removing the resist is descummed by irradiating the plasma. The method for manufacturing a semiconductor device according to claim 7 .

9. The thickness of the resist is 2 μm or more.

9. The method for manufacturing a semiconductor device according to claim 7.

10. The method further includes forming a passivation film on the first electrode layer before forming the resist, The resist is formed on the front surface of the wafer in a range inside the outer periphery of the passivation film. The method for manufacturing a semiconductor device according to any one of claims 7 to 9.

11. The method further includes the step of attaching a protective tape to the back surface of the wafer before the step of forming the second electrode layer by plating. The method for manufacturing a semiconductor device according to claim 1 .

12. The diameter of the protective tape is larger than the diameter of the wafer. The method for manufacturing a semiconductor device according to claim 11 .

13. The method further includes covering the outer periphery with a protective tape before forming the second electrode layer by plating. The method for manufacturing a semiconductor device according to claim 1 .

14. In the step of forming the second electrode layer by plating, the wafer is immersed in a plating solution with the outer peripheral region exposed. The method for manufacturing a semiconductor device according to claim 1 .

15. The first electrode layer is Al—Si, and the second electrode layer is Ni / Au. The method for manufacturing a semiconductor device according to claim 1 .

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