Method for fabricating field-effect transistors

Abstract

According to the present invention, a buffer layer (102) is formed in a substrate (101); a barrier layer (103) that is configured from a nitride semiconductor is formed on the buffer layer (102) so that the main surface of the barrier layer (103) has an N polarity (group V polarity); a channel layer (104) that is configured from a nitride semiconductor is subsequently formed on the barrier layer (103) so that the main surface of the channel layer (104) has an N polarity; an arsenide layer (122) is formed by subjecting a part of the channel layer (104) in the thickness direction in an electrode formation region (151) to arsenide conversion; and subsequently, the thus-formed arsenide layer (122) is removed by heating.

Description

[Technical Field]

[0001] The present invention relates to a field effect transistor. Ta's Regarding the manufacturing method. [Background technology]

[0002] A heterojunction field effect transistor (HFET), or high electron mobility transistor (HEMT), is a transistor that switches on and off by changing the carrier density in the channel layer using an electric field generated by a gate voltage.

[0003] When the above-mentioned transistors are constructed from nitride semiconductors such as GaN, for example, in an AlGaN / GaN heterojunction, a two-dimensional electron gas (2DEG) is often used, where electrons gather at the interface to compensate for the difference in polarization between the AlGaN layer and the GaN layer. In a typical Ga-polarity GaN HEMT (GaN-based HEMT), a gate electrode is formed on an AlGaN layer with a thickness of several nanometers to several tens of nanometers, and the 2DEG concentration at the AlGaN / GaN interface is controlled.

[0004] When considering high-frequency applications of GaN-based HEMTs, it is important to confine carriers to the thin region at the AlGaN / GaN interface and eliminate other leakage paths, which will speed up the response to voltage applied to the gate electrode and achieve stable operation.

[0005] GaN-based HEMTs are being developed for use in high-frequency devices, taking advantage of the high mobility of the 2DEG. However, Ga-polar HEMTs have problems with AlGaN, which has a large band gap, being placed on the device surface, such that (1) contact resistance is high, and (2) the AlGaN layer cannot be made thin to maintain carrier density, leading to short-channel effects.

[0006] These issues are hindering improvements in the high-frequency characteristics of GaN HEMTs. Techniques being considered to resolve these issues include (1) regrowth of the region directly under the ohmic electrodes, such as the source and drain electrodes, to reduce contact resistance, and (2) increasing the Al composition to make the AlGaN layer thinner to suppress the short-channel effect. However, there are limitations to how much ohmic contact resistance can be reduced.

[0007] N-polar GaN is a crystal obtained by inverting Ga-polar GaN, and it offers the following three advantages when fabricating HEMTs. First, it requires a high Al composition and a thickness of approximately 20 nm to supply carriers. The highly resistive AlGaN layer is located below the GaN channel layer and is not positioned between the ohmic electrode and the channel, which reduces contact resistance. Second, the thickness of the surface GaN layer does not significantly affect the carrier density, so it can be made thin to suppress the short-channel effect. Third, the AlGaN layer directly below the channel acts as a back barrier, suppressing the short-channel effect. Due to these advantages, fabricating HEMTs using N-polar GaN is expected to further improve the high-frequency characteristics of GaN HEMTs (Non-Patent Document 3).

[0008] Compared to Ga-polar GaN-HEMTs, N-polar GaN-HEMTs have the advantage of lowering contact resistance due to their epitaxial structure, but research is being conducted to further reduce contact resistance through processes. One such technique is to regrow n-type doped GaN in the region under the ohmic electrode. The GaN channel layer is not doped because impurities reduce the mobility of the 2DEG and degrade the performance of the electronic device.

[0009] Although the bandgap of GaN is smaller than that of AlGaN, it is still large among semiconductor materials, and therefore the resistance of undoped GaN is higher than that of other semiconductor materials. To reduce contact resistance without causing degradation of electronic device characteristics due to impurities, one technique is to etch only the region under the ohmic electrode in an undoped GaN channel layer and then regrow n-type doped GaN in this area to form a regrowth layer. This technique realizes a device structure in which the doped regrowth layer reduces contact resistance while maintaining high mobility in the channel portion under the gate electrode without being affected by doping.

[0010] Although the above-mentioned technology can reduce ohmic resistance, the following two issues remain to be resolved in order to further improve device characteristics.

[0011] First, there is a problem with using GaN. Although the regrown GaN is doped n-type, the fact remains that GaN with a large band gap is used, so when compared with other n-type semiconductors with similar doping concentrations, the contact resistance is higher than with other semiconductor materials. For example, when Si is doped at 1.5 x 10 18 cm -3 The contact resistance of doped n-type GaN is 1×10 -5 Ωcm 2 There is a report showing the degree of Si addition (Non-Patent Document 1). 18 cm -3 The contact resistance of doped n-type GaAs is 5 × 10 -7 Ωcm 2 There is also a report that states this (Non-Patent Document 2).

[0012] The Si doping concentration in the regrown GaN layer is limited to 10 18 cm -3 Therefore, the large band gap results in high contact resistance at the same doping concentration, which is an issue when using GaN as a material for the regrowth layer.

[0013] The second issue is the process. Regrowth requires etching the GaN channel layer once it has been grown. In this process, it is desirable to leave the 2DEG intact without completely etching the GaN, in order to ensure good contact between the 2DEG in the channel region and the regrowth layer. The 2DEG is located approximately 1 to 2 nm from the GaN / AlGaN interface below the channel layer. Therefore, in order to leave the 2DEG intact, etching must be performed to leave a thickness of approximately 5 nm of the channel layer. The channel layer is a thin layer, approximately 20 nm or less thick, and the required etching depth (thickness) is several nm to several tens of nm.

[0014] A large etching depth significantly reduces the carrier density of the 2DEG, while a small etching depth results in too much distance between the 2DEG and the regrowth layer. In either case, contact resistance increases, making it important to control the etching depth. Methods for controlling the etching depth include selective etching and controlling the etching time. However, in N-polarity GaN-based HEMTs, it is undesirable for the channel layer to contain layers composed of materials other than GaN in the unetched region under the gate electrode, so selective etching, which requires an etching stop layer, cannot be used. For this reason, etching depth control is primarily achieved by controlling the etching time.

[0015] However, in the case of reactive ion etching (ICP-RIE) using a chlorine-based gas plasma generated by inductive coupling, which is used for etching GaN, the etching rate is generally high, ranging from several dozen to several tens of nm / min. Therefore, in this etching process, a deviation in processing time of a few seconds can lead to an etching depth error of 1 nm or more, making it insufficient as a technology to reproducibly achieve the precision required for etching the above-mentioned regrowth layer.

[0016] Furthermore, the etched thin film must be exposed to the atmosphere before it can be introduced into a crystal growth furnace for regrowth. This exposure causes many impurities from the atmosphere to be adsorbed onto the surface before regrowth, and these impurities are then incorporated into the interface and regrowth layer, causing variations in doping concentration and resulting in unintended effects on device characteristics, such as fluctuations in contact resistance.

[0017] In recent years, atomic layer etching (ALE) technology using chlorine gas for etching GaN has been researched, and progress has been made in improving the controllability of etching depth. However, even in this case, exposure to the atmosphere after etching is unavoidable, and although wafer cleaning methods have been actively investigated, it is not possible to completely eliminate impurities from the atmosphere, and it is impossible to avoid unintended effects of atmospheric impurities on device characteristics. [Prior art documents] [Non-patent literature]

[0018] [Non-Patent Document 1] K. Hotta et al., "Annealing temperature dependence of alloy contact for N-polar GaN HEMT structure", Japanese Journal of Applied Physics, vol. 58, SCCD14, 2019. [Non-patent document 2] KS Chen et al., "A Cu-based alloyed Ohmic contact system on n-type GaAs", Applied Physics Letters, vol. 91, no. 23, 233511, 2007. [Non-patent document 3] MH Wong et al., "INVITED REVIEW N-polar GaN epitaxy and high electron mobility transistors", Semiconductor Science and Technology, vol. 28, 074009, 2013. [Non-patent document 4] S. Kolluri et al., "N-Polar GaN MIS-HEMTs With a 12.1-W / mm Continuous-Wave Output Power Density at 4 GHz on Sapphire Substrate", IEEE Electron Device Letters, vol. 32, no. 5, pp. 635-637, 2111. Summary of the Invention [Problem to be solved by the invention]

[0019] As mentioned above, reducing the contact resistance of ohmic electrodes in N-polar GaN-based HEMTs has had the following problems. First, the regrowth of n-type GaN alone is limited by the physical properties of GaN, restricting improvements in device characteristics. Furthermore, regrowth inevitably exposes the regrowth interface to the atmosphere, which can affect device characteristics due to impurities being incorporated into the regrowth interface and regrowth layer. Thus, reducing the contact resistance of ohmic electrodes in N-polar GaN-based HEMTs has traditionally been a problem that cannot be easily achieved.

[0020] The present invention has been made to solve the above problems, and has an object to easily achieve a reduction in the contact resistance of an ohmic electrode in an N-polarity GaN-based HEMT. [Means for solving the problem]

[0021] A method for fabricating a field-effect transistor according to the present invention includes the following steps: a first step of forming a barrier layer made of a nitride semiconductor on a substrate, the barrier layer having an N-polarity main surface; a second step of forming a channel layer made of a nitride semiconductor on the barrier layer, the channel layer having an N-polarity main surface; a third step of forming an As-doped layer by converting the channel layer to As at a location where an ohmic electrode will be located, the ohmic electrode being electrically connected to a channel formed by two-dimensional electron gas (2DEG) formed in the channel layer near the interface between the barrier layer and the channel layer, and then heating and removing the As-doped layer to form a recess in the channel layer; a fourth step of growing an n-type III-V compound semiconductor containing at least one of P, As, and Sb as a group V element so as to fill the recess, thereby forming a contact layer; and a fifth step of forming an ohmic electrode on the contact layer.

[0022] Also , electric The field-effect transistor includes: a barrier layer made of a nitride semiconductor and having an N-polarity main surface formed on a substrate; a channel layer made of a nitride semiconductor and having an N-polarity main surface formed on the barrier layer and forming a heterojunction with the barrier layer; a recess formed in the channel layer at a location where an ohmic electrode is to be disposed, the ohmic electrode being electrically connected to a channel formed by two-dimensional electron gas formed in the channel layer near the interface between the barrier layer and the channel layer; a contact layer made of an n-type III-V compound semiconductor containing at least one of P, As, and Sb as a group V element, formed to fill the recess; and an ohmic electrode formed on and in contact with the contact layer. [Effects of the Invention]

[0023] As explained above, according to the present invention, it is possible to easily achieve a reduction in the contact resistance of an ohmic electrode in an N-polarity GaN-based HEMT. [Brief explanation of the drawings]

[0024] [Figure 1A] FIG. 1A is a cross-sectional view showing a state of a field effect transistor in the middle of a process for explaining a method for manufacturing a field effect transistor according to an embodiment of the present invention. [Figure 1B] FIG. 1B is a cross-sectional view showing the state of the field effect transistor in the middle of a process for explaining the method for manufacturing the field effect transistor according to the embodiment of the present invention. [Figure 1C] FIG. 1C is a cross-sectional view showing the state of a field-effect transistor in the middle of a process for explaining a method for manufacturing a field-effect transistor according to an embodiment of the present invention. [Figure 1D] FIG. 1D is a cross-sectional view showing the state of a field-effect transistor in the middle of a process for explaining a method for manufacturing a field-effect transistor according to an embodiment of the present invention. [Figure 1E] FIG. 1E is a cross-sectional view showing a state of a field-effect transistor in the middle of a process for illustrating a method for manufacturing a field-effect transistor according to an embodiment of the present invention. [Figure 1F] FIG. 1F is a flowchart illustrating a method for fabricating a portion of a field effect transistor according to an embodiment of the present invention. [Figure 1G] FIG. 1G is a timing chart for explaining a method for manufacturing a part of a field effect transistor according to an embodiment of the present invention. [Figure 1H] FIG. 1H is a cross-sectional view showing the state of a field-effect transistor in the middle of a process for explaining a method for manufacturing a field-effect transistor according to an embodiment of the present invention. [Figure 1I] FIG. 1I is a cross-sectional view showing a state of a field-effect transistor in the middle of a process for explaining a method for manufacturing a field-effect transistor according to an embodiment of the present invention. [Figure 1J] FIG. 1J is a cross-sectional view showing a state of a field-effect transistor in the middle of a process for illustrating a method for manufacturing a field-effect transistor according to an embodiment of the present invention. [Figure 1K] FIG. 1K is a cross-sectional view showing the configuration of a field-effect transistor according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0025] A method for manufacturing a field effect transistor according to an embodiment of the present invention will be described below with reference to FIGS. 1A to 1J.

[0026] 1A, a buffer layer 102 is formed on a substrate 101, and a barrier layer 103 made of a nitride semiconductor is formed thereon with an N-polarity (group V polarity) major surface (first step). Subsequently, a channel layer 104 made of a nitride semiconductor is formed on the barrier layer 103 with an N-polarity major surface (second step). Subsequently, a gate insulating layer 105 is formed on the channel layer 104.

[0027] The substrate 101 may be, for example, sapphire, silicon carbide, silicon, GaN, etc. The buffer layer 102 may be, for example, made of GaN. The barrier layer 103 may be, for example, made of AlGaN. The channel layer 104 may be, for example, made of GaN. The gate insulating layer 105 may be, for example, made of an insulating material such as SiN.

[0028] For example, if the substrate 101 is a sapphire substrate, the surface of the substrate 101 is nitrided by high-temperature heat treatment in an atmosphere of a source gas such as ammonia, and then a nucleation layer is grown to a thickness of approximately 20 nm. After this, a buffer layer 102 is grown to a thickness of approximately several hundred nm to sufficiently reduce defects. The buffer layer 102 is formed with its main surface being N-polar. A nitride semiconductor (such as GaN or AlGaN) with an N-polar plane as its main surface orientation can be grown on the buffer layer 102 thus formed. On the other hand, if the substrate 101 is a GaN single crystal substrate or an AlN single crystal substrate with an N-polar plane as its main surface orientation, a nitride semiconductor with an N-polar plane as its main surface orientation can be grown without the above-mentioned nitriding or growth of a nucleation layer.

[0029] Furthermore, by bonding a layered structure of a channel layer and a barrier layer, which are crystal-grown on a growth substrate with a group III plane as the principal plane orientation, to the substrate 101 and then removing the growth substrate, it is possible to obtain a state in which a barrier layer 103 and a channel layer 104, each with an N plane as the principal plane orientation, are layered in this order on the substrate 101.

[0030] When the gate insulating layer 105 is made of SiN, for example, it can be formed by depositing it using a sputtering method or the like.

[0031] 1B, a mask pattern 121 having an opening region in an electrode formation region 151 is formed. The electrode formation region 151 is a location where an ohmic electrode is disposed, which is electrically connected to a channel of two-dimensional electron gas formed in the channel layer 104 near the interface between the barrier layer 103 and the channel layer 104, which are heterojunctions with each other. As will be described later, the mask pattern 121 will be exposed to high temperatures in a later process, and therefore can be made of a heat-resistant material such as silicon oxide.

[0032] Next, the gate insulating layer 105 is patterned by selective etching using the mask pattern 121, thereby exposing the upper surface of the channel layer 104 in the electrode formation region 151 as shown in FIG. 1C. For example, the gate insulating layer 105 made of SiN can be etched by RIE using an F-based gas.

[0033] 1D, a part of the channel layer 104 in the electrode formation region 151 in the thickness direction is converted to As to form an As-doped layer 122, and then the As-doped layer 122 is heated and removed to form a recess 123 in the channel layer 104a as shown in FIG. 1E (third step). The recess 123 is formed by repeatedly forming the As-doped layer 122 and removing the As-doped layer 122.

[0034] Here, the formation of the recess 123 will be described in more detail with reference to FIGS. 1F and 1G. First, in step S101, the substrate 101 is loaded into a growth chamber of a processing apparatus with the channel layer 104 exposed. The processing apparatus can be any apparatus capable of introducing AsH3 and H2 into the growth chamber and heating the sample loaded into the processing chamber to 700°C or higher. For example, an MOCVD furnace capable of growing GaAs crystals can be used, but the present invention is not limited thereto, and a dedicated processing apparatus can also be used.

[0035] Next, in step S102, the temperature inside the growth chamber is raised to a predetermined processing temperature, for example, 700°C. It is desirable to raise the temperature inside the growth chamber in an N2 atmosphere, which can suppress thermal decomposition reactions that utilize hydrogen. However, since GaN hardly decomposes at around 700°C even in an H2 atmosphere, an H2 atmosphere or an N2 / H2 atmosphere can also be used.

[0036] Once the temperature in the growth chamber reaches the set value (step S103: yes), the growth chamber is set to an H atmosphere. In step S104, AsH is supplied into the growth chamber together with H, and the growth chamber is maintained in an H atmosphere containing AsH. In this manner, in the channel layer 104 heated to approximately 700°C in the AsH atmosphere, N, a group V element constituting the layer, is replaced with As in the atmosphere, forming an As-doped layer 122 (FIG. 1D). The thickness of the As-doped layer 122 varies depending on the temperature inside the growth chamber and the time for which AsH is supplied, but is approximately 1 to 2 nm. The As-doped layer 122 formed on the surface of the GaN channel layer 104 is composed of GaAs.

[0037] After the As conversion process is performed for the set time (yes in step S105), the supply of AsH3 into the growth chamber is stopped in step S106, and the growth chamber is maintained in a H2 atmosphere for the set time. The As conversion layer 122 is heated in this state, and is removed by a thermal decomposition reaction caused by H2 (FIG. 1E).

[0038] When the time for maintaining the H atmosphere in the growth chamber reaches the set time (step S107), steps S104 to S107 are repeated until the As conversion and removal of the As conversion layer are repeated the set number of times (until step S108 returns yes). After the set number of times has been completed (step S108 returns yes), the temperature inside the processing chamber is lowered in step S109, and the gas inside the processing chamber is evacuated. Then, in step S110, the substrate 101 to be processed is carried out of the processing chamber.

[0039] The GaN constituting the channel layer 104 below the As layer 122 hardly undergoes thermal decomposition at temperatures of around 700°C, so etching proceeds only through the thickness of the surface As layer 122, and stops when the As layer 122 is completely removed and the surface of the channel layer 104a is exposed.

[0040] In this way, by repeating the steps (steps S104 to S106) of forming an As-doped layer 122 by arsenicizing the surface in an AsH3 / H2 atmosphere, and then stopping the supply of AsH3 and thermally decomposing the As-doped layer 122 in an H2 atmosphere, it is possible to etch the electrode formation region 151 of the channel layer 104 by 1 to 2 nm at a time.

[0041] With this etching technology, the etching amount per cycle is determined by the thickness of the arsenic layer that is formed. The thickness of the arsenic layer can be controlled by the temperature inside the processing chamber and the time for which AsH3 is flowed. Furthermore, the thermal decomposition reaction of the arsenic layer is a self-limiting reaction due to the difference in thermal decomposition temperature with nitride semiconductors such as GaN, making it possible to precisely control the etching amount for each cycle, resulting in highly reproducible etching.

[0042] Another advantage of this etching method is that it hardly forms a damaged layer on the thin film surface during etching. In etching methods such as RIE, which are commonly used for GaN etching, ions and other particles are irradiated onto the etching surface, which causes a damaged layer containing many defects to form on the surface after etching.

[0043] In the above-mentioned etching method using As and thermal decomposition of the As layer, no physical particle irradiation is performed, which reduces the factors that cause defects on the surface of the channel layer 104a after etching, leading to reduced damage.

[0044] As described above, by performing the arsenic conversion and thermal decomposition of the arsenic conversion layer a set number of times, a channel layer 104a is formed in the electrode formation region 151, with a recess 123 of a predetermined depth, as shown in FIG. 1H. The thickness of the channel layer 104a in the electrode formation region 151 with the recess 123 formed therein can be, for example, about 5 nm. Leaving a thin channel layer 104a in the electrode formation region 151 in this way is intended to leave a 2DEG formed near the interface between the channel layer 104a and the barrier layer 103 in the electrode formation region 151.

[0045] As the thin portion of the channel layer 104a in the electrode formation region 151 described above becomes thinner, the carrier density of the 2DEG decreases, and as it becomes thicker, the distance between the 2DEG and the contact layer described below increases, so variations in the thickness of the thin portion described above affect the contact resistance. For this reason, the etching of the recess 123 must be a highly reproducible process. The etching by arsenic conversion and thermal decomposition of the arsenic conversion layer described above is a highly reproducible process and is suitable for forming the recess 123.

[0046] Next, an n-type III-V compound semiconductor containing at least one of P, As, and Sb as a group V element is grown (regrown) so as to fill the recess 123, thereby forming contact layers 106 and 107 in the electrode formation region 151 as shown in FIG. 1I (step 4). The contact layers 106 and 107 can be made of, for example, GaAs, InAs, InGaAs, or a multilayer structure in which these are stacked. Thereafter, a source electrode 108 and a drain electrode 109 are formed on the contact layers 106 and 107 (step 5). A gate electrode 110 is also formed on the channel layer 104 (step 6). In this example, the source electrode 108 and the drain electrode 109, which are disposed on either side of the gate electrode 110, serve as ohmic electrodes.

[0047] 1J , the field-effect transistor obtained by the above-described fabrication method includes a barrier layer 103 made of a nitride semiconductor and having an N-polarity main surface formed on a substrate 101, a channel layer 104 made of a nitride semiconductor and having an N-polarity main surface formed on the barrier layer 103 and forming a heterojunction with the barrier layer 103, a recess 123 formed in the channel layer 104 at a location where an ohmic electrode is to be disposed, the ohmic electrode being electrically connected to a channel formed by two-dimensional electron gas in the channel layer 104 near the interface between the barrier layer 103 and the channel layer 104, contact layers 106 and 107 formed to fill the recess 123 and made of an n-type III-V compound semiconductor containing at least one of P, As, and Sb as a group V element, and ohmic electrodes formed on and in contact with the contact layers 106 and 107. In this example, a gate electrode 110 is formed on the channel layer 104, and the ohmic electrodes are a source electrode 108 and a drain electrode 109 disposed on either side of the gate electrode 110.

[0048] 1K, a recess can be formed through the channel layer 104b so that the channel layer 104b is completely removed below the source electrode 108 and the drain electrode 109. In this configuration, there is no channel layer below the contact layers 106 and 107, and no 2DEG is formed. In this configuration, the contact layers 106 and 107 contact (connect) with the 2DEG formed in the channel layer 104b near the interface between the barrier layer 103 and the channel layer 104b in the direction in which they are arranged (the direction parallel to the plane of the substrate 101). In other words, the contact layers 106 and 107 contact (connect) with the 2DEG on the side surfaces of the channel layer 104b.

[0049] In this configuration, the side surfaces of the channel layer 104b where the 2DEG is formed are exposed during the fabrication process, so it is important to minimize damage to these side surfaces. If damage is introduced to the side surfaces of the channel layer 104b where the 2DEG is formed, for example, by etching, defects formed by the damage can significantly affect the electrical characteristics of the device, such as carrier traps. However, the etching by the aforementioned arsenic addition and thermal decomposition of the arsenic layer does not, in principle, introduce damage due to particle irradiation such as reactive ions, so etching with low damage is possible.

[0050] As described above, according to the present invention, a contact layer is formed by forming a recess in a channel layer that forms a heterojunction on a barrier layer formed on a substrate having an N-polar main surface, for example, by etching using As-containing and thermal decomposition of the As-containing layer, and filling the recess with an n-type III-V compound semiconductor. This makes it possible to easily reduce the contact resistance of an ohmic electrode in an N-polarity GaN-based HEMT.

[0051] It should be noted that the present invention is not limited to the embodiments described above, and it is clear that many modifications and combinations can be made by a person having ordinary knowledge in the art within the technical concept of the present invention. [Explanation of symbols]

[0052] 101...substrate, 102...buffer layer, 103...barrier layer, 104, 104a...channel layer, 105...gate insulating layer, 106...contact layer, 107...contact layer, 108...source electrode, 109...drain electrode, 110...gate electrode, 121...mask pattern, 122...arsenic layer, 123...recess, 151...electrode formation region.

Claims

1. a first step of forming a barrier layer made of a nitride semiconductor on a substrate, the barrier layer having an N-polar main surface; a second step of forming a channel layer made of a nitride semiconductor on the barrier layer, the channel layer having an N-polarity main surface; a third step of forming an As-doped layer by converting the channel layer to As at a location where an ohmic electrode electrically connected to a channel of two-dimensional electron gas formed in the channel layer near an interface between the barrier layer and the channel layer, which are heterojunction with each other, is to be disposed, and removing the As-doped layer by heating, thereby forming a recess in the channel layer; a fourth step of growing an n-type III-V compound semiconductor containing at least one of P, As, and Sb as a V-group element so as to fill the recess to form a contact layer; a fifth step of forming the ohmic electrode on the contact layer; A method for fabricating a field effect transistor comprising:

2. 2. The method for fabricating a field effect transistor according to claim 1, The method for producing a field effect transistor is characterized in that the recess is formed by repeating the steps of forming the As-doped layer and removing the As-doped layer.

3. 3. The method for fabricating a field effect transistor according to claim 1, The method for manufacturing a field effect transistor, wherein the recess is formed so as to penetrate the channel layer.

4. The method for producing a field effect transistor according to any one of claims 1 to 3, a sixth step of forming a gate electrode on the channel layer; a source electrode and a drain electrode disposed on either side of the gate electrode;

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