Semiconductor Devices

Abstract

To provide a semiconductor device comprising a transistor part and a diode part.SOLUTION: A semiconductor device 100 comprises an N- type drift region provided in a semiconductor substrate 10, a plurality of trench parts, a plurality of mesa parts 91 to 93, a P type base region 14, an N+ type region 12, a gate metal layer 50 and an emitter electrode 52. The plurality of trench parts includes: gate trench parts 40 arrayed along a predetermined array direction and electrically connected with the gate metal layer; and emitter trench parts 60 arrayed along a predetermined array direction and electrically connected with the emitter electrode. The semiconductor device comprises a transistor part 70 having a pattern that at least three trench parts are continuously arrayed in the array direction, and the pattern includes: a gate trench part which is in contact with the N+ region; and a dummy trench part 30 which is not in contact with the N+ region.SELECTED DRAWING: Figure 2A

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device. [Background technology]

[0002] BACKGROUND ART Conventionally, semiconductor devices having a transistor section and a diode section are known (see, for example, Patent Document 1), and semiconductor devices having a current sensing section are also known (see, for example, Patent Documents 2 and 3). Patent Document 1: International Publication No. 2015 / 068203 Patent Document 2: JP 2015-179705 A Patent Document 3: Japanese Patent Application Laid-Open No. 10-107282 Summary of the Invention [Problem to be solved by the invention]

[0003] In semiconductor devices, there is a demand for improving the breakdown resistance of elements by reducing the influence of noise and mitigating current concentration. [Means for solving the problem]

[0004] A first aspect of the present invention provides a semiconductor device comprising: an N-type drift region provided in a semiconductor substrate; a plurality of trenches provided on an upper surface of the semiconductor substrate; a plurality of mesa portions provided between the plurality of trenches; a P-type base region provided in the mesa portion; an N+ type region provided between the base region and an upper surface of at least one of the mesa portions; a gate metal layer provided above the upper surface of the semiconductor substrate; and a top electrode provided above the upper surface of the semiconductor substrate. In the semiconductor device, the plurality of trenches may be arranged along a predetermined arrangement direction and may include first trenches electrically connected to the gate metal layer. In any of the semiconductor devices, the plurality of trenches may be arranged along a predetermined arrangement direction and may include second trenches electrically connected to the top electrode. Any of the semiconductor devices may include a transistor portion having a pattern in which at least three first trenches are consecutively arranged in the arrangement direction. In any of the above semiconductor devices, the pattern may include a gate trench portion in contact with the N+ type region and a dummy trench portion not in contact with the N+ type region.

[0005] Any of the above semiconductor devices may include an interlayer insulating film interposed between an upper surface of the semiconductor substrate and the gate metal layer and the upper electrode. In any of the above semiconductor devices, the multiple mesa portions may include a first mesa portion connected to the upper electrode via a contact hole provided in the interlayer insulating film in a cross section passing through the N+ type region in the arrangement direction. In any of the above semiconductor devices, the multiple mesa portions may include a second mesa portion adjacent to the dummy trench portion in the cross section and having an upper surface covered by the interlayer insulating film.

[0006] Any of the above semiconductor devices may include a first region including one or more of the first mesa portions. Any of the above semiconductor devices may include a second region including two or more of the second mesa portions and the pattern. Any of the above semiconductor devices may have the second regions disposed on both sides of the first region in the arrangement direction.

[0007] In any of the above semiconductor devices, the second trench portion may be provided in the first region.

[0008] In any of the above semiconductor devices, the pattern may be periodically provided in the transistor section.

[0009] In any of the above semiconductor devices, the trench portion may include a trench provided on the upper surface side of the semiconductor substrate, polysilicon provided inside the trench, and an insulating film provided between the inner wall of the trench and the polysilicon.

[0010] In any of the above semiconductor devices, the N+ type region may not be provided in the mesa portion adjacent to the dummy trench portion among the plurality of mesa portions.

[0011] A second aspect of the present invention provides a semiconductor device including an N-type drift region provided in a semiconductor substrate, a plurality of trenches provided on an upper surface of the semiconductor substrate, a plurality of mesa portions provided between the plurality of trenches, a P-type base region provided in the mesa portion, an N+ type region provided between the base region and an upper surface of at least one of the mesa portions, a gate metal layer provided above the upper surface of the semiconductor substrate, and an upper surface electrode provided above the upper surface of the semiconductor substrate. In the semiconductor device, the plurality of trenches may have a pattern in which first, second, and third trenches, each having polysilicon electrically connected to the gate metal layer, are continuously arranged in a predetermined arrangement direction. In any of the semiconductor devices, the polysilicon may include first polysilicon adjacent to the N+ type region across an insulating film and forming a channel in the base region when a predetermined voltage is applied, and second polysilicon not adjacent to the N+ type region across an insulating film.

[0012] In any of the above semiconductor devices, the gate-emitter capacitance may be adjusted by adjusting the ratio between the first polysilicon and the second polysilicon.

[0013] Any of the above semiconductor devices may further include an N-type accumulation region provided in the mesa portion between the drift region and the base region.

[0014] In any of the above semiconductor devices, the semiconductor substrate may be any of a silicon substrate, a silicon carbide substrate, and a nitride semiconductor substrate.

[0015] Any of the above semiconductor devices may be a reverse conducting IGBT having a diode portion.

[0016] The above summary of the invention does not list all of the features of the present invention, and subcombinations of these features may also be inventions. [Brief explanation of the drawings]

[0017] [Figure 1A] 1 is an example of a top view of a semiconductor device 100 according to a first embodiment. [Figure 1B] 1 is an example of a cross-sectional view of the semiconductor device 100 according to the first embodiment taken along the line aa'. [Figure 2A] 10 is an example of a top view of a semiconductor device 100 according to a second embodiment. [Figure 2B] 10 is an example of a cross-sectional view taken along the line bb' of the semiconductor device 100 according to the second embodiment. [Figure 3] 1 is a modified example of the semiconductor device 100. [Figure 4] FIG. 1 is a top view of a semiconductor device 500 according to a comparative example. [Figure 5] An example of an overall chip diagram of a semiconductor device 500 is shown. [Figure 6] 1 shows an example of an overall chip diagram of a semiconductor device 100. FIG. [Figure 7A] 1 is a graph showing a current density distribution. [Figure 7B] 10 is a graph showing turn-off waveforms of the semiconductor device 100 and the semiconductor device 500. [Figure 8A]1 shows the conduction current density distribution of a full-gate semiconductor device. [Figure 8B] 1 shows the conduction current density distribution of a semiconductor device having an emitter trench portion E. [Figure 8C] 1 shows the conduction current density distribution of a semiconductor device having an emitter trench portion E. [Figure 8D] 1 shows the conduction current density distribution of a semiconductor device having an emitter trench portion E. [Figure 9] 10 shows an example of the configuration of a semiconductor device 100 according to a third embodiment. [Figure 10] 1 shows an example of the configuration of a semiconductor device 100 according to a fourth embodiment. [Figure 11] 10 shows an example of the configuration of a semiconductor device 100 according to a fifth embodiment. [Figure 12] 10 is an example of a top view of a semiconductor device 200 according to a sixth embodiment. [Figure 13] 2 is a diagram showing an example of a cross section of a transistor section 70. FIG. [Figure 14] 2 is a diagram showing an example of a cross section of a current sensing section 210. FIG. [Figure 15] FIG. 10 is an enlarged top view of the vicinity of the outer region 104-2. [Figure 16] FIG. 2 is an enlarged top view of the vicinity of the opening 212. [Figure 17] 10 is a top view illustrating the distance between the second well region 218 and the emitter placement region 216. FIG. [Figure 18] FIG. 10 is a diagram illustrating a distance X1s. [Figure 19] FIG. 10 is a diagram illustrating a distance Y1s. [Figure 20] 10 is a diagram illustrating a distance X1t in a transistor section 70. FIG. [Figure 21] FIG. 17 is a diagram showing another example of the configuration of the area A in FIG. [Figure 22] 10 is a diagram illustrating a distance Y1t in the transistor section 70. FIG. DETAILED DESCRIPTION OF THE INVENTION

[0018] The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the scope of the invention according to the claims. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0019] In this specification, one side in a direction parallel to the depth direction of a semiconductor substrate is referred to as "top" and the other side as "bottom." Of the two main surfaces of a substrate, layer, or other member, one surface is referred to as the top surface and the other surface is referred to as the bottom surface. The directions of "top," "bottom," "front," and "back" are not limited to the direction of gravity or the direction in which the semiconductor device is attached to a substrate or the like when mounted.

[0020] In this specification, technical matters may be explained using orthogonal coordinate axes of X, Y, and Z. In this specification, a plane parallel to the top surface of the semiconductor substrate is defined as the XY plane, and the depth direction of the semiconductor substrate is defined as the Z axis. In this specification, the case where the semiconductor substrate is viewed in the Z axis direction is referred to as a planar view.

[0021] In each embodiment, an example is shown in which the first conductivity type is N-type and the second conductivity type is P-type, but the first conductivity type may be P-type and the second conductivity type may be N-type. In this case, the conductivity types of the substrate, layer, region, etc. in each embodiment will be opposite polarities.

[0022] In this specification, layers or regions marked with n or p have majority carriers of electrons or holes, respectively, and + and - after n or p indicate higher and lower doping concentrations, respectively, than layers or regions without that prefix.

[0023] 1A illustrates an example of the configuration of a semiconductor device 100 according to a first embodiment. The semiconductor device 100 of this example is a semiconductor chip including a transistor section 70 and a diode section 80. For example, the semiconductor device 100 is a reverse conducting IGBT (RC-IGBT).

[0024] The transistor section 70 is a region having the emitter region 12 and the gate trench portion 40. In this example, the transistor section 70 is a region obtained by projecting a collector region provided on the lower surface side of the semiconductor substrate 10 onto the upper surface of the semiconductor substrate 10, but is not limited to this. The collector region has a second conductivity type. In this example, the collector region is a P+ type, for example. The transistor section 70 includes a transistor such as an IGBT.

[0025] The diode section 80 includes a diode such as a free wheel diode (FWD) provided adjacent to the transistor section 70 on the upper surface of the semiconductor substrate 10. The diode section 80 in this example is a region obtained by projecting the cathode region 82 onto the upper surface of the semiconductor substrate 10, and is a region other than the transistor section 70, but is not limited to this.

[0026] 1A shows the area around the chip end portion, which is the edge side of the semiconductor device 100, and omits other areas. Note that in this example, for convenience, the edge on the negative side in the X-axis direction will be described, but the same applies to other edges of the semiconductor device 100.

[0027] The semiconductor substrate 10 may be a silicon substrate, a silicon carbide substrate, a nitride semiconductor substrate such as gallium nitride, etc. The semiconductor substrate 10 in this example is a silicon substrate.

[0028] The semiconductor device 100 of this example includes, on the upper surface of a semiconductor substrate 10, a gate trench portion 40, a dummy trench portion 30, an emitter trench portion 60, a well region 11, an emitter region 12, a base region 14, and a contact region 15. The semiconductor device 100 of this example also includes an emitter electrode 52 and a gate metal layer 50 provided above the upper surface of the semiconductor substrate 10.

[0029] The emitter electrode 52 and the gate metal layer 50 are formed of a material containing metal. For example, at least a portion of the emitter electrode 52 may be formed of aluminum, an aluminum-silicon alloy, or an aluminum-silicon-copper alloy. At least a portion of the gate metal layer 50 may be formed of aluminum, an aluminum-silicon alloy, or an aluminum-silicon-copper alloy. The emitter electrode 52 and the gate metal layer 50 may have a barrier metal formed of titanium, a titanium compound, or the like below the region formed of aluminum or the like. The emitter electrode 52 and the gate metal layer 50 are provided separately from each other.

[0030] The emitter electrode 52 and the gate metal layer 50 are provided above the semiconductor substrate 10, with an interlayer insulating film sandwiched therebetween. The interlayer insulating film is omitted in Fig. 1A. Contact holes 49, 54, and 56 are provided to penetrate the interlayer insulating film.

[0031] The contact hole 49 connects the gate metal layer 50 and the gate runner 48. A plug made of tungsten or the like may be formed inside the contact hole 49.

[0032] The gate runner 48 connects the gate metal layer 50 and the gate trench portion 40 of the transistor portion 70. In one example, the gate runner 48 is connected to the gate conductive portion in the gate trench portion 40 and the dummy conductive portion in the dummy trench portion 30 on the upper surface of the semiconductor substrate 10. The gate runner 48 is not connected to the emitter conductive portion in the emitter trench portion 60. For example, the gate runner 48 is formed of polysilicon doped with impurities. The gate metal layer 50 and the gate runner 48 are an example of a gate wiring portion.

[0033] The gate runner 48 in this example is provided from below the contact hole 49 to the end of the gate trench portion 40. An interlayer insulating film such as an oxide film is provided between the gate runner 48 and the upper surface of the semiconductor substrate 10. At the end of the gate trench portion 40, the gate conductive portion is exposed on the upper surface of the semiconductor substrate 10. The gate trench portion 40 comes into contact with the gate runner 48 at the exposed portion of the gate conductive portion.

[0034] The contact hole 56 connects the emitter electrode 52 and the emitter conductive portion in the emitter trench portion 60. A plug made of tungsten or the like may be provided inside the contact hole 56.

[0035] The connection portion 25 is provided between the emitter electrode 52 and the emitter conductive portion. The connection portion 25 is made of a conductive material such as polysilicon doped with impurities. The connection portion 25 is provided above the upper surface of the semiconductor substrate 10 via an interlayer insulating film such as an oxide film.

[0036] The gate trench portions 40 are arranged at predetermined intervals along a predetermined arrangement direction (in this example, the Y-axis direction). In this example, the gate trench portion 40 may have two extension portions 41 that extend parallel to the upper surface of the semiconductor substrate 10 and along an extension direction perpendicular to the arrangement direction (in this example, the X-axis direction), and a connection portion 43 that connects the two extension portions 41. In this example, the gate trench portion 40 is electrically connected to the gate metal layer 50. In addition, the gate trench portion 40 is in contact with the emitter region 12.

[0037] It is preferable that at least a portion of the connection portion 43 is curved. By connecting the ends of the two extension portions 41 of the gate trench portion 40, it is possible to alleviate electric field concentration at the ends of the extension portions 41. At the connection portion 43 of the gate trench portion 40, the gate runner 48 may be connected to the gate conductive portion.

[0038] Like the gate trench portions 40, the dummy trench portions 30 are arranged at predetermined intervals along a predetermined arrangement direction (the Y-axis direction in this example). Like the gate trench portions 40, the dummy trench portions 30 in this example may have a U-shape on the upper surface of the semiconductor substrate 10. That is, the dummy trench portions 30 may have two extension portions 31 extending along the extension direction and a connection portion 33 connecting the two extension portions 31. The dummy trench portions 30 are electrically connected to the gate metal layer 50. However, the dummy trench portions 30 differ from the gate trench portions 40 in that the dummy trench portions 30 are not in contact with the emitter region 12. For example, the semiconductor device 100 can adjust the gate-emitter capacitance by adjusting the ratio between the gate trench portions 40 and the dummy trench portions 30.

[0039] The emitter trenches 60, like the gate trenches 40, are arranged at predetermined intervals along a predetermined arrangement direction (the Y-axis direction in this example). Like the gate trenches 40, the emitter trenches 60 of this example may have a U-shape on the upper surface of the semiconductor substrate 10. That is, the emitter trenches 60 may have two extending portions 61 extending along the extension direction and a connecting portion 63 connecting the two extending portions 61. The emitter trenches 60 are electrically connected to the emitter electrode 52. For example, by providing the emitter trenches 60 in the diode section 80, the potential around the emitter trenches 60 is less likely to fluctuate.

[0040] The emitter electrode 52 is provided above the gate trench portion 40 , the dummy trench portion 30 , the emitter trench portion 60 , the well region 11 , the emitter region 12 , the base region 14 and the contact region 15 .

[0041] The well region 11 is a second conductivity type region provided on the upper surface of the semiconductor substrate 10 closer to the drift region 18 (described later). The well region 11 is, for example, P+ type. The well region 11 is provided within a predetermined range from the end of the active region on the side where the gate metal layer 50 is provided. The diffusion depth of the well region 11 may be deeper than the depths of the gate trench portion 40, the dummy trench portion 30, and the emitter trench portion 60. Part of the regions of the gate trench portion 40, the dummy trench portion 30, and the emitter trench portion 60 on the gate metal layer 50 side are provided in the well region 11. The bottoms of the ends of the gate trench portion 40, the dummy trench portion 30, and the emitter trench portion 60 in the extension direction may be covered by the well region 11.

[0042] The contact holes 54 are provided above the emitter region 12 and the contact region 15 in the transistor section 70. The contact holes 54 are provided above the base region 14 in the diode section 80. The contact holes 54 are provided above the contact region 15 in the boundary region 81. In this manner, one or more contact holes 54 are provided in the interlayer insulating film. The one or more contact holes 54 may be provided extending in the extension direction. In Example 1, the contact region 15 is provided on the upper surface of the boundary region 81, but the base region 14 may be provided on the upper surface of the boundary region 81 as in the diode section 80. This is not limited to Example 1, but also applies to Examples 2 to 5 described below.

[0043] The boundary region 81 is provided in a region where the transistor section 70 and the diode section 80 are adjacent to each other. In this specification, the boundary region 81 is a region provided in a region where the transistor section 70 and the diode section 80 are adjacent to each other to prevent interference between them. Specifically, the boundary region 81 has a device structure different from the device structure (so-called MOS structure) of the transistor section 70 and the device structure of a diode such as a free wheel diode of the diode section 80. Therefore, the boundary region 81 may have a device structure different from the device structure of the transistor section 70 and the device structure of the diode section 80, and may be a region located between the device structure in which the channel of the transistor section 70 is formed and the device structure of the diode of the diode section 80 in the arrangement direction of the trench sections.

[0044] The device structure of the boundary region 81 that differs from the device structure of the transistor portion 70 and the device structure of the diode portion 80 refers to a region having a device structure that differs from both the transistor portion 70 and the diode portion 80 in at least one of the emitter region 12, the contact region 15, the accumulation region 16, the trench portion, the depth of the trench portion, a lifetime killer (described later), the buffer region 20, the cathode region 82, and the collector region 22. The difference in the structure of the trench portion can be, for example, a deviation from the periodic structure (repeated structure) of both the trench portion of the transistor portion 70 and the trench portion of the diode portion 80. As in this example, the device structure that differs from the device structure of both the transistor portion 70 and the diode portion 80 does not only focus on a single range (e.g., a single trench) of the transistor portion 70 or the diode portion 80, but may also be a region that differs from the pattern even when focusing on the periodic structure (repeated structure) of the transistor portion 70 or the diode portion 80.

[0045] Furthermore, boundary region 81 may be 10 μm or more and 100 μm or less, or may be 50 μm or more and 100 μm or less. The base point of the length of boundary region 81 may be, for example, gate trench portion 40 where the channel of transistor portion 70 is formed, and boundary region 81 may be a region of 10 μm or more and 100 μm or less from gate trench portion 40 toward diode portion 80.

[0046] The thickness of the semiconductor substrate 10 may be determined according to the breakdown voltage of the semiconductor device 100, and the width of the boundary region 81 in the Y-axis direction may be determined according to the thickness of the semiconductor substrate 10. Specifically, the higher the breakdown voltage of the semiconductor device 100, the larger the width of the boundary region 81 in the Y-axis direction may be. Furthermore, the width of the boundary region 81 in the Y-axis direction may be determined according to the manner in which carriers flow and the amount of carriers in the semiconductor substrate 10. Specifically, the larger the amount of carriers flowing per unit time between the transistor section 70 and the diode section 80, the larger the width of the boundary region 81 in the Y-axis direction may be. Furthermore, the larger the amount of carriers in the semiconductor substrate 10, the larger the width of the boundary region 81 in the Y-axis direction may be.

[0047] The boundary region 81 may have multiple mesa portions. More preferably, the boundary region 81 may have four to ten mesa portions. The starting point of the mesa portion in the boundary region 81 may be, for example, the gate trench portion 40 where the channel of the transistor portion 70 is formed. The boundary region 81 may consist of four to ten mesa portions extending from the gate trench portion 40 toward the diode portion 80. The width of one mesa portion in the Y-axis direction may be approximately 10 μm. The length of four mesa portions sandwiching three trench portions in the Y-axis direction may be 50 μm, and the length of five mesa portions sandwiching four trench portions in the Y-axis direction may be 50 μm. Furthermore, the length of eight mesa portions sandwiching seven trench portions in the Y-axis direction may be 100 μm, and the length of ten mesa portions sandwiching nine trench portions in the Y-axis direction may be 100 μm.

[0048] By providing the boundary region 81 having a structure different from that of the non-boundary region 83 of the transistor section 70 or the diode section 80, it is possible to reduce current interference with the transistor section 70 or the diode section 80. In one example, the larger the width of the boundary region 81 in the Y-axis direction, the more effectively it is possible to reduce current interference.

[0049] In the first embodiment, the boundary region 81 is provided in the diode section 80. In addition, in the first embodiment, the boundary region 81 is a region between the gate trench section 40 and the emitter trench section 60 that does not have the emitter region 12. Because the boundary region 81 does not have the emitter region 12, the semiconductor device 100 is less likely to latch up. The boundary region 81 refers to the region between the region where the gate trench sections 40 of the transistor section 70 are arranged at a regular interval in the Y-axis direction and the region where the emitter trench sections 60 of the diode section 80 are arranged at a regular interval in the Y-axis direction.

[0050] The non-boundary region 83 is a region other than the boundary region 81 in the transistor section 70 or the diode section 80. In the first embodiment, the boundary region 81 is provided in the diode section 80, and therefore the region of the diode section 80 other than the boundary region 81 is referred to as the non-boundary region 83. In the first embodiment, the non-boundary region 83 is a region having the emitter trench portions 60 in a region different from the boundary region 81. Thus, the non-boundary region 83 includes a region where the emitter trench portions 60 are arranged at a regular interval within the region where the cathode region 82 is projected onto the upper surface of the semiconductor substrate 10. Note that the boundary region 81 is not provided in the transistor section 70, and therefore in this case, the entire transistor section 70 is a non-boundary region.

[0051] The dummy trench portion 30 is provided in the boundary region 81. However, the dummy trench portion 30 may also be provided in the non-boundary region 83. The dummy trench portion 30 may be provided only in the non-boundary region 83. Furthermore, the boundary region 81 may also include a gate trench portion 40 and an emitter trench portion 60. Note that half or more of the trench portions located within the boundary region 81 may be dummy trench portions 30, or all of them.

[0052] The first mesa portion 91, the second mesa portion 92, and the third mesa portion 93 are mesa portions provided adjacent to each trench portion in the Y-axis direction in a plane parallel to the upper surface of the semiconductor substrate 10. A mesa portion is a portion of the semiconductor substrate 10 sandwiched between two adjacent trench portions, and may be a portion from the upper surface of the semiconductor substrate 10 to the deepest bottom of each trench portion. An extension portion of each trench portion may be considered as one trench portion. In other words, the region sandwiched between the two extension portions may be considered as a mesa portion.

[0053] The first mesa portion 91 is provided in the transistor portion 70 adjacent to at least one of the gate trench portion 40 and the emitter trench portion 60. In this example, the first mesa portion 91 is also provided adjacent to the transistor portion 70 in the boundary region 81. The first mesa portion 91 has a well region 11, an emitter region 12, a base region 14, and a contact region 15 on the upper surface of the semiconductor substrate 10. In the first mesa portion 91, the emitter regions 12 and the contact regions 15 are provided alternately in the extension direction.

[0054] The second mesa portion 92 is a mesa portion provided in the boundary region 81. The second mesa portion 92 has a well region 11, a base region 14, and a contact region 15 on the upper surface of the semiconductor substrate 10. In the present embodiment 1, the second mesa portion 92 does not have the emitter region 12, but may have the emitter region 12. Also, in the present embodiment 1, the second mesa portion 92 has the contact region 15, but may not have the contact region 15.

[0055] The third mesa portion 93 is provided in a region of the diode portion 80 that is sandwiched between adjacent emitter trench portions 60. The third mesa portion 93 has a well region 11 and a base region 14 on the upper surface of the semiconductor substrate 10.

[0056] The base region 14 is a second conductivity type region provided on the upper surface side of the semiconductor substrate 10. The base region 14 is, for example, a P-type. The base region 14 may be provided on the upper surface of the semiconductor substrate 10 at both ends in the X-axis direction of the first mesa portion 91 and the second mesa portion 92. However, as shown in FIG. 1B, the base region 14 is introduced into almost the entire surface of the active region in cross section. Note that FIG. 1A shows only one end of the base region 14 in the X-axis direction.

[0057] The emitter region 12 is provided on the upper surface of the first mesa portion 91 in contact with the gate trench portion 40. The emitter region 12 may be provided in the Y-axis direction from one of two trench portions extending in the X-axis direction to the other, sandwiching the first mesa portion 91 therebetween. The emitter region 12 is also provided below the contact hole 54. The emitter region 12 in this example is of the first conductivity type. For example, the emitter region 12 is of N+ type.

[0058] The contact region 15 is a second conductivity type region having a higher doping concentration than the base region 14. In this example, the contact region 15 is P+ type, for example. The contact region 15 in this example is provided on the upper surface of the first mesa portion 91. The contact region 15 may be provided in the Y-axis direction from one to the other of two trench portions extending in the X-axis direction with the first mesa portion 91 in between. The contact region 15 may or may not be in contact with the gate trench portion 40. Furthermore, the contact region 15 may or may not be in contact with the emitter trench portion 60. The contact region 15 in this example is in contact with the dummy trench portion 30 and the gate trench portion 40. The contact region 15 is also provided below the contact hole 54.

[0059] The contact region 15 may also be provided on the upper surface of the second mesa portion 92. The area of ​​the contact region 15 provided on the upper surface of one second mesa portion 92 is larger than the area of ​​the contact region 15 provided on the upper surface of one first mesa portion 91. The contact region 15 on the upper surface of the second mesa portion 92 may be provided over the entire region sandwiched between the base regions 14 provided at both ends of the second mesa portion 92 in the X-axis direction.

[0060] The cathode region 82 is a region of a first conductivity type provided on the lower surface side of the semiconductor substrate 10 in the diode section 80. The cathode region 82 in this example is, for example, an N+ type. The region where the cathode region 82 is provided in plan view is indicated by a dashed line.

[0061] 1B is a diagram showing an example of the a-a' cross section in FIG. 1A. The a-a' cross section is a YZ plane passing through the emitter region 12, the base region 14, and the contact region 15 in the transistor section 70 and the diode section 80. In the a-a' cross section, the semiconductor device 100 of this example has a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, and a collector electrode 24. The emitter electrode 52 is provided on the upper surface 21 of the semiconductor substrate 10 and on the upper surface of the interlayer insulating film 38.

[0062] The drift region 18 is a region of a first conductivity type provided in the semiconductor substrate 10. In this example, the drift region 18 is, for example, an N-type. The drift region 18 may be a region remaining in the semiconductor substrate 10 without other doped regions being formed therein. That is, the doping concentration of the drift region 18 may be the same as the doping concentration of the semiconductor substrate 10.

[0063] The buffer region 20 is a region of a first conductivity type provided below the drift region 18. In this example, the buffer region 20 is, for example, N-type. The doping concentration of the buffer region 20 is higher than the doping concentration of the drift region 18. The buffer region 20 may function as a field stop layer that prevents a depletion layer spreading from the lower surface side of the base region 14 from reaching the collector region 22 of the second conductivity type and the cathode region 82 of the first conductivity type.

[0064] The collector region 22 is a second conductivity type region provided on the lower surface side of the semiconductor substrate 10 in the transistor section 70. The collector region 22 is, for example, a P+ type. The collector region 22 in this example is provided below the buffer region 20.

[0065] The cathode region 82 is provided below the buffer region 20 in the diode section 80. The boundary R is the boundary between the collector region 22 and the cathode region 82. The boundary R may coincide with the boundary between the transistor section 70 and the diode section 80, or may be different.

[0066] The collector electrode 24 is formed on the lower surface 23 of the semiconductor substrate 10. The collector electrode 24 is made of a conductive material such as a metal.

[0067] The accumulation region 16 is a region of a first conductivity type provided above the drift region 18 in the first mesa portion 91 and the second mesa portion 92. In this example, the accumulation region 16 is, for example, an N-type. The accumulation region 16 is provided in contact with the gate trench portion 40. The accumulation region 16 may or may not be in contact with the dummy trench portion 30. The doping concentration of the accumulation region 16 is higher than the doping concentration of the drift region 18. By providing the accumulation region 16, the carrier injection enhancement effect (IE effect) can be enhanced, and the on-voltage of the transistor portion 70 can be reduced. The accumulation region 16 may also be provided in the third mesa portion 93.

[0068] The base region 14 is a second conductivity type region provided above the accumulation region 16 in the first mesa portion 91, the second mesa portion 92, and the third mesa portion 93. The base region 14 is provided in contact with the gate trench portion 40. The base region 14 of the third mesa portion 93 is a so-called anode region.

[0069] The emitter region 12 is provided in the first mesa portion 91, between the base region 14 and the upper surface 21. The emitter region 12 is provided in contact with the gate trench portion 40. The doping concentration of the emitter region 12 is higher than the doping concentration of the drift region 18. An example of a dopant for the emitter region 12 is arsenic (As). The emitter region 12 may or may not be provided in the second mesa portion 92.

[0070] The contact region 15 is provided above the accumulation region 16 in the first mesa portion 91 and the second mesa portion 92. The contact region 15 is provided in the first mesa portion 91 and the second mesa portion 92 so as to contact the gate trench portion 40 and the dummy trench portion 30.

[0071] One or more gate trench portions 40 and one or more dummy trench portions 30 are provided on the upper surface 21. Each trench portion is provided from the upper surface 21 to the drift region 18. In regions where at least one of the emitter region 12, the base region 14, the contact region 15, and the accumulation region 16 is provided, each trench portion also penetrates these regions to reach the drift region 18. The trench portion penetrating the doped region is not limited to a case where the trench portion is formed after the doped region is formed. A case where the doped region is formed between the trench portions after the trench portions are formed is also included in the case where the trench portion penetrates the doped region.

[0072] The gate trench portion 40 has a gate trench, a gate insulating film 42, and a gate conductive portion 44 formed on the upper surface 21. The gate insulating film 42 is formed to cover the inner wall of the gate trench. The gate insulating film 42 may be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate trench. The gate conductive portion 44 is formed inside the gate trench, further inward than the gate insulating film 42. The gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is made of a conductive material such as polysilicon. The gate trench portion 40 is covered on the upper surface 21 with an interlayer insulating film 38.

[0073] The gate conductive portion 44 includes a region facing the adjacent base region 14 on the first mesa portion 91 side across the gate insulating film 42 in the depth direction of the semiconductor substrate 10. When a predetermined voltage is applied to the gate conductive portion 44, a channel, which is an electron inversion layer, is formed in the surface layer of the interface of the base region 14 that contacts the gate trench.

[0074] The dummy trench portion 30 may have the same structure as the gate trench portion 40. The dummy trench portion 30 has a dummy trench, a dummy insulating film 32, and a dummy conductive portion 34 formed on the upper surface 21 side. The dummy insulating film 32 is formed to cover the inner wall of the dummy trench. The dummy conductive portion 34 is formed inside the dummy trench and further inward than the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The dummy trench portion 30 is covered on the upper surface 21 with an interlayer insulating film 38.

[0075] The emitter trench portion 60 may have the same structure as the gate trench portion 40 and the dummy trench portion 30. The emitter trench portion 60 has an emitter trench, an emitter insulating film 62, and an emitter conductive portion 64 formed on the upper surface 21 side. The emitter insulating film 62 is formed to cover the inner wall of the emitter trench. The emitter conductive portion 64 is formed inside the emitter trench and is formed further inward than the emitter insulating film 62. The emitter insulating film 62 insulates the emitter conductive portion 64 from the semiconductor substrate 10. The emitter trench portion 60 is covered on the upper surface 21 with an interlayer insulating film 38.

[0076] The interlayer insulating film 38 is provided above the upper surface of the semiconductor substrate 10. The interlayer insulating film 38 is provided with one or more contact holes 54 for electrically connecting the emitter electrode 52 to the semiconductor substrate 10. Other contact holes 49 and 54 may also be provided penetrating the interlayer insulating film 38 in a similar manner. The emitter electrode 52 is provided above the interlayer insulating film 38.

[0077] The semiconductor device 100 of this example adjusts the gate-emitter capacitance by adjusting the ratio between the gate trench portions 40 and the dummy trench portions 30. The semiconductor device 100 can increase the gate-emitter capacitance by increasing the ratio of the dummy trench portions 30, and can decrease the gate-emitter capacitance by decreasing the ratio of the dummy trench portions 30. For example, if the number of gate trench portions 40 is G and the number of dummy trench portions 30 is D, the following equation holds true. 0.01 <D / (D+G)<0.2

[0078] The number of gate trench portions 40 refers to the number of extension portions 41. That is, even when a single gate trench portion 40 is formed by connecting a plurality of extension portions 41 with a connection portion 43, the number of gate trench portions 40 is essentially the same as the number of extension portions 41. Therefore, the number of gate trench portions 40 matches the number of gate trench portions 40 in the a-a' cross section, as shown in FIG. 1B.

[0079] Similarly, even when a single dummy trench portion 30 is formed by connecting a plurality of extension portions 31 via connection portions 33, the number of dummy trench portions 30 is essentially the same as the number of extension portions 31. Therefore, the number of dummy trench portions 30 matches the number of dummy trench portions 30 in the a-a' cross section, as shown in FIG. 1B.

[0080] FIG. 2A is an example of a top view of a semiconductor device 100 according to a second embodiment. FIG. 2B is a diagram showing an example of a cross section taken along line b-b' in FIG. 2A. The semiconductor device 100 according to the second embodiment differs from the semiconductor device 100 according to the first embodiment in that a boundary region 81 is provided in the transistor section 70. In the semiconductor device 100 according to the second embodiment, the boundary region 81 is provided in the transistor section 70, and therefore the region of the transistor section 70 other than the boundary region 81 is referred to as a non-boundary region 83. Note that the boundary region 81 is not provided in the diode section 80, and therefore the entire diode section 80 is a non-boundary region in this case.

[0081] In this second embodiment, the non-boundary region 83 is a region that has the gate trench portions 40 and the emitter trench portions 60 in a region different from the boundary region 81. Thus, the non-boundary region 83 includes a region where the gate trench portions 40 and the emitter trench portions 60 are arranged at a regular interval within the region where the collector region 22 is projected onto the upper surface of the semiconductor substrate 10.

[0082] The dummy trench portion 30 is provided in the boundary region 81. However, the dummy trench portion 30 may also be provided in the non-boundary region 83. The dummy trench portion 30 may be provided only in the non-boundary region 83. Furthermore, the boundary region 81 may be provided with a gate trench portion 40 or an emitter trench portion 60.

[0083] As described above, providing the boundary region 81 in the transistor section 70 means that the cathode region 82 is relatively short and the collector region 22 is relatively long. This makes it easier for electrons emitted from the emitter region 12 to flow into the collector region 22, thereby reducing the on-voltage.

[0084] The boundary region 81 may be provided across the transistor section 70 and the diode section 80. In this case, a non-boundary region 83 other than the boundary region 81 is provided in each of the transistor section 70 and the diode section 80.

[0085] 3 shows a modified example of the semiconductor device 100. In the semiconductor device 100 of this example, the contact hole 54 is not provided above at least a portion of the second mesa portion 92 adjacent to the dummy trench portion 30 in the boundary region 81. In the semiconductor device 100 of this example, the contact hole 54 is not provided above any of the second mesa portions 92 adjacent to the dummy trench portion 30 in the boundary region 81. In other words, the second mesa portions 92 adjacent to the dummy trench portion 30 are not electrically connected to the emitter electrode 52. Note that not providing the contact hole 54 in some or all of the mesa portions in the boundary region 81 may also be applied to Examples 1 and 2 and Examples 3 to 5 described below.

[0086] 4 is a top view of a semiconductor device 500 according to a comparative example. The semiconductor device 500 of this example differs from the semiconductor device 100 of Example 1 in that it does not have a dummy trench portion 30. The semiconductor device 500 includes a transistor portion 570 and a diode portion 580.

[0087] The semiconductor device 500 has an emitter trench portion 60 on the boundary side of the diode portion 580 with the transistor portion 570. That is, the semiconductor device 500 of this example does not have a dummy trench portion 30 in the boundary region 81. That is, trench portions other than the gate trench portion 40 are not connected to the gate metal layer 50, and therefore the gate-emitter capacitance is smaller than that of the semiconductor device 100 of the first example.

[0088] If noise occurs in the semiconductor device 500 while the semiconductor device 500 is operating in FWD mode, a potential difference equal to or greater than the threshold voltage Vth may occur, causing the transistor section 570 to erroneously turn on. The smaller the gate-emitter capacitance, the greater the effect of noise on the semiconductor device 500. If the transistor section 570 erroneously turns on, a short-circuit current may flow during reverse recovery, causing a short-circuit mode, and the semiconductor device 500 may be destroyed.

[0089] On the other hand, since the semiconductor device 100 has the dummy trench portion 30, the gate-emitter capacitance increases. This makes it less likely that the transistor portion 70 will be erroneously turned on even if noise occurs in the semiconductor device 100. In this way, providing the dummy trench portion 30 is equivalent to providing a noise-cutting capacitor. This reduces the effects of noise on the semiconductor device 100.

[0090] 5 shows an example of an overall chip diagram of a semiconductor device 500 according to a comparative example. The semiconductor device 500 of this example includes a plurality of transistor sections 570 and a plurality of diode sections 580.

[0091] In the semiconductor device 500 of this example, the width Wd of the diode section 580 in the Y-axis direction is smaller than the width Wt of the transistor section 570 in the Y-axis direction. In this example, the width of the transistor section 570 in the X-axis direction and the width of the diode section 580 in the X-axis direction are equal. The total area of ​​the multiple diode sections 580 is smaller than the total area of ​​the multiple transistor sections 570.

[0092] In the semiconductor device 500, current on the transistor section 570 side may gradually concentrate on the diode section 580 side during switching. In this case, the semiconductor device 500 may generate heat locally and be destroyed. As described above, current flows uniformly during turn-off, but may concentrate over time as it tries to flow to the cathode region. In the semiconductor device 500, the width Wd of the diode section 580 in the Y-axis direction is smaller than the width Wt of the transistor section 570 in the Y-axis direction, so heat generation due to current concentration is significant. In particular, when switching at high current density, the semiconductor device 500 may be destroyed.

[0093] 6 shows an example of an overall chip diagram of semiconductor device 100. Semiconductor device 100 of this example includes multiple transistor sections 70 and multiple diode sections 80. Semiconductor device 100 includes an edge termination region 102 and an outer region 104 outside the active region in which transistor sections 70 and diode sections 80 are provided.

[0094] Edge termination region 102 relieves electric field concentration on the top surface side of semiconductor substrate 10. For example, edge termination region 102 has a guard ring, a field plate, a resurf, or a structure that is a combination of these.

[0095] The outer region 104 is provided adjacent to the transistor section 70 and the diode section 80. For example, the outer region 104 includes a gate pad, a sense section, and a temperature detection section.

[0096] The semiconductor device 100 of this example includes 15 transistor sections 70 and 12 diode sections 80. In the semiconductor device 100 of this example, the width Wd of the diode sections 80 in the Y-axis direction is equal to or greater than the width Wt of the transistor sections 70 in the Y-axis direction, and is preferably greater than the width Wt. For example, the width Wd of the diode sections 80 in the Y-axis direction may be 500 μm or greater, 1000 μm or greater, or 1500 μm or greater. In this example, the width of the transistor sections 70 in the X-axis direction and the width of the diode sections 80 in the X-axis direction are equal to each other. In the semiconductor device 100 of this example, the total area of ​​the diode sections 80 is equal to or greater than the total area of ​​the transistor sections 70, and is preferably greater than the total area of ​​the transistor sections 70.

[0097] In the semiconductor device 100 of this example, the width Wd of the diode section 80 in the Y-axis direction is equal to or greater than the width Wt of the transistor section 70 in the Y-axis direction, so that the current flowing through the transistor section 70 also flows through the cathode region 82 of the diode section 80, thereby alleviating current concentration. Therefore, in the semiconductor device 100 of this example, current concentration is alleviated, making it less susceptible to breakdown.

[0098] The total area of ​​the diode section 80 may be more than 1.2 times, more than 1.5 times, or more than 2.0 times the total area of ​​the transistor section 70. The ratio of the total area of ​​the transistor section 70 to the total area of ​​the diode section 80 is set from the viewpoint of the trade-off between the conduction loss and current concentration of the semiconductor device 100. That is, the larger the total area of ​​the transistor section 70, the more likely the conduction loss will be reduced. On the other hand, the larger the total area of ​​the diode section 80, the more likely the current concentration will be alleviated.

[0099] When the semiconductor device 100 has diode portions 80 with a total area equal to or greater than the total area of ​​the transistor portions 70, the gate-emitter capacitance is smaller than when the total area of ​​the diode portions 80 is smaller than the total area of ​​the transistor portions 70. However, in the semiconductor device 100 of this example, by providing the dummy trench portions 30 in the boundary region 81, it is possible to suppress a reduction in the gate-emitter capacitance.

[0100] In the case where the size of the semiconductor chip is fixed, the semiconductor device 100 may have a configuration in which the total area of ​​the diode sections 80 is equal to or greater than the total area of ​​the transistor sections 70 and the number of the transistor sections 70 and the diode sections 80 is reduced. This reduces the area at the interface between the transistor sections 70 and the diode sections 80, i.e., the boundary area 81 for preventing interference between the transistor sections 70 and the diode sections 80, thereby reducing current loss.

[0101] The semiconductor device 100 of this example has more transistor sections 70 than diode sections 80 in the Y-axis direction. As a result, the transistor sections 70 are arranged at both ends in the Y-axis direction. By providing the transistor sections 70 at both ends in the Y-axis direction, current concentration in the diode sections 80 is less likely to occur.

[0102] For example, the semiconductor device 100 of this example includes five transistor sections 70 and four diode sections 80 in the Y-axis direction. However, the number of transistor sections 70 and diode sections 80 in the Y-axis direction is not limited to this. For example, the number of transistor sections 70 and diode sections 80 may be four and three, three and two, or two and one. Furthermore, the number of transistor sections 70 and diode sections 80 may be six and five, seven and six, or eight and seven. Note that the number of transistor sections 70 and diode sections 80 in the Y-axis direction may be the same.

[0103] Furthermore, the semiconductor device 100 includes three rows of transistor sections 70 and three rows of diode sections 80 in the X-axis direction. However, the number of rows of transistor sections 70 and diode sections 80 in the X-axis direction is not limited to this. For example, the number of rows of transistor sections 70 and diode sections 80 in the X-axis direction may be one, two, four, five, or more.

[0104] 7A is a graph showing the current density distribution. The vertical axis represents the current density [A / cm2 ], and the horizontal axis indicates an arbitrary position in the Y-axis direction.

[0105] Distribution D1 shows the current density distribution when the semiconductor device 100 is used. In this example, the semiconductor device 100 shows a case where the ratio of the total area of ​​the transistor section 70 to the total area of ​​the diode section 80 is 20:40. In other words, the total area of ​​the diode section 80 corresponds to approximately 66% of the total area of ​​the transistor section 70 and the diode section 80.

[0106] Distribution D2 shows the current density distribution when the semiconductor device 100 is used. In this example, the semiconductor device 100 shows a case where the ratio of the total area of ​​the transistor section 70 to the total area of ​​the diode section 80 is 20:20. In other words, the total area of ​​the diode section 80 corresponds to 50% of the total area of ​​the transistor section 70 and the diode section 80.

[0107] Distribution D3 shows the current density distribution when semiconductor device 500 is used. In this example, semiconductor device 500 shows a case where the ratio of the total area of ​​transistor section 570 to the total area of ​​diode section 580 is 20:6. In other words, the total area of ​​diode section 580 corresponds to approximately 23% of the total area of ​​transistor section 570 and diode section 580.

[0108] Comparing distributions D1 to D3, the maximum value of the current density decreases as the ratio of the diode section 80 increases. That is, in the semiconductor device 100, the maximum value of the current density can be reduced by making the total area of ​​the diode sections 80 equal to or greater than the total area of ​​the transistor sections 70.

[0109] 7B is a graph showing the turn-off waveforms of the semiconductor device 100 and the semiconductor device 500. This graph shows the collector current Ic [A / cm 2 ] and the collector-emitter voltage Vce over time. The collector current Ic of the semiconductor device 100 is larger than the collector current Ic of the semiconductor device 500. That is, the semiconductor device 100 can achieve switching at a higher current density than the semiconductor device 500 by making the width of the diode portion 80 larger than the width of the transistor portion 70.

[0110] 8A to 8D are diagrams for comparing the conduction current density distribution when the ratio of the gate trench portion G to the emitter trench portion E is changed. The vertical axis represents the conduction current density distribution [A / cm 2 ], and the horizontal axis indicates the position in the Y-axis direction near the transistor portion and the diode portion. The gate trench portion G is a trench portion electrically connected to the gate metal layer 50 and provided in contact with the emitter region 12. The emitter trench portion E is a trench portion electrically connected to the emitter electrode 52.

[0111] 8A shows the conduction current density distribution of a full-gate semiconductor device. In the semiconductor device of this example, all trench portions are gate trench portions G. That is, in the semiconductor device of this example, all trench portions are electrically connected to the gate metal layer 50.

[0112] 8B shows the conduction current density distribution of a semiconductor device having emitter trenches E. In this example, the semiconductor device has gate trenches G and emitter trenches E in a ratio of 2:1. That is, in this example, the number of gate trenches G is greater than the number of emitter trenches E.

[0113] 8C shows the conduction current density distribution of a semiconductor device having emitter trenches E. In the semiconductor device 500 of this example, the gate trenches G and the emitter trenches E are provided in a ratio of 1:1. That is, in the semiconductor device of this example, the number of gate trenches G is equal to the number of emitter trenches E.

[0114] 8D shows the conduction current density distribution of a semiconductor device having emitter trenches E. In the semiconductor device 500 of this example, the gate trenches G and the emitter trenches E are provided in a ratio of 1:2. That is, in the semiconductor device of this example, the number of gate trenches G is smaller than the number of emitter trenches E.

[0115] 8A to 8D, the conduction current density distribution tends to broaden as the ratio of the emitter trench portion E increases relative to the gate trench portion G. For example, the conduction current density distribution in FIG. 8A tends to be localized in a specific region compared to other examples. Furthermore, increasing the ratio of the emitter trench portion E reduces the channel region, which tends to increase the maximum value of the conduction current.

[0116] Here, we will show an example of a method for designing a semiconductor device 100 that suppresses current concentration while reducing the effects of noise. In a full-gate semiconductor device, all trenches are electrically connected to the gate metal layer 50, which can cause fluctuations in the potential around the trenches. For this reason, it is preferable for the semiconductor device to have both a gate trench G and an emitter trench E. However, as shown in Figures 8A to 8D, increasing the ratio of the emitter trench E to the gate trench G tends to increase the maximum value of the conduction current density distribution.

[0117] In order to suppress the maximum value of the conduction current density distribution, increasing the ratio of the total area of ​​the diode section 80 to the total area of ​​the transistor section 70 can suppress breakdown of the semiconductor device 100. In particular, in this Example 1, the boundary region 81 is provided in the diode section 80. By providing the boundary region 81 in the diode section 80, the cathode region 82 becomes relatively longer and the collector region 22 becomes relatively shorter. Therefore, electrons emitted from the emitter region 12 can more easily flow into the cathode region 82, effectively reducing the maximum value of the current density.

[0118] On the other hand, increasing the ratio of the total area of ​​the diode section 80 to the total area of ​​the transistor section 70 reduces the gate-emitter capacitance. Therefore, by providing the dummy trench section 30 in the boundary region 81, the semiconductor device 100 can ensure the gate-emitter capacitance while alleviating current concentration by increasing the diode section 80. This makes it possible to realize a semiconductor device 100 that is less susceptible to noise while suppressing element destruction due to current concentration.

[0119] The dummy trench portion 30 described above is not limited to the boundary region 81 where the transistor portion 70 and the diode portion 80 are adjacent, and may be provided so as to extend in the X-axis direction toward the edge termination region 102 of the transistor portion 70 adjacent to the edge termination region 102. That is, a dummy trench portion 30 that does not contact the emitter region 12 may be provided on the edge termination region 102 side of the transistor portion 70 adjacent to the edge termination region 102. The edge termination region 102 side of the transistor portion 70 on which this dummy trench portion 30 is provided is illustrated by a dashed line as an edge-adjacent region 84. The edge-adjacent region 84 is a region adjacent to the edge termination region 102 on the positive or negative side of the transistor portion 70 in the Y-axis direction. This ensures gate-emitter capacitance and forms an ineffective region that does not function as a transistor on the edge termination region 102 side of the transistor portion 70, thereby suppressing carrier concentration. Therefore, the number of dummy trench portions 30 inserted in the edge adjacent region 84 may be greater than the number of dummy trench portions 30 inserted in the boundary region 81. Furthermore, dummy trench portions 30 may be provided only in the edge adjacent region 84. When providing dummy trench portions 30 in the edge adjacent region 84, the width Wt of the transistor portion 70 in the Y-axis direction and the width Wd of the diode portion 80 in the Y-axis direction are not limited.

[0120] 9 shows an example of the configuration of a semiconductor device 100 according to Example 3. The semiconductor device 100 of this example differs from the semiconductor device 100 of Example 1 in that it includes an upper surface lifetime killer 95 and a lower surface lifetime killer 96.

[0121] The upper surface lifetime killer 95 and the lower surface lifetime killer 96 are used to adjust the carrier lifetime. The upper surface lifetime killer 95 and the lower surface lifetime killer 96 are provided by implanting ions from the upper surface side or the lower surface side of the semiconductor substrate 10. For example, the upper surface lifetime killer 95 and the lower surface lifetime killer 96 are formed by implanting helium.

[0122] The top surface lifetime killer 95 is provided on the top surface side of the semiconductor substrate 10. For example, the top surface lifetime killer 95 of Example 3 is provided in the diode section 80. The top surface lifetime killer 95 of this example is provided extending from the non-boundary region 83 to at least a part of the boundary region 81. The top surface lifetime killer 95 reduces the carrier lifetime on the anode region side of the diode section 80, thereby reducing the tail current and the reverse recovery loss Err.

[0123] The top surface lifetime killer 95 may or may not be provided in the transistor section 70. That is, in this example, the top surface lifetime killer 95 is provided extending from the non-boundary region 83 to partway through the boundary region 81, but it may be provided extending to the boundary R, ​​or may be provided extending beyond the boundary R to the transistor section 70. Also, in this example, the region obtained by projecting the collector region provided on the lower surface side of the semiconductor substrate 10 onto the top surface of the semiconductor substrate 10 is the transistor section 70, and the region obtained by projecting the cathode region 82 onto the top surface of the semiconductor substrate 10 but other than the transistor section 70 is the diode section 80. However, the region where the top surface lifetime killer 95 is not provided may be the transistor section 70, and the region where the top surface lifetime killer 95 is provided may be the diode section 80.

[0124] The bottom surface lifetime killer 96 is provided on the bottom surface side of the semiconductor substrate 10. In this example, the bottom surface lifetime killer 96 is provided in both the transistor portion 70 and the diode portion 80. The concentration of the bottom surface lifetime killer 96 may be lower on the transistor portion 70 side than on the diode portion 80 side. For example, the concentration of the bottom surface lifetime killer 96 in the boundary region 81 of the diode portion 80 is lower than the concentration of the bottom surface lifetime killer 96 in the non-boundary region 83 of the diode portion 80. This makes it easier for current to flow in the cathode region 82, and current concentration in the transistor portion 70 is more easily alleviated.

[0125] The cathode region 82 is provided so as to extend closer to the transistor section 70 than the upper surface lifetime killer 95. This allows current to flow more easily through the cathode region 82, and current concentration in the transistor section 70 is more likely to be alleviated.

[0126] Furthermore, the concentration of the cathode region 82 may be higher on the transistor section 70 side than on the diode section 80 side. For example, the concentration of the cathode region 82 in the boundary region 81 of the diode section 80 is higher than the concentration of the cathode region 82 in the non-boundary region 83 of the diode section 80. This makes it easier for current to flow through the cathode region 82, and current concentration in the transistor section 70 is more likely to be alleviated.

[0127] 10 shows an example of the configuration of a semiconductor device 100 according to Example 4. The semiconductor device 100 of this example differs from the semiconductor device 100 of Example 1 in the structure of the boundary region 81.

[0128] The accumulation region 16 is provided in the transistor portion 70. However, the accumulation region 16 is not provided in the boundary region 81. That is, the accumulation region 16 is not provided in the second mesa portion 92 adjacent to the dummy trench portion 30. On the other hand, a contact region 15 is provided in the second mesa portion 92. Since the semiconductor device 100 of this example does not have an accumulation region 16 in the second mesa portion 92 sandwiched between the dummy trench portions 30, holes can be easily extracted to the emitter electrode 52 in the boundary region 81.

[0129] 11 shows an example of the configuration of a semiconductor device 100 according to Example 5. The semiconductor device 100 of this example differs from the semiconductor device 100 of Example 1 in the structure of the dummy trench portion 30.

[0130] The dummy trench portion 30 has a different shape from the gate trench portion 40 and the emitter trench portion 60. The dummy trench portion 30 of this example can adjust the gate-emitter capacitance of the semiconductor device 100 by adjusting the insulating film in the trench and the trench depth.

[0131] The thickness of the dummy insulating film 32 is thinner than the gate insulating film 42 and the emitter insulating film 62. This increases the gate-emitter capacitance of the semiconductor device 100. In this example, the thickness of the dummy insulating film 32 is reduced without changing the width of the trenches formed on the upper surface side of the semiconductor substrate 10. However, the width of the trenches for providing the gate trench portion 40 and the emitter trench portion 60 may be increased to increase the thicknesses of the gate insulating film 42 and the emitter insulating film 62, thereby relatively reducing the thickness of the dummy insulating film 32.

[0132] The trench depth of the dummy trench portion 30 is deeper than the trench depth of the gate trench portion 40 and the trench depth of the emitter trench portion 60. This increases the gate-emitter capacitance of the semiconductor device 100. Note that, although the trench depth of the dummy trench portion 30 is deep in this example, the trench depth of the dummy trench portion 30 may be relatively deep by shallowing the depths of the trenches for providing the gate trench portion 40 and the emitter trench portion 60.

[0133] In the semiconductor device 100 of this example, the gate-emitter capacitance can be increased by reducing the film thickness of the dummy insulating film 32 and deepening the trench depth of the dummy trench portion 30. This reduces the effect of noise on the semiconductor device 100. Note that the gate-emitter capacitance of the semiconductor device 100 may also be increased by adjusting either the film thickness of the dummy insulating film 32 or the trench depth of the dummy trench portion 30.

[0134] 12 is an example of a top view of a semiconductor device 200 according to a sixth embodiment. The semiconductor device 200 of this embodiment includes a transistor unit 70 and a current sense unit 210. The structure of the transistor unit 70 may be the same as the structure of any of the transistor units 70 described in FIGS. 1A to 11 , or may be the same as the structure of a portion of the transistor unit 70 of any of the embodiments, or may be a different embodiment.

[0135] The transistor section 70 of this example has a gate trench section 40 and an emitter trench section 60. The mesa section in contact with the gate trench section 40 and the mesa section in contact with the emitter trench section 60 may have the same structure as the first mesa section 91 described with reference to Figures 1A to 11. The transistor section 70 may also include a dummy trench section 30 and a second mesa section 92 in contact with the dummy trench section 30.

[0136] The semiconductor device 200 may further include a diode section 80. In this case, the arrangement of the transistor section 70 and the diode section 80 may be the same as that of the semiconductor device 100 described with reference to Figures 1A to 11. In this example, the gate trench section 40, the emitter trench section 60, and the dummy trench section 30 are also provided extending in the X-axis direction and arranged in the Y-axis direction.

[0137] In this example, a gate pad 208 connected to the gate wiring portion 46, a current sense pad 202 connected to a current sense portion 210, an anode pad 204, and a cathode pad 206 are provided on the upper surface of the semiconductor substrate 10. The anode pad 204 and the cathode pad 206 are pads connected to a temperature detection portion arranged above the upper surface of the semiconductor substrate 10. The temperature detection portion is, for example, a PN diode formed of polysilicon or the like. Note that the pads arranged on the upper surface of the semiconductor substrate 10 are not limited to these.

[0138] As described above, each pad is arranged in the outer region 104. The current sense unit 210 may also be arranged in the outer region 104. At least a portion of the current sense unit 210 may be sandwiched between any two pads in a top view. By providing the current sense unit 210 in the outer region 104, it is possible to prevent a reduction in the area of ​​the transistor unit 70, etc.

[0139] In this example, the gate pad 208 and the current sense unit 210 and current sense pad 202 are arranged on opposite sides of the upper surface of the semiconductor substrate 10. In the example of FIG. 12, the outer region 104-1 in which the gate pad 208 is provided and the outer region 104-2 in which the current sense unit 210 and current sense pad 202 are provided are arranged on either side of the transistor unit 70 in the Y-axis direction. The anode pad 204 and cathode pad 206 may be arranged in the outer region 104-2. However, the arrangement of the pads is not limited to the example of FIG. 12. The arrangement of the pads may be the same as that of the semiconductor device 100 described with reference to FIGS. 1A to 11.

[0140] The gate wiring section 46 has a gate metal layer 50 and a gate runner 48. The gate metal layer 50 is arranged to surround the transistor section 70 (if a diode section 80 is provided, the transistor section 70 and the diode section 80) in a top view. The gate runner 48 may be arranged along the gate metal layer 50. The gate runner 48 may be arranged to at least partially overlap below the gate metal layer 50. The gate runner 48 may be arranged across the transistor section 70. The gate runner 48 may be arranged along the outer region 104. The gate runner 48 is connected to the gate trench section 40 and the dummy trench section 30 and transmits a gate voltage.

[0141] The current sense unit 210 detects the current flowing through the transistor unit 70. The current sense unit 210 of this example includes at least one gate trench unit 40 and a first mesa unit 91. In the current sense unit 210 of this example, the trenches also extend in the X-axis direction and are arranged in the Y-axis direction. However, the extension direction and arrangement direction of the trenches of the current sense unit 210 may differ from the extension direction and arrangement direction of the trenches of the transistor unit 70.

[0142] The current sense unit 210 of this example has a similar structure to the transistor unit 70, and thus simulates the current flowing through the transistor unit 70 at a ratio according to the channel area ratio when viewed from above. The area of ​​the current sense unit 210 when viewed from above is smaller than the area of ​​the transistor unit 70. The area of ​​the current sense unit 210 may be smaller than the area of ​​each pad, such as the gate pad 208, arranged on the upper surface of the semiconductor substrate 10.

[0143] In this example, the value G / E obtained by dividing the number G of gate trenches 40 included in a unit length in the arrangement direction of each trench by the number E of emitter trenches 60 is referred to as the gate-emitter ratio. Note that when dummy trenches 30 are provided, the gate-emitter ratio may be (G+D) / E obtained by dividing the sum of the number G of gate trenches 40 and the number D of dummy trenches 30 by the number E of emitter trenches 60.

[0144] The gate-emitter ratio of the current sense section 210 is greater than that of the transistor section 70. That is, the gate trench sections 40 are arranged at a higher density in the current sense section 210 than in the transistor section 70. The gate-emitter ratio of the current sense section 210 may be calculated from the number of all trench sections arranged in the Y-axis direction in the current sense section 210. The gate-emitter ratio of the transistor section 70 may also be calculated from the number of all trench sections arranged in the Y-axis direction in the transistor section 70.

[0145] The current sense section 210 has a smaller area than the transistor section 70, and therefore tends to have a lower dielectric strength. In response to this, by increasing the gate-emitter ratio of the current sense section 210, the capacitance of the insulating film between the gate and emitter in the current sense section 210 can be increased. This makes it possible to suppress a voltage rise even when charge is injected into each electrode due to ESD (electrostatic discharge) or the like. This increases the dielectric strength of the current sense section 210. Furthermore, if the current sense section 210 does not have an emitter trench section 60, the screening test of the emitter trench section 60 of the current sense section 210 can be omitted.

[0146] 13 is a diagram showing an example of a cross section of the transistor section 70. FIG. 13 shows a YZ cross section passing through the emitter region 12. In this example, the transistor section 70 has one gate trench section 40 and one emitter trench section 60 arranged alternately along the Y-axis direction. In this case, the gate-emitter ratio of the transistor section 70 is 1 / 1=1.

[0147] Each contact hole 54 may be provided with a barrier metal 57. The barrier metal 57 may include at least one of a titanium film and a titanium nitride film. The barrier metal 57 may be provided to cover the interlayer insulating film 38. Furthermore, a tungsten plug 58 may be provided in each contact hole 54. The barrier metal 57 and the tungsten plug 58 may also be provided in the semiconductor device 100 described with reference to FIGS. 1A to 11.

[0148] FIG. 14 is a diagram showing an example of a cross section of the current sense unit 210. FIG. 14 shows a YZ cross section passing through the emitter region 12. In the current sense unit 210 of this example, gate trenches 40 are continuously arranged along the Y-axis direction, and no emitter trenches 60 are provided. That is, all trenches in the current sense unit 210 of this example are gate trenches 40. In this case, the gate-emitter ratio of the current sense unit 210 is 1 / 0, which is an infinite value. Even in the current sense unit 210 of this example, several emitter trenches 60 may be provided at both ends of the trench arrangement direction (Y-axis direction). The gate-emitter ratio of the current sense unit 210 may be two or more times, or even ten or more times, the gate-emitter ratio of the transistor unit 70.

[0149] Furthermore, in each of the current sense unit 210 and the transistor unit 70, the value obtained by dividing the area of ​​the accumulation region 16 in a top view by the area of ​​the emitter region 12 is referred to as the area ratio of the accumulation region 16. In other words, the area ratio of the accumulation region 16 in the current sense unit 210 is the value obtained by dividing the total area of ​​the accumulation regions 16 included in the current sense unit 210 in a top view by the total area of ​​the emitter regions 12 included in the current sense unit 210. Similarly, the area ratio of the accumulation region 16 in the transistor unit 70 is the value obtained by dividing the total area of ​​the accumulation regions 16 included in the transistor unit 70 in a top view by the total area of ​​the emitter regions 12 included in the transistor unit 70.

[0150] The area ratio of the accumulation region 16 in the current sense unit 210 is preferably smaller than the area ratio of the accumulation region 16 in the transistor unit 70. By reducing the area ratio of the accumulation region 16 included in the current sense unit 210, the IE effect in the current sense unit 210 can be reduced, and a decrease in clamp voltage due to minority carrier accumulation can be suppressed. Therefore, even if the voltage is clamped in the transistor unit 70 during turn-off, for example, the occurrence of avalanche in the current sense unit 210 can be suppressed, and breakdown in the current sense unit 210 can be suppressed. Furthermore, by reducing the area ratio of the accumulation region 16 in the current sense unit 210, excessively steep fluctuations in the voltage waveform in the current sense unit 210 can be suppressed. Therefore, imbalances in operation within the current sense unit 210 can be suppressed, and breakdown of the current sense unit 210 can be suppressed.

[0151] In the example of Fig. 13, the transistor section 70 is provided with both the emitter region 12 and the accumulation region 16. In the example of Fig. 14, the current sense section 210 is provided with the emitter region 12 but is not provided with the accumulation region 16. In other words, the area ratio of the accumulation region 16 in the current sense section 210 shown in Fig. 14 is zero. The area ratio of the accumulation region 16 in the current sense section 210 may be half or less of the area ratio of the accumulation region 16 in the transistor section 70, or may be 1 / 10 or less.

[0152] 15 is an enlarged top view of the vicinity of the outer region 104-2. As described above, the gate runner 48 is provided to surround the outer region 104-2. In this example, the gate runner 48 has a crossing portion 47 that crosses the outer region 104-2 in a top view. In this example, the crossing portion 47 crosses the outer region 104-2 in the Y-axis direction. The crossing portion 47 connects two gate runners 48 that are provided along both ends of the outer region 104-2 in the Y-axis direction. The crossing portion 47 may be provided so as not to overlap the anode pad 204 and the cathode pad 206.

[0153] The gate wiring portion 46 has an opening 212 that penetrates from the top surface to the bottom surface of the gate wiring portion 46. In this example, the opening 212 is provided in the crossing portion 47 of the gate runner 48. The opening 212 penetrates the polysilicon gate runner 48. In FIG. 15, the area of ​​the gate runner 48 other than the opening 212 is hatched with diagonal lines.

[0154] The current sense unit 210 is arranged below the gate runner 48 in a region where at least a portion overlaps with the opening 212. The current sense unit 210 may be arranged so that at least a portion overlaps with a region of the gate runner 48 other than the opening 212. In the example of FIG. 15 , the entire current sense unit 210 is arranged so as to overlap with either the opening 212 or the gate runner 48. By arranging the current sense unit 210 below the gate runner 48, the gate trench portion 40 of the current sense unit 210 can be easily connected to the gate runner 48.

[0155] Furthermore, since at least a portion of the current sense unit 210 is exposed through the opening 212, the current sense unit 210 and the current sense pad 202 can be easily connected. At least a portion of the current sense pad 202 may be provided in the opening 212. In this example, the current sense pad 202 may be provided so as to extend from a position that does not overlap with the gate runner 48, passing above the gate runner 48, to the opening 212. In FIG. 15, the portion of the current sense pad 202 that is provided above the gate runner 48 is indicated by a dashed line. The current sense pad 202 and the gate runner 48 are insulated from each other by an interlayer insulating film or the like. The current sense pad 202 may be provided so as to cover the entire opening 212.

[0156] FIG. 16 is an enlarged top view of the vicinity of the opening 212. The current sense pad 202 is omitted from FIG. 16. In this example, a first well region 220 and a second well region 218 are provided in the semiconductor substrate 10. The first well region 220 and the second well region 218 are P+ type regions that extend from the upper surface of the semiconductor substrate 10 to a depth deeper than the lower end of the trench portion. The first well region 220 corresponds to the well region 11 of the semiconductor device 100 described with reference to FIGS. 1A to 11.

[0157] The first well region 220 is provided to surround the transistor section 70 (or the transistor section 70 and the diode section 80 if the diode section 80 is provided) in a top view. The second well region 218 is provided to surround the current sense section 210 in a top view. In this example, the second well region 218 is part of the current sense section 210. In other words, the outer periphery edge of the second well region 218 in a top view coincides with the outer periphery edge of the current sense section 210 in a top view.

[0158] The first well region 220 and the second well region 218 are arranged separately. For example, an N-type region such as the drift region 18 may be provided between the first well region 220 and the second well region 218.

[0159] The current sensing section 210 of this example has an emitter arrangement region 216 and a non-emitter arrangement region 214. The emitter arrangement region 216 is a region in which the emitter regions 12 are periodically arranged in a top view. For example, in the emitter arrangement region 216, as shown in FIG. 1A etc., the emitter regions 12 and the contact regions 15 are alternately arranged along the X-axis direction. The emitter arrangement region 216 may be a region that includes the center of the current sensing section 210 in a top view.

[0160] The non-emitter region 214 is a region where the emitter region 12 is not provided. A P-type region may be exposed on the upper surface of the non-emitter region 214. The P-type region may have the same doping concentration as the contact region 15, the same doping concentration as the base region 14, or a different doping concentration.

[0161] The emitter-free region 214 is provided to surround the emitter-placement region 216 in a top view. As an example, the emitter-placement region 216 and the emitter-free region 214 have a rectangular outer shape in a top view. The emitter-free region 214 is surrounded by the second well region 218 in a top view.

[0162] In the emitter placement region 216 and the non-emitter placement region 214, trench portions such as the gate trench portion 40 and each mesa portion are arranged. In FIG. 16, some of the trench portions are indicated by dashed lines. Each trench portion is provided extending in the X-axis direction. When the emitter placement region 216 and the non-emitter placement region 214 are arranged side by side in the X-axis direction, the trench portion may be provided continuously across both the emitter placement region 216 and the non-emitter placement region 214. The end of the gate trench portion 40 in the X-axis direction may be provided inside the second well region 218. This makes it possible to alleviate electric field concentration at the end of the gate trench portion 40.

[0163] The end of the gate trench 40 in the X-axis direction is preferably located at a position overlapping the gate runner 48. In other words, the end of the gate trench 40 is preferably located outside the opening 212. This allows the gate trench 40 and the gate runner 48 to be easily connected.

[0164] The emitter placement region 216 and the emitter non-placement region 214 may be entirely exposed by the opening 212. This allows the emitter placement region 216 and the emitter non-placement region 214 to be entirely connected to the current sense pad 202.

[0165] 16, the end of the opening 212 in top view is located above the second well region 218. In other examples, the end of the opening 212 may be located above the emitter-free region 214.

[0166] Fig. 17 is a top view illustrating the distance between the second well region 218 and the emitter-placement region 216. In Fig. 17, structures other than the second well region 218, the emitter-placement region 216, and the emitter-free region 214 are omitted.

[0167] In the X-axis direction, the shortest distance between the emitter placement region 216 and the second well region 218 is defined as X1s, and the length of the emitter placement region 216 is defined as X2s. The distance X1s is the shortest distance between the emitter region 12 arranged at the outermost position in the X-axis direction within the emitter placement region 216 and the second well region 218. The length X2s is the maximum distance in the X-axis direction between the emitter regions 12 arranged at both ends in the X-axis direction within the emitter placement region 216.

[0168] In the Y-axis direction, the shortest distance between the emitter placement region 216 and the second well region 218 is defined as Y1s, and the width of the emitter placement region 216 is defined as Y2s. The distance Y1s is the shortest distance between the emitter region 12 located at the outermost position in the Y-axis direction within the emitter placement region 216 and the second well region 218. The length Y2s is the maximum distance between the emitter regions 12 located at both ends in the Y-axis direction within the emitter placement region 216.

[0169] The current sense unit 210 of this example has a higher gate-emitter ratio than the transistor unit 70. Therefore, compared to when the current sense unit 210 has the same gate-emitter ratio as the transistor unit 70, even if the area of ​​the emitter arrangement region 216 is made smaller, an equivalent channel area can be ensured. Because the area of ​​the emitter arrangement region 216 can be made smaller, the distances X1s and Y1s between the second well region 218 and the emitter region 12 can be increased, making it easier to separate the current flowing in the current sense unit 210 from the current flowing in other regions.

[0170] For example, the distance X1s may be 10% or more, or 20% or more, of the length X2s, and the distance Y1s may be 10% or more, or 20% or more, or 30% or more, of the width Y2s.

[0171] Fig. 18 is a diagram illustrating the distance X1s. Fig. 18 is a top view showing an overview of region A in Fig. 16. Region A is a region that includes an emitter-placement region 216, a non-emitter region 214, and a second well region 218 that are arranged side by side in the X-axis direction.

[0172] As described above, the distance X1s is the shortest distance between the emitter region 12 arranged outermost in the X-axis direction and the second well region 218. At least one of the contact region 15 and the base region 14 may be provided between the emitter region 12 and the second well region 218. In the example of FIG. 18 , the base region 14 is arranged in more than half of the region between the outermost emitter region 12 and the second well region 218 in the X-axis direction. In another example, the contact region 15 may be arranged in more than half of the region between the outermost emitter region 12 and the second well region 218 in the X-axis direction. Note that the base region 14 and the contact region 15 may be arranged in the entire region between the outermost emitter region 12 and the second well region 218 in the X-axis direction.

[0173] Fig. 19 is a diagram illustrating the distance Y1s. Fig. 19 is a top view showing an overview of region B in Fig. 16. Region B is a region that includes an emitter-placement region 216, a non-emitter region 214, and a second well region 218 that are arranged side by side in the Y-axis direction.

[0174] As described above, the distance Y1s is the shortest distance between the emitter region 12 located outermost in the Y-axis direction and the second well region 218. At least one of the contact region 15 and the base region 14 may be provided between the emitter region 12 and the second well region 218. Note that, as some trench portions are indicated by dashed lines in FIG. 16 , gate trench portions 40 and emitter trench portions 60 extending in the X-axis direction may be provided within the range of the distance Y1s in this example.

[0175] 20 is a diagram illustrating the distance X1t in the transistor section 70. Fig. 20 partially illustrates a top view of the transistor section 70. The distance X1t is the shortest distance in the X-axis direction between the outermost emitter region 12 in the X-axis direction and the first well region 220 in the transistor section 70.

[0176] 18 may be greater than the distance X1t in the transistor section 70. As described above, increasing the distance X1s in the current sense section 210 makes it easier to separate the current flowing in the current sense section 210 from the current flowing in other regions. The distance X1s may be at least twice the distance X1t, or may be at least five times the distance X1t.

[0177] Fig. 21 is a diagram showing another example of the configuration of region A in Fig. 16. In Fig. 21, the length in the X-axis direction of the base region 14 that contacts the second well region 218 of the current sense unit 210 is denoted by Xb, and the distance between the outermost emitter region 12 and the base region 14 is denoted by Xc. In this example, too, the distance X1s in the current sense unit 210 is greater than the distance X1t in the transistor unit 70.

[0178] 18, the length Xb of the base region 14 in contact with the second well region 218 of the current sense unit 210 is longer than the length of the base region 14 in contact with the first well region 220 of the transistor unit 70. In other words, by making the base region 14 of the current sense unit 210 longer than the base region of the transistor unit 70, the distance X1s between the second well region 218 and the outermost emitter region 12 is increased.

[0179] In this example, the distance Xc between the outermost emitter region 12 and the base region 14 in contact with the second well region 218 is set to be greater than the distance between the outermost emitter region 12 and the base region 14 in contact with the first well region 218 in the transistor section 70. This allows the distance X1s in the current sensing section 210 to be greater than the distance X1t in the transistor section 70.

[0180] In the current sensing section 210, a contact region 15 may be provided between the outermost emitter region 12 and the base region 14 in contact with the second well region 218. In other words, the distance Xc is the length of the contact region 15 arranged between the outermost emitter region 12 and the base region 14 in contact with the second well region 218. In the current sensing section 210, the length Xc of the contact region 15 arranged outermost in the X-axis direction may be greater than the length of the contact region 15 arranged outermost in the X-axis direction in the transistor section 70.

[0181] 22 is a diagram illustrating the distance Y1t in the transistor section 70. FIG. 22 partially illustrates a top view of the transistor section 70. The distance Y1t is the shortest distance in the Y-axis direction between the outermost emitter region 12 in the Y-axis direction and the first well region 220 in the transistor section 70. Note that, as in FIG. 19 , the gate trench portion 40 and the emitter trench portion 60 extending in the X-axis direction may be provided within the range of the distance Y1t in this example.

[0182] 19 may be greater than the distance Y1t in the transistor section 70. As described above, increasing the distance Y1s in the current sense section 210 makes it easier to separate the current flowing in the current sense section 210 from the current flowing in other regions. The distance Y1s may be at least twice the distance Y1t, or may be at least five times the distance Y1t.

[0183] The current sensing section 210 of the semiconductor device 200 may be provided with a bottom surface lifetime killer 96, similar to the transistor section 70. The current sensing section 210 may also be provided with a top surface lifetime killer 95. For example, if the transistor section 70 is provided with a top surface lifetime killer 95, the current sensing section 210 will also be provided with a top surface lifetime killer 95.

[0184] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the claims that such modifications and improvements can also be included within the technical scope of the present invention.

[0185] The present specification and drawings also disclose the embodiments described in the following items. (Item 1) A semiconductor device having a transistor portion and a diode portion, the transistor section and the diode section are formed in adjacent regions, and a boundary region is provided to prevent interference between the transistor section and the diode section; the transistor section and the diode section each include a plurality of trench sections arranged in a predetermined arrangement direction, the diode section includes a cathode region of a first conductivity type on a surface opposite to the front surface side of the semiconductor substrate, a width of the diode section in the arrangement direction is larger than a width of the transistor section in the arrangement direction; The cathode region is provided so as to extend to the boundary region in the arrangement direction. Semiconductor device. (Item 2) The width of the diode portion in the arrangement direction is 1500 μm or more. Item 1. The semiconductor device according to item 1. (Item 3) a plurality of transistor portions and a plurality of diode portions; The total area of ​​the plurality of diode sections is greater than the total area of ​​the plurality of transistor sections. Item 3. The semiconductor device according to item 1 or 2. (Item 4) a gate metal layer disposed above a top surface of the semiconductor substrate; an emitter electrode provided above the upper surface of the semiconductor substrate; an emitter region of a first conductivity type provided on an upper surface side of the semiconductor substrate in the transistor portion; a gate trench portion provided on an upper surface side of the semiconductor substrate in the transistor portion, electrically connected to the gate metal layer, and in contact with the emitter region; an emitter trench portion provided on the upper surface side of the semiconductor substrate in the diode portion and electrically connected to the emitter electrode, The emitter trench portions are also arranged at a regular interval between the gate trench portions in the transistor portion. Item 4. The semiconductor device according to any one of items 1 to 3. (Item 5) a dummy trench portion provided on the upper surface side of the semiconductor substrate, electrically connected to the gate metal layer, and not in contact with the emitter region; Item 5. The semiconductor device according to item 4. (Item 6) The boundary region is a region having a device structure different from the device structure of the transistor section and the device structure of the diode section. Item 6. The semiconductor device according to any one of items 1 to 5. (Item 7) an interlayer insulating film provided above the upper surface of the semiconductor substrate; a contact hole provided in the interlayer insulating film between the trench portions in the transistor portion and the diode portion, into which an emitter electrode is embedded; The interlayer insulating film between the trench portions in the boundary region does not have the contact hole. 7. The semiconductor device according to any one of items 1 to 6. (Item 8) the diode portion has the boundary region and a non-boundary region, The concentration of the cathode region in the boundary region of the diode portion is higher than the concentration of the cathode region in the non-boundary region of the diode portion. 8. The semiconductor device according to any one of items 1 to 7. (Item 9) a bottom surface lifetime killer provided on the opposite side of the semiconductor substrate from the top surface side, the diode portion has the boundary region and a non-boundary region, The concentration of the bottom surface lifetime killer in the boundary region of the diode portion is lower than the concentration of the bottom surface lifetime killer in the non-boundary region of the diode portion. Item 9. The semiconductor device according to any one of items 1 to 8. (Item 10) Further, an upper surface lifetime killer is introduced into at least a non-boundary region of the diode portion on the upper surface side of the semiconductor substrate, The cathode region is provided so as to extend toward the transistor portion side beyond the upper surface lifetime killer. 10. The semiconductor device according to any one of items 1 to 9.

[0186] It should be noted that the execution order of each process, such as operations, procedures, steps, and stages, in the devices, systems, programs, and methods shown in the claims, specifications, and drawings is not specifically stated as "before," "prior to," etc., and that the processes can be performed in any order unless the output of a previous process is used in a subsequent process. Even if the operational flow in the claims, specifications, and drawings is described using "first," "next," etc. for convenience, this does not mean that the processes must be performed in this order. [Explanation of symbols]

[0187] 10 semiconductor substrate, 11 well region, 12 emitter region, 14 base region, 15 contact region, 16 accumulation region, 18 drift region, 20 buffer region, 21 upper surface, 22 collector region, 23 lower surface, 24 collector electrode, 25 connection portion, 30 dummy trench portion, 31 extension portion, 32 dummy insulating film, 33 connection portion, 34 dummy conductive portion, 38 Interlayer insulating film, 40...gate trench portion, 41...extension portion, 42...gate insulating film, 43...connection portion, 44...gate conductive portion, 46...gate wiring portion, 47...crossing portion, 48...gate runner, 49...contact hole, 50...gate metal layer, 52...emitter electrode, 54...contact hole, 56...contact hole, 57...barrier metal, 58...tungsten plug, 60...emitter trench portion , 61...extension portion, 62...emitter insulating film, 63...connection portion, 64...emitter conductive portion, 70...transistor portion, 80...diode portion, 81...boundary region, 82...cathode region, 83...non-boundary region, 84...edge adjacent region, 91...first mesa portion, 92...second mesa portion, 93...third mesa portion, 95...upper surface lifetime killer, 96...lower surface lifetime killer, 100...semiconductor device, 102...edge Termination region, 104...outside region, 200...semiconductor device, 202...current sense pad, 204...anode pad, 206...cathode pad, 208...gate pad, 210...current sense section, 212...opening, 214...emitter non-placement region, 216...emitter placement region, 218...second well region, 220...first well region, 500...semiconductor device, 570...transistor section, 580...diode section

Claims

1. A semiconductor device comprising: an N- type drift region provided in a semiconductor substrate; a plurality of trench portions provided on the upper surface side of the semiconductor substrate; a plurality of mesa portions provided between the plurality of trench portions; a P- type base region provided in the mesa portion; an N+ type region provided between the base region and an upper surface of at least one of the mesa portions; a gate metal layer provided above the upper surface of the semiconductor substrate; and an upper surface electrode provided above the upper surface of the semiconductor substrate, The plurality of trench portions include: a first trench portion arranged along a predetermined arrangement direction and electrically connected to the gate metal layer; second trench portions arranged along a predetermined arrangement direction and electrically connected to the upper surface electrodes; Including, The semiconductor device includes a transistor portion having a pattern in which at least three of the first trench portions are continuously arranged in the arrangement direction, the pattern including a gate trench portion in contact with the N+ type region and a dummy trench portion not in contact with the N+ type region; an interlayer insulating film interposed between the upper surface of the semiconductor substrate and the gate metal layer and the upper surface electrode; The plurality of mesas include: a first mesa portion connected to the upper electrode via a contact hole formed in the interlayer insulating film in a cross section passing through the N+ type region in the arrangement direction; a second mesa portion adjacent to the dummy trench portion in the cross section and having an upper surface covered with the interlayer insulating film, a first region including one or more of the first mesas; a second region including two or more of the second mesas and the pattern; the second regions are disposed on both sides of the first region in the arrangement direction, The second trench portion is provided in the first region. Semiconductor device.

2. A semiconductor device comprising: an N- type drift region provided in a semiconductor substrate; a plurality of trench portions provided on the upper surface side of the semiconductor substrate; a plurality of mesa portions provided between the plurality of trench portions; a P- type base region provided in the mesa portion; an N+ type region provided between the base region and an upper surface of at least one of the mesa portions; a gate metal layer provided above the upper surface of the semiconductor substrate; and an upper surface electrode provided above the upper surface of the semiconductor substrate, The plurality of trench portions include: a first trench portion arranged along a predetermined arrangement direction and electrically connected to the gate metal layer; second trench portions arranged along a predetermined arrangement direction and electrically connected to the upper surface electrodes; Including, The semiconductor device includes a transistor portion having a pattern in which at least three of the first trench portions are continuously arranged in the arrangement direction, the pattern including a gate trench portion in contact with the N+ type region and a dummy trench portion not in contact with the N+ type region; the gate trench portion is disposed between the second trench portion and the dummy trench portion, an N-type accumulation region provided in the mesa portion between the drift region and the base region; In a cross section passing through the N+ type region in the arrangement direction, each of the dummy trench portions is in contact with the accumulation region on both sides. Semiconductor device.

3. A semiconductor device comprising: an N-type drift region provided in a semiconductor substrate; a plurality of trench portions provided on the upper surface side of the semiconductor substrate; a plurality of mesa portions provided between the plurality of trench portions; a P-type base region provided in the mesa portion; an N+ type region provided between the base region and an upper surface of at least one of the mesa portions; a gate metal layer provided above the upper surface of the semiconductor substrate; and an upper surface electrode provided above the upper surface of the semiconductor substrate, The plurality of trench portions include: a first trench portion arranged along a predetermined arrangement direction and electrically connected to the gate metal layer; second trench portions arranged along a predetermined arrangement direction and electrically connected to the upper surface electrodes; Including, The semiconductor device includes a transistor portion having a pattern in which at least three of the first trench portions are continuously arranged in the arrangement direction, the pattern including a gate trench portion in contact with the N+ type region and a dummy trench portion not in contact with the N+ type region; the gate trench portion is disposed between the second trench portion and the dummy trench portion, an N-type accumulation region provided in the mesa portion between the drift region and the base region; Among the plurality of mesa portions, the mesa portion adjacent to the dummy trench portion is not provided with the accumulation region. Semiconductor device.

4. A semiconductor device comprising: an N- type drift region provided in a semiconductor substrate; a plurality of trench portions provided on the upper surface side of the semiconductor substrate; a plurality of mesa portions provided between the plurality of trench portions; a P- type base region provided in the mesa portion; an N+ type region provided between the base region and an upper surface of at least one of the mesa portions; a gate metal layer provided above the upper surface of the semiconductor substrate; and an upper surface electrode provided above the upper surface of the semiconductor substrate, The plurality of trench portions include: a first trench portion arranged along a predetermined arrangement direction and electrically connected to the gate metal layer; second trench portions arranged along a predetermined arrangement direction and electrically connected to the upper surface electrodes; Including, The semiconductor device includes a transistor portion having a pattern in which at least three of the first trench portions are continuously arranged in the arrangement direction, the pattern including a gate trench portion in contact with the N+ type region and a dummy trench portion not in contact with the N+ type region; the gate trench portion is disposed between the second trench portion and the dummy trench portion, an N-type accumulation region provided in the mesa portion between the drift region and the base region; the semiconductor device is a reverse conducting IGBT having a diode portion, The diode portion has the accumulation region. Semiconductor device.

5. The pattern is periodically provided in the transistor section. The semiconductor device according to claim 1 .

6. The trench portion includes a trench provided on the upper surface side of the semiconductor substrate, polysilicon provided inside the trench, and an insulating film provided between an inner wall of the trench and the polysilicon; The semiconductor device according to claim 1 , further comprising:

7. Among the plurality of mesa portions, the mesa portion adjacent to the dummy trench portion is not provided with the N+ type region. The semiconductor device according to claim 1 .

8. A semiconductor device comprising: an N- type drift region provided in a semiconductor substrate; a plurality of trenches provided on the upper surface side of the semiconductor substrate; a plurality of mesa portions provided between the plurality of trenches; a P- type base region provided in the mesa portion; an N+ type region provided between the base region and an upper surface of at least one of the mesa portions; a gate metal layer provided above the upper surface of the semiconductor substrate; and an upper surface electrode provided above the upper surface of the semiconductor substrate, the plurality of trenches have a pattern in which a first trench, a second trench, and a third trench, each having polysilicon electrically connected to the gate metal layer provided therein, are successively arranged in a predetermined arrangement direction; the polysilicon includes first polysilicon adjacent to the N+ type region across an insulating film and forming a channel in the base region when a predetermined voltage is applied, and second polysilicon not adjacent to the N+ type region across an insulating film; The gate-emitter capacitance is adjusted by the ratio of the first polysilicon to the second polysilicon. Semiconductor device.

9. The mesa portion includes an N-type accumulation region provided between the drift region and the base region.

9. The semiconductor device according to claim 1.

10. The semiconductor substrate is a silicon substrate, a silicon carbide substrate, or a nitride semiconductor substrate. The semiconductor device according to claim 1 .

11. The semiconductor device is a reverse conducting IGBT having a diode portion.

10. The semiconductor device according to claim 1, wherein the first insulating film is a semiconductor material.

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