Semiconductor Devices

Abstract

To provide a semiconductor device having a semiconductor element having a main electrode and a control electrode on its main surface, and provide techniques for reducing the size of the control electrode.SOLUTION: A semiconductor device disclosed in this specification includes a semiconductor element having a main electrode and a control electrode formed on one main surface thereof, and a terminal substrate to which wires are bonded. A bonding terminal is formed on the front surface of the terminal substrate, a relay terminal is formed on the rear surface of the terminal substrate, and the bonding terminal and the relay terminal are electrically connected. The terminal substrate is joined to the semiconductor element such that the control electrodes and the relay terminals are in contact with each other. The area of the bonding terminal is larger than the area of the control electrode. A step is provided on the rear surface of the terminal substrate, and the side surface of the element substrate is in contact with the step. By providing a bonding terminal to which a wire is bonded on a substrate (terminal substrate) separate from the semiconductor element, the size of the control electrode can be reduced.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The technology disclosed in this specification relates to a semiconductor device. [Background technology]

[0002] In conventional semiconductor devices (particularly power semiconductor devices for power conversion), a main electrode and a control electrode are formed on one main surface of a semiconductor element. A current flowing through the control electrode is smaller than the current flowing through the main electrode, and therefore the area of ​​the control electrode is smaller than the area of ​​the main electrode. Patent Document 1 illustrates such a semiconductor device. In conventional semiconductor devices, a metal block is connected to the main electrode, and a wire (bonding wire) is joined to the control electrode. The bonding wire is often made of aluminum and has a diameter of about 500 μm.

[0003] Patent Document 2 discloses a wiring sheet that is attached to one main surface of a semiconductor element. An electrode terminal that connects to a main electrode and a control terminal that connects to a control electrode are arranged on one surface of the wiring sheet. A copper material is provided inside the wiring sheet, one end of which is connected to the control terminal. The other end of the copper material is connected to the control electrode terminal, which extends outward from the wiring sheet. Because the control electrode of the semiconductor element is connected to the copper material via the control terminal on the wiring sheet rather than via a wire, the distance between the main electrode and the control electrode can be shortened. A flexible printed circuit board is used for the wiring sheet. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2020-161807 [Patent Document 2] Japanese Patent Application Laid-Open No. 2013-073945 Summary of the Invention [Problem to be solved by the invention]

[0005] Because only a small current flows through the control electrode, in terms of current capacity, the control electrode can be significantly smaller than the main electrode. However, in conventional semiconductor devices, a wire (bonding wire) is bonded to the control electrode. To bond the wire, the control electrode needs to have an area larger than the cross-sectional area of ​​the wire. Making the control electrode wider just to bond the wire results in an unnecessary increase in the area of ​​the main surface of the semiconductor element. If the area of ​​the control electrode can be reduced, the area of ​​the main surface of the semiconductor element (i.e., the external dimensions of the semiconductor element) can be reduced. SiC substrates and GaN substrates, which have attracted attention in recent years, are expensive, so reducing the area of ​​the main surface leads to a reduction in the cost of the semiconductor device.

[0006] According to the technology of Patent Document 2, the area of ​​the control electrode can be reduced, and the area of ​​the main surface of the semiconductor element can be reduced accordingly. However, the technology of Patent Document 2 uses a flexible wiring sheet, making it difficult to align the control electrode of the semiconductor element with the terminal on the wiring sheet. The control electrode of the semiconductor element requires an area large enough to allow for positional error with the terminal on the wiring sheet. This specification provides a technology for reducing the area of ​​the control electrode in a semiconductor device compared to conventional technology. [Means for solving the problem]

[0007] The semiconductor device disclosed in this specification includes a semiconductor element having a main electrode and a control electrode arranged on one principal surface, and a terminal substrate to which wires are bonded. Bonding terminals are arranged on the front surface of the terminal substrate, and relay terminals are arranged on the back surface of the terminal substrate, and the bonding terminals and relay terminals are electrically connected. The terminal substrate is bonded to the semiconductor element so that the control electrode and relay terminal are in contact. The area of ​​the bonding terminal is larger than the area of ​​the control electrode. A step is provided on the back surface of the terminal substrate, and the side of the element substrate abuts against the step.

[0008] By providing the bonding terminals to which the wires are bonded on a substrate (terminal substrate) separate from the semiconductor element, the control electrodes on the main surface can be made smaller. Furthermore, by abutting the side of the semiconductor element against the step on the back surface of the terminal substrate, the position of the terminal substrate relative to the semiconductor element can be accurately determined. This reduces the positional error between the control electrodes of the semiconductor element and the relay terminals of the terminal substrate, allowing the control electrodes to be made smaller accordingly.

[0009] An example of a step is as follows: The terminal substrate has a thin plate portion including relay terminals and a thick plate portion including bonding terminals. The thickness of the thin plate portion is thinner than the thickness of the thick plate portion. On the back surface of the terminal substrate, the boundary between the thin plate portion and the thick plate portion corresponds to the step described above. The thin plate portion is bonded to the semiconductor element. Furthermore, it is preferable that the back surface of the terminal substrate in the thick plate portion is flush with the other main surface of the semiconductor element. If there is a flat surface below the semiconductor element and the thick plate portion, both the semiconductor element and the thick plate portion are supported by the flat surface. Therefore, when bonding a wire to the bonding terminal, the semiconductor element and the thick plate portion do not shift in the thickness direction.

[0010] A protrusion may be provided on the rear surface of the terminal substrate, and the protrusion may form the step described above. Details and further improvements of the technology disclosed in this specification will be described in the following "Mode for Carrying Out the Invention". [Brief explanation of the drawings]

[0011] [Figure 1] 1 is a perspective view of a semiconductor device according to a first embodiment; [Figure 2] FIG. 2 is an exploded perspective view of the semiconductor device (a resin package is not shown). [Figure 3] FIG. 2 is a perspective view of a semiconductor element and a terminal substrate. [Figure 4] FIG. 2 is a plan view of the semiconductor device (the resin package and the upper heat sink are not shown). [Figure 5] FIG. 5 is a cross-sectional view taken along line VV in FIG. [Figure 6] FIG. 10 is a perspective view of a terminal board according to a first modified example. [Figure 7]FIG. 10 is a perspective view of a terminal board according to a second modified example. [Figure 8] FIG. 10 is a cross-sectional view of a semiconductor device to which a terminal substrate according to a second modified example is attached. DETAILED DESCRIPTION OF THE INVENTION

[0012] (First embodiment) A semiconductor device 2 of the first embodiment will be described with reference to the drawings. Fig. 1 shows a perspective view of the semiconductor device 2. Fig. 2 shows an exploded perspective view of the semiconductor device 2. The semiconductor device 2 is a device in which a semiconductor element 20 is sealed in a resin package 10. In Fig. 1, the semiconductor element 20 is not visible because it is covered by the resin package 10. Fig. 2 shows the semiconductor device 2 in a state in which the resin package 10 is not shown and the first heat sink 14 has been removed.

[0013] The semiconductor element 20 is a switching element for power conversion, such as an IGBT or a MOSFET, and is known as a power semiconductor element. A first main electrode 21 and a plurality of control electrodes 23 (see FIG. 5) are arranged on one main surface (first main surface 20a) of the semiconductor element 20. In FIG. 2, the control electrode 23 is hidden by the terminal substrate 30 and cannot be seen. A second main electrode 22 is arranged on the other main surface (second main surface 20b) of the semiconductor element 20. The first main electrode 21 and the second main electrode 22 are connected to the source and drain of the switching element, and a large current (for example, 10 amperes or more) flows through them.

[0014] The lower surface of copper block 17 is joined to first main electrode 21 on first main surface 20a, and first heat sink 14 is joined to the upper surface of copper block 17. A first main terminal 11 extends from the edge of first heat sink 14. A second main electrode 22 (see FIG. 5) is arranged on second main surface 20b, and second heat sink 15 is joined to second main surface 20b including second main electrode 22. A second main terminal 12 extends from the edge of second heat sink 15.

[0015] 1, first heat sink 14 is exposed on one wide surface of resin package 10, and first main terminal 11 extends outward from resin package 10. Although second heat sink 15 is not visible in FIG. 1, second heat sink 15 is also exposed on the other wide surface of resin package 10, and second main terminal 12 extends outward from resin package 10. First heat sink 14 serves both as a heat sink and as a conductive path between first main electrode 21 of semiconductor element 20 and first main terminal 11. Second heat sink 15 similarly serves both as a heat sink and as a conductive path between second main electrode 22 of semiconductor element 20 and second main terminal 12.

[0016] Although not visible in FIGS. 1 and 2 , a first main electrode 21 and multiple control electrodes 23 are exposed on the first main surface 20a of the semiconductor element 20. A terminal substrate 30 is attached to the semiconductor element 20, and multiple bonding terminals 33 are exposed on the front surface 30a of the terminal substrate 30. As will be described in detail later, each of the multiple control electrodes 23 of the semiconductor element 20 is electrically connected to a respective bonding terminal 33. One end of a bonding wire 16 is bonded to each bonding terminal 33, and the other end of each bonding wire 16 is bonded to a respective control terminal 13. The terms "front surface" and "back surface" of the terminal substrate 30 are used for convenience to distinguish between a pair of surfaces facing in opposite directions. The terms "front surface" and "back surface" may also be rephrased as "one surface" and "other surface" of a pair of surfaces facing in opposite directions.

[0017] 1, the plurality of control terminals 13 extend outward from the resin package 10. The plurality of control electrodes 23 disposed on the first main surface 20a of the semiconductor element 20 are connected to the gate, sense emitter, temperature sensor, etc. inside the semiconductor element 20. The bonding wires 16 are conductive. The plurality of control electrodes 23 of the semiconductor element 20 are electrically connected to the plurality of control terminals 13 via the terminal substrate 30 and the plurality of bonding wires 16.

[0018] The semiconductor element 20 and the terminal board 30 are covered by a resin package 10, but an external device is electrically connected to the first main electrode 21 and the control electrode 23 of the semiconductor element 20 via the main terminals 11, 12 and the control terminal 13.

[0019] 3 shows a perspective view of the semiconductor element 20 separated from the terminal substrate 30. As described above, a plurality of control electrodes 23 are arranged on the first main surface 20a of the semiconductor element 20 together with the first main electrode 21. As described above, the control electrode 23 is connected to the gate, sense emitter, and temperature sensor, and only a smaller current flows through the control electrode 23 than through the main electrode. Therefore, the area of ​​the control electrode 23 is significantly smaller than the area of ​​the first main electrode 21.

[0020] For ease of explanation, the surface of terminal board 30 facing the +Z direction will be referred to as front surface 30a, and the surface facing the -Z direction will be referred to as back surface 30b. In the upper right corner of Figure 3, a diagram of terminal board 30 drawn on the left side is shown upside down.

[0021] Fig. 4 shows a plan view of the semiconductor device 2, and Fig. 5 shows a cross-sectional view taken along line VV in Fig. 4. However, the resin package 10, the first heat sink 14, and the copper block 17 are not shown in Fig. 4. The internal structure of the semiconductor element 20 is not shown in Fig. 5. The structure of the terminal substrate 30 will be described in detail with reference to Figs. 3 to 5.

[0022] A plurality of bonding terminals 33 are arranged on the front surface 30a of the terminal substrate 30, and a plurality of relay terminals 34 are arranged on the back surface 30b. Each of the plurality of bonding terminals 33 is electrically connected to each of the plurality of relay terminals 34 inside the terminal substrate 30.

[0023] The terminal board 30 is divided into a thin plate portion 31 having a small thickness and a thick plate portion 32 having a large thickness. The thickness of the thin plate portion 31 is thinner than the thickness of the thick plate portion 32. A plurality of relay terminals 34 are arranged on the back surface 30b of the thin plate portion 31. On the back surface 30b of the terminal board 30, the boundary between the thin plate portion 31 and the thick plate portion 32 forms a step 35.

[0024] The terminal substrate 30 is bonded to the semiconductor element 20 so that each of the relay terminals 34 is in contact with and electrically connected to each of the control electrodes 23. At this time, the terminal substrate 30 is fixed to the semiconductor element 20 so that the side surface 20c of the semiconductor element 20 abuts against the step 35 (more precisely, the side surface of the step) (see FIG. 5). In other words, the corner between the first main surface 20a and the side surface 20c of the semiconductor element 20 abuts against the corner of the step 35.

[0025] Each of the multiple relay terminals 34 is arranged to face each of the multiple control electrodes 23 when the side surface 20c of the semiconductor element 20 abuts against the step 35. When the terminal substrate 30 is attached to the semiconductor element 20 so that the side surface 20c abuts against the step 35, each of the multiple relay terminals 34 comes into contact with each of the multiple control electrodes 23, establishing electrical continuity. The step 35 serves to accurately position the terminal substrate 30 relative to the semiconductor element 20 at a target position.

[0026] The bonding wire 16 is often made of aluminum and has a diameter of approximately 500 μm. As shown in FIG. 5, the tip of the bonding wire 16 (the tip bonded to the bonding terminal 33) is larger than its diameter because it is melted by heat. As clearly shown in FIGS. 3 to 5, the bonding terminal 33 has an area sufficient to secure the bonding wire 16. In other words, the area of ​​the bonding terminal 33 is larger than the cross-sectional area of ​​the bonding wire 16. On the other hand, the terminal substrate 30 is accurately positioned relative to the semiconductor element 20 by the step 35, so the control electrode 23 and the relay terminal 34 are in reliable contact even though their areas are small. The area of ​​the bonding terminal 33 is significantly larger than the areas of the control electrode 23 and the relay terminal 34. In other words, the areas of the control electrode 23 and the relay terminal 34 are smaller than the area of ​​the bonding terminal 33.

[0027] In the semiconductor device 2 of the first embodiment, the control electrode 23 provided on the first main surface 20a of the semiconductor element 20 can be made smaller while the terminal substrate 30 ensures that the bonding terminal 33 has a sufficient area for bonding the bonding wire 16. As a result, the main surface of the semiconductor element 20 can be made smaller. In other words, the semiconductor element 20 can be made smaller.

[0028] As shown in FIG. 5, the bonding terminals 33 provided on the front surface 30a of the terminal board 30 and the relay terminals 34 provided on the back surface 30b are electrically connected by a conductive pattern 38 inside the terminal board 30.

[0029] Most of the bonding terminals 33 are provided on the thick plate portion 32 of the terminal substrate 30, and the relay terminals 34 are provided on the thin plate portion 31, which is bonded to the first main surface 20a of the semiconductor element 20. As shown in FIG. 5 , the back surface 30b of the thick plate portion 32 is flush with the second main surface 20b of the semiconductor element 20, and both the back surface 30b and the second main surface 20b abut against the flat second heat sink 15. When the terminal substrate 30 is bonded to the semiconductor element 20, the back surface 30b abuts against the second heat sink 15. Therefore, when bonding the bonding wires 16 to the bonding terminals 33, the terminal substrate 30 does not shift relative to the semiconductor element 20.

[0030] (First Modification) FIG. 6 shows a perspective view of a terminal substrate 130 of a first modification. The terminal substrate 130 has a step 135 on its rear surface 130b, and the step 135 has side surfaces 135a and 135b in two directions. The side surfaces 135a and 135b are perpendicular to each other. The side surfaces 135a and 135b of the step 135 face the -X and -Y directions, respectively, of the coordinate system in the figure. When the terminal substrate 130 is attached to the semiconductor element 20, the side surfaces 135a and 135b of the step 135 abut against the side surfaces 20c and 20d of the semiconductor element 20, respectively. The side surface 20d intersects with the side surface 20c. By providing the step 135 with the side surfaces 135a and 135b in two directions, the terminal substrate 130 is accurately positioned relative to the semiconductor element 20 in two orthogonal directions.

[0031] Instead of providing the second side surface 135b on the step 135, a ridge guide may be provided on the second heat sink 15. The surfaces of the terminal substrate 30 and the semiconductor element 20 of the first embodiment that face the Y direction are pressed against the ridge guide. This allows the terminal substrate 30 to be accurately positioned relative to the semiconductor element 20 in the Y direction as well.

[0032] (Second Modification) A terminal substrate 230 of a second modification will be described with reference to Figures 7 and 8. Figure 7 shows a perspective view of the terminal substrate 230 and the semiconductor element 20. Figure 8 shows a cross-sectional view of a semiconductor device 202 equipped with the terminal substrate 230. The upper right corner of Figure 7 shows a perspective view of the left terminal substrate 230 turned upside down. Figure 7 corresponds to Figure 3, and Figure 8 corresponds to Figure 5.

[0033] Terminal board 230 has multiple protrusions 231 instead of thick plate portion 32 of terminal board 30 of the first embodiment. A diagram showing terminal board 230 with back surface 230b facing upward is shown in the upper right of Figure 7. Multiple bonding terminals 33 are arranged on front surface 230a of terminal board 230, and multiple relay terminals 34 are arranged on back surface 230b. Each of bonding terminals 33 is electrically connected to each of relay terminals 34 inside terminal board 230.

[0034] A plurality of protrusions 231 are provided on the rear surface 230b of the terminal substrate 230. The side surfaces of the protrusions 231 correspond to the steps 35 of the terminal substrate 30 of the first embodiment. More precisely, the height difference between the rear surface 230b of the terminal substrate 230 and the tip surfaces of the protrusions 231 corresponds to the steps.

[0035] When the terminal substrate 230 is attached to the semiconductor element 20, the side surface of the protrusion 231 (corresponding to the side surface of the step) abuts against the side surface 20c of the semiconductor element 20. By abutting the side surface of the protrusion 231 against the side surface 20c of the semiconductor element 20, the position of the terminal substrate 230 relative to the semiconductor element 20 in the X direction can be accurately determined.

[0036] Another feature of the semiconductor device 2 (202) of the embodiment will be described. The terminal substrate 30 (130, 230) is made of the same material as the resin package 10 that covers the semiconductor element 20. Typical materials are polyimide or polyamide. By making the terminal substrate 30 (130, 230) from the same material as the resin package 10, it is possible to reduce stress that occurs near the boundary between the resin package 10 and the terminal substrate 30 (130, 230) when the resin package 10 is injection molded.

[0037] Here are some points to note regarding the techniques described in the embodiments. Multiple terminal substrates may be attached to one semiconductor element. Also, multiple control electrodes may be distributed and arranged at multiple locations on the first main surface of semiconductor element 20.

[0038] Although specific examples of the present invention have been described in detail above, these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and variations of the specific examples exemplified above. The technical elements described in this specification or drawings exhibit technical utility alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Furthermore, the technology exemplified in this specification or drawings can achieve multiple objectives simultaneously, and achieving one of these objectives alone is technically useful. [Explanation of symbols]

[0039] 2, 202: semiconductor device 10: resin package 11, 12: main terminal 13: control terminal 14, 15: heat sink 16: bonding wire 17: copper block 20: semiconductor element 20a: first main surface 20b: second main surface 20c, 20d: side surface 21, 22: main electrode 23: control electrode 30, 130, 230: terminal board 30a, 230a: front surface 30b, 130b, 230b: back surface 31: thin plate portion 32: thick plate portion 33: bonding terminal 34: relay terminal 35, 135: step 38: conductive pattern 135a, 135b: side surface 231: protrusion

Claims

1. a semiconductor element having a main electrode and a control electrode disposed on one main surface; a terminal board having bonding terminals to which wires are bonded on its front surface and relay terminals on its back surface, the bonding terminals and the relay terminals being electrically connected to each other; a main terminal electrically connected to the main electrode and extending parallel to the main electrode; It is equipped with the area of ​​the bonding terminal is larger than the area of ​​the control electrode; the terminal substrate is bonded to the semiconductor element so that the control electrode and the relay terminal are in contact with each other; A semiconductor device, wherein a step is provided on the rear surface, and a side surface of the semiconductor element abuts against the step.

2. the terminal board has a thin plate portion including the relay terminals and a thick plate portion including the bonding terminals, The thickness of the thin plate portion is thinner than the thickness of the thick plate portion, The boundary between the thin plate portion and the thick plate portion corresponds to the step, the thin plate portion is joined to the semiconductor element; The semiconductor device according to claim 1 .

3. 3. The semiconductor device according to claim 2, wherein said back surface of said thick plate portion is flush with the other main surface of said semiconductor element.

4. The semiconductor device according to claim 1 , wherein a protrusion that forms the step is provided on the rear surface.

5. A semiconductor device described in any one of claims 1 to 4, further comprising a control terminal that is electrically conductive with the bonding terminal and extends parallel to the main electrode.

6. A semiconductor device as described in Claim 5, wherein the control terminal extends in the opposite direction to the main terminal.

7. A resin package is provided to cover the semiconductor element and the terminal substrate, one surface of the heat sink electrically connected to the main electrode is exposed from the resin package; The semiconductor device according to claim 1 .

8. A semiconductor device as described in Claim 7, wherein a conductive spacer is sandwiched between the main electrode and the heat sink.

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