Semiconductor Devices

Abstract

To improve the characteristics of a transistor.SOLUTION: A semiconductor device of an embodiment comprises: a first and a second gate electrode; a first spacer layer covering the first gate electrode and a second spacer layer covering the second gate electrode; a first liner layer covering the first gate electrode via the first spacer layer and a second liner layer covering the second gate electrode via the second spacer layer; a first contact extending from above the first liner layer toward below the first spacer layer and including a first conductive layer connected to the first gate electrode; and a second contact extending from above the second liner layer toward below the second spacer layer and including a second conductive layer connected to the second gate electrode. The first conductive layer is in contact with a side surface of the first spacer layer via a first insulation layer covering a side wall of the first conductive layer, and the second conductive layer is directly in contact with a side surface of the second spacer layer.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] FIELD OF THE INVENTION An embodiment of the present invention relates to a semiconductor device. [Background technology]

[0002] In semiconductor devices including CMOS transistors, improvements in various transistor characteristics are desired, such as leakage current between transistors, resistance at the poly / metal interface in polymetal gate structures, and negative bias temperature instability. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2020-027865 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of one embodiment is to provide a semiconductor device capable of improving transistor characteristics. [Means for solving the problem]

[0005] The semiconductor device of the embodiment comprises first and second gate electrodes, first and second spacer layers covering the first and second gate electrodes, respectively, first and second liner layers covering the first and second gate electrodes via the first and second spacer layers, a first contact extending from above the first liner layer to below the first spacer layer and having a first conductive layer connected to the first gate electrode, and a second contact extending from above the second liner layer to below the second spacer layer and having a second conductive layer connected to the second gate electrode, wherein the first conductive layer is in side contact with the first spacer layer via a first insulating layer covering the sidewalls of the first conductive layer, and the second conductive layer is in direct side contact with the second spacer layer. [Brief explanation of the drawings]

[0006] [Figure 1] 1 is a cross-sectional view showing an example of a configuration of a semiconductor device according to an embodiment; [Figure 2] 1A to 1C are cross-sectional views illustrating a part of a procedure of a method for manufacturing a semiconductor device according to an embodiment in order. [Figure 3] 1A to 1C are cross-sectional views illustrating a part of a procedure of a method for manufacturing a semiconductor device according to an embodiment in order. [Figure 4] 1A to 1C are cross-sectional views illustrating a part of a procedure of a method for manufacturing a semiconductor device according to an embodiment in order. [Figure 5] 1A to 1C are cross-sectional views illustrating a part of a procedure of a method for manufacturing a semiconductor device according to an embodiment in order. [Figure 6] 1A to 1C are cross-sectional views illustrating in order some steps of a method for manufacturing a semiconductor device according to a comparative example. [Figure 7] 1A to 1C are cross-sectional views illustrating in order some steps of a method for manufacturing a semiconductor device according to a comparative example. [Figure 8] 1A and 1B are partially enlarged cross-sectional views of semiconductor devices according to an embodiment and a comparative example. [Figure 9] 5A to 5C are cross-sectional views illustrating in order some steps of a method for manufacturing a semiconductor device according to a first modified example of the embodiment. [Figure 10] 5A to 5C are cross-sectional views illustrating in order some steps of a method for manufacturing a semiconductor device according to a first modified example of the embodiment. [Figure 11] 10A to 10C are diagrams illustrating in order some of the steps of a method for manufacturing a semiconductor device according to a second modification of the embodiment. [Figure 12] 10A to 10C are diagrams illustrating in order some of the steps of a method for manufacturing a semiconductor device according to a second modification of the embodiment. [Figure 13] 10A to 10C are diagrams illustrating in order some of the steps of a method for manufacturing a semiconductor device according to a second modification of the embodiment. [Figure 14] 10A to 10C are diagrams illustrating in order some of the steps of a method for manufacturing a semiconductor device according to a second modification of the embodiment. [Figure 15] FIG. 10 is a block diagram of a semiconductor memory device according to another embodiment. [Figure 16]FIG. 10 is an equivalent circuit diagram showing an example of the configuration of a memory cell array and a row decoder included in a semiconductor memory device according to another embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] The present invention will be described in detail below with reference to the drawings. Note that the present invention is not limited to the following embodiments. Furthermore, the components in the following embodiments include those that can be easily imagined by a person skilled in the art or that are substantially the same.

[0008] [Embodiment] Hereinafter, the embodiments will be described in detail with reference to the drawings.

[0009] (Configuration of semiconductor device) 1 is a cross-sectional view showing an example of the configuration of a semiconductor device 1 according to an embodiment. In this specification, the surface of a substrate 100 on which a transistor 10 (described later) and other components are formed is referred to as the upper surface, and the direction in which a polysilicon electrode 12 and a metal electrode 13 of the transistor 10 are stacked is referred to as the upper side of the semiconductor device 1.

[0010] As shown in FIG. 1, the semiconductor device 1 includes, on a substrate 100, transistors 10 to 30, interlayer insulating layers 211 and 212, contacts 71s to 73s and 71g to 73g, and a wiring D0.

[0011] The substrate 100 is a semiconductor substrate such as a silicon substrate. The substrate 100 is provided with an element isolation layer 110 that electrically isolates the formation regions of the transistors 10 to 30. In other words, the transistors 10 to 30 are electrically isolated from one another. In the formation regions of the transistors 10 to 30 in the substrate 100, dopants of a predetermined conductivity type are diffused to form source / drain regions.

[0012] A plurality of transistors 10 to 30 are provided on the substrate 100. However, these transistors 10 to 30 do not have to be arranged on the substrate 100 in the order shown in FIG. 1 . Furthermore, these transistors 10 to 30 do not have to be adjacent to each other with the element isolation layer 110 sandwiched therebetween. In addition, the number and types of transistors 10 to 30 provided on the substrate 100 can vary in various ways.

[0013] The transistor 10 is configured as, for example, a high voltage (HV) N-channel MOS (Metal Oxide Semiconductor) transistor.

[0014] The transistor 10 includes a gate insulating layer 11, a polysilicon electrode 12, a metal electrode 13, and a cap layer 14 serving as a second cap layer, which are stacked in this order from the substrate 100 side. The polysilicon electrode 12 and the metal electrode 13 form a gate electrode of the transistor 10 serving as a second gate electrode. In other words, the transistor 10 is configured as a transistor having a polymetal gate structure.

[0015] The transistor 10 also includes a spacer layer 15 as a second spacer layer that covers the gate insulating layer 11, the polysilicon electrode 12, the metal electrode 13, and the side surfaces of the cap layer 14, as well as the top surface of the cap layer 14, and a liner layer 16 as a second liner layer that covers the spacer layer 15.

[0016] The transistor 20 is configured as, for example, a low voltage (LV: Low Voltage / VLV: Very Low Voltage) P-channel MOS transistor.

[0017] The transistor 20 includes a gate insulating layer 21, a polysilicon electrode 22, a metal electrode 23, and a cap layer 24 serving as a second cap layer, which are stacked in this order from the substrate 100 side. The polysilicon electrode 22 and the metal electrode 23 form a gate electrode of the transistor 20 serving as a second gate electrode. In other words, the transistor 20 is configured as a transistor having a polymetal gate structure.

[0018] The transistor 20 also includes a spacer layer 25 as a second spacer layer that covers the gate insulating layer 21, the polysilicon electrode 22, the metal electrode 23, and the side surfaces of the cap layer 24, as well as the top surface of the cap layer 24, and a liner layer 26 as a second liner layer that covers the spacer layer 25.

[0019] The transistor 30 is configured as, for example, a high-voltage P-channel MOS transistor. These transistors 10 and 30 are also called high-voltage MOS transistors.

[0020] The transistor 30 includes a gate insulating layer 31, a polysilicon electrode 32, a metal electrode 33, and a cap layer 34 serving as a first cap layer, which are stacked in this order from the substrate 100 side. The polysilicon electrode 32 and the metal electrode 33 form a gate electrode of the transistor 30 serving as a first gate electrode. In other words, the transistor 30 is configured as a transistor having a polymetal gate structure.

[0021] The transistor 30 also includes a spacer layer 35 as a first spacer layer that covers the gate insulating layer 31, the polysilicon electrode 32, the metal electrode 33, and the side surfaces of the cap layer 34, as well as the top surface of the cap layer 34, and a liner layer 36 as a first liner layer that covers the spacer layer 35.

[0022] Here, the gate insulating layers 11 to 31 of these transistors 10 to 30 are, for example, silicon oxide layers, hafnium oxide layers, zirconium oxide layers, or the like.

[0023] The polysilicon electrodes 12 to 32 are, for example, conductive polysilicon layers and function as poly gates as described above. The metal electrodes 13 to 33 are, for example, tungsten silicide layers and function as metal gates as described above.

[0024] The cap layers 14 to 34, the spacer layers 15 to 35, and the liner layers 16 to 36 are all insulating layers. The cap layers 14 to 34 and the liner layers 16 to 36 are nitride layers such as silicon nitride layers, and the spacer layers 15 to 35 are oxide layers such as silicon oxide layers. More specifically, the spacer layers 15 to 35 are, for example, TEOS (Tetra Ethoxy Silane) layers.

[0025] The spacer layers 15-35 and liner layers 16-36 cover the polysilicon electrodes 12-32 and metal electrodes 13-33 of the transistors 10-30, and also cover the substrate 100 around them. The spacer layers 15-35 of the individual transistors 10-30 may cover the substrate 100 continuously with the regions between the transistors 10-30 interposed therebetween. The liner layers 16-36 may cover the spacer layers 15-35 continuously with the regions between the transistors 10-30 interposed therebetween.

[0026] Furthermore, these transistors 10 to 30 are entirely covered by interlayer insulating layers 211 and 212. The interlayer insulating layer 211 is a silicon oxide layer such as an NSG (Non-doped Silicate Glass) layer, and directly covers the transistors 10 to 30. The interlayer insulating layer 212 is a silicon oxide layer such as a TEOS layer, and covers the transistors 10 to 30 via the interlayer insulating layer 211.

[0027] The plurality of contacts 71s to 73s and 71g to 73g are connected to the transistors 10 to 30.

[0028] Contact 71g as a second contact penetrates interlayer insulating layers 212 and 211, liner layer 16, spacer layer 15, and cap layer 14, and is connected to metal electrode 13 of transistor 10. Contact 71g includes conductive layer 61g as a second conductive layer and insulating layer 51g as a second insulating layer.

[0029] The conductive layer 61g penetrates the interlayer insulating layers 212 and 211, the liner layer 16, the spacer layer 15, and the cap layer 14 to reach the metal electrode 13 of the transistor 10. The conductive layer 61g is a metal layer such as a tungsten layer or a copper layer. The conductive layer 61g may also be a metal layer having a barrier metal layer (not shown) on its surface. The barrier metal layer may be, for example, a titanium layer, a titanium nitride layer, a tantalum layer, or a tantalum nitride layer.

[0030] The insulating layer 51g is a silicon oxide layer such as an LTO (Low Temperature Oxide) layer, and covers the sidewall of the conductive layer 61g above the liner layer 16. That is, the insulating layer 51g extends through the interlayer insulating layers 212 and 211 and reaches the liner layer 16. More specifically, the lower end of the insulating layer 51g remains on the upper surface of the liner layer 16 or in the liner layer 16, and does not penetrate the liner layer 16.

[0031] As a result, the conductive layer 61g of the contact 71g is in direct side contact with the spacer layer 15 and the cap layer 14 below the liner layer 16. As described above, if the conductive layer 61g is a single metal layer or the like, the sidewalls of the metal layer are in contact with the spacer layer 15 and the cap layer 14. If the conductive layer 61g is a metal layer or the like having a barrier metal layer, the barrier metal layer is in contact with the spacer layer 15 and the cap layer 14.

[0032] A pair of contacts 71s penetrates the interlayer insulating layers 212, 211, the liner layer 16, and the spacer layer 15 to connect to source / drain regions provided in the substrate 100 on both sides of the polysilicon electrode 12 and the metal electrode 13 of the transistor 10. Each of the contacts 71s includes a conductive layer 61s and an insulating layer 51s.

[0033] The conductive layer 61s penetrates the interlayer insulating layers 212 and 211, the liner layer 16, and the spacer layer 15 to reach the substrate 100 on both sides of the transistor 10. Like the conductive layer 61g described above, the conductive layer 61s is a single metal layer or a metal layer having a barrier metal layer on its surface.

[0034] Similar to the insulating layer 51g described above, the insulating layer 51s is a silicon oxide layer such as an LTO layer, and covers the sidewall of the conductive layer 61s above the liner layer 16. That is, the insulating layer 51s extends through the interlayer insulating layers 212 and 211 and reaches the liner layer 16. The conductive layer 61s of the contact 71s extends through the spacer layer 15 while directly contacting the spacer layer 15 on the side below the liner layer 16, and is connected to the upper surface of the substrate 100.

[0035] A contact 72g as a second contact penetrates the interlayer insulating layers 212 and 211, the liner layer 26, the spacer layer 25, and the cap layer 24, and is connected to the metal electrode 23 of the transistor 20. The contact 72g includes a conductive layer 62g as a second conductive layer and an insulating layer 52g as a second insulating layer.

[0036] The conductive layer 62g penetrates the interlayer insulating layers 212 and 211, the liner layer 26, the spacer layer 25, and the cap layer 24 to reach the metal electrode 23 of the transistor 20. Like the conductive layer 61g and the like described above, the conductive layer 62g is a single metal layer or a metal layer having a barrier metal layer on its surface.

[0037] The insulating layer 52g, like the insulating layer 51g described above, is a silicon oxide layer such as an LTO layer, and covers the sidewall of the conductive layer 62g above the liner layer 26. That is, the insulating layer 52g extends through the interlayer insulating layers 212 and 211 and reaches the liner layer 26. More specifically, the lower end of the insulating layer 52g remains on the upper surface of the liner layer 26 or in the liner layer 26, and does not penetrate the liner layer 26.

[0038] As a result, the conductive layer 62g of the contact 72g directly contacts the side surfaces of the spacer layer 25 and the cap layer 24 below the liner layer 26. In other words, the side surfaces of the metal layer, which is the conductive layer 62g, or the barrier metal layer of the metal layer contacts the spacer layer 25 and the cap layer 24.

[0039] The pair of contacts 72s penetrates the interlayer insulating layers 212, 211, the liner layer 26, and the spacer layer 25, and is connected to source / drain regions provided in the substrate 100 on both sides of the polysilicon electrode 22 and the metal electrode 23 of the transistor 20 via an epitaxial layer 121. The epitaxial layer 121 is a layer formed by epitaxially growing a crystalline silicon layer or the like from the upper surface of the substrate 100. Each of the contacts 72s includes a conductive layer 62s and an insulating layer 52s.

[0040] The conductive layer 62s penetrates the interlayer insulating layers 212 and 211, the liner layer 26, and the spacer layer 25 to reach the substrate 100 on both sides of the transistor 20. Like the above-described conductive layer 61g, the conductive layer 62s is a single metal layer or a metal layer having a barrier metal layer on its surface.

[0041] Similar to the insulating layer 51g described above, the insulating layer 52s is a silicon oxide layer such as an LTO layer, and covers the sidewall of the conductive layer 62s above the liner layer 26. That is, the insulating layer 52s extends through the interlayer insulating layers 212 and 211 and reaches the liner layer 26. The conductive layer 62s of the contact 72s extends through the spacer layer 25 below the liner layer 26 while directly contacting the spacer layer 25 on the side, and is connected to the upper surface of the substrate 100.

[0042] Contact 73g as a first contact penetrates interlayer insulating layers 212 and 211, liner layer 36, spacer layer 35, and cap layer 34, and is connected to metal electrode 33 of transistor 30. Contact 73g includes conductive layer 63g as a first conductive layer and insulating layer 53g as a first insulating layer.

[0043] The conductive layer 63g penetrates the interlayer insulating layers 212 and 211, the liner layer 36, the spacer layer 35, and the cap layer 34 to reach the metal electrode 33 of the transistor 30. Like the conductive layer 61g and the like described above, the conductive layer 63g is a single metal layer or a metal layer having a barrier metal layer on its surface.

[0044] Similar to the insulating layer 51g described above, the insulating layer 53g is a silicon oxide layer such as an LTO layer, and covers the sidewall of the conductive layer 63g from above to below the liner layer 36. That is, the insulating layer 53g extends through the interlayer insulating layers 212 and 211, the liner layer 36, and the spacer layer 35, and reaches the cap layer 36. More specifically, the lower end of the insulating layer 53g reaches a predetermined depth in the cap layer 34.

[0045] As a result, the conductive layer 63g of the contact 73g is in contact with the spacer layer 35 on its side via the insulating layer 53g, even below the liner layer 36. Furthermore, the conductive layer 63g is in contact with the cap layer 34 on its side via the insulating layer 53g up to a predetermined depth in the cap layer 34, and below that, is in contact with the cap layer 34 on its side without the insulating layer 53g. In other words, the side of the metal layer that is the conductive layer 63g, or a barrier metal layer that the metal layer has, is in contact with the spacer layer 35 and a portion of the cap layer 34 in the depth direction.

[0046] The pair of contacts 73s penetrates the interlayer insulating layers 212, 211, the liner layer 36, and the spacer layer 35, and is connected to source / drain regions provided in the substrate 100 on both sides of the polysilicon electrode 32 and the metal electrode 33 of the transistor 30 via an epitaxial layer 131 such as a crystalline silicon layer. Each of the contacts 73s includes a conductive layer 63s and an insulating layer 53s.

[0047] The conductive layer 63s penetrates the interlayer insulating layers 212 and 211, the liner layer 36, and the spacer layer 35 to reach the substrate 100 on both sides of the transistor 30. Like the above-described conductive layer 61g, the conductive layer 63s is a single metal layer or a metal layer having a barrier metal layer on its surface.

[0048] The insulating layer 53s is a silicon oxide layer such as an LTO layer, similar to the insulating layer 51g described above, and covers the sidewall of the conductive layer 63s above the liner layer 36. That is, the insulating layer 53s extends through the interlayer insulating layers 212 and 211 and reaches the liner layer 36. The conductive layer 63s of the contact 73s extends through the spacer layer 35 while directly contacting the spacer layer 35 on the side below the liner layer 36, and is connected to the upper surface of the substrate 100.

[0049] Each of the plurality of contacts 71s-73s, 71g-73g is connected at its upper end to a wiring D0 provided in the interlayer insulating layer 212. The wiring D0 is a metal layer such as a tungsten layer or a copper layer. The wiring D0 may also be a metal layer having a barrier metal layer (not shown) on its surface. Furthermore, the conductive layers 61s-63s, 61g-63g of the plurality of contacts 71s-73s, 71g-73g and the wiring D0 may be the same metal layer or different metal layers.

[0050] As a result, each of the transistors 10 to 30 is connected to a power supply, a semiconductor element, etc. (not shown) via the plurality of contacts 71s to 73s, 71g to 73g and the plurality of wirings D0.

[0051] For example, a relatively high gate voltage is applied to the polysilicon electrode 12 and metal electrode 13 of transistor 10 via the wiring D0 and contact 71g. Also, a gate voltage lower than that of transistor 10 is applied to the polysilicon electrode 22 and metal electrode 23 of transistor 20 via the wiring D0 and contact 72g. Also, a high gate voltage similar to that of transistor 10 is applied to the polysilicon electrode 32 and metal electrode 33 of transistor 30 via the wiring D0 and contact 73g.

[0052] These transistors 10 to 30 are also combined in various ways and used as, for example, a drive circuit for driving a semiconductor element or the like electrically connected to these transistors 10 to 30.

[0053] In this case, among the transistors 10 to 30, for example, the transistor 10 can be used as the main component of the drive circuit, and multiple transistors 10 can be densely arranged within the drive circuit. On the other hand, the transistors 20 and 30 can be used as auxiliary components of the drive circuit, and a predetermined number of the transistors 20 and 30 can be arranged within the drive circuit. In this case, the transistor 20 configured as a low-voltage MOS transistor, for example, is applied to a portion of the drive circuit that requires high-speed operation.

[0054] (Method of manufacturing a semiconductor device) Next, a method for manufacturing the semiconductor device 1 according to the embodiment will be described with reference to Figures 2 to 5. Figures 2 to 5 are cross-sectional views illustrating in order some of the steps of the method for manufacturing the semiconductor device 1 according to the embodiment.

[0055] As shown in FIG. 2(a), a dopant of a predetermined conductivity type is diffused into a substrate 100 such as a silicon substrate.

[0056] Furthermore, an insulating layer such as a silicon oxide layer, a polysilicon layer, a metal layer, and an insulating layer such as a silicon nitride layer are stacked in this order on the substrate 100 and shaped into a predetermined shape by etching or the like, thereby forming gate insulating layers 11-31, polysilicon electrodes 12-32, metal electrodes 13-33, and cap layers 14-34 of the respective transistors 10-30.

[0057] The element isolation layer 110 is formed on the substrate 100 after, for example, a polysilicon layer is formed.

[0058] 2(b), spacer layers 15 to 35 are formed to cover the side surfaces of the gate insulating layers 11 to 31, the polysilicon electrodes 12 to 32, the metal electrodes 13 to 33, and the cap layers 14 to 34, as well as the upper surfaces of the cap layers 14 to 34. At this time, these spacer layers 15 to 35 may be integrally formed by forming a silicon oxide layer such as a TEOS layer over the entire upper surface of the substrate 100.

[0059] Furthermore, liner layers 16 to 36 are formed to cover the spacer layers 15 to 35. At this time, by forming an insulating layer such as a silicon nitride layer over the entire upper surface of the substrate 100, these liner layers 16 to 36 may be formed integrally.

[0060] As a result, the transistors 10 to 30 are formed.

[0061] 2(c), an interlayer insulating layer 211 such as an NSG layer is formed to cover the transistors 10 to 30. An interlayer insulating layer 212 such as a TEOS layer is formed to cover the interlayer insulating layer 211. A mask pattern 91 having a plurality of hole patterns 91h is formed on the interlayer insulating layer 212. The mask pattern 91 is, for example, a resist pattern in which the hole patterns 91h are provided in a resin layer such as a resist layer.

[0062] As shown in FIG. 3(a), the interlayer insulating layers 212 and 211 are etched using a mask pattern 91 to form a plurality of contact holes 81s to 83s and 81g to 83g.

[0063] A pair of contact holes 81s reach liner layer 16 on substrate 100 on either side of transistor 10. A pair of contact holes 82s reach liner layer 26 on substrate 100 on either side of transistor 20. A pair of contact holes 83s reach liner layer 36 on substrate 100 on either side of transistor 30.

[0064] The contact holes 81g to 83g penetrate the interlayer insulating layers 212, 211 and reach the liner layers 16 to 36 that cover the transistors 10 to 30, respectively. At this time, etching conditions that have high selectivity for the liner layers 16 to 36 are used. As a result, the lower ends of the contact holes 81g to 83g, which reach positions shallower than the contact holes 81s to 83s, do not penetrate the liner layers 16 to 36 but remain on the upper surfaces of or within the liner layers 16 to 36, respectively.

[0065] Thereafter, the mask pattern 91 is removed by ashing using oxygen plasma or the like.

[0066] 3(b), a mask pattern 92 such as a resist pattern having openings at the positions where the contact holes 82s, 83s, and 83g will be formed is formed on the interlayer insulating layer 212. As a result, the other contact holes 81s, 81g, and 82g are covered with the mask pattern 92. The mask material constituting the mask pattern 92 may fill part or all of the contact holes 81s, 81g, and 82g.

[0067] Furthermore, the liner layers 26 and 36 and the spacer layers 25 and 35 are removed from the bottom surfaces of the contact holes 82s, 83s, and 83g that are not covered with the mask pattern 92. At the bottom surface of the contact hole 83g, a portion of the cap layer 34 is also etched away, so that the lower end of the contact hole 83g reaches a predetermined depth in the cap layer 34.

[0068] Thereafter, the mask pattern 92 is removed by ashing using oxygen plasma or the like.

[0069] 4(a), epitaxial layers 121, 131 such as crystalline silicon layers are formed by epitaxial growth on the substrate 100 exposed at the bottom surfaces of the contact holes 82s, 83s. No epitaxial layer is formed on the lower ends of the contact holes 81s, 81g, 82g located on the cap layers 16, 26, respectively, and on the lower end of the contact hole 83g located in the cap layer 34.

[0070] 4(b), an insulating layer 50 such as an LTO layer is formed on the interlayer insulating layer 212. The insulating layer 50 is also formed on the side walls and bottom surfaces of the contact holes 81s to 83s and 81g to 83g.

[0071] 5(a), the insulating layer 50 on the bottom surfaces of the contact holes 81s to 83s and 81g to 83g is removed, thereby exposing the upper surfaces of the epitaxial layers 121 and 131 from the bottom surfaces of the contact holes 82s and 83s, respectively.

[0072] On the other hand, in the contact hole 81s, the liner layer 16 and the spacer layer 15 at the bottom of the contact hole 81s are also removed, and the upper surface of the substrate 100 is exposed.

[0073] In the contact holes 81g and 82g, the liner layers 16 and 26 and the spacer layers 15 and 25 on the bottom surfaces of the contact holes 81g and 82g are removed, and the cap layers 14 and 24 are also etched away. As a result, the bottom ends of the contact holes 81g and 82g penetrate the cap layers 14 and 24 and reach the metal electrodes 13 and 23.

[0074] Furthermore, the remaining cap layer 34 is etched away from the contact hole 83g, so that the bottom end of the contact hole 83g penetrates the cap layer 34 and reaches the metal electrode 33.

[0075] Furthermore, when removing the insulating layer 50 on the bottom surfaces of the contact holes 81s to 83s and 81g to 83g, the insulating layer 50 on the upper surface of the interlayer insulating layer 212 is also removed. As a result, the contact holes 81s to 83s and 81g to 83g have the insulating layers 51s to 53s and 51g to 53g on their respective side walls.

[0076] However, in the contact hole 81s, the depth of the insulating layer 51s remains on the top surface of the liner layer 16 or within the liner layer 16, and at least the lower part of the contact hole 81s that penetrates the spacer layer 15 does not have the insulating layer 51s.

[0077] In addition, in contact holes 81g, 82g, the depth of the insulating layers 51g, 52g remains on the top surface of the liner layers 16, 26 or within the liner layers 16, 26, respectively, and there is no insulating layer 51g, 52g at least below the contact holes 81g, 82g that penetrate the spacer layers 15, 25 and the cap layers 14, 24.

[0078] In the contact hole 83g, the depth of the insulating layer 53g extends beyond the liner layer 36 and the spacer layer 35 to a predetermined depth in the cap layer 34. The contact hole 83g does not have the insulating layer 53g below the contact hole 83g, which extends from the predetermined depth in the cap layer 34 to the metal electrode 33.

[0079] In the contact holes 82s, 83s, the insulating layers 52s, 53s cover the entire sidewalls of the contact holes 82s, 83s up to the lower portions of the contact holes 82s, 83s that reach the epitaxial layers 121, 131, respectively.

[0080] As shown in FIG. 5(b), a plurality of trenches TR are formed in the interlayer insulating layer 212 so as to be connected to the upper ends of the contact holes 81s to 83s and 81g to 83g, respectively.

[0081] Thereafter, the contact holes 81s to 83s and 81g to 83g and the trenches TR are filled with a metal layer such as a tungsten layer or a copper layer.

[0082] As a result, conductive layers 61s-63s, 61g-63g are formed in the contact holes 81s-83s, 81g-83g, respectively, to obtain a plurality of contacts 71s-73s, 71g-73g, and a plurality of wirings D0 connected to these contacts 71s-73s, 71g-73g.

[0083] However, the filling of the contact holes 81s to 83s and 81g to 83g with a metal layer and the filling of the grooves TR with a metal layer may be carried out separately. In this case, the contact holes 81s to 83s and 81g to 83g and the grooves TR may be filled with different types of metal layers.

[0084] In this manner, the semiconductor device 1 of the embodiment is manufactured.

[0085] (Comparative Example) Next, a method for manufacturing a semiconductor device according to a comparative example will be described with reference to Figures 6 and 7. Figures 6 and 7 are cross-sectional views illustrating in order some of the steps of the method for manufacturing a semiconductor device according to the comparative example.

[0086] 2(a) to 3(a) are also performed in the semiconductor device of the comparative example, thereby forming comparative example transistors 10x to 30x including gate insulating layers 11x to 31x, polysilicon electrodes 12x to 32x, metal electrodes 13x to 33x, cap layers 14x to 34x, and spacer layers 15x to 35x and liner layers 16x to 36x covering these, and comparative example contact holes 81sx to 83sx and 81gx to 83gx above these transistors 10x to 30x, as shown in FIG.

[0087] However, in the semiconductor device of the comparative example, the lower ends of the contact holes 81gx-83gx penetrate the liner layers 16x-36x and the spacer layers 15x-35x and reach the cap layers 14x-34x, respectively. Such contact holes 81gx-83gx can be obtained by, for example, performing excessive over-etching on the contact holes 81gx-83gx that are shallower than the contact holes 81sx-83sx.

[0088] As shown in FIG. 6(b), the liner layers 26x, 36x and the spacer layers 25x, 35x at the bottoms of the contact holes 82sx, 83sx are removed. At this time, a mask pattern having openings at the positions where the contact holes 82sx, 83sx, and 83gx are to be formed is formed on the interlayer insulating layer 212, similar to the mask pattern 92 shown in FIG. 3(b) described above. This also causes a portion of the cap layer 34x at the bottom of the contact hole 83gx to be etched away. Furthermore, epitaxial layers 121, 131 are formed on the upper surface of the substrate 100 exposed at the bottoms of the contact holes 82sx, 83sx, respectively.

[0089] As shown in FIG. 7(a), an insulating layer 50x is formed on the upper surface of the interlayer insulating layer 212 and on the side walls and bottom surfaces of the contact holes 81sx to 83sx and 81gx to 83gx.

[0090] 7(b), the insulating layer 50x on the bottom surfaces of the contact holes 81sx-83sx and 81gx-83gx is removed. At this time, the insulating layer 50x on the interlayer insulating layer 212 is also removed, so that the contact holes 81sx-83sx and 81gx-83gx have the insulating layers 51sx-53sx and 51gx-53gx on their respective side walls.

[0091] Furthermore, the liner layer 16x and the spacer layer 15x at the bottom of the contact hole 81sx are removed to expose the upper surface of the substrate 100. Furthermore, the lower ends of the contact holes 81gx to 83gx penetrate the cap layers 14x to 34x and reach the metal electrodes 13x to 33x, respectively.

[0092] Thereafter, similarly to the semiconductor device 1 of the above-described embodiment, a plurality of trenches are formed so as to be connected to the upper ends of the contact holes 81sx-83sx and 81gx-83gx, respectively, and the contact holes 81sx-83sx and 81gx-83gx and the trenches are filled with a metal layer.

[0093] In this way, the semiconductor device of the comparative example is manufactured.

[0094] In the semiconductor device of the comparative example manufactured as described above, variations in the characteristics of the transistors 10x, 20x, etc. may occur. The inventors believe that such variations in characteristics are due to hydrogen contamination in the transistors 10x, 20x. Such hydrogen is thought to originate from hydrogen contained in the constituent materials of, for example, the interlayer insulating layers 211, 212 that cover the transistors 10x, 20x. Hydrogen in the constituent materials may remain in the interlayer insulating layers 211, 212 even after the interlayer insulating layers 211, 212 are formed.

[0095] Generally, the sidewalls of the isolation layer that separates transistors are implanted with dopants that act as channel stoppers. If hydrogen is introduced into a transistor, the dopants implanted in the sidewalls of the isolation layer can be inactivated, which can increase leakage current between adjacent transistors. It can also increase the resistance at the interface between the polysilicon electrode and the metal electrode.

[0096] On the other hand, when hydrogen is mixed into a transistor, dangling bonds at the interface between the gate electrode and the silicon that makes up the substrate are terminated, which is expected to improve negative bias temperature instability (NBTI) in P-channel MOS transistors, for example.

[0097] Hereinafter, the differences between the semiconductor device 1 of the embodiment and the semiconductor device of the comparative example will be described with reference to FIG.

[0098] 8A and 8B are enlarged cross-sectional views of a portion of the semiconductor device according to the embodiment and the comparative example. More specifically, Fig. 8A is a cross-sectional view of the transistor 10 of the semiconductor device 1 according to the embodiment, Fig. 8B is a cross-sectional view of the transistor 10x of the semiconductor device according to the comparative example, and Fig. 8C is a cross-sectional view of the transistor 30 of the semiconductor device 1 according to the embodiment.

[0099] As shown in FIG. 8(b), in the comparative example transistor 10x, the contact 71gx connected to the metal electrode 13x of the transistor 10x has an insulating layer 51gx that penetrates the liner layer 16x and the spacer layer 15x and reaches into the cap layer 14x.

[0100] The silicon nitride layer or the like used in the liner layer 16x is a denser layer than, for example, a silicon oxide layer, and prevents hydrogen from entering the transistor 10x from the interlayer insulating layers 211 and 212. The present inventors speculated that hydrogen enters the transistor 10x through the insulating layer 51gx, which penetrates the liner layer 16x and reaches the inside of the transistor 10x.

[0101] As described above, the increase in leakage current between transistors 10x caused by the inactivation of dopants on the sidewalls of the element isolation layer by the mixed hydrogen can be a factor that significantly degrades the characteristics of transistors 10x that are densely arranged within a drive circuit, for example, as a main component of the drive circuit.

[0102] Also, in the transistor 20x of the comparative example, it is thought that hydrogen gets into the transistor 20x via the insulating layer 52gx of the contact 72gx that penetrates the liner layer 26x and reaches the inside of the transistor 20x.

[0103] As described above, an increase in the resistance value at the interface between the polysilicon electrode and the metal electrode due to the mixed hydrogen can reduce the operating speed of the transistor 20x, which is required to operate at high speed in a drive circuit, for example, and can be a factor in significantly degrading the characteristics of the transistor 20x.

[0104] As shown in Figure 8(a), in the transistor 10 of the embodiment, the insulating layer 51g of the contact 71g connected to the metal electrode 13 of the transistor 10 remains on the upper surface of the liner layer 16 or within the liner layer 16, and does not penetrate through the liner layer 16 into the transistor 10.

[0105] Therefore, the liner layer 16x, which is a dense silicon nitride layer or the like, prevents residual hydrogen and the like in the interlayer insulating layers 211 and 212 from entering the transistor 10. Furthermore, since the insulating layer 51g does not penetrate the liner layer 16, the intrusion of hydrogen into the transistor 10 through the insulating layer 51g is also suppressed.

[0106] This prevents an increase in leakage current between adjacent transistors 10, for example, in transistors 10 arranged at high density in a drive circuit as a main component of the drive circuit, thereby improving the characteristics of the transistors 10.

[0107] Also in the transistor 20 of the embodiment, the liner layer 26 covering the transistor 20 prevents hydrogen from entering the transistor 20, and hydrogen is also prevented from entering the transistor 20 via the insulating layer 52g.

[0108] This prevents a decrease in the operating speed of the transistor 20, which is required to operate at high speed, and improves the characteristics of the transistor 20.

[0109] On the other hand, in a transistor configured as a P-channel MOS transistor and used as an auxiliary component of a drive circuit, such as transistor 30 in the above-described embodiment, an increase in threshold voltage due to NBTI can cause more serious degradation of the transistor than an increase in leakage current between transistors due to hydrogen contamination inside the transistor.

[0110] As shown in FIG. 8(c), in the transistor 30 of the embodiment, an insulating layer 53g of a contact 73g connected to a metal electrode 33 of the transistor 30 penetrates the liner layer 36 and enters the transistor 30.

[0111] As a result, residual hydrogen and the like in the interlayer insulating layers 211 and 212 are introduced into the transistor 30 appropriately via the insulating layer 53g. This improves NBTI of the transistor 30, suppresses fluctuations in the threshold voltage, and improves the reliability of the transistor 30.

[0112] (Overview) According to the semiconductor device 1 of the embodiment, the insulating layer 53g of the contact 73g connected to the metal electrode 33 of the transistor 30 covers the conductive layer 63g of the contact 73g from above to below the liner layer 36. This allows hydrogen to be introduced into the transistor 30 to improve NBTI in the transistor 30, thereby improving the reliability of the transistor 30.

[0113] According to the semiconductor device 1 of the embodiment, the insulating layer 51g of the contact 71g connected to the metal electrode 13 of the transistor 10 extends from above the liner layer 16 to the liner layer 16 and remains on or in the liner layer 16. This prevents hydrogen from entering the transistor 10 and prevents an increase in leakage current between adjacent transistors 10, thereby improving the characteristics of the transistor 10.

[0114] According to the semiconductor device 1 of the embodiment, the insulating layer 52g of the contact 72g connected to the metal electrode 23 of the transistor 20 extends from above the liner layer 26 to the liner layer 26 and remains on or in the liner layer 26. This prevents hydrogen from entering the transistor 20, prevents a decrease in the operating speed of the transistor 20, and improves the characteristics of the transistor 20.

[0115] (Variation 1) 9 and 10, a semiconductor device 2 according to a first modification of the embodiment will be described. The semiconductor device 2 according to the first modification is different from the above-described embodiment in that the contact 171g connected to the transistor 10a, which is a high-voltage N-channel MOS transistor or the like, and the transistor 20a, which is a low-voltage P-channel MOS transistor or the like, do not have an insulating layer.

[0116] 9 and 10 are cross-sectional views illustrating in order some of the steps of the method for manufacturing the semiconductor device 2 according to the first modified example of the embodiment. In Fig. 9 and 10, the same components as those in the semiconductor device 1 of the above-described embodiment are denoted by the same reference numerals, and the description thereof may be omitted.

[0117] 2(a) to 5(a) are also performed on the semiconductor device 2 of Modification 1. As a result, the transistors 10a, 20a, and 30 of Modification 1 and the contact holes 81s to 83s and 81g to 83g connected to these transistors 10a, 20a, and 30 are formed, as shown in FIG.

[0118] In the processing up to this point, the transistors 10a and 20a have the same configuration as the transistors 10 and 20 of the above-described embodiment. However, for ease of explanation, in order to distinguish them from the transistors 10 and 20 of the above-described embodiment, in Modification 1, these will be referred to as transistors 10a and 20a.

[0119] 9(b), a mask pattern 193 such as a resist pattern having openings corresponding to the contact holes 81s, 81g, and 82g is formed on the interlayer insulating layer 212. As a result, the other contact holes 82s, 83s, and 83g are covered with the mask pattern 193. The mask material constituting the mask pattern 193 may fill part or all of the contact holes 82s, 83s, and 83g.

[0120] Furthermore, the insulating layers 51s, 51g, and 52g on the side walls of the contact holes 81s, 81g, and 82g that are not covered with the mask pattern 92 are removed by wet etching or the like. At this time, a step may be formed between the portions of the contact holes 81s, 81g, and 82g that were originally covered with the insulating layers 51s, 51g, and 52g and the lower ends of the contact holes 81s, 81g, and 82g below them.

[0121] That is, the apparent diameters of the contact holes 81s, 81g, and 82g may be expanded at the portions where the insulating layers 51s, 51g, and 52g are removed, so that the side walls of the contact holes 81s, 81g, and 82g may have steps at the height of the liner layers 16 and 26. Furthermore, the apparent diameters of the contact holes 81s, 81g, and 82g may be narrower below these steps.

[0122] Thereafter, the mask pattern 193 is removed by ashing using oxygen plasma or the like.

[0123] As shown in FIG. 10(a), a plurality of trenches TR are formed in the interlayer insulating layer 212 so as to be connected to the upper ends of the contact holes 81s to 83s and 81g to 83g, respectively.

[0124] As shown in FIG. 10(b), the contact holes 81s to 83s and 81g to 83g and the trenches TR are filled with a metal layer such as a tungsten layer or a copper layer all at once or separately.

[0125] As a result, conductive layers 161s, 62s, 63s, 161g, 162g, and 63g are formed in the contact holes 81s to 83s and 81g to 83g, respectively, and a plurality of contacts 171s, 72s, 73s, 171g, 172g, and 73g are formed. In addition, a plurality of wirings D0 are formed to connect to these contacts 171s, 72s, 73s, 171g, 172g, and 73g.

[0126] As described above, if steps are formed in the contact holes 81s, 81g, and 82g, the conductive layers 161s, 161g, and 162g filled in these contact holes 81s, 81g, and 82g also have steps.

[0127] That is, in this case, the conductive layers 161s, 161g, and 162g of the contacts 171s, 171g, and 172g may have steps at the height of the liner layers 16 and 26. Also, the diameters of the conductive layers 161s, 161g, and 162g may be narrower below these steps.

[0128] In this way, the semiconductor device 2 of the first modification is manufactured.

[0129] In the semiconductor device 2 of the first modification, the conductive layers 161g and 162g of the contacts 171g and 172g connected to the metal electrodes 13 and 23 of the transistors 10a and 20a are in direct side contact with the liner layers 16 and 26 over the entire thickness direction of the liner layers 16 and 26. This further suppresses the intrusion of hydrogen, and further improves the characteristics of the transistors 10a and 20a, as will be described below.

[0130] 3(a), for example, a sufficient etching selectivity with respect to the liner layers 16, 26 may not be obtained, and the bottom ends of the contact holes 81g, 82g may penetrate the liner layers 16, 26. In this case, the insulating layers 51g, 52g subsequently formed on the side walls of the contact holes 81g, 82g may extend beyond the liner layers 16, 26 and extend into the transistors 10a, 20a.

[0131] However, the insulating layers 51g and 52g covering the sidewalls of the conductive layers 161g and 162g are removed from the contacts 171g and 172g of Modification 1. Therefore, even if the bottom ends of the contact holes 81g and 82g penetrate the liner layers 16 and 26 and the insulating layers 51g and 52g penetrate into the transistors 10a and 20a, it is possible to prevent hydrogen from entering the transistors 10a and 20a through the insulating layers 51g and 52g.

[0132] In addition, the semiconductor device 2 of the first modification has the same effects as the semiconductor device 1 of the above-described embodiment.

[0133] (Variation 2) As described above, contacts having no insulating layer on the sidewalls of the conductive layer can also be obtained by forming contacts connected to individual transistors in separate processes. A method for manufacturing a semiconductor device different from that of Modification 1 will now be described with reference to FIGS.

[0134] 11 to 14 are cross-sectional views illustrating in order some of the steps of the method for manufacturing the semiconductor device 3 according to the modified example 2 of the embodiment. In Fig. 11 to 14, the same components as those in the semiconductor device 1 of the above-described embodiment are denoted by the same reference numerals, and the description thereof may be omitted.

[0135] 2(a) and 2(b) are also performed on the semiconductor device 3 of Modification 2. As a result, the transistors 10b, 20b, and 30 of Modification 2 are formed as shown in Fig. 11(a). Furthermore, as in Fig. 2(c) above, interlayer insulating layers 211 and 212 covering the transistors 10b, 20b, and 30 are sequentially formed.

[0136] In the processing up to this point, the transistors 10b and 20b have the same configuration as the transistors 10 and 20 of the above-described embodiment. However, for ease of explanation, in order to distinguish them from the transistors 10 and 20 of the above-described embodiment, in Modification 2, these will be referred to as transistors 10b and 20b. Further, a mask pattern 291 a such as a resist pattern having a plurality of hole patterns 291 ha is formed on the interlayer insulating layer 212 .

[0137] Furthermore, the interlayer insulating layers 212 and 211, the liner layers 26 and 36, and the spacer layers 25 and 35 are etched using the mask pattern 291a to form a plurality of contact holes 82s, 83s, and 83g.

[0138] As a result, the contact holes 82s and 83s penetrate the interlayer insulating layers 212 and 211, the liner layers 26 and 36, and the spacer layers 25 and 35, and reach the top of the substrate 100 on both sides of the transistors 20b and 30. The contact hole 83g penetrates the interlayer insulating layers 212 and 211, the liner layer 36, and the spacer layer 35, and reaches a predetermined depth in the cap layer 34.

[0139] Thereafter, the mask pattern 291a is removed by ashing using oxygen plasma or the like.

[0140] As shown in FIG. 11(b), epitaxial layers 121 and 131 such as crystalline silicon layers are formed by epitaxial growth on the substrate 100 exposed at the bottoms of the contact holes 82s and 83s.

[0141] 12(a), an insulating layer 250 such as an LTO layer is formed on the upper surface of the interlayer insulating layer 212. The insulating layer 250 is also formed on the sidewalls and bottom surfaces of the contact holes 82s, 83s, and 83g.

[0142] 12(b), a mask pattern 291b such as a resist pattern having a plurality of hole patterns 291hb and covering the contact holes 82s, 83s, and 83g is formed on the interlayer insulating layer 212. At this time, the mask material constituting the mask pattern 291b may fill part or all of the contact holes 82s, 83s, and 83g.

[0143] 13(a), the interlayer insulating layers 212 and 211 are etched via a mask pattern 291b to form a plurality of contact holes 281s, 281g, and 282g. At this time, for example, excessive over-etching is performed on the contact holes 281g and 282gx, which are shallower than the contact hole 281s.

[0144] As a result, the bottom end of the contact hole 281s reaches the liner layer 16 on the substrate 100 on both sides of the transistor 10b. The bottom ends of the contact holes 281g and 282g pass through the liner layers 16 and 26 and the spacer layers 15 and 25 to reach the cap layers 14 and 24, respectively.

[0145] Thereafter, the mask pattern 291b is removed by ashing using oxygen plasma or the like.

[0146] 13(b), the insulating layer 250 on the bottom surfaces of the contact holes 82s, 83s, and 83g is removed. At this time, the insulating layer 250 on the interlayer insulating layer 212 is also removed. As a result, the contact holes 82s, 83s, and 83g have insulating layers 52s, 53s, and 53g on their side walls, respectively.

[0147] Furthermore, the liner layer 16 and the spacer layer 15 on the bottom surface of the contact hole 281s are removed, and the lower end of the contact hole 281s reaches the substrate 100. Furthermore, the lower ends of the contact holes 281g, 282g, and 83g penetrate the cap layers 14 to 34 and reach the metal electrodes 13 to 33, respectively.

[0148] As shown in FIG. 14(a), a plurality of trenches TR are formed in the interlayer insulating layer 212, each of which is connected to the upper end of the contact holes 281s, 82s, 83s, 281g, 282g, and 83g.

[0149] As shown in FIG. 14(b), the contact holes 281s, 82s, 83s, 281g, 282g, and 83g and the trenches TR are filled with a metal layer such as a tungsten layer or a copper layer all at once or separately.

[0150] As a result, conductive layers 261s, 62s, 63s, 261g, 262g, and 63g are formed in the contact holes 281s, 82s, 83s, 281g, 282g, and 83g, respectively, to obtain a plurality of contacts 271s, 72s, 73s, 271g, 272g, and 73g. In addition, a plurality of wirings D0 are obtained to be connected to these contacts 271s, 72s, 73s, 271g, 272g, and 73g.

[0151] In the above method, since the insulating layer 250 is not formed in the contact holes 281s, 281g, 282g from the beginning, the contact holes 281s, 281g, 282g and the conductive layers 261s, 261g, 262g filled in the contact holes 281s, 281g, 282g, respectively, do not have steps like those in the above-mentioned variant example 1.

[0152] According to the semiconductor device 3 of the second modification, the conductive layers 261g and 262g of the contacts 271g and 272g connected to the metal electrodes 13 and 23 of the transistors 10b and 20b are in direct side contact with the liner layers 16 and 26, respectively, over the entire thickness direction of the liner layers 16 and 26. In this way, the contacts 271g and 272g do not originally have an insulating layer, which further suppresses the intrusion of hydrogen and further improves the characteristics of the transistors 10b and 20b.

[0153] According to the semiconductor device 3 of the second modification, the contacts 271s, 72s, 73s, 271g, 272g, and 73g connected to the transistors 10b, 20b, and 30 are formed separately. This increases the number of manufacturing steps for the semiconductor device 3, but allows the individual contacts 271s, 72s, 73s, 271g, 272g, and 73g to be formed more precisely.

[0154] In addition, the semiconductor device 3 of the second modification has the same effects as the semiconductor device 1 of the above-described embodiment.

[0155] [Application examples of semiconductor devices] The configurations of the above-described embodiment and modifications 1 and 2 can be applied to, for example, transistors that are provided around memory cells of a semiconductor memory device and that constitute a drive circuit that drives the memory cells. Below, with reference to the drawings, a configuration example of a semiconductor memory device including a transistor to which the configuration of any of the above-described embodiment and modifications 1 and 2 is applied will be described.

[0156] (Schematic configuration of semiconductor memory device) 15 is a block diagram of a semiconductor memory device 5 according to another embodiment. As shown in Fig. 15, the semiconductor memory device 5 includes an input / output circuit 310, a logic control circuit 320, a status register 330, an address register 340, a command register 350, a sequencer 360, a ready / busy circuit 370, a voltage generation circuit 380, a memory cell array 510, a row decoder 520, a sense amplifier module 530, a data register 540, and a column decoder 550.

[0157] The input / output circuit 310 controls input and output of a signal DQ to and from an external device such as a memory controller (not shown) that controls the semiconductor memory device 5. The input / output circuit 310 includes an input circuit and an output circuit (not shown).

[0158] The input circuit transmits data DAT such as write data WD received from an external device to the data register 540 , transmits an address ADD to the address register 340 , and transmits a command CMD to the command register 350 .

[0159] The output circuit transmits the status information STS received from the status register 330, the data DAT such as the read data RD received from the data register 540, and the address ADD received from the address register 340 to an external device.

[0160] The logic control circuit 320 receives, for example, a chip enable signal CEn, a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal WEn, and a read enable signal REn from an external device, and controls the input / output circuit 310 and the sequencer 360 in response to the received signals.

[0161] The status register 330 temporarily holds status information STS for, for example, data write, read, and erase operations, and notifies an external device whether the operation has ended normally.

[0162] The address register 340 temporarily holds an address ADD received from an external device via the input / output circuit 310. The address register 340 also transfers a row address RA to the row decoder 520 and a column address CA to the column decoder 550.

[0163] The command register 350 temporarily stores a command CMD received from an external device via the input / output circuit 310 and transfers it to the sequencer 360 .

[0164] The sequencer 360 controls the overall operation of the semiconductor memory device 5. More specifically, the sequencer 360 controls, for example, the status register 330, the ready / busy circuit 370, the voltage generation circuit 380, the row decoder 520, the sense amplifier module 530, the data register 540, and the column decoder 550 in accordance with the command CMD held in the command register 350, and executes a write operation, a read operation, an erase operation, and the like.

[0165] The ready / busy circuit 370 transmits a ready / busy signal R / Bn to an external device depending on the operating status of the sequencer 360 .

[0166] The voltage generation circuit 380 generates voltages required for write, read, and erase operations under the control of the sequencer 360, and supplies the generated voltages to, for example, the memory cell array 510, the row decoder 520, and the sense amplifier module 530. The row decoder 520 and the sense amplifier module 530 apply the voltages supplied from the voltage generation circuit 380 to the memory cells in the memory cell array 510.

[0167] The memory cell array 510 includes a plurality of blocks BLK (BLK0 to BLKn), where n is an integer equal to or greater than 2. A block BLK is a set of a plurality of memory cells associated with bit lines and word lines, and serves as, for example, a unit for erasing data. The memory cells are configured as, for example, transistors, and hold non-volatile data.

[0168] By including such memory cells, the semiconductor memory device 5 is configured as, for example, a NAND-type nonvolatile memory. However, the semiconductor memory device 5 may also be configured as another type of nonvolatile memory, such as a NOR-type.

[0169] The row decoder 520 decodes the row address RA, selects one of the blocks BLK based on the decoding result, and applies a required voltage to the block BLK.

[0170] During a read operation, the sense amplifier module 530 senses data read from the memory cell array 510. The sense amplifier module 530 also transmits read data RD to the data register 540. During a write operation, the sense amplifier module 530 transmits write data WD to the memory cell array 510.

[0171] The data register 540 includes a plurality of latch circuits. The latch circuits hold write data WD and read data RRD. For example, in a write operation, the data register 540 temporarily holds the write data WD received from the input / output circuit 310 and transmits it to the sense amplifier module 530. For example, in a read operation, the data register 540 temporarily holds the read data RD received from the sense amplifier module 530 and transmits it to the input / output circuit 310.

[0172] The column decoder 550 decodes the column address CA during, for example, a write operation, a read operation, or an erase operation, and selects a latch circuit in the data register 540 according to the decoding result.

[0173] The above-described components of the semiconductor memory device 5, excluding the memory cell array 510, are also referred to as peripheral circuits. The peripheral circuits are a group of circuits arranged around the memory cell array 510, and include an input / output circuit 310, a logic control circuit 320, a status register 330, an address register 340, a command register 350, a sequencer 360, a ready / busy circuit 370, a voltage generation circuit 380, a row decoder 520, a sense amplifier module 530, a data register 540, and a column decoder 550.

[0174] As described above, the semiconductor memory device 5 includes a memory cell array 510 including a plurality of memory cells, and peripheral circuits that operate the plurality of memory cells.

[0175] (Circuit configuration of memory cell array and row decoder) 16 is an equivalent circuit diagram showing an example of the configuration of a memory cell array 510 and a row decoder 520 included in a semiconductor memory device 5 according to another embodiment. First, an example of the circuit configuration of the memory cell array 510 included in the semiconductor memory device 5 will be described below.

[0176] As described above, the memory cell array 510 includes a plurality of blocks BLK. Each of the plurality of blocks BLK includes a plurality of string units SU. Each of the plurality of string units SU includes a plurality of memory strings MS. One end of each of the plurality of memory strings MS is connected to peripheral circuits such as a row decoder 520 and a sense amplifier module 530 via a bit line BL. The other end of each of the plurality of memory strings MS is connected to the peripheral circuits via a common source line SL.

[0177] The memory string MS includes a drain select transistor STD connected in series between a bit line BL and a source line SL, a plurality of memory cells MC, and a source select transistor STS. Hereinafter, the drain select transistor STD and the source select transistor STS may be simply referred to as select transistors (STD, STS).

[0178] The memory cells MC are, for example, field effect transistors (FETs) that include a charge storage layer in a gate insulating layer. The threshold voltage of the memory cells MC varies depending on the amount of charge in the charge storage layer. By providing one or more threshold voltages, the memory cells MC may be able to store one or more bits of data. A word line WL is connected to each of the gate electrodes of the memory cells MC corresponding to one memory string MS. Each of these word lines WL is commonly connected to all the memory strings MS in one block BLK.

[0179] The select transistors (STD, STS) are, for example, field-effect transistors. Select gate lines (SGD, SGS) are connected to the gate electrodes of the select transistors (STD, STS), respectively. The drain select line SGD connected to the drain select transistor STD is provided corresponding to the string unit SU and is commonly connected to all memory strings MS in one string unit SU. The source select line SGS connected to the source select transistor STS is commonly connected to all memory strings MS in one block BLK.

[0180] Next, the circuit configuration of the row decoder 520 included in the semiconductor memory device 5 will be described.

[0181] The row decoder 520 includes an address decoder 521, a block selection circuit 522, and a voltage selection circuit 523. The row decoder 520 includes, in these circuits, a transistor TR 1 to which, for example, any of the configurations of the above-described embodiment and modifications 1 and 2 is applied. 22 ,TR 23 etc.

[0182] The address decoder 521 includes a plurality of block select lines BLKSEL and a plurality of voltage select lines VOLSEL.

[0183] The address decoder 521, in accordance with a control signal from the sequencer 360, for example, refers to the address data in the address register 340 (see FIG. 15) included in the peripheral circuit described above.

[0184] The address decoder 521 also decodes the referenced address data and selects a transistor TR corresponding to the address data. 22 and transistor TR 23 and the other transistors TR 22 and transistor TR 23 The transistor TR 22 and transistor TR 23are transistors included in a block selection circuit 522 and a voltage selection circuit 523, which will be described later.

[0185] Furthermore, the address decoder 521 sets the voltages of the block selection line BLKSEL and voltage selection line VOLSEL corresponding to the address data to, for example, the "H" state, and sets the other voltages to the "L" state.

[0186] 16, the address decoder 521 is provided with one block selection line BLKSEL for each block BLK in the memory cell array 510. However, this configuration can be changed as appropriate. For example, one block selection line BLKSEL may be provided for each of two or more blocks BLK.

[0187] The block selection circuit 522 includes a plurality of block selection units 522a to 522c, each corresponding to a block BLK of the memory cell array 510. Each of the plurality of block selection units 522a to 522c includes a plurality of transistors TR corresponding to the word lines WL and the select gate lines (SGD, SGS). 22 Equipped with.

[0188] Transistor TR 22 is, for example, a high-voltage N-channel MOS transistor, and functions as a block driver transistor. 22 The drain electrodes of the transistors TR are electrically connected to the corresponding word lines WL or select gate lines (SGD, SGS). 22 The source electrodes of the transistors TR are electrically connected to the voltage output terminal OTM via the wiring WR and the voltage selection circuit 523. 22 The gate electrodes of the gate electrodes are commonly connected to the corresponding block selection line BLKSEL.

[0189] The block selection circuit 522 also includes a plurality of transistors (not shown). These transistors are high-voltage CMOS transistors connected between the select gate lines (SGD, SGS) and a ground voltage supply terminal. These transistors electrically connect the select gate lines (SGD, SGS) included in the unselected blocks BLK in the memory cell array 510 to the ground voltage supply terminal. Note that the word lines WL included in the unselected blocks BLK are in a floating state.

[0190] The voltage selection circuit 523 includes a plurality of voltage selection units 523a to 523i corresponding to the word lines WL and the select gate lines (SGD, SGS). Each of the plurality of voltage selection units 523a to 523i includes a plurality of transistors TR 23 Equipped with.

[0191] Transistor TR 23 is a high-voltage N-channel MOS transistor that functions as a voltage selection transistor. 23 The drain terminals of the transistors 521 and 522 are electrically connected to the corresponding word lines WL or select gate lines (SGD, SGS) via wiring WR and a block selection circuit 522. The source terminals are electrically connected to the corresponding voltage output terminals OTM. The gate electrodes are connected to the corresponding voltage selection lines VOLSEL.

[0192] In this way, the row decoder 520 belonging to the peripheral circuit has a plurality of transistors TR 22 ,TR 23 These transistors TR 22 ,TR 23 are transistors that are arranged in high density in the row decoder 520 and are the main components of the row decoder 520, and correspond to the transistors 10, 10a, and 10b in any of the above-described embodiment and modified examples 1 and 2, for example.

[0193] However, the circuit configuration of the row decoder 520 shown in FIG. 16 is an example, and the transistor TR 22 ,TR23 The number and type of the etc. may also vary.

[0194] In addition to the above, the row decoder 520 also includes a high-voltage P-channel MOS transistor and a low-voltage P-channel MOS transistor, which are auxiliary components of the row decoder 520. These correspond to, for example, the transistor 30 or the transistors 20, 20a, and 20b in any of the above-described embodiments and modifications 1 and 2.

[0195] [Note] Preferred embodiments of the present invention will be described below.

[0196] (Appendix 1) According to one aspect of the present invention, first and second gate electrodes; first and second spacer layers covering the first and second gate electrodes, respectively; first and second liner layers covering the first and second gate electrodes, respectively, via the first and second spacer layers; a first contact having a first conductive layer extending from above the first liner layer to below the first spacer layer and connected to the first gate electrode; a second contact having a second conductive layer extending from above the second liner layer to below the second spacer layer and connected to the second gate electrode; The first conductive layer comprises: a first insulating layer covering a sidewall of the first conductive layer and contacting the first spacer layer at a side surface thereof; The second conductive layer comprises: directly flanked by the second spacer layer; A semiconductor device is provided.

[0197] (Appendix 2) In the semiconductor device of Supplementary Note 1, further comprising first and second cap layers on the first and second gate electrodes, respectively; The first and second conductive layers pass through the first and second cap layers and are connected to the first and second gate electrodes, respectively.

[0198] (Appendix 3) In the semiconductor device of Supplementary Note 2, The first insulating layer comprises: The first cap layer is formed to a predetermined depth.

[0199] (Appendix 4) In the semiconductor device according to Supplementary Note 3 or Supplementary Note 4, The second conductive layer comprises: It is directly laterally bounded by the second cap layer.

[0200] (Appendix 5) According to another aspect of the present invention, first and second gate electrodes; first and second liner layers covering the first and second gate electrodes, respectively; a first contact connected to the first gate electrode; a second contact connected to the second gate electrode; The first contact comprises: a first conductive layer extending downward from above the first liner layer and reaching the first gate electrode; a first insulating layer covering a sidewall of the first conductive layer and extending downward from above the first liner layer; The second contact comprises: a second conductive layer extending downward from above the second liner layer and reaching the second gate electrode; a second insulating layer on the sidewall, covering the sidewall of the second conductive layer, extending from above the second liner layer to the second liner layer, and remaining on or within the second liner layer; A semiconductor device is provided.

[0201] (Appendix 6) In the semiconductor device of Supplementary Note 5, the first and second insulating layers are oxide layers; The first and second liner layers are nitride layers.

[0202] (Appendix 7) In the semiconductor device according to Supplementary Note 5 or 6, further comprising first and second cap layers on the first and second gate electrodes, respectively; The first and second conductive layers pass through the first and second cap layers and are connected to the first and second gate electrodes, respectively.

[0203] (Appendix 8) In the semiconductor device of Supplementary Note 7, The first insulating layer comprises: The first cap layer is formed to a predetermined depth.

[0204] (Appendix 9) In the semiconductor device according to Supplementary Note 7 or 8, The second conductive layer comprises: It is directly laterally bounded by the second cap layer.

[0205] (Appendix 10) In any one of the semiconductor devices according to Supplementary Note 5 to Supplementary Note 9, The first gate electrode is The gate electrode of a high-voltage P-channel transistor, The second gate electrode is It is the gate electrode of a high-voltage N-channel transistor or a low-voltage P-channel transistor.

[0206] (Appendix 11) According to yet another aspect of the present invention, A gate electrode; a liner layer covering the gate electrode; a contact connected to the gate electrode, The contact a conductive layer extending downward from above the liner layer and reaching the gate electrode; an insulating layer on the sidewalls of the conductive layer, extending from above the liner layer to the liner layer, and remaining on or within the liner layer; A semiconductor device is provided.

[0207] (Appendix 12) In the semiconductor device of Supplementary Note 11, the insulating layer is an oxide layer, The liner layer is a nitride layer.

[0208] (Appendix 13) In the semiconductor device according to claim 11 or 12, a cap layer on the gate electrode; The conductive layer is The electrode is in direct contact with the cap layer at the side thereof, penetrates the cap layer, and is connected to the gate electrode.

[0209] (Appendix 14) In the semiconductor device according to any one of Supplementary Note 11 to Supplementary Note 13, The gate electrode is It is the gate electrode of a high-voltage N-channel transistor or a low-voltage P-channel transistor.

[0210] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0211] 10, 10a, 10b, 20, 20a, 20b, 30...transistors, 12-32...polysilicon electrodes, 13-33...metal electrodes, 14-34...cap layers, 15-35...spacer layers, 16-36...liner layers, 51s-53s, 51g-53g...insulating layers, 61s-63s, 61g-63g, 161g, 162g, 161s, 261g, 262g, 261s...conductive layers, 71g-73g, 71s-73s, 171g, 172g, 171s, 271g, 272g, 271s...contacts.

Claims

1. first and second gate electrodes; first and second spacer layers covering the first and second gate electrodes, respectively; first and second liner layers covering the first and second gate electrodes, respectively, via the first and second spacer layers; a first contact having a first conductive layer extending from above the first liner layer to below the first spacer layer and connected to the first gate electrode; a second contact having a second conductive layer extending from above the second liner layer to below the second spacer layer and connected to the second gate electrode; The first conductive layer comprises: a first insulating layer covering a sidewall of the first conductive layer and contacting the first spacer layer at a side surface thereof; The second contact comprises: a second insulating layer covering the second conductive layer above the second liner layer; The second insulating layer comprises: extending from above the second liner layer to the second liner layer and remaining on or within the second liner layer; The second conductive layer comprises: directly flanked by the second spacer layer; Semiconductor device.

2. The first insulating layer comprises: the first liner layer covers the first conductive layer from above to below; The semiconductor device according to claim 1 .

3. the first and second insulating layers are oxide layers; the first and second liner layers are nitride layers; The semiconductor device according to claim 2 .

4. The second conductive layer comprises: the second liner layer is in direct side contact with the second liner layer throughout the thickness of the second liner layer; The semiconductor device according to claim 1 .

5. The second conductive layer comprises: The second liner layer has a step at a height position thereof, The diameter of the second conductive layer is The step is narrowed at a lower position thereof. The semiconductor device according to claim 4 .

6. The first gate electrode is a gate electrode of a high-voltage P-channel transistor; The second gate electrode is A gate electrode of a high-voltage N-channel transistor or a low-voltage P-channel transistor.

6. The semiconductor device according to claim 1.

7. First and second gate electrodes; first and second spacer layers covering the first and second gate electrodes, respectively; first and second liner layers covering the first and second gate electrodes, respectively, via the first and second spacer layers; a first contact having a first conductive layer extending from above the first liner layer to below the first spacer layer and connected to the first gate electrode; a second contact having a second conductive layer extending from above the second liner layer to below the second spacer layer and connected to the second gate electrode; The first contact comprises: a first insulating layer covering a sidewall of the first conductive layer and extending from above the first liner layer to below the first spacer layer, the first conductive layer being in contact with the first spacer layer at a side surface via the first insulating layer; The second contact comprises: The second conductive layer has a configuration in which the second conductive layer directly contacts the second spacer layer at a side thereof without having an insulating layer covering the sidewall of the second conductive layer and extending from above the second liner layer to below the second spacer layer. Semiconductor device.

8. first and second gate electrodes; first and second liner layers covering the first and second gate electrodes, respectively; a first contact connected to the first gate electrode; a second contact connected to the second gate electrode; The first contact comprises: a first conductive layer extending downward from above the first liner layer to reach the first gate electrode; a first insulating layer covering a sidewall of the first conductive layer and extending downward from above the first liner layer; The second contact comprises: a second conductive layer extending downward from above the second liner layer to reach the second gate electrode; a second insulating layer on the sidewall, the second insulating layer covering the sidewall of the second conductive layer and extending from above the second liner layer to the second liner layer and remaining on or within the second liner layer; Semiconductor device.

9. A gate electrode; a liner layer covering the gate electrode; a contact connected to the gate electrode, The contact a conductive layer extending downward from above the liner layer and reaching the gate electrode; an insulating layer on the sidewalls of the conductive layer, extending from above the liner layer to the liner layer, and remaining on or within the liner layer; Semiconductor device.

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