Tunnel current drive element

Abstract

To obtain large on-state current using an indirect transition type semiconductor and suppress variation in electric characteristic between elements.SOLUTION: A tunnel current driving element 10 includes: a first conductivity type semiconductor layer 1; a second conductivity type semiconductor layer 2; and an intermediate layer in which a first base material layer 3a, a quantum well layer 4, and a second base material layer 3b are stacked in this order in a direction from the first conductivity type semiconductor layer 1 toward the second conductivity type semiconductor layer 2. The first base material layer 3a is formed of a first semiconductor material. The second base material layer 3b is formed of a second semiconductor material. The quantum well layer 4 is formed of a third semiconductor material that is different in species from the first semiconductor material or the second semiconductor material. The third semiconductor material has at least one of a band structure in which a valence band edge exists at an energy position higher than that of the first semiconductor material and the second semiconductor material, and a band structure in which a conduction band edge exists at an energy position lower than the conduction band edge of the first semiconductor material and the second semiconductor material.SELECTED DRAWING: Figure 2(a)

Description

[Technical Field]

[0001] The present invention relates to a tunnel current driven element that is driven by a tunnel current generated by a band-to-band tunneling phenomenon. [Background technology]

[0002] Known tunnel current-driven elements include tunnel diodes and tunnel field-effect transistors, which are driven by a tunnel current generated by the band-to-band tunneling phenomenon. However, there is a problem in that the tunnel current (on-current) during operation is small.

[0003] The semiconductor materials used to manufacture the tunnel current driving element are classified into two types: direct transition semiconductors and indirect transition semiconductors. The former mainly includes compound semiconductors, while the latter mainly includes group IV semiconductors. Generally, the probability of the band-to-band tunneling phenomenon occurring is higher in direct transition semiconductors than in indirect transition semiconductors, and therefore the use of compound semiconductors is considered to be effective in increasing the on-current (see Non-Patent Document 1). However, the method of using compound semiconductors has a problem in that it is not possible to use many of the existing semiconductor element manufacturing facilities for manufacturing the tunnel current driving element, which requires new capital investment and increases manufacturing costs.

[0004] On the other hand, typical materials of the group IV semiconductor are silicon and germanium, and although the tunnel current driving element can be manufactured using existing semiconductor element manufacturing facilities, the probability of the band-to-band tunneling phenomenon occurring is low, and there still remains a challenge in increasing the on-current. That is, in the energy band structure of the indirect transition semiconductor, the momentum at the top of the valence band does not match the momentum at the bottom of the conduction band, and there is a difference in momentum between the electrons at the top of the valence band and the electrons at the bottom of the conduction band. The transition of electron states from the valence band to the conduction band due to the band-to-band tunneling must satisfy the law of conservation of momentum. Due to the constraints of this law of conservation of momentum, it is difficult to obtain a large tunnel current in the tunnel current driving element using the indirect transition semiconductor in which there is a momentum misalignment.

[0005] To address this issue, the present inventors have reported the tunnel current driving element in which the on-current is increased by introducing an isoelectronic trap (IET) forming impurity into the indirect transition semiconductor (see Patent Document 1). FIG. 1(a) shows an example of the configuration of a tunnel diode using IET-forming impurities. The tunnel diode 100 according to this example is N + Semiconductor layer 101 and P + The intrinsic semiconductor layer 103 is disposed between the semiconductor layer 102 and the IET-forming impurities are introduced thereinto. When a reverse voltage is applied to this tunnel diode 100, electrons can tunnel from the valence band to the conduction band using the IET level formed in the band gap as a bridge, as shown in Figure 1(b), thereby increasing the probability of the band-to-band tunneling phenomenon occurring. Figure 1(b) shows the band structure of a tunnel diode using IET-forming impurities.

[0006] However, the IET-forming impurities introduced into the tunnel diode 100 are N + Semiconductor layer 101, P + The IET-forming impurities are introduced into the semiconductor layer 102 and the intrinsic semiconductor layer 103 by ion implantation and distributed randomly. Therefore, the introduction positions of the IET-forming impurities cannot be controlled as shown in FIG. 1(a), and the IET levels vary and are formed randomly at multiple positions as shown in FIG. 1(b). As a result, the tunnel diode 100 has a problem in that the electrical characteristics tend to vary from one production to the next. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] Patent No. 6253034 [Non-patent literature]

[0008] [Non-Patent Document 1] G. Dewey et al., 2011 International Electron Devices Meeting Technical Digest, 33.6, “Fabrication, characterization, and physics of III-V heterojunction tunneling Field Effect Transistors (H-TFET) for steep sub-threshold swing” Summary of the Invention [Problem to be solved by the invention]

[0009] The present invention aims to solve the above-mentioned problems in the prior art and to achieve the following object: to provide a tunnel current driving element that uses an indirect transition semiconductor to obtain a large on-current and that can suppress variations in electrical characteristics between elements. [Means for solving the problem]

[0010] The means for solving the above problems are as follows: <1> It is made of an indirect transition semiconductor material and has a first conductivity type, which is either p-type or n-type, and an impurity concentration of 3×10 19 cm -3a second conductivity type semiconductor layer formed of the indirect transition type semiconductor material and having a second conductivity type different from the first conductivity type; and an intermediate layer sandwiched between the first conductivity type semiconductor layer and the second conductivity type semiconductor layer and formed of either an intrinsic semiconductor or an impurity-containing semiconductor having an impurity concentration lower than the impurity concentrations of the first conductivity type semiconductor layer and the second conductivity type semiconductor layer, wherein the intermediate layer has a layered structure in which at least one first base material layer and one quantum well layer are alternately stacked in this order on the first conductivity type semiconductor layer serving as a base layer, with a first direction from the first conductivity type semiconductor layer toward the second conductivity type semiconductor layer as a stacking direction, and a second base material layer is stacked on the quantum well layer closest to the second conductivity type semiconductor layer, the first base material layer is formed of a first semiconductor material selected from the indirect transition type semiconductor materials and has a thickness in the first direction of 0.5 nm to 20 nm, and the second base material layer is selected from the indirect transition type semiconductor materials. The a tunnel current driving element, characterized in that the quantum well layer is formed of two semiconductor materials and has a thickness of 10 nm to 500 nm in the first direction, the quantum well layer is formed of a third semiconductor material selected from the indirect transition semiconductor materials different from the first semiconductor material and the second semiconductor material and has a thickness of 0.5 nm to 10 nm in the first direction, and the third semiconductor material is selected from the indirect transition semiconductor materials having at least one of a first band structure in which a valence band edge is located at a higher energy position than the valence band edges of the first semiconductor material and the second semiconductor material, and a second band structure in which a conduction band edge is located at a lower energy position than the conduction band edges of the first semiconductor material and the second semiconductor material. <2> The band structure is at least one of a first band structure in which the valence band edge is located at an energy position that is higher by more than 0.1 eV than the valence band edge having the highest energy position of either the first semiconductor material or the second semiconductor material, and a second band structure in which the conduction band edge is located at an energy position that is lower by more than 0.1 eV than the conduction band edge having the lowest energy position of either the first semiconductor material or the second semiconductor material. <1> The tunnel current driving element according to claim 1. <3> The first semiconductor material, the second semiconductor material, and the third semiconductor material are selected from any combination of the following (1) to (6): <1> from <2> 2. The tunnel current driving element according to claim 1, wherein (1) The first semiconductor material and the second semiconductor material are Si, and the third semiconductor material is Si, where x is greater than 0 and less than 1. 1-x Ge x The combination is: (2) A combination in which the first semiconductor material and the second semiconductor material are Si, and the third semiconductor material is Ge. (3) The first semiconductor material and the second semiconductor material are Si, where x is greater than 0 and less than 1. 1-x Ge x and the third semiconductor material is Si, where y is greater than 0 but less than 1 and greater than x. 1-y Ge y The combination is: (4) The first semiconductor material and the second semiconductor material are Si, where x is greater than 0 and less than 1. 1-x Ge x and the third semiconductor material is Ge. (5) The first semiconductor material and the second semiconductor material are Si, and the third semiconductor material is Si, where x is greater than 0 and less than 1. 1-x C x The combination is: (6) The first semiconductor material and the second semiconductor material are Si, and the third semiconductor material is Si, where x is greater than 0 and less than 1, y is greater than 0 and less than 1, and x + y is less than 1. 1-x-y Ge x C y The combination is: <4> The first semiconductor material, the second semiconductor material, and the third semiconductor material are the combination of (1), and x is 0.12 or more. <3> The tunnel current driving element according to claim 1. <5> The first conductive type semiconductor layer, the second conductive type semiconductor layer and the intermediate layer are formed as single crystal layers of indirect transition type semiconductor materials. <1> from <4> 2. The tunnel current driving element according to claim 1, wherein <6> The thickness of the first base material layer in the first direction is 8 nm or less. <1> from <5> 2. The tunnel current driving element according to claim 1, wherein <7> The device structure of a tunnel diode includes an n-type semiconductor layer and a p-type semiconductor layer, and a low-impurity-concentration layer formed of either an intrinsic semiconductor or an impurity-containing semiconductor having an impurity concentration lower than the impurity concentrations of the n-type semiconductor layer and the p-type semiconductor layer is disposed between the n-type semiconductor layer and the p-type semiconductor layer, and the device structure includes the n-type semiconductor layer formed of a first conductivity type semiconductor layer having an n-type as a first conductivity type, and the p-type semiconductor layer formed of a second conductivity type semiconductor layer having a p-type as a second conductivity type. layer and a first element structure in which the low impurity concentration layer is an intermediate layer, and the p-type semiconductor layer is a first conductive type semiconductor layer in which the first conductive type is p-type, and the n-type semiconductor layer is a second conductive type semiconductor layer in which the second conductive type is n-type. layer and a second element structure in which the low impurity concentration layer is formed by the intermediate layer. <1> from <6> 2. The tunnel current driving element according to claim 1, wherein <8> The device structure of a tunnel field effect transistor has a channel region formed between a source region and a drain region, and a gate electrode formed on the channel region via a gate insulating film, wherein the source region is made of a first conductivity type semiconductor layer, the drain region is made of a second conductivity type semiconductor layer, and the channel region is made of an intermediate layer. <1> from <6> 2. The tunnel current driving element according to claim 1, wherein <9> The length of the quantum well layer in a second direction perpendicular to the first direction as viewed from a position in contact with the gate insulating film is at least 5 nm. <8> The tunnel current driving element according to claim 1. [Effects of the Invention]

[0011] According to the present invention, it is possible to solve the above-mentioned problems in the prior art, and to provide a tunnel current driving element that uses an indirect transition semiconductor to obtain a large on-current and that can suppress variations in electrical characteristics between elements. [Brief explanation of the drawings]

[0012] [Figure 1(a)] FIG. 1 is a diagram showing a configuration example of a tunnel diode using an IET-forming impurity. [Figure 1(b)] FIG. 1 is a diagram showing the band structure of a tunnel diode using IET-forming impurities in the on-state. [Figure 2(a)] 1 is a cross-sectional view illustrating a tunnel current driving element according to an embodiment of the present invention. [Figure 2(b)] FIG. 2 is a diagram showing a band structure in the on-state of the tunnel current driving element according to the present invention. [Figure 3] FIG. 1 is a diagram showing a band structure in a typical heterojunction. [Figure 4] FIG. 2 is an explanatory diagram for explaining the relationship between a tunnel window and a quantum well. [Figure 5] 10 is a cross-sectional view illustrating a modified example of the tunnel current driver 10. FIG. [Figure 6(a)] FIG. 11 is a diagram (1) showing an example of a band structure in an on-state of a tunnel current driving element according to a modified example. [Figure 6(b)] FIG. 10 is a diagram (2) showing an example of a band structure in an on-state of a tunnel current driving element according to a modified example. [Figure 7(a)] FIG. 10 is a cross-sectional view illustrating a configuration example of a practical tunnel current driving element when applied as a tunnel diode. [Figure 7(b)] 1 is a schematic cross-sectional view (1) for explaining an outline of the manufacturing process of the tunnel current drive element 20. FIG. [Figure 7(c)] 10 is a schematic cross-sectional view (2) for explaining an outline of the manufacturing process of the tunnel current drive element 20. FIG. [Figure 7(d)] 10 is a schematic cross-sectional view (3) for explaining an outline of the manufacturing process of the tunnel current drive element 20. FIG. [Figure 7(e)] 10 is a schematic cross-sectional view (4) for explaining an outline of the manufacturing process of the tunnel current drive element 20. FIG. [Figure 8] FIG. 10 is a cross-sectional view illustrating a tunnel current driving element when applied to a tunnel field effect transistor. [Figure 9(a)]FIG. 1 is a band structure diagram (1) for explaining the operation of an N-type tunnel field effect transistor. [Figure 9(b)] FIG. 2 is a band structure diagram (2) for explaining the operation of an N-type tunnel field effect transistor. [Figure 10(a)] FIG. 1 is a band structure diagram (1) for explaining the operation of a P-type tunnel field effect transistor. [Figure 10(b)] This is a band structure diagram (2) that explains the operation of a P-type tunnel field effect transistor. [Figure 11(a)] FIG. 1 is a cross-sectional view illustrating a practical configuration example of a practical tunnel current driving element when applied to a tunnel field effect transistor. [Figure 11(b)] 1 is a schematic cross-sectional view (1) for explaining an outline of the manufacturing process of the tunnel current drive element 40. FIG. [Figure 11(c)] 10 is a schematic cross-sectional view (2) for explaining an outline of the manufacturing process of the tunnel current drive element 40. FIG. [Figure 11(d)] 10 is a schematic cross-sectional view (3) for explaining an outline of the manufacturing process of the tunnel current drive element 40. FIG. [Figure 11(e)] 10 is a schematic cross-sectional view (4) for explaining an outline of the manufacturing process of the tunnel current drive element 40. FIG. [Figure 11(f)] 10 is a schematic cross-sectional view (5) for explaining an outline of the manufacturing process of the tunnel current driver 40. FIG. [Figure 12] 10 is a cross-sectional view illustrating a modified example of the tunnel current drive element 30. FIG. [Figure 13] FIG. 1 is a diagram showing a test target model for a simulation test. [Figure 14] 10 is an explanatory diagram illustrating a setting state of the distance (x0) between the N+ type Si semiconductor layer and the center position of the SiGe quantum well layer in the first direction. FIG. [Figure 15] FIG. 1 is a diagram showing the energy band structures of Si and SiGe (Ge composition 60%) obtained by a simulation test. [Figure 16] FIG. 10 is a diagram showing the tunnel current characteristics of a pin-type tunnel diode in a simulation test. [Figure 17(a)] FIG. 10 is a diagram showing the positional relationship between a tunnel window and a quantum well formed by a SiGe quantum well layer in a model where x0 is 5.6 nm. [Figure 17(b)] FIG. 10 is a diagram showing the positional relationship between a tunnel window and a quantum well formed by a SiGe quantum well layer in a model where x0 is 8.8 nm. [Figure 18] FIG. 1 is an explanatory diagram showing the configuration of a tunnel current driving element according to an embodiment. [Figure 19] FIG. 10 is a diagram showing the carrier (electron, hole) density distribution in a tunnel current drive element according to a comparative example. [Figure 20] FIG. 10 is a diagram showing a TEM image of a laminated structure portion of an intermediate layer (i-Si / i-SiGe / i-Si) of the tunnel current drive element according to the example. [Figure 21] FIG. 10 is a diagram showing the results of measuring the IV characteristics of each tunnel current driving element according to the example and the comparative example. DETAILED DESCRIPTION OF THE INVENTION

[0013] (Tunnel current drive element) The tunnel current driving element of the present invention will be described with reference to the drawings. FIG. 2(a) shows a tunnel current driving device according to one embodiment of the present invention. As shown in FIG. 2(a), the tunnel current driving element 10 includes a first conductivity type semiconductor layer 1, a second conductivity type semiconductor layer 2, and an intermediate layer having a first base material layer 3a, a quantum well layer 4, and a second base material layer 3b. In this specification, the term "tunnel current driven element" refers to a semiconductor element that is driven by a tunnel current based on the band-to-band tunneling phenomenon that occurs in the element, and includes tunnel diodes such as Esaki diodes and resonant tunneling diodes, and tunnel field effect transistors.

[0014] <First Conductivity Type Semiconductor Layer> The first conductive type semiconductor layer 1 is made of an indirect transition semiconductor material and is of the first conductive type, which is either p-type or n-type, and has an impurity concentration of 3×1019 cm -3 That is all.

[0015] The indirect transition semiconductor material is not particularly limited and can be appropriately selected depending on the purpose. Examples include various materials for forming semiconductor layers containing high concentrations of impurities in known tunnel diodes and various materials for forming semiconductor layers that serve as source and drain regions in known tunnel field effect transistors. A typical example of a suitable indirect bandgap semiconductor material is Si (silicon), since it can be easily manufactured using many of the existing semiconductor device manufacturing facilities.

[0016] The impurity concentration of the first conductive type semiconductor layer 1 is 3×10 19 cm -3 Although it is acceptable if it is above 3×10, the higher the better. 20 cm -3 That's about it. The impurity that imparts the conductivity type is not particularly limited and can be appropriately selected depending on the purpose, and examples thereof include impurities used in the manufacture of known semiconductor elements. A representative example of a p-type impurity is B (boron), and a representative example of an n-type impurity is P (phosphorus).

[0017] The method for forming the first conductivity type semiconductor layer 1 is not particularly limited and can be appropriately selected depending on the purpose. Examples include various methods for forming semiconductor layers containing a high concentration of impurities in known tunnel diodes, and various methods for forming semiconductor layers that serve as source and drain regions in known tunnel field effect transistors. A suitable method for forming the semiconductor layer is an epitaxial growth method using a semiconductor layer having a crystal orientation as a template, from the viewpoint of suppressing variations in electrical characteristics with a high-quality semiconductor layer. Furthermore, the first conductivity type semiconductor layer 1 can be configured as a single crystal layer, a polycrystalline layer, or an amorphous layer of the indirect transition semiconductor material, but from the viewpoint of suppressing variations in electrical characteristics by using a high-quality semiconductor layer, it is preferable to configure it as a single crystal layer of the indirect transition semiconductor material.

[0018] <Second Conductivity Type Semiconductor Layer> The second conductivity type semiconductor layer 2 is formed of the indirect transition semiconductor material and is of a second conductivity type that is different from the first conductivity type. Unlike the first conductivity type semiconductor layer 1, which requires tunneling of carriers at the junction interface with the first base material layer 3a described later, the second conductivity type semiconductor layer 2 does not require a steep difference in impurity concentration at the junction interface with the second base material layer 3b described later. Therefore, the second conductivity type semiconductor layer 2 can be configured by appropriately selecting from a layer having an impurity concentration distribution in which the junction interface side with the second base material layer 3b is a low concentration region and other regions are high concentration regions, a layer in which the impurity concentration itself is uniformly high, etc. Typical examples include a layer in which the impurity concentration itself is uniformly high and a layer including a high impurity concentration region. In the description of the second conductivity type semiconductor layer 2, the high impurity concentration means that the impurity concentration is 3×10 19 cm -3 This means that the upper limit is 3×10 20 cm -3 In addition, the impurity concentration is low when the impurity concentration is 3×10 19 cm -3 The lower limit is 0cm. -3 Any concentration exceeding this is sufficient.

[0019] The same explanations as for the first conductivity type semiconductor layer 1 can be applied to the second conductivity type semiconductor layer 2, except that the conductivity type is different and the impurity introduction setting may be different, and the same explanations as for the first conductivity type semiconductor layer 1 can be applied to the formation material and formation method thereof. In addition, the first conductiveThe first conductivity type semiconductor layer 1 and the second conductivity type semiconductor layer 2 may be formed using different materials and different methods selected from among the common description items.

[0020] <Middle class> The intermediate layer is sandwiched between the first conductivity type semiconductor layer 1 and the second conductivity type semiconductor layer 2, and is formed of either an intrinsic semiconductor or an impurity-containing semiconductor having an impurity concentration lower than the impurity concentrations of the first conductivity type semiconductor layer 1 and the second conductivity type semiconductor layer 2. The intermediate layer has a laminated structure in which at least one first base material layer 3a and one quantum well layer 4 are alternately laminated in this order on the first conductivity type semiconductor layer 1 serving as a base layer, with the lamination direction being a first direction from the first conductivity type semiconductor layer 1 toward the second conductivity type semiconductor layer 2, and a second base material layer 3b is laminated on the quantum well layer 4 closest to the second conductivity type semiconductor layer 2 (however, the example shown in Figure 2(a) is an example in which there is one first base material layer 3a and one quantum well layer 4). The lamination direction is an expression when viewing the structure of the product, and does not mean the lamination direction in the method of forming the product. That is, as a formation method, it is not only possible to alternately laminate at least one first base material layer 3a and one quantum well layer 4 in this order on the first conductive type semiconductor layer 1 from the first direction (rightward in FIG. 2(a)) and laminate a second base material layer 3b on the quantum well layer 4 closest to the second conductive type semiconductor layer 2, but also possible to laminate at least one second base material layer 3b on the second conductive type semiconductor layer 2 from the second conductive type semiconductor layer 2 from the direction opposite to the first direction (leftward in FIG. 2(a)) and laminate at least one quantum well layer 4 and one first base material layer 3a on the second base material layer 3b in this order. Furthermore, when the second conductivity type semiconductor layer 2 is configured as a layer including a high concentration region of the impurity (partially including a low concentration region of the impurity), and the intermediate layer is configured as a layer of the impurity-containing semiconductor, the impurity concentration of the impurity-containing semiconductor layer being lower than the impurity concentration of the second conductivity type semiconductor layer 2 means that the impurity concentration of the impurity-containing semiconductor layer is lower than the impurity concentration in the high concentration region of the impurity in the second conductivity type semiconductor layer 2, and does not mean that it is lower than the impurity concentration in the low concentration region of the impurity.

[0021] When the intermediate layer is formed as a layer of the impurity-containing semiconductor, if the impurity concentration is high, the band is difficult to bend in the on state, making it difficult to obtain a band structure suitable for band-to-band tunneling of carriers, and unintended leakage current is likely to occur in the off state. Therefore, the lower the impurity concentration is, the more preferable it is, and specifically, it is preferably one order of magnitude lower than the impurity concentrations of the first conductivity type semiconductor layer 1 and the second conductivity type semiconductor layer 2. For example, when the impurity concentrations of the first conductivity type semiconductor layer 1 and the second conductivity type semiconductor layer 2 are both 3×10 19 cm -3 When the impurity concentration of the intermediate layer is 3×10 18 cm -3 It is more preferable that it is less than 10 ...

[0022] -1st base material layer- The first base material layer 3a is selected from the indirect transition semiconductor materials. The The layer is made of a semiconductor material and has a thickness in the first direction of 0.5 nm to 20 nm. If the thickness is less than 0.5 nm, defects may occur in the layer, causing the quantum well layer 4 to partially bond with the first conductivity type semiconductor layer 1, which is a high-concentration impurity layer, and this may hinder the tunneling of carriers through the localized levels formed by the quantum well layer 4. If the thickness exceeds 20 nm, the distance between the first conductivity type semiconductor layer 1 and the quantum well layer 4 exceeds the distance over which carriers can tunnel, hindering the tunneling of carriers through the intermediate energy levels formed between bands by the quantum well layer 4.

[0023] The first semiconductor material is not particularly limited and can be selected depending on the purpose. Examples include Si, SiGe (silicon germanium), GaP (gallium phosphide), AlP (aluminum phosphide), and AlAs (aluminum arsenide). Among these, Si and SiGe are preferred because they can be easily manufactured using many of the existing semiconductor device manufacturing facilities.

[0024] The method for forming the first base material layer 3a is not particularly limited and can be appropriately selected depending on the purpose, and examples thereof include various known methods for forming semiconductor layers. A suitable method for forming the semiconductor layer is an epitaxial growth method using a semiconductor layer having a crystal orientation as a template, from the viewpoint of suppressing variations in electrical characteristics with a high-quality semiconductor layer. Furthermore, the first base material layer 3a can be configured as a single crystal layer, a polycrystalline layer, or an amorphous layer of the first semiconductor material, but from the viewpoint of suppressing variations in electrical characteristics by using a high-quality semiconductor layer, it is preferable to configure it as a single crystal layer of the first semiconductor material.

[0025] -Second base material layer- The second base material layer 3b is made of a second semiconductor material selected from the indirect transition semiconductor materials and has a thickness in the first direction of 10 nm to 500 nm. If the thickness is less than 10 nm, unintended leakage current cannot be controlled by ON / OFF operation, and if it exceeds 500 nm, the size of the tunnel current driver 10 becomes unnecessarily large.

[0026] The second semiconductor material is not particularly limited and can be selected depending on the purpose. Examples include Si, SiGe (silicon germanium), GaP (gallium phosphide), AlP (aluminum phosphide), and AlAs (aluminum arsenide). Among these, Si and SiGe are preferred because they can be easily manufactured using many of the existing semiconductor device manufacturing facilities. Furthermore, the second semiconductor material may be the same type of semiconductor material as the first semiconductor material or a different type of semiconductor material, but from the viewpoint of simplifying the manufacturing process, it is preferable that the second semiconductor material be the same type of semiconductor material as the first semiconductor material. Furthermore, the same methods for forming and crystallinity of the second base material layer 3b as those described for the first base material layer 3a can be applied.

[0027] -Quantum well layer- The quantum well layer 4 is formed of a third semiconductor material selected from the indirect bandgap semiconductor materials different from the first and second semiconductor materials. The third semiconductor material is selected from the indirect transition semiconductor materials having at least one of a first band structure in which the valence band edge is located at a higher energy position than the valence band edges of the first semiconductor material and the second semiconductor material, and a second band structure in which the conduction band edge is located at a lower energy position than the conduction band edges of the first semiconductor material and the second semiconductor material. The band structure means a band structure determined from the energy band value inherent to the material, and whether the tunneling current driver device 10 has such a band structure can be confirmed by analyzing the constituent materials.

[0028] The third semiconductor material is not particularly limited and can be selected depending on the purpose. Examples include Si, Ge (germanium), SiGe, SiC, SiGeC (silicon germanium carbon), AlAs, GaP, etc. Among these, Si, Ge, SiGe, SiC, and SiGeC are preferred because they can be easily manufactured using many of the existing semiconductor element manufacturing facilities.

[0029] The method for forming the quantum well layer 4 is not particularly limited and can be appropriately selected depending on the purpose, and examples thereof include various known methods for forming semiconductor layers. A suitable method for forming the semiconductor layer is an epitaxial growth method using a semiconductor layer having a crystal orientation as a template, from the viewpoint of suppressing variations in electrical characteristics with a high-quality semiconductor layer. Furthermore, the quantum well layer 4 can be configured as a single crystal layer, a polycrystalline layer, or an amorphous layer of the third semiconductor material, but is preferably configured as a single crystal layer of the third semiconductor material from the viewpoint of suppressing variations in electrical characteristics by using a high-quality semiconductor layer.

[0030] The quantum well layer 4 is a layer having a thickness in the first direction of 0.5 nm to 10 nm. With such a thickness, a quantum well that brings about interband tunneling can be formed between bands.

[0031] In the present invention, unlike the IET levels of the tunnel current driving device in the prior art (see Figs. 1(a) and 1(b)), interband tunneling is brought about by bridging the localized intermediate energy level due to the quantum well formed between the bands, as shown in Fig. 2(b). Fig. 2(b) shows the band structure in the tunnel current driving device according to the present invention. The energy depth (eV) of the quantum well formed by such quantum well layer 4 can be intentionally controlled by selecting the third semiconductor material relative to the first semiconductor material and the second semiconductor material, and the position of the quantum well in the band structure can be intentionally controlled by the location where the quantum well layer is formed in the intermediate layer. As a result, in the tunnel current driving element 10, unlike the IET level formed by the random distribution of the IET impurities (see FIG. 2(b)), the intermediate energy level that brings about interband tunneling can be formed at an intended position, and it is possible to suppress variations in electrical characteristics between elements while having the effect of increasing the tunnel current.

[0032] In the present invention, the core of the technology is to realize band-to-band tunneling through the intermediate energy level formed by this quantum well, and in this sense, the selection of the third semiconductor material relative to the first semiconductor material and the second semiconductor material is crucial. In the following, a case where the first semiconductor material and the second semiconductor material are the same type of semiconductor material will be described first. Figure 3 shows the band structure of a typical heterojunction. Of these, in the Type-I band structure in which the energy levels at the valence band edge (Ev) and the conduction band edge (Ec) shift in opposite directions, in the first band structure from the left in Figure 3, in which the energy levels at the valence band edge (Ev) and the conduction band edge (Ec) both shift in directions away from each other, a concave energy level is not formed in the forbidden band, and the quantum well is not formed. In contrast, the quantum well is formed in the band structure shown second from the left in Fig. 3, in which the energy levels at the valence band edge (Ev) and the conduction band edge (Ec) shift toward each other. That is, in the band structure shown second from the left in Fig. 3, a concave energy level in the forbidden band is formed as the quantum well. In the Type-II two-band structure in which the energy levels at the valence band edge (Ev) and the conduction band edge (Ec) shift in the same direction, a concave energy level in the forbidden band is formed as the quantum well on either the valence band edge (Ev) or the conduction band edge (Ec). In this case, band-to-band tunneling can be achieved through the quantum well formed on either the valence band edge (Ev) or the conduction band edge (Ec). Therefore, the combination of the third semiconductor material with the first semiconductor material and the second semiconductor material is a combination that forms the second band structure from the left in FIG. 3 for Type-I, and a combination that forms the band structure of Type-II.

[0033] The combination of the first semiconductor material, the second semiconductor material, and the third semiconductor material can be appropriately selected from the materials described above in accordance with the above principles. Among them, the following combinations (1) to (6) are preferred because they can be easily manufactured using many of the existing semiconductor element manufacturing facilities. (1) The first semiconductor material and the second semiconductor material are Si, and the third semiconductor material is Si, where x is greater than 0 and less than 1. 1-x Ge x The combination is: (2) A combination in which the first semiconductor material and the second semiconductor material are Si, and the third semiconductor material is Ge. (3) The first semiconductor material and the second semiconductor material are Si, where x is greater than 0 and less than 1. 1-x Ge x and the third semiconductor material is Si, where y is greater than 0 but less than 1 and greater than x. 1-y Ge y The combination is: (4) The first semiconductor material and the second semiconductor material are Si, where x is greater than 0 and less than 1. 1-x Ge x and the third semiconductor material is Ge. (5) The first semiconductor material and the second semiconductor material are Si, and the third semiconductor material is Si, where x is greater than 0 and less than 1. 1-x C x The combination is: (6) The first semiconductor material and the second semiconductor material are Si, and the third semiconductor material is Si, where x is greater than 0 and less than 1, y is greater than 0 and less than 1, and x + y is less than 1. 1-x-y Ge x C y The combination is:

[0034] Furthermore, in the combination of the first semiconductor material, the second semiconductor material, and the third semiconductor material, the deeper the energy depth (eV) of the quantum well, the easier it is to obtain the effect of increasing the tunnel current. That is, as shown in FIG. 4, in the bent band structure during the on-state operation, the conduction band edge on the first conductivity type semiconductor layer 1 side and the conduction band edge on the second conductivity type semiconductor layer 2 side are bent. layerThe deeper the energy depth (eV) of the quantum well is with respect to the tunnel window (the energy band surrounded by the dotted line in FIG. 4, where band-to-band tunneling is likely to occur), which is a band-shaped energy band located between the valence band edge on the upper side and the conduction band edge on the lower side, the more the intermediate energy level between the valence band edge and the conduction band edge of the quantum well layer 4 can be positioned within the tunnel window, thereby improving the probability of band-to-band tunneling using the intermediate energy level as a bridge. As a result, a deeper energy depth (eV) of the quantum well can achieve a greater increase in tunnel current than a shallower energy depth. FIG. 4 is an explanatory diagram illustrating the relationship between the tunnel window and the quantum well. Therefore, the first band structure in the band structure (at least one of the first band structure and the second band structure) of the third semiconductor material is preferably a band structure in which the valence band edge is located at an energy position that is more than 0.1 eV higher than the valence band edge which has the highest energy position of either the first semiconductor material or the second semiconductor material, and the second band structure is preferably a band structure in which the conduction band edge is located at an energy position that is more than 0.1 eV lower than the conduction band edge which has the lowest energy position of either the first semiconductor material or the second semiconductor material (hereinafter, this condition will be referred to as the "preferable condition for the combination").

[0035] Specific examples of combinations that satisfy the above-mentioned preferable conditions for combination include the following combinations. The combination (1) (wherein the first semiconductor material and the second semiconductor material are Si, where x is greater than 0 and less than 1) 1-x Ge x and the third semiconductor material is Ge), wherein x is 0.12 or more and less than 1. The combination (2) (the combination in which the first semiconductor material and the second semiconductor material are Si, and the third semiconductor material is Ge). The combination (3) (wherein the first semiconductor material and the second semiconductor material are Si, where x is more than 0 and less than 1) 1-x Ge xand the third semiconductor material is Si, where y is greater than 0 but less than 1 and greater than x. 1-y Ge y In the above combinations, y and x are 0.12 or greater. The combination of (5) (the first semiconductor material and the second semiconductor material are Si, and the third semiconductor material is Si, where x is more than 0 and less than 1) 1-x C x In the above combinations, x is greater than or equal to 0.015 and less than 1. The combination of (6) (the first semiconductor material and the second semiconductor material are Si, the third semiconductor material is Si, where x is greater than 0 and less than 1, y is greater than 0 and less than 1, and x + y is less than 1) 1-x-y Ge x C y In the above combination, x is approximately 0.06 and y is 0.015 or more. Although the preferred conditions for the combination are not satisfied, the combination (4) (where the first semiconductor material and the second semiconductor material are Si, where x is greater than 0 and less than 1) 1-x Ge x and the third semiconductor material is Ge), if the Ge composition is large, the manufacturing process becomes more difficult and the off-current also increases, so it is preferable that x is less than 0.5.

[0036] Next, a case where the first semiconductor material and the second semiconductor material are different types of semiconductor materials will be described. As described above, it is preferable that the first semiconductor material and the second semiconductor material are the same type of semiconductor material from the viewpoint of manufacturing, but in principle they may be different types of semiconductor materials. That is, as described with reference to FIGS. 3 and 4 , in order to improve the probability of band-to-band tunneling using the quantum well layer 4 as a bridge between the intermediate energy levels, it is sufficient to form an energy level of the quantum well on the valence band edge side, or to form an energy level of the quantum well on the conduction band edge side, or to form energy levels of the quantum well on both the valence band edge and the conduction band edge side, through selection of the third semiconductor material relative to the first semiconductor material and the second semiconductor material. This can be achieved by designing the band structure between the second semiconductor material and the third semiconductor material in addition to between the first semiconductor material and the third semiconductor material. For example, the combination (3) (where the first semiconductor material and the second semiconductor material are Si, where x is more than 0 and less than 1) 1-x Ge x and the third semiconductor material is Si, where y is greater than 0 but less than 1 and greater than x. 1-y Ge y In the combination (combination of (a) and (b)), the first semiconductor material and the second semiconductor material may be heterogeneous materials having different x values, and the third semiconductor material may be a heterogeneous material having a y value larger than the x values ​​of these two materials.

[0037] In the present invention, it is essential that the quantum well layer 4 is not in contact with the first conductivity type semiconductor layer 1, which is a high concentration impurity layer. That is, as can be seen from FIG. 4, when the quantum well layer 4 and the first conductivity type semiconductor layer 1 are configured to be in contact with each other, interband tunneling via the intermediate energy level of the quantum well does not occur, and interband tunneling occurs due to a direct tunneling phenomenon with a low probability, and therefore the effect of increasing the tunnel current cannot be expected. In the present invention, the first base material layer 3a serves to keep the quantum well layer 4 and the first conductivity type semiconductor layer 1 out of contact with each other. The first base material layer 3a was described above as being a layer having a thickness of 20 nm or less in the first direction in relation to the distance that carriers can travel through the tunnel. However, in relation to the tunnel window, it is preferable that the first base material layer 3a be a layer having a thickness of 8 nm or less in the first direction. That is, as can be seen from FIG. 4 , if the distance between the quantum well layer 4 and the first conductivity type semiconductor layer 1, which is controlled by the thickness of the first base material layer 3 a, is too long, the quantum well formed by the quantum well layer 4 is located on the second conductivity type semiconductor layer 2 side and is too far away from the first conductivity type semiconductor layer 1. As a result, the energy region of the quantum well that overlaps with the tunnel window is reduced, and the probability of band-to-band tunneling via the intermediate energy level is likely to decrease.

[0038] [Variations] Next, a modified example of the tunnel current driver 10 will be described with reference to FIG. As shown in FIG. 5, the tunnel current driving device 10′ according to the modified example differs from the tunnel current driving device 10 in that the intermediate layer is composed of the first base material layer 3a / quantum well layer 4 / first base material layer 3a′ / quantum well layer 4′ / second base material layer 3b in that the intermediate layer is composed of the first base material layer 3a / quantum well layer 4 / first base material layer 3a′ / quantum well layer 4′ / second base material layer 3b. Here, the first base material layer 3a' and the quantum well layer 4' are configured in the same manner as described for the first base material layer 3a and the quantum well layer 4. The intermediate layer may have a laminated structure in which the first base material layers 3a and the quantum well layers 4 are alternately and repeatedly laminated.

[0039] The first base material layer 3a' is formed of the same material as the first base material layer 3a, and is also formed of the same material as the first base material layer 3a, if the material is selected from the first semiconductor forming materials. a and The quantum well layer 4' may be formed of a material different from that of the quantum well layer 4. In addition to being formed of the same material as that of the quantum well layer 4, the quantum well layer 4' may be formed of a material different from that of the quantum well layer 4, as long as it is selected from the third semiconductor forming materials. When the quantum well layer 4' is formed of the third semiconductor material different from that of the quantum well layer 4, the effect of increasing the tunneling current due to band-to-band tunneling via the intermediate energy level is obtained in the band structure examples shown in Figures 6(a) and 6(b). When the quantum well layer 4' is formed of the second semiconductor material of the same type as that of the quantum well layer 4, the effect of increasing the tunneling current due to band-to-band tunneling via the intermediate energy level is obtained in the band structure shown in Figure 6(b). Note that Figure 6(a) is a diagram (1) showing an example of the band structure of a tunneling current driver device according to a modified example in the on state, and Figure 6(b) is a diagram (2) showing an example of the band structure of a tunneling current driver device according to a modified example in the on state.

[0040] [Tunnel diode] The tunnel current driving element of the present invention can be applied to a known tunnel diode (e.g., a PIN tunnel diode) in which a low-impurity concentration layer formed of either an intrinsic semiconductor or an impurity-containing semiconductor having an impurity concentration lower than the impurity concentrations of the n-type semiconductor layer and the p-type semiconductor layer is disposed between an n-type semiconductor layer and a p-type semiconductor layer, thereby obtaining an effect of increasing the tunnel current. Referring again to FIG. 2(a), the tunnel current driving element will be described when applied to the tunnel diode.

[0041] When applied to the tunnel diode, the tunnel current driving element 10 is configured such that the n-type semiconductor layer is a first conductivity type semiconductor layer 1 having an n-type as the first conductivity type, and the p-type semiconductor layer is a second conductivity type semiconductor layer having a p-type as the second conductivity type. layer a first element structure in which the low impurity concentration layer is formed by the intermediate layer (first base material layer 3a, quantum well layer 4, and second base material layer 3b); and a second element structure in which the p-type semiconductor layer is formed by a first conductivity type semiconductor layer 1 having a first conductivity type of p-type, and the n-type semiconductor layer is formed by a second conductivity type semiconductor layer having a second conductivity type of n-type. layer 2, and the low impurity concentration layer is formed by the intermediate layer (first base material layer 3a, quantum well layer 4, and second base material layer 3b). These configurations are extremely practical because they can provide an increased tunnel current effect by simply changing the configuration of the low impurity concentration layer in a known tunnel diode (e.g., a PIN tunnel diode) and disposing the quantum well layer 4 in a layer having the low impurity concentration layer as a base material.

[0042] FIG. 7(a) shows an example of the configuration of a tunnel current driver which has a configuration equivalent to that of the tunnel current driver 10 and is more practical when applied to the tunnel diode. 7(a), the tunnel current drive element 20 has a layered structure in which a second conductivity type semiconductor layer 22, a second base material layer 23b, a quantum well layer 24, a first base material layer 23a, and a first conductivity type semiconductor layer 21 are layered in this order on a support substrate S. The element is also covered with an interlayer insulating film I for wiring, and is provided with a metal electrode 25 connected to the first conductivity type semiconductor layer 21 for wiring connection and a metal electrode 26 connected to the second conductivity type semiconductor layer 22, enabling the tunnel diode to operate as a two-terminal device. This tunnel current drive element 20 is configured as a vertical element in which the current direction is perpendicular to the surface of the support substrate S. If each of the second conductivity type semiconductor layer 22, the second base material layer 23b, the quantum well layer 24, the first base material layer 23a and the first conductivity type semiconductor layer 21 is formed by a known chemical vapor deposition epitaxial growth method using the support substrate S having a crystal orientation as a base, it can be formed as a high-quality layer with few defects and a uniform crystal orientation, and can be practically manufactured using existing equipment. The tunnel current driving element 20 may be manufactured in the reverse order of stacking from the illustrated example, so as to have a stacked structure in which the first conductivity type semiconductor layer 21, the first base material layer 23a, the quantum well layer 24, the second base material layer 23b, and the second conductivity type semiconductor layer 22 are stacked in this order on the support substrate S.

[0043] A specific example of manufacturing the tunnel current driver 20 will be described with reference to Figures 7(b) to 7(e). Figures 7(b) to 7(e) are schematic cross-sectional views (1) to (4) for explaining an outline of the manufacturing process of the tunnel current driver 20. First, the second conductive type semiconductor layer 22, the second base material layer 23b, the quantum well layer 24, the first base material layer 23a, and the first conductive type semiconductor layer 21 are successively grown on the support substrate S by a known chemical vapor deposition epitaxial growth method (see FIG. 7(b)). Next, by using a known lithography processing method or the like, parts of the support substrate S, the second conductivity type semiconductor layer 22, the second base material layer 23b, the quantum well layer 24, the first base material layer 23a and the first conductivity type semiconductor layer 21 are etched away to perform element isolation (see Figure 7(c)). Next, using a known lithography process or the like, parts of the second base material layer 23b, the quantum well layer 24, the first base material layer 23a and the first conductivity type semiconductor layer 21 are etched away to form a mesa structure (see FIG. 7(d)). Next, a known insulating material is deposited on the first conductive type semiconductor layer 21 by a known chemical vapor deposition method or the like to form the second conductive type semiconductor layer 22, the second base material layer 23b, the quantum well layer 24, the first base material layer 23a, and the first conductive type semiconductor layer 23b. 21 An interlayer insulating film I is formed to cover the above (see FIG. 7(e)). Finally, contact holes are formed in the interlayer insulating layer I by a known lithography processing method or the like, and then metal electrodes 25, 26 are formed at the positions of the contact holes by a known physical vapor deposition method or the like, thereby manufacturing the tunnel current driving element 20 (see Figure 7(a)).

[0044] [Tunnel field-effect transistor] The tunnel current driving element of the present invention can be applied to a known tunnel field effect transistor in which a channel region is formed between a source region and a drain region and a gate electrode is formed on the channel region via a gate insulating film, thereby achieving an increased tunnel current. With reference to FIG. 8, the tunnel current driving element will be described when applied to the tunnel field effect transistor.

[0045] 8, in the tunnel current driver 30, the source region is made up of a first conductivity type semiconductor layer 31, the drain region is made up of a second conductivity type semiconductor layer 32, and the channel region is made up of the intermediate layer. The first conductivity type semiconductor layer 31 and the second conductivity type semiconductor layer 32 are configured similarly to the first conductivity type semiconductor layer 1 and the second conductivity type semiconductor layer 2 described for the tunnel current driver, and the intermediate layer is made up of a first base material layer 33a, a quantum well layer 34, and a second base material layer 33b similar to the first base material layer 3a, the quantum well layer 4, and the second base material layer 3b described for the tunnel current driver 10. The source electrode 35 connected to the first conductivity type semiconductor layer 31 (the source region), the drain electrode 36 connected to the second conductivity type semiconductor layer 32 (the drain region), the gate insulating film 37, and the gate electrode 38 are configured similarly to the corresponding components in known tunnel field effect transistors. This configuration is extremely practical because it is possible to obtain an increased tunnel current effect by simply changing the configuration of the channel region of a known tunnel field effect transistor, for example, by disposing the quantum well layer 34 in a layer whose base material is the constituent material of the channel region.

[0046] Furthermore, the tunnel current driving element 30 allows for complementary operation similar to that of a known tunnel field effect transistor. That is, if the conductivity type of the first conductivity type semiconductor layer 31 (the source region) is set to p-type and the conductivity type of the second conductivity type semiconductor layer 32 (the drain region) is set to n-type, it operates as an N-type tunnel field effect transistor. More specifically, by selecting the third semiconductor material for the intermediate layer (the channel region) relative to the first and second semiconductor materials, a concave energy level in the forbidden band as the quantum well is formed on the valence band edge side (see FIG. 9(a)), a concave energy level in the forbidden band as the quantum well is formed on the conduction band edge side (see FIG. 9(b)), or both (see the second from the left in FIG. 3 and FIG. 6(a)), thereby operating as an N-type tunnel field-effect transistor with an increased tunnel current. Note that FIG. 9(a) is a band structure diagram (1) for explaining the operation of an N-type tunnel field-effect transistor, and FIG. 9(b) is a band structure diagram (2) for explaining the operation of an N-type tunnel field-effect transistor. On the other hand, if the polarity is reversed and the conductivity type of the first conductivity type semiconductor layer 31 (the source region) is set to n-type and the conductivity type of the second conductivity type semiconductor layer 32 (the drain region) is set to p-type, it operates as a P-type tunnel field effect transistor. More specifically, by selecting the third semiconductor material for the intermediate layer (the channel region) relative to the first and second semiconductor materials, a concave energy level in the forbidden band as the quantum well is formed on the valence band edge side (see FIG. 10(a)), a concave energy level in the forbidden band as the quantum well is formed on the conduction band edge side (see FIG. 10(b)), or both (see FIG. 6(a)), the transistor operates as a P-type tunnel field effect transistor with an increased tunnel current. Note that FIG. 10(a) is a band structure diagram (1) for explaining the operation of a P-type tunnel field effect transistor, and FIG. 10(b) is a band structure diagram (2) for explaining the operation of a P-type tunnel field effect transistor.

[0047] FIG. 11(a) shows an example of the configuration of a tunnel current driver which has a configuration equivalent to that of the tunnel current driver 30 and is more practical when applied to the tunnel field effect transistor. 11(a), the tunnel current driving element 40 has a laminated structure in which a second conductivity type semiconductor layer 42, a second base material layer 43b, a quantum well layer 44, a first base material layer 43a, and a first conductivity type semiconductor layer 41 are laminated in this order on a support substrate S. A gate insulating film 47 and a gate electrode 48a (and a metal electrode 48b for terminal connection) are formed, and are covered with an interlayer insulating film I for wiring. A source electrode 45 connected to the first conductivity type semiconductor layer 41 for wiring connection and a drain electrode 46 connected to the second conductivity type semiconductor layer 42 are formed, and the tunnel electric field transistor can operate as a three-terminal device. This tunnel current drive element 40 is configured as a vertical element in which the current direction is perpendicular to the surface of the support substrate S. If each of the second conductivity type semiconductor layer 42, the second base material layer 43b, the quantum well layer 44, the first base material layer 43a, and the first conductivity type semiconductor layer 41 is formed by a known chemical vapor deposition epitaxial growth method using the support substrate S having a crystal orientation as a base, it can be formed as a high-quality layer with few defects and a uniform crystal orientation, and can be practically manufactured using existing equipment. The tunnel current driving element 40 may be manufactured in the reverse order of the layers in the illustrated example, so as to have a layered structure in which the first conductivity type semiconductor layer 41, the first base material layer 43a, the quantum well layer 44, the second base material layer 43b, and the second conductivity type semiconductor layer 42 are layered in this order on the support substrate S.

[0048] A specific example of manufacturing the tunnel current driver 40 will be described with reference to Fig. 11(b) to Fig. 11(f). Fig. 11(b) to Fig. 11(f) are schematic cross-sectional views (1) to (5) for explaining an outline of the manufacturing process of the tunnel current driver 40. First, the second conductive type semiconductor layer 42, the second base material layer 43b, the quantum well layer 44, the first base material layer 43a, and the first conductive type semiconductor layer 41 are successively grown on the support substrate S by a known chemical vapor deposition epitaxial growth method (see FIG. 11(b)). Next, by using a known lithography processing method or the like, portions of the support substrate S, the second conductivity type semiconductor layer 42, the second base material layer 43b, the quantum well layer 44, the first base material layer 43a, and the first conductivity type semiconductor layer 41 are etched away to perform element isolation (see Figure 11(c)). Next, similarly by known lithography processing or the like, the second base material layer 43b, the quantum well layer 44, the first base material layer 43a, and a portion of the first conductivity type semiconductor layer 41 are etched away to form a mesa structure (see FIG. 11(d)). Although not shown, the etching depth during the formation of the mesa structure may be made deeper so that a portion of the side surface of the second conductivity type semiconductor layer 42 is exposed. Next, a known insulating material is deposited on the first conductive type semiconductor layer 41 by a known chemical vapor deposition method or the like to form a second conductive type semiconductor layer 42, a second base material layer 43b, a quantum well layer 44, a first base material layer 43a, and a first conductive type semiconductor layer 43b. 41 After forming a gate insulating film 47 to cover the intermediate layer (second base material layer 43b, quantum well layer 44, and first base material layer 43a), a gate electrode 48a is formed by a known deposition method or the like to cover the side positions of the intermediate layer (second base material layer 43b, quantum well layer 44, and first base material layer 43a) formed as the channel region, thereby forming a gate stack (see Figure 11(e)). Next, a known insulating material is deposited from above by a known chemical vapor deposition method or the like to form an interlayer insulating film I so as to cover the gate insulating film 47 and the gate electrode 48a (see FIG. 11(f)). Finally, contact holes are formed in the interlayer insulating layer I and the gate insulating film 47 by a known lithography processing method or the like, and then metal electrodes 45, 46, 48b are formed at the positions of the contact holes by a known physical vapor deposition method or the like, thereby manufacturing the tunnel current driving element 40 (see FIG. 11(a)). In the illustrated example, the gate stack is made up of the gate insulating film 47 and the gate electrode 48a, but the gate stack may be formed in a double gate structure in which a gate electrode is arranged on the surface of the intermediate layer opposite to the surface on which the gate electrode 48a is arranged, in accordance with the structure of a known tunnel field effect transistor, or the gate stack may be formed in an all-around structure in which the gate electrode is arranged on the entire periphery of the intermediate layer.

[0049] [Variations] Next, a modified example of the tunnel current driver 30 (see FIG. 8) will be described with reference to FIG. As shown in FIG. 12, the tunnel current driving element 30′ according to the modified example is configured such that, in the tunnel current driving element 30, the quantum well layer 34 whose length in a second direction (downward in FIG. 8) perpendicular to the first direction (rightward in FIG. 8) as viewed from the position in contact with the gate insulating film 37 is the same as the length of the first base material layer 33a (and the second base material layer 33b) is replaced with a quantum well layer 34′ whose length in the second direction (downward in FIG. 12) (d in FIG. 12) is shorter than the length of the base material layer 33. In this configuration, when a line (current path) in the first direction passing through the position of the quantum well layer 34' and heading from the first conductivity type semiconductor layer 31 to the second conductivity type semiconductor layer 32 is viewed, the line passes through the base material layer 33 twice, and the region of the base material layer 33 that the line passes through the first time can be regarded as the first base material layer 33a, and the region of the base material layer 33 that the line passes through the second time can be regarded as the second base material layer 33b. Thus, in the present invention, the stacking relationship of the first base material layer, the quantum well layer, and the second base material layer in the first direction means the stacking relationship on a line (current path) in the first direction that passes through the position of the quantum well layer and goes from the first conductivity type semiconductor layer to the second conductivity type semiconductor layer, and it is not necessary for the quantum well layer to be stacked on the first base material layer (and the second base material layer) with the same length in the second direction.

[0050] The region where band-to-band tunneling occurs between the first conductivity type semiconductor layer 31 and the intermediate layer (the channel region) due to the gate voltage applied to the gate electrode 38 extends approximately 5 nm in the second direction (downward in FIG. 12 ) from the position of one surface of the intermediate layer (the channel region) in contact with the gate insulating film 37 toward the other surface of the intermediate layer on the side where the gate insulating film 37 is not disposed, and the effect of increasing the tunnel current can be sufficiently exhibited if the length (d in FIG. 12 ) of the quantum well layer 34′ in the second direction (downward in FIG. 12 ) is at least 5 nm. Note that the upper limit of the length d is the same as the length of the base material layer 33 in the second direction, and the length of the base material layer 33 in the second direction is not particularly limited, as it conforms to the length of the channel region in the second direction in known tunnel field effect transistors. This differs from the tunnel current driving element 10 (see FIG. 2(a)) when used as the tunnel diode, in which the band-to-band tunneling phenomenon occurs at all junction surfaces of the quantum well layer 4 that contact the first base material layer 3a. In the tunnel current driving element 10 when used as the tunnel diode, as shown in FIG. 2(a), it is preferable that the length of the quantum well layer 4 in the second direction (downward in FIG. 2(b)) perpendicular to the first direction (rightward in FIG. 2(a)) is the same as the length of the first base material layer 3a (and the second base material layer 3b). [Example]

[0051] (simulation) In order to confirm the effectiveness of the present invention, a simulation test was carried out on the tunnel diode to examine the increase in tunnel current. In this simulation test, the energy band structure near the tunnel interface was calculated by first-principles calculation, and the tunnel current was calculated based on the energy band structure. The calculation of the energy band structure was performed using software (Vienna Ab initio Simulation Package (VASP)) developed mainly by the University of Vienna, and the calculation of the tunnel current was performed using software independently developed by the applicant (Chiba University, a national university corporation).

[0052] The test model is a pin-type tunnel diode shown in FIG. 13, and the first conductive type semiconductor layer is an N + the second conductivity type semiconductor layer is a P + The intermediate layer is made of an intrinsic SiGe (Ge composition 60 atomic %; Si 0.40 Ge 0.60 ) semiconductor, and is composed of a SiGe quantum well layer. Note that Figure 13 shows a test model for the simulation test. In the model under test, N + Si semiconductor layer and P + The distance between the SiGe quantum well layer and the SiGe-type semiconductor layer was 10 nm, and the thickness of the SiGe quantum well layer in the first direction (the right direction in FIG. 13) was 2.3 nm. As a comparative model, a state without a SiGe quantum well layer was set, and a N + Si semiconductor layer and P + An intrinsic Si semiconductor layer having a thickness of 10 nm in the first direction was set between the intrinsic Si semiconductor layer and the intrinsic Si semiconductor layer. Also, N + The distance (x0) between the central position of the SiGe quantum well layer in the first direction and the type Si semiconductor layer was made variable by changing the formation position of the SiGe quantum well layer in the Si intrinsic semiconductor layer, which is the base material (see FIG. 14), and was set to three values: 2.4 nm, 5.6 nm, and 8.8 nm. + 10 is an explanatory diagram illustrating how the distance (x0) between the central position in the first direction of the SiGe quantum well layer and the type Si semiconductor layer is set. FIG. Furthermore, taking into consideration that the SiGe quantum well layer is an epitaxially grown layer and that the crystal lattice size of SiGe is larger than that of Si, biaxial compressive strain is applied to the SiGe crystal lattice in the SiGe quantum well layer in the plane (up and down in Figure 13 and toward the front of the page), so that the SiGe crystal lattice expands without strain in the direction perpendicular to the directions of the two axes, while the lattice size in the directions of the two axes matches the lattice size of the parent Si material.

[0053] FIG. 15 shows the energy band structures of Si and SiGe (Ge composition 60%) obtained by the simulation test. As shown in FIG. 15, the upper end of the valence band of SiGe is located higher than the upper end of the valence band of Si, and it is confirmed that a quantum well can be formed using a Si / SiGe / Si stacked structure.

[0054] FIG. 16 shows the tunnel current characteristics of the pin-type tunnel diode in the simulation test. As shown in FIG. 16, it can be seen that the tunnel current tends to be significantly higher in all three models with x0 of 2.4 nm, 5.6 nm, and 8.8 nm than in the comparison model (Si bulk) without the SiGe quantum well layer. In particular, it is confirmed that the models with x0 of 2.4 nm and 5.6 nm provide larger tunnel currents than the model with x0 of 8.8 nm. This is because in the model with x0 of 8.8 nm, the quantum well formed by the SiGe quantum well layer is + Located on the Si semiconductor layer side, N + This is because the electrons are too far from the type Si semiconductor layer, making it difficult to form an energy level for tunneling in the tunnel window shown by the dark colored bands in FIGS. 17(a) and (b). From this, it can be concluded that models with x0 of 2.4 nm and 5.6 nm are more suitable, and that in an actual element, the thickness of the first base material layer (the intrinsic Si semiconductor layer on the left in Figure 13) that controls this distance x0 is more suitable to be 8 nm or less. FIG. 17(a) is a diagram showing the positional relationship between the tunnel window and the quantum well formed by the SiGe quantum well layer in a model where x0 is 5.6 nm, and FIG. 17(b) is a diagram showing the positional relationship between the tunnel window and the quantum well formed by the SiGe quantum well layer in a model where x0 is 8.8 nm.

[0055] (Example) In order to confirm the validity of the simulation results, the tunnel current driving device was manufactured and its performance was evaluated. The tunnel current driving device according to the example has the device structure of the tunnel diode and was manufactured in the configuration shown in Fig. 18. Specifically, it was manufactured as follows. First, an n-type (100) crystal-oriented silicon support substrate (a phosphorus-doped silicon wafer with a diameter of 200 mm manufactured by the Czochralski method (CZ method), manufactured by GlobalWafers, "n-Si" in FIG. 18) was prepared. Next, as the second conductive type semiconductor layer, boron (B) is deposited on the silicon support substrate at 7×10 19 cm -3 Doped with a concentration of p + type Si semiconductor layer (see "p" in Figure 18) + -Si") was formed to a thickness of 200 nm. Next, as the second base material layer, + An intrinsic Si semiconductor layer ("i-Si" at the bottom in FIG. 18) was formed to a thickness of 200 nm on the type Si layer. Next, as the quantum well layer, intrinsic SiGe (Ge composition 60 atomic %; Si 0.40 Ge 0.60 An intrinsic SiGe semiconductor layer ("i-SiGe" in FIG. 18) was formed to a thickness of 6 nm. The composition ratio of Si and Ge in the intrinsic SiGe semiconductor layer was confirmed using an analyzer (UVISEL, M200-FUV-FGMS-HNSTSS, manufactured by Horiba Jobin Yvon). Next, an intrinsic Si semiconductor layer ("i-Si" on the upper side in FIG. 18) was formed again on the intrinsic SiGe semiconductor layer to a thickness of 6 nm as the first base material layer. Next, as the first conductive type semiconductor layer, phosphorus (P) was implanted at 4×10 19 cm -3 Doped n + Type Si semiconductor layer (in Figure 18, "n + -Si") was formed to a thickness of 100 nm. These layers on the silicon support substrate were formed by successive growth by chemical vapor deposition epitaxial growth using a chemical vapor deposition apparatus (Epsilon 2000, ASM, Netherlands). In this manner, the tunnel current driving device according to the example was manufactured.

[0056] (Comparative Example) The intrinsic SiGe semiconductor layer is not formed as the quantum well layer, and the intrinsic Si semiconductor layer is formed as the first base material layer and the second base material layer. + A tunneling current driving device according to the comparative example was manufactured in the same manner as the tunneling current driving device according to the example, except that the layers were formed together on the mold Si layer to a thickness of 206 nm.

[0057] The carrier (electron, hole) density distribution in the tunneling current-driven device according to the comparative example is shown in Figure 19. This carrier density distribution was obtained by evaluation using a microscope (Bruker AXS NanoScope V / Dimension Icon) with scanning capacitance microscopy (SCM) and scanning microwave microscopy (SMM). This evaluation was carried out for the purpose of evaluating the carrier concentration, and in order to improve the analytical accuracy, the evaluation was carried out on a tunnel current driving element according to a comparative example in which the intrinsic SiGe semiconductor layer was not formed as the quantum well layer. In Figure 19, "P type, 1 x 10 17 cm -3 The regions marked with "" correspond to the intrinsic Si semiconductor layer as the first base material layer and the second base material layer. As shown in FIG. 19, unexpected carrier generation occurs in the intrinsic Si semiconductor layer, but the concentration of the carriers is + Si semiconductor layer (7×1019 cm -3 ) and the n + Si semiconductor layer (4×10 19 cm -3 ) and it is confirmed that it functions as a PIN-type tunnel diode.

[0058] FIG. 20 shows a TEM image of the layered structure of the intermediate layer (i-Si / i-SiGe / i-Si) of the tunnel current drive element according to the embodiment, taken using a cross-sectional transmission electron microscope (TEM, Hitachi High-Tech Corporation, H-9500). As shown in FIG. 20, it is confirmed that the intrinsic SiGe semiconductor layer serving as the quantum well layer is formed with high quality without defects and in accordance with the crystal orientation of the intrinsic Si semiconductor layer ("i-Si" at the bottom in FIG. 18).

[0059] FIG. 21 shows the results of measuring the IV characteristics of the tunnel current driving devices according to the example and the comparative example. As shown in FIG. 21, the tunnel current driving device according to the example can be confirmed to have a tunnel current increase of four orders of magnitude or more compared to the tunnel current driving device according to the comparative example, and it can be concluded that the tunnel current increases due to the formation of the quantum well layer. [Explanation of symbols]

[0060] 1, 21, 31, 41 First conductive type semiconductor layer 2, 22, 32, 42 Second conductive type semiconductor layer 3a,23a,33a,43a 1st base material layer 3b,23b,33b,43b 2nd base material layer 4,4',24,34,34',44 quantum well layers 10,10',20,30,30',40 Tunnel current drive element 25,26 metal electrode 33 Base material layer 35,45 Source electrode 36,46 Drain electrode 37,47 Gate insulating film 38,48a Gate electrode 48b Metal electrode 100 Tunnel Diode 101 N + Semiconductor layer 102 pages + Semiconductor layer 103 Intrinsic semiconductor layer I Interlayer insulation layer S Support board

Claims

1. The semiconductor device is formed of an indirect transition semiconductor material, and has a first conductivity type, which is either p-type or n-type, and has an impurity concentration of 3×10 １９ cm －３ The first conductivity type semiconductor layer described above; a second conductivity type semiconductor layer formed of the indirect transition semiconductor material and having a second conductivity type different from the first conductivity type; an intermediate layer sandwiched between the first conductivity type semiconductor layer and the second conductivity type semiconductor layer, and formed of either an intrinsic semiconductor or an impurity-containing semiconductor having an impurity concentration lower than the impurity concentrations of the first conductivity type semiconductor layer and the second conductivity type semiconductor layer, the intermediate layer has a stacking direction that is a first direction from the first conductivity type semiconductor layer toward the second conductivity type semiconductor layer, and is a layer having a stacking structure in which at least one first base material layer and one quantum well layer are stacked alternately in this order on the first conductivity type semiconductor layer that serves as a base layer, and a second base material layer is stacked on the quantum well layer closest to the second conductivity type semiconductor layer, the first base material layer is formed of a first semiconductor material selected from the indirect transition semiconductor materials and has a thickness of 0.5 nm to 20 nm in the first direction; the second base material layer is formed of a second semiconductor material selected from the indirect transition semiconductor materials and has a thickness in the first direction of 10 nm to 500 nm; a tunnel current driving element, characterized in that the quantum well layer is formed of a third semiconductor material selected from the indirect transition semiconductor materials different from the first semiconductor material and the second semiconductor material, and has a thickness of 0.5 nm to 10 nm in the first direction, and the third semiconductor material is selected from the indirect transition semiconductor materials having at least one of a first band structure in which a valence band edge is located at a higher energy position than the valence band edges of the first semiconductor material and the second semiconductor material, and a second band structure in which a conduction band edge is located at a lower energy position than the conduction band edges of the first semiconductor material and the second semiconductor material.

2. 2. The tunnel current driving element according to claim 1, wherein the band structure is at least one of a first band structure in which the valence band edge is located at an energy position that is more than 0.1 eV higher than the valence band edge that has the highest energy position of either the first semiconductor material or the second semiconductor material, and a second band structure in which the conduction band edge is located at an energy position that is more than 0.1 eV lower than the conduction band edge that has the lowest energy position of either the first semiconductor material or the second semiconductor material.

3. 3. The tunnel current driving element according to claim 1, wherein the first semiconductor material, the second semiconductor material, and the third semiconductor material are selected from any combination of the following (1) to (6): (1) The first semiconductor material and the second semiconductor material are Si, and the third semiconductor material is Si, where x is greater than 0 and less than 1. １－ｘ Ge ｘ The combination is: (2) A combination in which the first semiconductor material and the second semiconductor material are Si, and the third semiconductor material is Ge. (3) The first semiconductor material and the second semiconductor material are Si, where x is greater than 0 and less than 1. １－ｘ Ge ｘ and the third semiconductor material is Si, where y is greater than 0 but less than 1 and greater than x. １－ｙ Ge ｙ The combination is: (4) The first semiconductor material and the second semiconductor material are Si, where x is greater than 0 and less than 1. １－ｘ Ge ｘ and the third semiconductor material is Ge. (5) The first semiconductor material and the second semiconductor material are Si, and the third semiconductor material is Si, where x is greater than 0 and less than 1. １－ｘ C ｘ The combination is: (6) The first semiconductor material and the second semiconductor material are Si, and the third semiconductor material is Si, where x is greater than 0 and less than 1, y is greater than 0 and less than 1, and x + y is less than 1. １－ｘ－ｙ Ge ｘ C ｙ The combination is:

4. 4. The tunnel current driving element according to claim 3, wherein the first semiconductor material, the second semiconductor material, and the third semiconductor material are the combination of (1), and x is 0.12 or more.

5. 5. The tunnel current driver element according to claim 1, wherein the first conductivity type semiconductor layer, the second conductivity type semiconductor layer and the intermediate layer are formed as single crystal layers of indirect transition semiconductor materials.

6. 6. The tunneling current drive element according to claim 1, wherein the thickness of the first base material layer in the first direction is 8 nm or less.

7. a tunnel diode element structure in which a low-impurity-concentration layer formed of either an intrinsic semiconductor or an impurity-containing semiconductor having an impurity concentration lower than the impurity concentrations of the n-type semiconductor layer and the p-type semiconductor layer is disposed between an n-type semiconductor layer and a p-type semiconductor layer, 7. The tunnel current driving element according to claim 1, wherein the element structure is either a first element structure in which the n-type semiconductor layer is made of a first conductivity type semiconductor layer having a first conductivity type of n-type, the p-type semiconductor layer is made of a second conductivity type semiconductor layer having a second conductivity type of p-type, and the low impurity concentration layer is made of an intermediate layer, or a second element structure in which the p-type semiconductor layer is made of the first conductivity type semiconductor layer having the first conductivity type of p-type, the n-type semiconductor layer is made of the second conductivity type semiconductor layer having the second conductivity type of n-type, and the low impurity concentration layer is made of the intermediate layer.

8. a tunnel field effect transistor element structure in which a channel region is formed between a source region and a drain region, and a gate electrode is formed on the channel region via a gate insulating film; 7. The tunnel current driving element according to claim 1, wherein the source region is made of a first conductivity type semiconductor layer, the drain region is made of a second conductivity type semiconductor layer, and the channel region is made of an intermediate layer.

9. 9. The tunnel current driver element according to claim 8, wherein the length of the quantum well layer in a second direction perpendicular to the first direction as viewed from a position where the quantum well layer contacts the gate insulating film is at least 5 nm.

Images