High electron mobility transistor and method for manufacturing same

Abstract

To provide a high electron mobility transistor (HEMT) in which the component manufacturing efficiency is improved and the process cost is reduced, and a manufacturing method for the same.SOLUTION: A manufacturing method for a HEMT includes the steps of: providing a substrate 11; forming a semiconductor layer 13 on the substrate, forming a source electrode 14 and a drain electrode 15 on the semiconductor layer, and forming a passivation layer 16 on the source electrode and the drain electrode; forming a through-hole 151 between the source electrode and the drain electrode by etching the passivation layer in order to expose a region R1 of the semiconductor layer through the through-hole; forming a photoresist layer on the passivation layer, covering a first small region R11 of the region with the photoresist layer and not covering a second small region R12 of the region with the photoresist layer; forming a gate electrode 191 by forming a metal layer 19 on the second small region; and removing the passivation layer.SELECTED DRAWING: Figure 1F

Description

[Technical Field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims the benefit of Taiwan Patent Application No. 112132022, filed August 25, 2023, the subject matter of which is incorporated herein by reference.

[0002] The present invention relates to a high electron mobility transistor (HEMT) and a method for fabricating the same, and more particularly to an I-gate electrode HEMT and a method for fabricating the same. [Background technology]

[0003] High electron mobility transistors (HEMTs) have the advantages of high switching speed, high electron mobility, high breakdown power, and wide energy gap, and are applicable to high voltage or high frequency electronic components. At present, it is known that electron beam lithography can be used to prepare HEMTs with gate electrodes having short gate lengths.

[0004] Electron beam lithography process is widely used to form various patterning structures, and has advantages such as high resolution, high process reliability, high precision positioning or alignment, and high degree of freedom pattern reproduction, etc. However, electron beam lithography process still has disadvantages, the main one of which is long working time and high cost.

[0005] Therefore, it is desirable to develop a new process that improves upon the above-mentioned shortcomings of the electron beam lithography process. Summary of the Invention

[0006] SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a HEMT, which can effectively improve component manufacturing efficiency and reduce process costs.

[0007] A method for manufacturing a HEMT provided by the present invention includes the following steps: providing a substrate, on which a semiconductor layer is formed, and forming a source electrode and a drain electrode on the semiconductor layer; forming a passivation layer on the source electrode and the drain electrode; etching the passivation layer to form a through-hole between the source electrode and the drain electrode, whereby a region of the semiconductor layer is exposed through the through-hole; forming a photoresist layer on the passivation layer, whereby a first small region of the region of the semiconductor layer is covered by the photoresist layer and a second small region of the region of the semiconductor layer is not covered by the photoresist layer; forming a metal layer on the second small region to form a gate electrode; and removing the passivation layer.

[0008] In the method of the present invention, the gate electrode area is defined by the passivation layer and the shielding photoresist layer to prepare a HEMT with a gate electrode having a short gate length. In particular, the method of the present invention can improve the shortcomings of the electron beam lithography process, improve the device manufacturing efficiency, and reduce the process cost.

[0009] In the method of the present invention, the method may further comprise the step of forming an etching photoresist masking layer on the passivation layer between the step of forming the passivation layer on the source electrode and the drain electrode and the step of etching the passivation layer, whereby a through-hole exposing the semiconductor layer can be defined, the through-hole being located between the source electrode and the drain electrode.

[0010] In the method of the present invention, the photoresist masking layer for etching and the photoresist layer used to define the deposition areas for the metal layer can be formed using the same mask.

[0011] In the method of the present invention, in the step of forming a photoresist layer on the passivation layer, a portion of the passivation layer adjacent to a second small region of the semiconductor layer (the region not covered by the photoresist layer) is not covered by the photoresist layer, and in the step of forming a metal layer on the second small region of the semiconductor layer (the region not covered by the photoresist layer), a metal layer is further formed on the portion of the passivation layer not covered by the photoresist layer.

[0012] In the method of the present invention, the location of the gate electrode can be defined by two-step exposure and development at different locations using the shielding of the passivation layer. More specifically, the exposure and development process at a first location can form a photoresist masking layer for etching to define a through-hole that exposes the semiconductor layer between the source electrode and the drain electrode. This is a first lithography process. The exposure and development process at a second location can form another photoresist layer to define the deposition location of the metal layer. This is a second lithography process. The exposure and development processes at the first and second locations can be performed using a stepper exposure machine. Furthermore, the second location is offset toward the source electrode or the drain electrode compared to the first location. Therefore, during the second lithography process, the first small area of ​​the semiconductor layer exposed through the through-hole is covered with the photoresist layer, and the second small area of ​​the semiconductor layer exposed through the through-hole is not covered with the photoresist layer. Thus, once the metal layer is formed, a metal layer can be deposited through a photoresist layer formed by a second lithography process and the shielding of the passivation layer onto a second small area of ​​the semiconductor layer not covered by the photoresist layer to form a gate electrode.

[0013] Furthermore, when the masks used in the exposure and development processes at the first position and the second position are the same mask, by shifting the second position toward the source electrode or the drain electrode compared with the first position, a portion of the passivation layer adjacent to the second small region of the semiconductor layer (the region not covered by the photoresist layer) is not covered by the photoresist layer, and a subsequently deposited metal layer can be further formed on the portion of the passivation layer not covered by the photoresist layer. When the passivation layer is subsequently removed, the metal layer deposited on the passivation layer can also be removed at the same time, leaving only the gate electrode of the metal layer located on the semiconductor layer.

[0014] In the method of the present invention, the thickness of the metal layer can be less than the thickness of the passivation layer. Therefore, when a subsequently deposited metal layer is simultaneously formed on the portion of the passivation layer not covered by the photoresist layer, the metal layer formed on the portion of the passivation layer and the metal layer that will become the gate electrode are not connected to each other. When the passivation layer is subsequently removed, the formed gate electrode is not affected.

[0015] In one embodiment of the present invention, the difference between the thickness of the metal layer and the thickness of the passivation layer may be in the range of 0.01 μm to 0.7 μm, for example, 0.01 μm to 0.6 μm, 0.01 μm to 0.5 μm, 0.01 μm to 0.3 μm, 0.01 μm to 0.2 μm, 0.01 μm to 0.1 μm, or 0.03 μm to 0.1 μm.

[0016] In the method of the present invention, the passivation layer may be etched by dry etching or wet etching to form a through-hole between the source electrode and the drain electrode. In one embodiment of the present invention, the passivation layer may be etched using inductively coupled plasma (ICP) etching, but the present invention is not limited thereto. In one embodiment of the present invention, lateral etching may occur when etching the passivation layer. In this case, the angle between the sidewall of the through-hole and the exposed surface of the semiconductor layer region may be less than 90 degrees. For example, the angle may be in the range of 40 to 85 degrees, 50 to 85 degrees, or 60 to 85 degrees, but the present invention is not limited thereto. The angle formed depends on the process or materials (e.g., the material of the passivation layer).

[0017] In the method of the present invention, after the step of removing the passivation layer, the method further comprises the step of forming a protective layer covering the gate electrode, the source electrode, the drain electrode and the semiconducting layer to prevent moisture from penetrating into the components.

[0018] The present invention further provides a HEMT prepared by the above method, the HEMT comprising: a substrate; a semiconductor layer disposed on the substrate; a source electrode disposed on the semiconductor layer; a drain electrode disposed on the semiconductor layer; and a gate electrode disposed on the semiconductor layer and between the source electrode and the drain electrode, the gate electrode having a lower surface and an upper surface opposite to the lower surface, the lower surface being a surface of the gate electrode in contact with the semiconductor layer, and the width of the upper surface being equal to or less than the width of the lower surface.

[0019] In the HEMT of the present invention, the width of the upper surface of the gate electrode is equal to or less than the width of the lower surface of the gate electrode. Preferably, the width of the upper surface of the gate electrode is substantially equal to the width of the lower surface of the gate electrode, so that the HEMT of the present invention is an I-gate electrode HEMT. In one embodiment of the present invention, the difference between the width of the upper surface of the gate electrode and the width of the lower surface of the gate electrode can be less than 10 nm.

[0020] In the HEMT of the present invention, the gate length of the gate electrode may be in the range of 0.05 μm to 0.5 μm, for example, 0.05 μm to 0.4 μm, 0.1 μm to 0.4 μm, or 0.1 μm to 0.3 μm. In one embodiment of the present invention, the gate length of the gate electrode may be approximately 0.2 μm. In the present invention, the gate length of the gate electrode refers to the width of the gate electrode measured on the underside of the gate electrode in a cross-sectional view of the HEMT.

[0021] The HEMT of the present invention may further include a protective layer covering the gate electrode, the source electrode, the drain electrode, and the semiconductor layer, and may further include a buffer layer disposed between the substrate and the semiconductor layer.

[0022] In the present invention, the substrate may be a rigid substrate or a flexible substrate, and the material of the substrate may include, but is not limited to, quartz, glass, wafer, sapphire, resin, epoxy resin, polycarbonate (PC), polyimide (PI), polypropylene (PP), polyethylene terephthalate (PET), polymethyl methacrylate (PMMA), other plastic materials, or combinations thereof.

[0023] In the present invention, the semiconductor layer may comprise a GaN layer and an AlGaN layer, but the present invention is not limited thereto and other materials that can be used in HEMTs are also included in the present invention.

[0024] In the present invention, the etching photoresist masking layer formed by the first lithography process and the photoresist layer formed by the second lithography process can be positive or negative photoresist, respectively.

[0025] In the present invention, the materials of the passivation layer, the protection layer, and the buffer layer may each include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon oxycarbide, aluminum oxide, or a combination thereof. The passivation layer, the protection layer, and the buffer layer may each have a single-layer or multi-layer structure. In one embodiment of the present invention, the passivation layer is a SiN layer. In one embodiment of the present invention, the protection layer is a SiN layer. However, the present invention is not limited thereto.

[0026] In the present invention, the materials of the gate electrode (metal layer), source electrode, and drain electrode may each include indium (In), tin (Sn), aluminum (Al), gold (Au), platinum (Pt), zinc (Zn), germanium (Ge), silver (Ag), lead (Pb), palladium (Pd), copper (Cu), gold-beryllium (AuBe), beryllium-germanium (BeGe), nickel (Ni), lead-tin (PbSn), chromium (Cr), gold-zinc (AuZn), titanium (Ti), tungsten (W), titanium-tungsten (TiW), alloys thereof, or combinations thereof. Furthermore, the gate electrode (metal layer), source electrode, and drain electrode may each have a single-layer or multi-layer structure.

[0027] In the present invention, the passivation layer, protective layer, buffer layer, photoresist layer, gate electrode (metal layer), source electrode, and drain electrode can each be prepared using any suitable method. Suitable methods include, but are not limited to, electroplating, chemical plating, chemical vapor deposition, sputtering, coating, photolithography, or a combination thereof. The coating method can be, but is not limited to, dip coating, spin coating, roller coating, blade coating, spray coating, or a combination thereof.

[0028] Other novel features of the present invention will become more apparent from the following detailed description when considered in conjunction with the accompanying drawings. [Brief explanation of the drawings]

[0029] [Figure 1A] FIG. 1A shows a schematic cross-sectional view of a method for manufacturing a HEMT according to one embodiment of the present invention. [Figure 1B] FIG. 1B shows a schematic cross-sectional view of a method for manufacturing a HEMT according to one embodiment of the present invention. [Figure 1C] FIG. 1C shows a schematic cross-sectional view of a method for manufacturing a HEMT according to one embodiment of the present invention. [Figure 1D] FIG. 1D shows a schematic cross-sectional view of a method for fabricating a HEMT according to one embodiment of the present invention. [Figure 1E] FIG. 1E shows a schematic cross-sectional view of a method for manufacturing a HEMT according to one embodiment of the present invention. [Figure 1F] FIG. 1F shows a schematic cross-sectional view of a method for manufacturing a HEMT according to one embodiment of the present invention. [Figure 1G] FIG. 1G shows a schematic cross-sectional view of a method for manufacturing a HEMT according to one embodiment of the present invention. [Figure 1H] FIG. 1H shows a schematic cross-sectional view of a method for manufacturing a HEMT according to one embodiment of the present invention. [Figure 2] FIG. 2 shows the DC characteristics of a HEMT according to one embodiment of the present invention. [Figure 3] FIG. 3 shows the high frequency characteristics of a HEMT according to one embodiment of the present invention. [Figure 4] FIG. 4 shows the results of a load-pull measurement of a HEMT according to one embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0030] The following are specific embodiments illustrating examples of the present invention. Those skilled in the art will easily understand other advantageous effects of the present invention from the contents disclosed herein. The present invention can also be implemented or applied by various other specific embodiments, and various details in this specification can be modified and changed according to various viewpoints and applications without departing from the spirit of the present invention.

[0031] It should be noted that, in this specification, when a component / part is described as having an element, it means that the component / part may have one or more of the element, and does not mean that the component / part has only one of the element, unless otherwise specified. Furthermore, ordinal numbers such as "first," "second," etc. used in the specification and claims are intended only to describe the claimed elements and do not imply or represent any sequential order of the claimed elements, nor do they imply or represent any permutation between one claimed element and another claimed element or between steps in a manufacturing method. The use of these ordinal numbers merely distinguishes one claimed element having a particular designation from other claimed elements having the same designation.

[0032] In the present specification and the appended claims, certain words are used to refer to specific elements. Those skilled in the art should understand that manufacturers of electronic devices may refer to the same component / part by different names. This specification does not distinguish between elements that have the same function but different names. In the following description and claims, words such as "comprises," "includes," "includes," and "has" are open-ended words, and therefore should be interpreted as meaning "including, but not limited to." Thus, when the terms "comprises," "includes," "includes," and / or "has" are used in the description of the present invention, they specify the presence of corresponding features, regions, steps, operations, and / or components / parts, but do not exclude the presence of one or more corresponding features, regions, steps, operations, and / or components / parts.

[0033] Terms such as "about," "equal," "comparable," "same," "substantially," or "approximately" are generally interpreted as within 10%, 5%, 3%, 2%, 1%, or 0.5% of a given value or range. Quantities given herein are approximate, i.e., "about," "approximately," "substantially," and "approximately" can be implied without specifying "about," "approximately," "substantially," and "approximately." Furthermore, when a value "ranges from a first value to a second value" or "ranges between a first value and a second value," the value can be the first value, the second value, or any other value between the first and second values.

[0034] In this specification, unless otherwise specified, the terms used herein (including technical and scientific terms) have the meanings commonly known by those skilled in the art. In addition, unless otherwise specified, in the embodiments of the present invention, these terms (for example, terms defined in commonly used dictionaries) have the same meanings as those known in the art, the background of the present invention, or the context of this specification, and should not be read in an idealized or overly formal manner.

[0035] Furthermore, relative terms such as "below" or "under" and "on," "above," or "over" may be used in embodiments to describe the relative relationship between an element and another element in a drawing. If a device in a drawing is turned upside down, it should be understood that the elements described relative to the "lower" side would become the elements described relative to the "upper" side. When a unit (e.g., a layer or region) is referred to as being "on" another unit, it may be directly on the other unit, or there may be other units between them. Furthermore, when a unit is referred to as being "directly on" another unit, there are no units between them. Furthermore, when a unit is referred to as being "on another unit," the two are in an up-down relationship in a top view, and the unit may be disposed above or below the other unit. The up-down relationship depends on the orientation of the device.

[0036] In the present invention, the distance and thickness can be measured by using an optical microscope or by cross-sectional images with an electron microscope, but the present invention is not limited thereto. Furthermore, any two values ​​or directions used for comparison may have a certain error. If the first value is equal to the second value, it suggests that there may be an error of about 10% between the first value and the second value.

[0037] 1A to 1H are schematic cross-sectional views showing a method for manufacturing a HEMT according to one embodiment of the present invention.

[0038] 1A, a substrate 11 is first provided, a semiconductor layer 13 is formed on the substrate 11, and a source electrode 14 and a drain electrode 15 are formed on the semiconductor layer 13. In this embodiment, a buffer layer 12 is further disposed between the substrate 11 and the semiconductor layer 13. The semiconductor layer 13 further includes a GaN layer 131 and an AlGaN layer 132 disposed on the GaN layer 131. The source electrode 14 and the drain electrode 15 are Ti / Al / Ni / Au metal layers, respectively, with the thicknesses of the Ti layer, Al layer, Ni layer, and Au layer being 20 nm, 120 nm, 25 nm, and 100 nm, respectively, although the present invention is not limited thereto. Thus, the ohmic contacts of the components are prepared, and the active region is defined.

[0039] Next, a passivation layer 16 is formed on the source electrode 14 and the drain electrode 15. Here, the passivation layer 16 can be formed using a plasma-enhanced chemical vapor deposition system (PECVD), and the passivation layer 16 is a SiN layer with a thickness in the range of 250 nm to 800 nm. In this embodiment, the thickness of the passivation layer 16 is approximately 250 nm.

[0040] As shown in Figure 1B, an etching photoresist masking layer 17 is formed on the passivation layer 16. A stepper exposure machine can now be used to perform a first lithography process to define the area of ​​the gate electrode.

[0041] As shown in FIG. 1C, the passivation layer 16 is etched to form a through-hole 151 between the source electrode 14 and the drain electrode 15, and a region R1 of the semiconductor layer 13 is exposed through the through-hole 151. Inductively coupled plasma (ICP) dry etching can be used to etch the passivation layer 16 to create the region R1 where the metal of the gate electrode can contact the semiconductor layer 13. Furthermore, the angle between the sidewall 151a of the through-hole 151 and the surface 13a of the region R1 of the semiconductor layer 13 is less than 90 degrees. Then, as shown in FIG. 1D, the etching photoresist masking layer 17 is removed.

[0042] As shown in FIG. 1E, the mask pattern is shifted toward the drain electrode 15, and a second photolithography process is performed to form a photoresist layer 18 on the passivation layer 16. Here, the etching photoresist masking layer 17 (shown in FIG. 1C) formed in the first lithography process and the photoresist layer 18 formed in the second lithography process can be formed using the same mask. After the second lithography process, a first small region R11 of the region R1 of the semiconductor layer 13 is covered with the photoresist layer 18, while a second small region R12 of the region R1 of the semiconductor layer 13 is not covered with the photoresist layer 18. Furthermore, a portion R2 of the passivation layer 16 adjacent to the second small region R12 is not covered with the photoresist layer 18.

[0043] 1F, a metal layer 19 is formed on the second small region R12 to form a gate electrode 191. Furthermore, another portion 192 of the metal layer 19 is further formed on the portion R2 of the passivation layer 16 that is not covered by the photoresist layer 18 (as shown in FIG. 1E). In this embodiment, the metal layer 19 is a Ni / Au metal layer, and the thicknesses of the Ni layer and the Au layer are 50 nm and 150 nm, respectively, but the present invention is not limited thereto.

[0044] In this embodiment, a stepper exposure machine is used to perform the first lithography process and the second lithography process. By shifting the mask pattern toward the drain electrode 15 (in other embodiments of the present invention, the mask pattern can be shifted toward the source electrode 14), the overlapping area between the second lithography area and the first etching area is the area of ​​the gate electrode 191.

[0045] As shown in FIGS. 1F and 1G, the passivation layer 16 is removed. In this embodiment, by using the shielding of the passivation layer 16, the remaining portion 192 of the metal layer 19 deposited on the passivation layer 16 is removed together with the passivation layer 16 using an HF solution. Furthermore, since the thickness T1 of the metal layer 19 is less than the thickness T2 of the passivation layer 16, the metal layer 19 can be divided into two non-connected pieces (e.g., the gate electrode 191 and the portion 192) during deposition, which can facilitate the removal of the excess portion 192 of the metal layer 19 on the passivation layer 16. Here, the difference between the thickness T1 of the metal layer 19 and the thickness T2 of the passivation layer 16 can be adjusted as needed and may be, for example, in the range of 0.01 μm to 0.7 μm.

[0046] 1H, a protective layer 20 is formed to cover the gate electrode 191, the source electrode 14, the drain electrode 15, and the semiconductor layer 13. In this embodiment, a SiN layer having a thickness of 100 nm may be deposited as the protective layer 20 to cover the surfaces of the gate electrode 191, the source electrode 14, the drain electrode 15, and the semiconductor layer 13, but the present invention is not limited thereto.

[0047] 1H , after the above process, a HEMT of this embodiment can be obtained, which includes a substrate 11, a semiconductor layer 13 disposed on the substrate 11, a source electrode 14 disposed on the semiconductor layer 13, a drain electrode 15 disposed on the semiconductor layer 13, and a gate electrode 191 disposed on the semiconductor layer 13 and positioned between the source electrode 14 and the drain electrode 15. Furthermore, the HEMT of this embodiment further includes a protection layer 20 covering the gate electrode 191, the source electrode 14, the drain electrode 15, and the semiconductor layer 13.

[0048] Here, the semiconductor layer 13 includes a GaN layer 131 and an AlGaN layer 132 disposed on the GaN layer 131. Furthermore, the gate electrode 191 has a lower surface 191a and an upper surface 191b opposite the lower surface 191a, and the lower surface 191a is the surface of the gate electrode 191 in contact with the semiconductor layer 13. The width W1 of the upper surface 191b is equal to or smaller than the width W2 of the lower surface 191a. For example, the difference between the width W1 of the upper surface 191b and the width W2 of the lower surface 191a is 10 nm or less. In this embodiment, the width W1 of the upper surface 191b and the width W2 of the lower surface 191a are substantially the same. Furthermore, the gate length of the gate electrode 191 may be in the range of 0.05 μm to 0.5 μm. The gate length of the gate electrode 191 is the width W2 of the lower surface 191a. In this embodiment, the gate length of the gate electrode 191 is approximately 0.2 μm.

[0049] Here, the electrical characteristics of the HEMT prepared in the above embodiment are measured.

[0050] FIG. 2 shows the DC characteristics of a HEMT according to one embodiment of the present invention. From the drawing, it can be seen that the steady-state current density (I dss ) reaches 1050mA / mm, and the maximum transconductance (g m、max ) can reach 365 mS / mm.

[0051] 3 shows the high frequency characteristics of the HEMT according to one embodiment of the present invention. T ) reaches 27GHz, and the maximum oscillation frequency (f max ) can reach 106 GHz.

[0052] 4 shows the load-pull measurement results of the HEMT according to one embodiment of the present invention. From the figure, it can be seen that the power-added efficiency (PAE) of the HEMT according to the present invention reaches 34.23%, and the maximum output power density (P out、max ) can reach 2.39 W / mm.

[0053] While conventional electron beam lithography processes can expose shorter gate lengths with greater precision, they have the disadvantages of long time consumption and high cost. As described above, the present invention uses a lower-cost stepper exposure machine to perform two-step exposure by shifting the exposure position. The overlapping area between the two exposures is used as the gate electrode area, allowing the gate length of the gate electrode to be further shortened. At the same time, the present invention increases the thickness of the passivation layer so that when the gate electrode metal is evaporated, it can be divided into two disconnected pieces above and below the passivation layer. This improves the success rate of forming the gate electrode structure, and the height tolerance of the gate electrode metal can be increased by increasing the thickness of the passivation layer. Furthermore, the gate electrode structure produced by the present invention does not require the use of silicon nitride below the gate electrode to improve mechanical stability, thereby further reducing parasitic capacitance.

[0054] Although the present invention has been described in relation to embodiments thereof, it will be understood that many other possible variations and modifications can be made without departing from the spirit and scope of the present disclosure as hereinafter claimed.

Claims

1. 1. A method for fabricating a high electron mobility transistor, comprising: providing a substrate, wherein a semiconductor layer is formed on the substrate, and a source electrode and a drain electrode are formed on the semiconductor layer; forming a passivation layer on the source electrode and the drain electrode; etching the passivation layer to form a through hole between the source electrode and the drain electrode, wherein a region of the semiconductor layer is exposed through the through hole; forming a photoresist layer on the passivation layer, wherein a first subregion of the region of the semiconductor layer is covered by the photoresist layer and a second subregion of the region of the semiconductor layer is not covered by the photoresist layer; forming a metal layer on the second subregion to form a gate electrode; removing the passivation layer; A method for providing

2. The method of claim 1 , wherein the semiconductor layer comprises a GaN layer and an AlGaN layer.

3. The method of claim 1 , wherein the passivation layer is a SiN layer.

4. The method of claim 1 , wherein the thickness of the metal layer is less than the thickness of the passivation layer.

5. 5. The method of claim 4, wherein the difference between the thickness of the metal layer and the thickness of the passivation layer is in the range of 0.01 μm to 0.7 μm.

6. 2. The method of claim 1, wherein the gate length of the gate electrode is in the range of 0.05 μm to 0.5 μm.

7. 2. The method of claim 1, wherein the gate electrode has a lower surface and an upper surface opposite the lower surface, the lower surface being a surface of the gate electrode in contact with the semiconductor layer, and the width of the upper surface being equal to or less than the width of the lower surface.

8. The method of claim 7 , wherein the difference between the width of the upper surface and the width of the lower surface is 10 nm or less.

9. The method of claim 1 , wherein an angle between a sidewall of the through hole and a surface of the region of the semiconductor layer is less than 90 degrees.

10. The method of claim 1 , further comprising, after removing the passivation layer, forming a protective layer covering the gate electrode, the source electrode, the drain electrode, and the semiconductor layer.

11. 10. The method of claim 1, further comprising the step of forming an etching photoresist masking layer on the passivation layer between the step of forming the passivation layer on the source electrode and the drain electrode and the step of etching the passivation layer.

12. 12. The method of claim 11, wherein the etching photoresist masking layer and the photoresist layer are formed using the same mask.

13. 2. The method of claim 1, wherein in the step of forming the photoresist layer on the passivation layer, a portion of the passivation layer adjacent to the second subregion is not covered by the photoresist layer.

14. 14. The method of claim 13, wherein the step of forming the metal layer on the second subregion further comprises forming the metal layer on the portion of the passivation layer not covered by the photoresist layer.

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