Wafer processing method

Abstract

To provide a wafer processing method capable of grinding a wafer without causing chipping in the wafer in which an outer peripheral excess region thinner than a device region exists inside a chamfering part of an outer peripheral region when compared with the device region.SOLUTION: A wafer processing method includes an annular removing step (101), a segmentation processing step (102), and a grinding step (103). The annular removing step annularly removes an outer peripheral part of a wafer by annularly processing the wafer along an outer peripheral edge at a position inside a prescribed distance from the outer peripheral edge of the wafer. The segmentation processing step performs processing for segmenting an outer peripheral excess region which cannot be removed by the annular removing step (101) and the device region for a division schedule line at a position closest to the outer peripheral edge among division schedule lines set in the wafer. The grinding step forms the wafer to a prescribed finishing thickness by grinding a rear surface side of the wafer after performing the annular removing step (101) and the segmentation processing step (102).SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to a wafer processing method. [Background technology]

[0002] Semiconductor wafers have their outer peripheral surfaces chamfered in an arc shape to prevent defects such as chipping that occur when they are transported between processes until they are divided into device chips. When the backside of a wafer having such a chamfered portion on its outer periphery is ground to thin it, the outer peripheral portion of the wafer becomes acute-angled (a so-called knife edge), which causes a problem of the edge being prone to chipping or cracking during grinding. If this edge chipping or cracking progresses, it may lead to damage to the device. Therefore, a technique has been proposed in which a portion of the outer peripheral portion is removed before wafer grinding (see, for example, Patent Documents 1 and 2). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2000-173961 [Patent Document 2] Japanese Patent Application Laid-Open No. 2006-108532 Summary of the Invention [Problem to be solved by the invention]

[0004] Incidentally, some semiconductor wafers have wafer IDs formed near the edge to identify wafers for traceability purposes. Since devices cannot be formed in the area where the wafer ID is formed, the thickness is thinner than the device area.

[0005] If the techniques described in Patent Documents 1 and 2 are applied to such wafers and the backside is ground after removing the chamfered portion of the outer periphery, the formation of a knife edge can be prevented, but the thin outer periphery excess region where the wafer ID is formed (where no device is formed) separates from the holding surface of the chuck table during grinding. Therefore, as grinding progresses, the thin outer periphery excess region separates from the holding surface of the chuck table, and is unable to withstand the suction pressure on the chuck table, resulting in chipping of the wafer.

[0006] The present invention has been made in consideration of the above facts, and its object is to provide a wafer processing method that can grind a wafer that has an outer peripheral excess region that is thinner than the device region inside the chamfered portion of the outer peripheral edge without causing chipping. [Means for solving the problem]

[0007] In order to solve the above-mentioned problems and achieve the object, the wafer processing method of the present invention is a wafer processing method for processing a wafer having a device region in which devices are formed in an area partitioned by a plurality of intersecting planned dividing lines set on the front surface, and a peripheral excess region that surrounds the device region and is thinner than the device region, and the peripheral edge is chamfered in an arc shape, the method comprising: an annular removal step of performing annular processing along the peripheral edge of the wafer at a position a predetermined distance inside the peripheral edge of the wafer, thereby annularly removing the peripheral portion of the wafer; a dividing processing step of performing processing along the dividing line that is closest to the peripheral edge among the planned dividing lines set on the wafer, to divide the peripheral excess region that cannot be removed in the annular removal step and the device region; and a grinding step of grinding the back side of the wafer to a predetermined finished thickness after the annular removal step and the dividing processing step have been performed. a tape application step of applying a tape to the backside of the ground wafer after the grinding step; Including A wafer ID is formed in the peripheral excess area that cannot be removed in the annular removal step, and in the tape attachment step, the divided wafer ID is attached to the tape together with the wafer. It is characterized by:

[0008] In the wafer processing method, the annular removal step and the dividing step may form a modified layer inside the wafer by irradiating a laser beam of a wavelength that is transparent to the wafer from the back side of the wafer.

[0009] In the wafer processing method , applicable a device chip manufacturing step in which, after the tape attaching step, the wafer is divided into device chips by performing processing along the planned dividing lines from the front surface side of the wafer; P It may further include. [Effects of the Invention]

[0011] The present invention has the effect of being able to grind a wafer having an outer peripheral excess region that is thinner than the device region and located inside the chamfered portion of the outer peripheral edge without causing chipping. [Brief explanation of the drawings]

[0012] [Figure 1] FIG. 1 is a perspective view of a wafer to be processed by the wafer processing method according to the first embodiment. [Figure 2] FIG. 2 is a side view of the wafer shown in FIG. [Figure 3] FIG. 3 is a flowchart showing the flow of the wafer processing method according to the first embodiment. [Figure 4] FIG. 4 is a perspective view schematically showing the annular removal step of the wafer processing method shown in FIG. [Figure 5] FIG. 5 is a side view, partly in section, schematically showing the annular removal step of the wafer processing method shown in FIG. [Figure 6] FIG. 6 is a perspective view schematically showing the dividing step of the wafer processing method shown in FIG. [Figure 7] FIG. 7 is a side view, partly in section, schematically showing the dividing step of the wafer processing method shown in FIG. [Figure 8]FIG. 8 is a side view, partly in section, schematically showing the grinding step of the wafer processing method shown in FIG. [Figure 9] FIG. 9 is a side view, partly in section, schematically showing the wafer processing method shown in FIG. 3 at the end of the grinding step. [Figure 10] FIG. 10 is a side view, partly in section, schematically showing a state in which tape is applied to the back surface of the wafer in the tape application step of the wafer processing method shown in FIG. [Figure 11] Figure 11 is a side view, partially in cross section, showing a state in which a tape having an annular frame attached to its outer edge is adhered to the back surface of a wafer in the tape application step of the wafer processing method shown in Figure 3. [Figure 12] FIG. 12 is a perspective view schematically showing a device chip manufacturing step of the wafer processing method shown in FIG. DETAILED DESCRIPTION OF THE INVENTION

[0013] Modes (embodiments) for carrying out the present invention will be described in detail with reference to the drawings. The present invention is not limited to the contents described in the following embodiments. Furthermore, the components described below include those that can be easily imagined by a person skilled in the art and those that are substantially the same. Furthermore, the configurations described below can be combined as appropriate. Furthermore, various omissions, substitutions, or modifications of the configuration can be made within the scope of the gist of the present invention.

[0014] [Embodiment 1] A wafer processing method according to a first embodiment of the present invention will be described with reference to the drawings. Fig. 1 is a perspective view of a wafer to be processed by the wafer processing method according to the first embodiment. Fig. 2 is a side view of the wafer shown in Fig. 1. Fig. 3 is a flowchart showing the flow of the wafer processing method according to the first embodiment.

[0015] (wafer) The wafer processing method according to the first embodiment is a processing method for processing a wafer 1 shown in Fig. 1. The wafer 1 to be processed by the wafer processing method according to the first embodiment is a disk-shaped semiconductor wafer, optical device wafer, or the like, having a substrate 2 made of silicon, sapphire, gallium arsenide, SiC (silicon carbide), or the like. As shown in Figs. 1 and 2, the wafer 1 has a front surface 3 and a back surface 4 on the rear side of the front surface 3, and is formed in a disk shape with the front surface 3 and the back surface 4 parallel to each other.

[0016] As shown in FIG. 2, the wafer 1 has a chamfered portion 5 formed on its outer periphery, the chamfered portion 5 having an arc-shaped cross section extending from the front surface 3 to the back surface 4, with the center in the thickness direction protruding most toward the outer periphery.

[0017] The wafer 1 has a device region 6 and a peripheral excess region 7. In the device region 6, a plurality of planned division lines 8 that intersect with each other are set on the front surface 3, and devices 9 are formed in each of the regions partitioned by the planned division lines 8 set on the front surface 3.

[0018] In embodiment 1, the device 9 is, for example, an integrated circuit such as an IC (Integrated Circuit) or an LSI (Large Scale Integration), an image sensor such as a CCD (Charge Coupled Device) or a CMOS (Complementary Metal Oxide Semiconductor), a MEMS (Micro Electro Mechanical Systems), or various memories (semiconductor memory devices).

[0019] The peripheral surplus region 7 is a region that surrounds the entire device region 6, is provided on the outer edge of the wafer 1, and includes the chamfered portion 5 described above. The peripheral surplus region 7 is a region where no devices 9 are formed on the front surface 3. In other words, the peripheral surplus region 7 is a region that is closer to the outer periphery of the wafer 1 than the outer edge of the outermost device 9 among the multiple devices 9 in the device region 6.

[0020] In the first embodiment, the outer peripheral surplus region 7 includes an annular portion 71 having a circular ring shape and an inner peripheral portion 72 disposed inside the annular portion 71. The annular portion 71 is formed in a ring shape and is a region on the outer peripheral side of the wafer 1 relative to a circular boundary line 73 (shown by a dotted line in FIG. 1 ) formed by connecting the arc-shaped outer edges of the outer edges of the outermost devices 9 of the multiple devices 9 in the device region 6. The inner peripheral portion 72 is a region surrounded by the boundary line 73, a linear boundary line 74 (shown by a dotted line in FIG. 1 ) that follows the planned division line 8 of the outer edge of the outermost device 9 of the multiple devices 9 in the device region 6, and the annular portion 71.

[0021] The inner peripheral portion 72 corresponds to the outer peripheral excess region that cannot be removed in the annular removal step 101 described in the claims. The boundary lines 73 and 74 are imaginary lines and do not exist on the front surface 3 of the wafer 1.

[0022] The thickness 61 of the device region 6 is the sum of the thickness of the substrate 2 and the thickness of the device formed on the surface 3 of the substrate 2, and the thickness 75 of the peripheral surplus region 7 is the thickness of the substrate 2. For this reason, the thickness 75 of the peripheral surplus region 7 is thinner than the thickness 61 of the device region 6. In this way, the wafer 1 has the peripheral surplus region 7, which has a thickness 75 thinner than the device region 6, located inside the chamfered portion 5 on the outer periphery.

[0023] In addition, in the first embodiment, the wafer 1 has a wafer ID 10 formed on the surface 3 of the inner peripheral portion 72 of the outer peripheral surplus region 7 for identifying the wafers 1 from one another. In the first embodiment, the wafer ID 10 is formed using at least one of letters, numbers, and symbols, but in the present invention, it may also be a well-known barcode or two-dimensional code. The wafer ID 10 is formed by printing or the like on the surface 3 of the inner peripheral portion 72 of the outer peripheral surplus region 7. In the present invention, the wafer 1 does not necessarily have to have a wafer ID 10 formed on the surface 3 of the inner peripheral portion 72 of the outer peripheral surplus region 7.

[0024] The wafer 1 having the above-described configuration has the peripheral excess region 7 removed from the device region 6, is thinned to a predetermined finished thickness 12, and is then divided into individual device chips 13. Each device chip 13 includes a part of the substrate 2 and a device 9 formed on the surface 3 of the substrate 2.

[0025] (Wafer Processing Method) The wafer processing method according to the first embodiment is a method of removing the peripheral excess region 7 of the wafer 1, thinning the wafer 1 to a predetermined finished thickness 12, and dividing the wafer 1 into individual device chips 13. As shown in Fig. 3, the wafer processing method according to the first embodiment includes an annular removing step 101, a dividing step 102, a grinding step 103, a tape attaching step 104, and a device chip manufacturing step 105.

[0026] (Annular Removal Step) Fig. 4 is a perspective view schematically showing the annular removal step of the wafer processing method shown in Fig. 3. Fig. 5 is a side view, partially in cross section, schematically showing the annular removal step of the wafer processing method shown in Fig. 3.

[0027] The annular removal step 101 is a step of performing annular processing along the outer peripheral edge of the wafer 1 at a position a predetermined distance inside the outer peripheral edge, to perform processing to annularly remove annular portion 71 of the outer peripheral excess region 7, which is the outer peripheral portion of the wafer 1. In the annular removal step 101, the laser processing device 20 suction-holds the front surface 3 of the wafer 1 on the holding surface 22 of the chuck table 21, captures an image of the wafer 1 with an infrared camera, and performs alignment of the wafer 1 with a laser beam irradiation unit 24 that irradiates a laser beam 23 with a wavelength that is transparent to the wafer 1.

[0028] In the annular removal step 101, the laser processing device 20 positions the focal point of the laser beam irradiation unit 24 inside the substrate 2, and irradiates a pulsed laser beam 23 along the boundary line 73 from the back surface 4 side of the wafer 1 while moving the chuck table 21 and the laser beam irradiation unit 24 relatively along the boundary line 73, as shown in Fig. 4. Note that since the laser beam 23 has a wavelength that is transparent to the wafer 1, in the annular removal step 101, the laser processing device 20 forms a modified layer 14 along the boundary line 73 inside the substrate 2 of the wafer 1, as shown in Fig. 5.

[0029] Thus, in the first embodiment, in the annular removal step 101, the laser processing apparatus 20 performs annular laser processing on the wafer 1 along the outer periphery by irradiating the back surface 4 of the wafer 1 with a laser beam 23 having a wavelength that is transparent to the wafer 1 along the boundary line 73. This performs annular laser processing on the wafer 1 along the outer periphery, forming a modified layer 14 within the substrate 2 of the wafer 1 to annularly remove the annular portion 71 of the outer periphery excess region 7. The modified layer 14 refers to a region in which the density, refractive index, mechanical strength, and other physical properties are different from those of the surrounding area. Examples of the modified layer 14 include a melt-processed region, a cracked region, a dielectric breakdown region, a refractive index change region, and a mixture of these regions. Furthermore, the modified layer 14 has lower mechanical strength and the like than other portions of the substrate 2 of the wafer 1.

[0030] Furthermore, in the first embodiment, in the annular removal step 101, the laser processing device 20 irradiates the laser beam 23 along the boundary line 73 from the back surface 4 side, and repeats this process multiple times while changing the height of the focal point, thereby forming multiple modified layers 14 in the thickness direction within the substrate 2 of the wafer 1 along the boundary line 73. Furthermore, in the first embodiment, in the annular removal step 101, the laser processing device 20 irradiates the laser beam 23 along the boundary line 73, but in the present invention, the laser beam 23 may be irradiated along the outer periphery between the boundary line 73 and the outer periphery. Furthermore, in the present invention, the laser beam 23 may be incident from the front surface 3 instead of the back surface 4.

[0031] (Dividing processing step) Fig. 6 is a perspective view schematically showing the dividing step of the wafer processing method shown in Fig. 3. Fig. 7 is a side view schematically showing, in partial cross section, the dividing step of the wafer processing method shown in Fig. 3.

[0032] The dividing step 102 is a step of performing processing on the dividing line closest to the outer periphery among the dividing lines 8 set on the wafer 1, in order to divide the inner peripheral portion 72 of the outer periphery excess region 7 that cannot be removed in the annular removal step 101 and the device region 6. In the dividing step 102, the laser processing device 20 positions the focal point of the laser beam irradiation unit 24 inside the substrate 2, and irradiates a pulsed laser beam 23 from the back surface 4 side of the wafer 1 to a position on the outer periphery side of the boundary line 74 along the dividing line 8 close to the outer periphery, while moving the chuck table 21 and the laser beam irradiation unit 24 relatively along the boundary line 74, i.e., the dividing line 8 close to the outer periphery, as shown in FIG.

[0033] Note that, since the laser beam 23 has a wavelength that is transparent to the wafer 1, in the dividing processing step 102, similar to the annular removal step 101, the laser processing apparatus 20 forms a modified layer 14 along the dividing line 8 near the outer periphery at a position on the outer periphery side of the boundary line 74 inside the substrate 2 of the wafer 1, as shown in Fig. 6. As described above, in the dividing processing step 102 in the first embodiment, the laser processing apparatus 20 applies the laser beam 23, having a wavelength that is transparent to the wafer 1, from the back surface 4 side of the wafer 1 to a position on the outer periphery side of the boundary line 74 along the dividing line 8 near the outer periphery, thereby performing linear laser processing along the dividing line 8 near the outer periphery, and processing the wafer 1 to form a modified layer 14 for dividing the inner periphery 72 of the outer periphery excess region 7 and the device region 6 inside the substrate 2 of the wafer 1, as shown in Fig. 7.

[0034] Also, in the first embodiment, in the dividing step 102, the laser processing device 20 irradiates the rear surface 4 with the laser beam 23 at a position on the outer periphery side of the boundary line 74 along the dividing line 8 closer to the outer periphery, and repeats this process multiple times while changing the height of the focusing point, thereby forming multiple modified layers 14 in the thickness direction within the substrate 2 of the wafer 1 along the dividing line 8 closer to the outer periphery than the boundary line 74. Also, in the first embodiment, in the dividing step 102, the laser processing device 20 irradiates the laser beam 23 at a position on the outer periphery side of the boundary line 74, but in the present invention, the laser beam 23 may also be irradiated to the boundary line 74 along the dividing line 8 closer to the outer periphery.

[0035] In addition, in embodiment 1, the annular removal step 101 is performed followed by the dividing processing step 102, but the present invention is not limited to this, and the annular removal step 101 may be performed after the dividing processing step 102.

[0036] (Grinding step) Fig. 8 is a side view, partially in cross section, schematically showing the grinding step of the wafer processing method shown in Fig. 3. Fig. 9 is a side view, partially in cross section, schematically showing the end of the grinding step of the wafer processing method shown in Fig. 3. The grinding step 103 is a step in which the back surface 4 side of the wafer 1 is ground to a predetermined finished thickness 12 after the annular removal step 101 and the division processing step 102 are performed.

[0037] In the grinding step 103, a surface protection tape 15 is applied to the front surface 3 of the wafer 1, and a grinding device 30 suction-holds the front surface 3 of the wafer 1 on a holding surface 32 of a chuck table 31 via the surface protection tape 15. In the grinding step 103, as shown in Fig. 8, a grinding wheel 34 for grinding is rotated about its axis by a spindle 33, and the chuck table 31 is rotated about its axis, and while a grinding fluid is supplied from a grinding fluid nozzle (not shown), a grinding stone 35 of the grinding wheel 34 is brought into contact with the back surface 4 of the substrate 2 of the wafer 1 and moved toward the chuck table 31 at a predetermined feed rate, and the back surface 4 of the wafer 1 is ground with the grinding stone 35.

[0038] In the grinding step 103, the back surface 4 side of the wafer 1 is ground until the thickness 61 of the device region 6 of the wafer 1 reaches the finished thickness 12 shown in Fig. 9. Since the modified layer 14 described above has been formed in the annular removing step 101 and the dividing processing step 102, when the back surface 4 of the wafer 1 is pressed by the grinding wheel 35, the wafer 1 is broken starting from the modified layer 14 by the force of this pressing, as shown in Fig. 9, and the inner peripheral portion 72 and the annular portion 71 of the outer peripheral excess region 7 are separated from the device region 6. The broken and separated inner peripheral portion 72 and the annular portion 71 on which the wafer ID 10 is formed are pressed against the surface protection tape 15.

[0039] (Tape application step) Fig. 10 is a side view, partially in cross section, schematically showing a state in which tape is applied to the back surface of a wafer in the tape application step of the wafer processing method shown in Fig. 3. Fig. 11 is a side view, partially in cross section, schematically showing a state in which tape having an annular frame attached to its outer edge is applied to the back surface of a wafer in the tape application step of the wafer processing method shown in Fig. 3.

[0040] The tape application step 104 is a step of applying a tape 16 to the back surface 4 of the ground wafer 1 after the grinding step 103. In the first embodiment, in the tape application step 104, a tape 16 having an outer diameter larger than that of the wafer 1, as shown in FIG. 10 , is applied to the back surface 4 of the wafer 1 after the grinding step 103, which is held by suction on the chuck table 31. At this time, in the tape application step 104, the inner peripheral portion 72 and the annular portion 71 on which the divided wafer IDs 10 are formed are applied to the tape 16 together with the device region 6 of the wafer 1. Also, in the first embodiment, in the tape application step 104, as shown in FIG. 11 , an annular frame 17 having an inner diameter larger than the outer diameter of the wafer 1 is attached to the outer edge of the tape 16, and the wafer 1 is supported by the tape 16 within an opening inside the annular frame 17.

[0041] In the first embodiment, in the tape application step 104, a roller that moves along the back surface 4 of the wafer 1 and rolls on the tape 16 presses the tape 16 against the back surface 4 of the wafer 1, thereby applying the tape 16 to the back surface 4 of the wafer 1. However, in the present invention, the tape 16 may be applied to the wafer 1 by a vacuum mount that accommodates the wafer 1 and the tape 16 in a vacuum chamber whose interior is reduced in pressure, and applies the tape 16 to the back surface 4 of the wafer 1 by using the air pressure difference between the spaces partitioned by the tape 16 in the vacuum chamber.

[0042] (Device chip manufacturing step) Fig. 12 is a perspective view schematically showing the device chip manufacturing step of the wafer processing method shown in Fig. 3. Note that the tape 16 and the annular frame 17 are omitted from Fig. 12. The device chip manufacturing step 105 is a step in which, after the tape attachment step 104, the wafer 1 is divided into device chips 13 by processing the wafer 1 from the front surface 3 side along the planned division lines 8.

[0043] In the device chip manufacturing step 105, the surface protection tape 15 is peeled off from the front surface 3 of the wafer 1, and the cutting device 40 suction-holds the back surface 4 of the wafer 1 to the holding surface 42 of the chuck table 41 via the tape 16, and an imaging unit images the wafer 1 to perform alignment by aligning the planned dividing line 8 with the cutting blade.

[0044] In the device chip manufacturing step 105, as shown in Figure 12, the cutting device 40 moves the chuck table 41 and the cutting blade 43, which rotates around its axis by a spindle, relatively along the planned dividing line 8, and causes the cutting blade 43 to cut into the planned dividing line 8 of the wafer 1 until it reaches the tape 16.

[0045] Thus, in the device chip manufacturing step 105 of the first embodiment, the cutting device 40 performs a cutting process in which the cutting blade 43 cuts into the planned dividing lines 8 of the wafer 1, thereby dividing the wafer 1 into individual device chips 13. In the device chip manufacturing step 105, once the cutting blade 43 has cut into all of the planned dividing lines 8 of the wafer 1 to manufacture the device chips 13, the wafer processing method of the first embodiment is completed.

[0046] The wafer processing method according to the first embodiment described above performs processing to form a modified layer 14 in the annular removal step 101 and the dividing step 102 to remove the annular portion 71 and the inner peripheral portion 72 of the outer circumferential excess region 7 from the device region 6. In the wafer processing method according to the first embodiment, after the annular removal step 101 and the dividing step 102, the back surface 4 of the wafer 1 is ground in the grinding step 103. This allows the wafer 1 to be broken starting from the modified layer 14 and divided into the device region 6 and the outer circumferential excess region 7, thereby suppressing chipping of the wafer 1 in the grinding step 103.

[0047] As a result, the wafer processing method according to embodiment 1 has the effect of being able to grind a wafer 1 that has an outer peripheral excess region 7 inside the chamfered portion 5 on the outer periphery and that has a thickness 75 thinner than that of the device region 6 without causing chipping.

[0048] Furthermore, in the wafer processing method according to embodiment 1, when the back surface 4 is ground, the wafer 1 is processed so that the thin outer peripheral surplus region 7, which has a thickness 75 that is separated from the holding surface 32 of the chuck table 31, is pre-divided. Therefore, even if the thin outer peripheral surplus region 7 is broken due to the suction pressure on the chuck table 31 as the grinding progresses, the crack can be prevented from extending into the device region 6, thereby making it possible to suppress chipping.

[0049] Furthermore, in the wafer processing method according to embodiment 1, the inner circumference 72 on which the wafer ID 10 is formed is also transferred to the tape 16 by the tape attachment step 104, so that it is possible to trace the history of how the wafer 1 has been processed.

[0050] The present invention is not limited to the above-described embodiment. In other words, various modifications can be made without departing from the gist of the present invention. For example, in the annular removing step 101 and the dividing step 102, a cutting process may be performed in which a cutting blade is inserted into the front surface 3 of the wafer 1, or a laser beam having a wavelength absorbable by the wafer 1 may be irradiated onto the front surface 3 of the wafer 1 to form a groove in the front surface 3 of the wafer 1 instead of the modified layer 14. [Explanation of symbols]

[0051] 1 wafer 3 surface 4 Back side 6 Device Area 7 Surplus outer area 8 Planned division line 9 Devices 10 Wafer ID 12 Finished thickness 13 Device Chips 14 Modified layer 16 Tape 23 Laser Beam 71 Annular part (outer periphery) 72 Inner circumference (excess outer circumference area that cannot be removed) 75 Thickness 101 Circular Removal Step 102 Cutting processing step 103 Grinding Step 104 Tape application steps 105 Device Chip Manufacturing Steps

Claims

1. A wafer processing method for processing a wafer having a device region in which devices are formed in an area partitioned by a plurality of intersecting planned division lines set on a surface, and an outer peripheral excess region surrounding the device region and having a thickness thinner than the device region, the outer peripheral edge of which is chamfered in an arc shape, comprising: an annular removal step of performing annular processing along the outer periphery of the wafer at a position a predetermined distance inside the outer periphery of the wafer, thereby annularly removing the outer periphery of the wafer; a dividing processing step of performing processing on the dividing line closest to the outer periphery of the dividing lines set on the wafer to divide the device region from an outer periphery excess region that cannot be removed in the annular removing step; a grinding step of grinding the back surface side of the wafer to a predetermined finished thickness after the annular removing step and the dividing step are performed; a tape application step of applying a tape to the backside of the ground wafer after the grinding step; Including, a wafer ID is formed in the peripheral excess region that cannot be removed in the annular removal step; The method for processing a wafer is characterized in that in the tape attaching step, the divided wafer ID is attached to a tape together with the wafer.

2. The annular removing step and the dividing step include: Irradiating the wafer from the back side with a laser beam having a wavelength that is transparent to the wafer, 2. The wafer processing method according to claim 1, further comprising forming a modified layer inside the wafer.

3. 3. The wafer processing method according to claim 1, further comprising a device chip manufacturing step of manufacturing device chips by dividing the wafer by processing the wafer from the front surface side along the planned dividing lines after the tape attaching step.

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