Method for manufacturing a laminated device and a laminated device

Abstract

To provide a fabrication method of a stacked device, in which a test on at least part of a plurality of circuit portions is performed during fabrication, and a stacked device.SOLUTION: A stacked device 1 includes: a plurality of circuit layers 2_1, 2_4 having circuit portions 20_1, 20_4, respectively; insulating layers 3_2, 3_3 which each cover a plurality of circuit portions included in a part of circuit layers of the plurality of circuit layers; and a plurality of conductive vias 4_2, 4_3 provided in the respective insulating layers and electrically connected to the plurality of circuit portions. The conductive via electrically connected to a partial circuit portion of the plurality of circuit portions is electrically insulated on an end surface on an opposite side to the plurality of circuit portions, and the partial circuit portion is a wreckage broken at least partially along a stacking direction.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a method for manufacturing a multilayer device and a multilayer device. [Background technology]

[0002] Patent documents 1 to 4 state that "in the process of forming the electrode pad 200...at least a part of the surface of the electrode pad 200 that is to be connected to the bonding wire 400 (described later) is made to protrude from the protective insulating film 300 to form the protruding portion 201...after the operation test process of the semiconductor element, a polishing process of the electrode pad 200 is carried out..." [Prior art document] [Patent documents] [Patent Document 1] JP 2012-5448 A [Patent Document 2] International Publication No. 2012 / 11207 [Patent Document 3] Japanese Patent Application Laid-Open No. 11-16971 [Patent Document 4] Patent No. 5632584 Summary of the Invention

[0003] In a first aspect of the present invention, there is provided a method for manufacturing a laminated device. The method for manufacturing a laminated device may include a lamination step of laminating, on a formed object, conductive paths that are electrically connected to multiple circuit portions of a formed object, the multiple circuit layers of which have been formed up to some of the circuit layers in the laminated device. The method for manufacturing a laminated device may include a testing step of testing at least some of the multiple circuit portions using the conductive paths. The method for manufacturing a laminated device may include a removal step of destructively removing the conductive paths.

[0004] The method for manufacturing a laminated device may further include, after the removing step, a step of laminating another circuit layer, which is different from some of the plurality of circuit layers, on the formed product.

[0005] The plurality of circuit portions may include a first circuit portion that constitutes a circuit of the stacked device, and a second circuit portion that is used for testing the first circuit portion.

[0006] The second circuit portion may have at least one of an ESD protection circuit that protects the first circuit portion from electrostatic discharge that occurs during the testing phase, a BIST circuit that tests the first circuit portion, a process monitor circuit that monitors physical characteristics of the first circuit portion, and a switching circuit that switches connections between multiple first circuit portions.

[0007] The method for manufacturing a laminated device may further include, after the testing step, a step of destroying at least a part of the second circuit portion along the stacking direction of the laminated device.

[0008] The conductive path may have an area along the surface of the formation that carries electrical current.

[0009] The conductive path may include at least a portion of the conductive paths formed in the stacked device that is not included in the formed object.

[0010] The conductive paths may have electrode pads that are electrically connected to probes used during testing.

[0011] In the laminating step, a heat dissipation structure for dissipating heat from the plurality of circuit portions may be laminated on the formed product together with the conductive paths. In the removing step, the heat dissipation structure may be further removed.

[0012] The formed product may have an insulating layer covering the plurality of circuit portions. The formed product may have a plurality of conductive vias electrically connected to the plurality of circuit portions and exposed on the surface of the insulating layer. In the lamination step, conductive paths electrically connecting the plurality of circuit portions through the plurality of conductive vias may be formed on the surface of the insulating layer.

[0013] In a second aspect of the present invention, a stacked device is provided. The stacked device may include a plurality of circuit layers, each having a circuit portion. The stacked device may include an insulating layer covering a plurality of circuit portions included in some of the plurality of circuit layers. The stacked device may include a plurality of conductive vias provided in the insulating layer and electrically connected to the plurality of circuit portions. The conductive vias electrically connected to some of the plurality of circuit portions may be electrically insulated at an end face opposite to the plurality of circuit portions.

[0014] At least a portion of the circuit portion may be destroyed along the stacking direction.

[0015] Some circuit portions may include at least one of an ESD protection circuit, a BIST circuit, a process monitor circuit, a switching circuit that switches connections, and remnants of any of these circuits having been destroyed in at least a portion along the stacking direction.

[0016] The above summary of the invention does not list all of the necessary features of the present invention, and subcombinations of these features may also constitute inventions. [Brief explanation of the drawings]

[0017] [Figure 1] 1 shows a multilayer device 1 according to a first embodiment. [Figure 2] FIG. [Figure 3] FIG. 2 is a diagram illustrating the first lamination stage. [Figure 4] FIG. 1 is a diagram illustrating a test stage. [Figure 5] FIG. 10 is a diagram illustrating the removal stage. [Figure 6] The formation 10 is shown after the removal step has been performed. [Figure 7] FIG. 10 is a diagram illustrating the second lamination stage. [Figure 8] 1 shows a multilayer device 1c according to a second embodiment. [Figure 9] Formation 10c is shown after the first formation stage. [Figure 10] Formation 10c is shown after the removal step. [Figure 11] FIG. 10 is a diagram illustrating the second lamination stage. [Figure 12] 10 shows a multilayer device 1d according to a third embodiment. [Figure 13] FIG. [Figure 14] FIG. 2 is a diagram illustrating the first lamination stage. [Figure 15] FIG. 1 is a diagram illustrating a test stage. [Figure 16] FIG. 10 is a diagram illustrating the removal stage. [Figure 17] Formation 10d is shown after the removal step has been performed. [Figure 18] FIG. 10 is a diagram illustrating the second lamination stage. DETAILED DESCRIPTION OF THE INVENTION

[0018] The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the scope of the invention according to the claims. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0019] [1. First embodiment] [1.1. Stacked Device 1] FIG. 1 shows a multilayer device 1 according to this embodiment. The multilayer device 1 includes a plurality of circuit layers 2 (two circuit layers 2 in this embodiment, for example). _1 ,2 _4 ) and a plurality of insulating layers 3 (in this embodiment, as an example, two insulating layers 3 _2 ,3 _3 ) and a plurality of conductive vias 4. In FIG. 1, the cross section of the multilayer device 1 is shown with the stacking direction X of the multilayer device 1 being the up-down direction in the drawing. The multilayer device 1 is made up of circuit layers 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 1 _1 , insulating layer 3 _2 , insulating layer 3 _3 and Circuit Layer 2 _4 may be provided.

[0020] [1.1-1.Circuit layer 2] Each circuit layer 2 has one or more circuit portions 20. Each circuit portion 20 may be a portion that constitutes part of a circuit, or may be a portion that can constitute part of a circuit by being electrically connected. Each circuit portion 20 may include a conductive path, or may include passive elements such as resistors, coils, and capacitors, or may include active elements such as transistors and diodes.

[0021] In this embodiment, as an example, the circuit layer 2 _1 is a plurality of circuit parts 20 _1 and a circuit layer 2 _4 is a plurality of circuit parts 20 _4 Circuit layer 2 _4 Each circuit portion 20 provided in _4 may constitute the circuit of the multilayer device 1.

[0022] circuit layer 2 _1 A plurality of circuit portions 20 provided in _1 Of these, some circuit parts 20 _1 (Circuit part 20a _1 The circuit portions 20 may be an example of a first circuit portion and may constitute the circuit of the laminated device 1. _1 Among these, the circuit portion 20a _1 Other circuit parts different from 20 _1 (Circuit part 20b _1 The circuit portion 20b may be an example of a second circuit portion and may not constitute the circuit of the laminated device 1. _1 is circuit layer 2 _1 Within the circuit portion 20a _1 The circuit portion 20b may not be electrically connected to the _1 During the manufacturing of the laminated device 1, the circuit portion 20a _1 It may be the part used in the test.

[0023] For example, circuit portion 20b _1The stacked device 1 may include at least one of an ESD protection circuit, a BIST circuit, a process monitor circuit, and a switching circuit. _1 Circuit portion 20a above _1 By temporarily connecting the circuit portion 20a to the _1 It may be a circuit for protecting the

[0024] The BIST circuit is implemented on circuit layer 2 during the fabrication of stacked device 1. _1 Circuit portion 20a above _1 By temporarily connecting the circuit portion 20a _1 For example, a BIST circuit may be a circuit that performs testing of one or more circuit portions 20. _1 The operation of each circuit portion 20 may be tested. _1 It is permissible to test for continuity, open circuit, characteristic defects, capacitance, etc.

[0025] The process monitor circuit monitors the circuit layer 2 during the fabrication of the laminated device 1. _1 Circuit portion 20a above _1 By temporarily connecting the circuit portion 20a _1 It may be a circuit that monitors a physical property of, for example, circuit portion 20a _1 The process monitor circuit may monitor the continuity, disconnection, characteristic defects, capacitance, etc. The process monitor circuit may include a transistor, a resistor, a ring oscillator, etc.

[0026] The switching circuitry is formed on circuit layer 2 during the fabrication of the laminated device 1. _1 Circuit portion 20a above _1 By temporarily connecting the circuit portions 20a _1 For example, the switching circuit may be an I / O selector.

[0027] [1.1-2. Insulating layer 3] Each insulating layer 3 is formed of an insulating material such as silicon oxide (SiO2) or silicon oxycarbide (SiOC). Each insulating layer 3 may be provided adjacent to the circuit layer 2 in the stacking direction X. In this embodiment, as an example, the insulating layer 3_3 is circuit layer 2 _4 and an insulating layer 3 _2 is circuit layer 2 _1 The insulating layer 3 is provided adjacent to the upper surface of the insulating layer 3. _2 are a plurality of circuit portions 20 included in some of the circuit layers 2 (in this embodiment, as an example, circuit layer 2 _1 Circuit portion 20 included in _1 ) may be covered.

[0028] [1.1-3. Conductive via 4] Each conductive via 4 is formed of a conductive material such as tungsten, copper, aluminum, etc. Each conductive via 4 may be provided in the insulating layer 3 and electrically connected to any one of the circuit portions 20.

[0029] Among the plurality of conductive vias 4, the insulating layer 3 _3 One or more conductive vias 4 (conductive vias 4 _3 (also referred to as "circuit layer 2") _4 One or more circuit portions 20 included in _4 may be electrically connected to

[0030] Among the plurality of conductive vias 4, the insulating layer 3 _2 A plurality of conductive vias 4 (conductive vias 4 _2 (also referred to as "circuit layer 2") _1 A plurality of circuit portions 20 included in _1 These conductive vias 4 _2 Among these, the circuit portion 20a _1 Conductive via 4 electrically connected to _2 (Conductive via 4a _2 Also called conductive via 4 _3 This allows the circuit layer 2 _1 Any circuit portion 20 of _1 and circuit layer 2 _4 Any circuit portion 20 of _4 are electrically connected to each other.

[0031] In addition, a plurality of conductive vias 4 _2 Among these, the circuit portion 20b_1 Conductive via 4 electrically connected to _2 (Conductive via 4b _2 (also referred to as "circuit portion 20") _1 The end surface opposite to the insulating layer 3 _3 In this embodiment, as an example, the conductive via 4b _2 is the insulating layer 3 _3 The end face may be covered by

[0032] This results in the circuit portion 20b _1 The circuit layer 2 may be embedded in the laminated device 1 and electrically isolated from other circuit portions 20. _4 and insulating layer 3 _3 are removed from the stacked device 1 to form a plurality of conductive vias 4 _2 through each of the plurality of circuit portions 20 _1 When a conductive path electrically connecting to the circuit portion 20b is formed, _1 is the circuit part 20a _1 may be available for testing.

[0033] According to the above-described stacked device 1, the plurality of conductive vias 4 _2 is insulating layer 3 _2 A plurality of circuit portions 20 _1 , the conductive via 4 is electrically connected to the _2 through a plurality of circuit portions 20 _1 At least a part of (in this embodiment, as an example, the circuit portion 20a _1 Therefore, by manufacturing the multilayer device 1 while determining whether it is good or bad during the manufacturing process, the quality of the multilayer device 1 can be reliably improved.

[0034] Also, a plurality of circuit portions 20 _1 A part of the circuit portion 20b _1 Conductive via 4b electrically connected to _2 is the circuit part 20 _1 Since the end face opposite to the circuit portion 20b is electrically insulated from the circuit portion 20b,_1 Conductive via 4 _2 1. Therefore, the multilayer device 1 can be more reliably improved in quality by being connected to other circuit portions 20 via the multilayer device 1.

[0035] Also, circuit layer 2 _1 Circuit portion 20b included in _1 has an ESD protection circuit, the circuit portion 20a _1 while protecting the circuit portion 20a from electrostatic discharge. _1 In addition, the circuit portion 20b _1 has a BIST circuit, the circuit portion 20a _1 The circuit part 20b _1 Also, the circuit portion 20b _1 has a process monitor circuit, the circuit portion 20a _1 The physical characteristics of the circuit portion 20b can be tested. _1 has a switching circuit, the circuit portion 20a _1 Testing can be performed while switching between the two.

[0036] [1.2. Manufacturing Method of Multilayer Device 1] The manufacturing method of the laminated device 1 according to this embodiment may include a formation step, a first stacking step, a testing step, a removal step, and a second stacking step. Note that in this embodiment, as an example, an assembly of multiple laminated devices 1 may be formed on a semiconductor substrate such as silicon through the formation step to the second stacking step, and the manufacturing method of the laminated device may further include a shredding step of singulating the individual laminated devices 1 included in the assembly.

[0037] [1.2-1. Formation stage] FIG. 2 is a diagram illustrating the formation stage. In the formation stage, a formation 10 may be formed in which some of the circuit layers 2 in the stacked device 1 are formed. In this embodiment, as an example, a group of a plurality of formations 10 may be formed together on a semiconductor substrate.

[0038] Each of the formations 10 may have an insulating layer 3 on its surface as long as it has formed thereon a part of the circuit layer 2 of the laminated device 1. In this embodiment, as an example, each of the formations 10 has a plurality of circuit portions 20a. _1 ,20b _1 Circuit layer 2 having _1 and a plurality of circuit portions 20a _1 ,20b _1 Insulating layer 3 covering _2 and a plurality of circuit portions 20a _1 ,20b _1 is electrically connected to the insulating layer 3 _2 a plurality of conductive vias 4 exposed on the surface of the _2 and

[0039] In addition, the insulating layer 3 of the formation 10 formed in the formation stage _2 and Conductive Via 4 _2 represents the insulating layer 3 in the laminated device 1. _2 and Conductive Via 4 _2 In this way, the insulating layer 3 formed thicker than the laminated device 1 may be formed thicker. _2 and Conductive Via 4 _2 The portion on the surface side of the conductive via 4 (also referred to as the excess portion 100) may be the portion to be removed by over-polishing in the removal step described later. _2 The excess portion 100 is formed by the conductive via 4 _2 It may be made of the same material as the other parts, or may be made of a different material.

[0040] The circuit layer 2 may be formed by providing circuit elements and conductive paths on a semiconductor substrate using a conventionally known method. The insulating layer 3 and conductive vias 4 may be formed using a conventionally known method. For example, the insulating layer 3 may be formed by a CVD method.

[0041] [1.2-2. First lamination stage] 3 is a diagram illustrating the first lamination step. In the first lamination step, a conductive path 5 electrically connecting to a plurality of circuit portions 20 in the formed object 10 may be laminated on the formed object 10. In this embodiment, as an example, a plurality of conductive vias 4 _2 through a plurality of circuit portions 20 _1 The conductive path 5 electrically connecting to the insulating layer 3 _2 Alternatively, a plurality of conductive paths 5 may be formed on the surface of a group of a plurality of formations 10. The number of conductive paths 5 formed on each formation 10 may be one or more. When a plurality of conductive paths 5 are formed, each conductive path 5 may be formed on one or more circuit portions 20. _1 may be electrically connected to

[0042] The formed conductive path 5 may have a region where a current flows along the surface of the formation 10, in other words, a region where a current flows in the in-plane direction of the surface of the formation 10. The conductive path 5 may also have an electrode pad 50 that is electrically connected to a probe 500 (see FIG. 4) used for testing during manufacturing.

[0043] The conductive path 5 may be formed by patterning, for example, by forming the insulating layer 3 _2 After forming an organic conductive film on the surface, the conductive paths 5 may be laminated by lithography and etching. The conductive paths 5 may also be laminated by inkjet printing or offset printing using conductive ink. When forming electrode pads 50 on the conductive paths 5, the electrode pads 50 may be formed by sputtering or vapor deposition using aluminum or an Al-Si alloy.

[0044] In the first lamination step, a plurality of circuit portions 20 _1 A heat dissipation structure (not shown) for dissipating heat from the insulating layer 3 may be laminated on the formation 10 together with the conductive path 5. _2The heat dissipation structure may extend from an area of ​​the surface of the laminated device 10 corresponding to a position (also called a hot spot) that will become hot in the formation 10 when testing is performed in the testing stage, to the edge of the surface. The heat dissipation structure may be formed to simulate a heat dissipation path included in the finished laminated device 1. The heat dissipation structure may be formed from a material with high thermal conductivity (for example, a metal such as copper or aluminum).

[0045] [1.2-3. Testing Phase] 4 is a diagram illustrating a test stage. In the test stage, a plurality of circuit portions 20a are connected to each other using the conductive path 5. _1 In the present embodiment, as an example, the test may be performed by bringing a probe 500 of a test device (not shown) into contact with the electrode pad 50 of the conductive path 5 and passing an electric signal from the probe 500 to the circuit portion 20b. _1 Utilizing the circuit portion 20a _1 In this figure, the conductive circuit portion 20 is shown with a double frame.

[0046] In this embodiment, as an example, each circuit portion 20a of the plurality of formations 10 included in the assembly _1 A test may be performed on the formations 10. If the proportion or number of formations 10 that have tested good among the formations 10 contained in the assembly is equal to or greater than a standard, the next removal step and subsequent steps may be performed to manufacture the laminated device 1. If the proportion or number of formations 10 that have tested bad among the formations 10 contained in the assembly is less than the standard, the assembly may be discarded.

[0047] [1.2-4. Removal Stage] FIG. 5 is a diagram illustrating the removal step. In the removal step, the conductive paths 5 may be destructively removed. If a heat dissipation structure is formed in the first lamination step, the heat dissipation structure may also be removed in the removal step. The conductive paths 5 and the heat dissipation structure may be removed by polishing (for example, CMP: Chemical Mechanical Polishing), etching, and cleaning. As long as the conductive paths 5 are destructively removed, the insulating layer 3 below the conductive paths 5 may be removed._2 and insulating layer 3 _2 Conductive via 4 formed in _2 At least a portion of the structure 10 (the above-mentioned excess portion 100 in this embodiment) may be further destroyed and removed, or, as an example, over-polishing may be performed. Note that this figure illustrates, as an example, a state in which the structure 10 is over-polished by the polishing pad 501.

[0048] 6 shows the structure 10 after the removal step has been performed. In the structure 10 after the removal step, the insulating layer 3 formed in the formation step is removed. _2 and conductive via 4 _2 The excess portion 100 may be removed.

[0049] [1.2-5. Second Lamination Stage] 7 is a diagram illustrating the second lamination step. In the second lamination step, at least one other circuit layer 2 may be laminated on the formed product 10. In this embodiment, as an example, an insulating layer 3 is laminated on the formed product 10. _3 and Circuit Layer 2 _4 The lamination of another circuit layer 2 may be performed by attaching a substrate (for example, a PCB: Printed Circuit Board) having one or more circuit layers 2 to the formed object 10. _2 If the end face of the _2 The circuit layer 2 _4 Circuit part 20 _4 In this way, an assembly of the multilayer devices 1 may be formed.

[0050] [1.2-6. Shredding stage] In the cutting step, the assembly of stacked devices 1 formed on the semiconductor substrate may be cut into individual stacked devices 1. For example, the semiconductor substrate may be cut along pre-set scribe lines. In this way, the finished stacked devices 1 are manufactured.

[0051] According to the above manufacturing method, the circuit layer 2 _1The circuit portion 20 included in the formation 10 formed up to _1 A conductive path 5 electrically connected to the circuit portion 20a is laminated on the formation 10. _1 Since the test is performed on the conductive paths 5, it is possible to determine whether the laminated device 1 is good or bad during manufacture. Furthermore, since the conductive paths 5 are destroyed and removed after the test, it is possible to prevent the test conductive paths 5 from remaining in the finished laminated device 1, which would increase the size of the laminated device 1. It is also possible to prevent traces of the test (for example, probe marks formed on the conductive paths 5 and particles generated from the electrode pads 50 due to probing) from remaining in the finished laminated device 1 and adversely affecting the quality.

[0052] In addition, the plurality of circuit portions 20 of the formed object 10 include a circuit portion 20a that constitutes the circuit of the laminated device 1. _1 and circuit portion 20a _1 Circuit portion 20b used for testing _1 Since the circuit portion 20b includes _1 Utilizing the circuit portion 20a _1 Tests can be conducted.

[0053] In the first lamination step, a plurality of circuit portions 20 are connected to each other through a plurality of conductive vias 4. _1 The insulating layer 3 is provided with a conductive path 5 electrically connecting the _2 Since the surface of the circuit is formed, unintended circuit portions 20 _1 This prevents the conductive path 5 from being electrically connected to the conductive layer 5, thereby facilitating the formation of the conductive path 5.

[0054] Furthermore, since the conductive path 5 has an area along the surface of the formation 10 through which current flows, the circuit portions 20 within the formation 10 can be easily connected together for testing.

[0055] Furthermore, since the conductive path 5 has the electrode pad 50 electrically connected to the probe 500, the probe 500 can be brought into contact with the electrode pad 50 to perform testing.

[0056] Furthermore, in the first stacking stage, a heat dissipation structure that dissipates heat from the multiple circuit portions 20 is stacked on the formed product 10 together with the conductive paths 5, so that testing can be performed while dissipating heat from the circuit portions 20. Furthermore, by forming a heat dissipation structure that imitates the finished laminated device 1, testing can be performed by placing the formed product 10 in a heat dissipation state similar to that of the finished laminated device 1. Furthermore, since the heat dissipation structure is removed in the removal stage, it is possible to prevent the laminated device 1 from becoming larger due to the heat dissipation structure that was temporarily installed for testing remaining in the finished laminated device 1.

[0057] After the conductive path 5 is broken and removed, the circuit layer 2 is formed on the formation 10. _4 Therefore, the circuit layer 2 _4 The laminated device 1 can be completed by forming the above.

[0058] In the first embodiment, the circuit layer 2 _1 Circuit portion 20b _1 By Circuit Layer 2 _1 Circuit portion 20a _1 However, the circuit layer 2 _1 Circuit portion 20a _1 Additionally or alternatively, circuit portions 20 in other circuit layers 2 that have already been formed may be tested.

[0059] [2. Second Embodiment] [2.1. Stacked Devices] Fig. 8 shows a multilayer device 1c according to this embodiment. In the multilayer device 1c according to this embodiment, components that are substantially the same as those in the multilayer device 1 shown in Fig. 1 are designated by the same reference numerals, and descriptions thereof will be omitted.

[0060] The stacked device 1c includes a plurality of circuit layers 2 (two circuit layers 2 in this embodiment, for example). _12 ,2 _13 ) and a plurality of insulating layers 3 (in this embodiment, as an example, two insulating layers 3 _11 ,3 _14 ) and a plurality of conductive vias 4. The laminated device 1c includes an insulating layer 3 in this order from the bottom. _11 , circuit layer 2 _12, circuit layer 2 _13 and insulating layer 3 _14 may be provided.

[0061] [2.1-1.Circuit layer 2 _12 ,2 _13 ] circuit layer 2 _12 is a plurality of circuit parts 20 _12 and a circuit layer 2 _13 is a plurality of circuit parts 20 _13 Circuit layer 2 _12 Each circuit portion 20 provided in _12 The circuit layer 2 may constitute the circuit of the laminated device 1c. _13 A plurality of circuit portions 20 provided in _13 Of these, some circuit parts 20 _13 (Circuit part 20a _13 The first circuit portion 1c may be an example of a first circuit portion, and may constitute the circuit of the laminated device 1c.

[0062] Also, a plurality of circuit portions 20 _13 Among these, the circuit portion 20a _13 Other circuit parts different from 20 _13 (Circuit part 20b _13 The circuit portion 20b may be an example of a second circuit portion and may not constitute the circuit of the laminated device 1c. _13 is circuit layer 2 _13 Within the circuit portion 20a _13 The circuit portion 20b may not be electrically connected to the _13 is the circuit portion 20b in the first embodiment described above. _1 Similarly, during the manufacturing of the laminated device 1c, the circuit portion 20a _13 It may be the part used in the test.

[0063] However, the circuit portion 20b _13 is the circuit portion 20b _1 Unlike the above, the circuit portion 20b may be destroyed during the manufacturing process of the laminated device 1c. _13The circuit portion 20b may be a remnant of at least a portion of the ESD protection circuit, the BIST circuit, the process monitor circuit, or the switching circuit destroyed along the stacking direction X. _13 may be formed containing common semiconductor materials (e.g., Si, SiO2, SiN, etc.), dopants (e.g., B, P, As), insulators, and conductive materials (e.g., W, Ti, Mo, Ru, Ta, Cu, etc.).

[0064] [2.1-2. Insulation Layer 3 _11 ,3 _14 ] Insulation layer 3 _11 is circuit layer 2 _12 and an insulating layer 3 _14 is circuit layer 2 _13 The insulating layer 3 is provided adjacent to the upper surface of the insulating layer 3. _14 is circuit layer 2 _13 A plurality of circuit portions 20 included in _13 may be covered.

[0065] [2.1-3. Conductive via 4] Among the plurality of conductive vias 4, the insulating layer 3 _14 One or more conductive vias 4 (conductive vias 4 _14 (also referred to as "circuit layer 2") _13 A plurality of circuit portions 20 included in _13 These conductive vias 4 _14 Among these, the circuit portion 20b _13 Conductive via 4 electrically connected to _14 (Conductive via 4b _14 (also referred to as "circuit portion 20b") _13 In this embodiment, the conductive via 4b may be electrically insulated from the other end surface (the upper end surface in this embodiment) of the conductive via 4b. _14 The end faces of the circuit portion 20b may be covered with an insulating film (not shown). _13 may be embedded in the laminated device 1c and electrically isolated from other circuit portions 20.

[0066] In addition, among the plurality of conductive vias 4, the insulating layer 3_14 One or more other conductive vias 4 (conductive vias 4 _14-13 (also referred to as "circuit layer 2") _13 and the circuit layer 2 _12 A plurality of circuit portions 20 included in _12 At least one conductive via 4 _14-13 is the circuit portion 20b _13 Position on circuit layer 2 _13 This allows the circuit portion 20b _13 The conductive via 4 may be broken at least in part along the stacking direction X. The broken part along the stacking direction X means that the broken part extends in the stacking direction X (in this embodiment, as an example, the conductive via 4 _14-13 The conductive vias 4 may have a thickness of 1 / 2 mm or an inner circumferential surface thereof, or may be cut in the lamination direction X. _14 and one or more conductive vias 4 _14-13 and insulating layer 3 _14 The electrodes may be electrically connected to each other on the surface thereof.

[0067] According to the above-described laminated device 1, the circuit portion 20b _13 is at least partially destroyed along the lamination direction X, so that the circuit portion 20b _13 is used for testing other circuit parts 20a _13 When the test is performed, the circuit portion 20b for the test is _13 This reliably prevents the test circuit portion 20b from becoming conductive and becoming an unnecessary capacitance component in the finished laminated device 1c, thereby improving the quality of the laminated device 1c. _13 Since the formation positions of the conductive vias 4 can be utilized as the formation positions of the conductive vias 4, the stacked device 1c can be made smaller.

[0068] [2.2. Manufacturing Method of Stacked Device 1c] The laminated device 1c according to this embodiment may be manufactured by a first forming step, a first stacking step, a testing step, a removal step, a second forming step, a second stacking step, and a cutting step. The steps from the first forming step to the removal step may be performed in the same manner as the steps from the forming step to the removal step in the first embodiment.

[0069] 9 shows the formation 10c after the first formation step. FIG. 10 shows the formation 10c after the removal step. The formation 10c according to this embodiment has an insulating layer 3 _14 and Circuit Layer 2 _13 The insulating layer 3 may include _14 Conductive via 4b provided in _14 may not be insulated at the top surface after the forming and removing steps.

[0070] In the second step, the test circuit portion 20b _13 The through holes are formed in the insulating layer 3 _13 After insulating the inner peripheral surface of the through hole, a conductive via 4 is formed inside the through hole. _14-13 This allows the circuit portion 20b _13 At least a part of the laminated device 1c is destroyed along the stacking direction X.

[0071] 11 is a diagram illustrating the second lamination step. In the second lamination step, at least one other circuit layer 2 may be laminated on the formation 10c in the same manner as in the first embodiment. In this embodiment, as an example, the lower surface of the formation 10c, that is, the circuit layer 2 _13 Circuit layer 2 on the underside _12 and circuit layer 2 _13 Each conductive via 4 exposed on the bottom surface of _14-13 The circuit layer 2 _12 Circuit part 20 _12 In this way, an assembly of stacked devices 1c may be formed. In the second stacking step, the insulating layer 3 _14 Conductive via 4b provided in _14 may be insulated at the top surface.

[0072] Then, in the cutting step, the assembly of the stacked devices 1c formed on the semiconductor substrate may be cut into individual stacked devices 1c in the same manner as in the first embodiment described above, thereby manufacturing the finished stacked devices 1c.

[0073] According to the above manufacturing method, after the test, the circuit portion 20b _13 At least a part of the circuit portion 20b used in the test is destroyed along the stacking direction X of the stacked device 1c. _13 Conductive via 4 is made by using the position of _14-13 Therefore, the test circuit portion 20b can be formed during the manufacturing process. _13 This can prevent the stacked device 1c from becoming large in size due to the provision of the insulating film.

[0074] In the second embodiment, the conductive via 4 _14-13 The second forming step forms the circuit portion 20b _13 However, they may be destroyed in the cutting step of dividing the stacked device 1c into individual pieces. _14-13 may be formed in advance on the scribe lines of the laminated device 1c.

[0075] 3. Third Embodiment [3.1. Stacked Devices] Fig. 12 shows a multilayer device 1d according to this embodiment. In the multilayer device 1d according to this embodiment, components that are substantially the same as those in the multilayer devices 1 and 1c shown in Figs. 1 and 8 are designated by the same reference numerals, and descriptions thereof will be omitted.

[0076] The stacked device 1d includes a plurality of circuit layers 2 (two circuit layers 2 in this embodiment, for example). _21 ,2 _24 ) and a plurality of insulating layers 3 (in this embodiment, as an example, two insulating layers 3 _22 ,3 _23 ) and a plurality of conductive vias 4. The laminated device 1d includes, in order from the bottom, a circuit layer 2 _21 , insulating layer 3 _22 , insulating layer 3 _23and Circuit Layer 2 _24 may be provided.

[0077] [3.1-1.Circuit layer 2 _21 ,2 _24 ] circuit layer 2 _21 is a plurality of circuit parts 20 _21 and a circuit layer 2 _24 is a plurality of circuit parts 20 _24 Each circuit portion 20 _21 ,twenty two _24 may constitute the circuit of the stacked device 1d.

[0078] [3.1-2. Insulation layer 3 _22 ,3 _23 ] Insulation layer 3 _22 is circuit layer 2 _21 an insulating layer 3 _23 is circuit layer 2 _24 The insulating layer 3 is provided adjacent to the lower surface of the insulating layer 3. _22 is circuit layer 2 _21 A plurality of circuit portions 20 included in _21 may be covered.

[0079] [3.1-3. Conductive via 4] Among the plurality of conductive vias 4, the insulating layer 3 _22 Conductive via 4 (conductive via 4 _22 (also referred to as "circuit layer 2") _21 A plurality of circuit portions 20 included in _21 The conductive vias 4 may be electrically connected to the insulating layer 3. _23 Conductive via 4 (conductive via 4 _23 (also referred to as "circuit layer 2") _24 A plurality of circuit portions 20 included in _24 The conductive via 4 may be electrically connected to the _22 and conductive via 4 _23 and may be electrically connected to each other in a one-to-one correspondence. _21 Any circuit portion 20 of _21 and circuit layer 2 _24 Any circuit portion 20 of _24are electrically connected to each other.

[0080] [3.2. Manufacturing Method of Stacked Device 1d] The laminated device 1d according to this embodiment may be manufactured through a forming step, a first laminating step, a testing step, a removing step, a second laminating step, and a chopping step.

[0081] [3.2-1. Formation stage] 13 is a diagram illustrating the formation stage. In the formation stage of this embodiment, a formation 10d in which up to a part of the circuit layer 2 in the stacked device 1d is formed may be formed in the same manner as in the first embodiment. The formation 10d includes a plurality of circuit portions 20 _21 Circuit layer 2 having _21 and a plurality of circuit portions 20 _21 Insulating layer 3 covering _22 and a plurality of circuit portions 20 _21 is electrically connected to the insulating layer 3 _22 a plurality of conductive vias 4 exposed on the surface of the _22 and

[0082] [3.2-2. First lamination stage] 14 is a diagram illustrating the first lamination step. In the first lamination step of this embodiment, a plurality of circuit portions 20 in a formed object 10d are laminated in the same manner as in the first embodiment. _21 The conductive path 5d may be laminated on the formation 10d, and may include at least a portion of the conductive paths formed in the finished laminated device 1d that are not included in the formation 10d. _24 A plurality of circuit portions 20 in _24 The conductive path may be a path that mimics at least a part of the above.

[0083] In the first lamination step of this embodiment, a plurality of circuit portions 20 are laminated in the same manner as in the first embodiment. _21 A heat dissipation structure (not shown) for dissipating heat from the conductive path 5d may be laminated on the formation 10d.

[0084] [3.2-3. Testing Phase] 15 is a diagram illustrating a test stage. In the test stage of this embodiment, similarly to the first embodiment, a plurality of circuit portions 20 are connected using the conductive paths 5d. _21 In this embodiment, as an example, a test may be performed on at least a part of the plurality of circuit portions 20 _21 Tests for each of the above may be performed.

[0085] [3.2-4. Removal Stage] 16 is a diagram illustrating the removal step. In the removal step of this embodiment, the conductive path 5d may be destroyed and removed in the same manner as in the first embodiment described above.

[0086] 17 shows the formation 10d after the removal step has been performed. In the formation 10d after the removal step, the insulating layer 3 formed in the formation step is _22 and conductive via 4 _22 The excess portion 100 on the front surface side (upper surface side in the drawing) may be removed.

[0087] [3.2-5. Second Lamination Stage] 18 is a diagram illustrating the second lamination step. In the second lamination step of this embodiment, at least one other circuit layer 2 may be laminated on the formation 10d in the same manner as in the first embodiment. In this embodiment, as an example, an insulating layer 3 may be laminated on the formation 10d. _23 and Circuit Layer 2 _24 may be stacked together, thereby forming an assembly of stacked devices 1d.

[0088] [3.2-6. Shredding stage] Then, in the cutting step, the assembly of the stacked devices 1d formed on the semiconductor substrate may be cut into individual stacked devices 1d in the same manner as in the first embodiment described above, thereby manufacturing the finished stacked devices 1d.

[0089] According to the above manufacturing method, the conductive path 5d includes at least a part of the conductive path formed by the circuit portion 20 in the laminated device 1d that is not included in the formation 10d. _21 In other words, the test can be performed by simulating the electrical connection state of the finished laminated device 1d.

[0090] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the claims that such modifications and improvements can also be included within the technical scope of the present invention.

[0091] It should be noted that the execution order of each process, such as operations, procedures, steps, and stages, in the devices, systems, programs, and methods shown in the claims, specifications, and drawings is not specifically stated as "before," "prior to," etc., and that the processes can be performed in any order unless the output of a previous process is used in a subsequent process. Even if the operational flow in the claims, specifications, and drawings is described using "first," "next," etc. for convenience, this does not mean that the processes must be performed in this order. [Explanation of symbols]

[0092] 1. Stacked devices 2 circuit layers 3. Insulation layer 4 Conductive vias 5 Conductive Path 10 formations 20 Circuit part 50 electrode pads 500 probes

Claims

1. a lamination step of laminating, on a formation formed up to some circuit layers in a laminated device having a plurality of circuit layers, conductive paths electrically connected to the plurality of circuit portions of the formation; a testing step of testing at least some of the plurality of circuit portions using the conductive path; a removing step of destructively removing the conductive path; Equipped with In the lamination step, a heat dissipation structure for dissipating heat from the plurality of circuit portions is laminated on the formed object together with the conductive paths; In the removing step, the heat dissipation structure is further removed.

2. a lamination step of laminating, on a formation formed up to some circuit layers in a laminated device having a plurality of circuit layers, conductive paths electrically connected to the plurality of circuit portions of the formation; a testing step of testing at least some of the plurality of circuit portions using the conductive path; a removing step of destructively removing the conductive path; After the removing step, a step of stacking another circuit layer different from the part of the circuit layers among the plurality of circuit layers on the formed object; A method for manufacturing a laminated device comprising:

3. A method for manufacturing a laminated device, comprising: a lamination step of laminating, on a formation formed up to some circuit layers in a laminated device having a plurality of circuit layers, conductive paths electrically connected to the plurality of circuit portions of the formation; a testing step of testing at least some of the plurality of circuit portions using the conductive path; a removing step of destructively removing the conductive path; Equipped with the plurality of circuit portions, a first circuit portion that constitutes a circuit of the laminated device; a second circuit portion used for testing the first circuit portion; and The manufacturing method for a laminated device further includes, after the testing step, a step of forming a conductive via through the second circuit portion and destroying at least a portion of the second circuit portion along the stacking direction of the laminated device.

4. The second circuit portion an ESD protection circuit for protecting the first circuit portion from electrostatic discharges occurring during the testing phase; a BIST circuit for testing the first circuit portion; a process monitor circuit for monitoring a physical characteristic of the first circuit portion; a switching circuit for switching connections between the plurality of first circuit portions; The method for manufacturing a laminated device according to claim 3 , further comprising at least one of the following steps:

5. The method for manufacturing a multilayer device according to claim 1 , wherein the conductive path has a region through which a current flows along a surface of the formation.

6. The method for manufacturing a multilayer device according to claim 1 , wherein the conductive path includes at least a part of the conductive paths formed in the multilayer device that is not included in the formation.

7. The method for manufacturing a laminated device according to claim 1 , wherein the conductive path has an electrode pad electrically connected to a probe used in the testing step.

8. The formation is an insulating layer covering the plurality of circuit portions; a plurality of conductive vias electrically connected to the plurality of circuit portions and exposed on the surface of the insulating layer; and 8. The method for manufacturing a laminated device according to claim 1, wherein in the lamination step, the conductive paths electrically connecting the plurality of circuit portions via the plurality of conductive vias are formed on a surface of the insulating layer.

9. a plurality of circuit layers each having a circuit portion; an insulating layer covering a plurality of circuit portions included in some of the plurality of circuit layers; a plurality of conductive vias provided in the insulating layer and electrically connected to the plurality of circuit portions; Equipped with The plurality of conductive vias are a first conductive via electrically connected to a part of the plurality of circuit portions and electrically insulated from the end face opposite to the plurality of circuit portions; a second conductive via electrically connected to another part of the plurality of circuit portions and provided to penetrate the part of the circuit portions; and A stacked device, wherein the partial circuit portion is penetrated by the second conductive via and is broken at least in part along the stacking direction.

10. a plurality of circuit layers each having a circuit portion; an insulating layer covering a plurality of circuit portions included in some of the plurality of circuit layers; a plurality of conductive vias provided in the insulating layer and electrically connected to the plurality of circuit portions; Equipped with a conductive via electrically connected to a part of the plurality of circuit portions is electrically insulated from an end face opposite to the plurality of circuit portions; The partial circuit portion has remains of at least a portion of a destroyed circuit portion that is used for testing a circuit portion different from the partial circuit portion among the plurality of circuit portions.

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