Method for measuring electrical properties of test specimen and multi-layer test specimen

Abstract

To measure electric characteristics of a magnetic tunnel junction used in an embedded MRAM memory or the like.SOLUTION: The method uses a multi-point probe having a plurality of probe tips which are brought into contact with a designated area of test specimen, particularly an area which is electrically isolated from the test target portion of the test specimen. Electrical connection means is arranged below the magnetic tunnel junction and communicates with the designated area.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to measuring at least one electrical property of a test specimen, such as a multilayer stack, eg, a magnetic tunnel junction (MTJ), consisting of a conductive layer and at least one tunneling barrier. [Background technology]

[0002] Microscopic multi-point probes are typically used to perform in-plane current tunneling measurements on, for example, magnetoresistive random access memory (MRAM) wafers to determine various electrical properties of the specimen, i.e., to test whether the wafer complies with specifications.

[0003] Possible electrical properties include the resistance area product, the sheet resistance of a first conductive sheet above the tunneling barrier, the sheet resistance of a second sheet (bottom sheet) below the tunneling barrier, and the magnetic tunneling resistance.

[0004] For test specimens containing several tunneling barriers and conductive sheets stacked on top of each other, multiple resistance-area products can be defined. A specimen containing multiple tunneling barriers can also be modeled using a single-barrier mathematical model. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] U.S. Patent Application Publication No. 2002 / 0097063 [Patent Document 2] U.S. Patent Application Publication No. 2016 / 0320430 Summary of the Invention [Problem to be solved by the invention]

[0006] In the typical method of placing a multi-point probe above the wafer and contacting the tip of the probe's electrode with the top surface of the wafer, for example in the case of a single tunneling barrier model, erroneous measurements can occur if the sheet resistance of the upper sheet is lower than that of the lower sheet.

[0007] It is an object of the present invention to achieve improved metrology. [Means for solving the problem]

[0008] The above objects and advantages, as well as numerous other objects and advantages which will become apparent from the description of the invention, are achieved in accordance with a first aspect of the invention, in a method for measuring electrical properties of a multilayer test specimen, e.g., a magnetic tunnel junction, comprising providing the multilayer test specimen having a stack with at least first and second layers, the stack above an electrical insulating layer; providing a first test specimen terminal above the electrical insulating layer for a first connection to a measurement circuit; providing a second test specimen terminal above the electrical insulating layer for a second connection to the measurement circuit; and connecting the first test specimen terminal, the second test specimen terminal, and the stack. a first conductive path embedded in the electrical insulating layer, electrically interconnecting the first test specimen terminal and the stack; and a second conductive path embedded in the electrical insulating layer, electrically interconnecting the second test specimen terminal and the stack; further comprising the steps of: providing a measurement circuit having a first measurement terminal and a second measurement terminal; contacting the first measurement terminal with the first test specimen terminal and the second measurement terminal with the second test specimen terminal; and measuring the electrical characteristics of the stack using the measurement circuit.

[0009] The terms electric, electronic, and electrically should be understood to be interchangeable.

[0010] A third test specimen terminal may be provided above the electrical insulating layer for a third connection to a measurement circuit, and a third measurement terminal may be brought into contact with the third test specimen terminal.

[0011] A fourth test specimen terminal may be provided above the electrical insulating layer for a fourth connection with a measurement circuit, and a fourth measurement terminal may be brought into contact with the fourth test specimen terminal.

[0012] The test specimen may be provided with or embedded with embedded means / features for embedded measurement of the electronic properties; embedded measurement means measuring the electronic properties of the test specimen by means of features embedded in the test specimen during microfabrication of the test specimen.

[0013] The embedding means may be formed by the two terminals and the conductive path below the stack and terminals.

[0014] The stack may be supported by the insulating layer below the stack, and similarly, the test specimen terminal may be supported by the insulating layer.

[0015] The first layer may be made of a conductive material and the second layer may also be made of a conductive material.

[0016] Alternatively, one of the two layers (preferably the second layer, eg the layer below the first layer) may be made of an electrical insulator.

[0017] Each of the first layer and / or the second layer may be divided into multiple layers / sheets.

[0018] An electrical insulator may be sandwiched between the first layer and the second layer so that the stack is a three-layer stack, and the electrical insulator may constitute a tunneling barrier / layer.

[0019] The multi-layer specimen may be a semiconductor wafer having multiple conductive layers and tunneling layers.

[0020] The multilayer specimen may be, for example, a magnetoresistive random access memory, with each memory cell being formed by a magnetic tunnel junction, and each junction being formed by a pillar.

[0021] There may be a high contact resistance barrier, such as a Schottky barrier, between the first (conductive) layer and the second (conductive) layer.

[0022] The stack may comprise electronic circuits for the desired purpose of the die of the semiconductor wafer, for example two layers of which may be for memory or sensor purposes.

[0023] The wafer is understood to refer to the substrate on which microelectronic devices are constructed during the wafer microfabrication process.

[0024] The microelectronic circuit may comprise electronic components that direct the desired purpose and circuits or members that control the electronic components, such as memory cells and switches for the memory cells.

[0025] The wafer may be fabricated by etching and / or layer growth, which may be repeated in multiple steps in a typical wafer fabrication process.

[0026] The measurement circuit may have a movable probe that moves the first measurement terminal and the second measurement terminal toward the test specimen, so that contact can be established between the first measurement terminal and the first test specimen terminal and between the second measurement terminal and the second test specimen terminal.

[0027] The first test specimen terminal and the second test specimen terminal may each constitute a landing pad for each of the two measurement terminals, so that the measurement terminal can be brought into (electrical) contact with the test specimen terminal when it is landed thereon.

[0028] Each of the first and second test specimen terminals may be created during the manufacture of the semiconductor wafer by etching each test specimen terminal as an island, i.e., by etching around the area of ​​the semiconductor wafer allocated to that test specimen terminal to leave a protruding structure.

[0029] The etching may penetrate a three-layer stack (e.g., comprising an MTJ stack) so that the test specimen itself has three layers, just like the unetched remainder of the wafer.

[0030] Alternatively, the specimen terminal may be constructed such that the material for that terminal is deposited / grown only in the area designated for that specimen terminal.

[0031] The test specimen terminals may be located within the scribe lines of the test specimen, i.e., the lines that separate the test specimen into individual dies containing integrated circuits that make up the electronic circuit.

[0032] The scribe lines are typically arranged in a rectangular grid, with the grid lines intersecting each other at right angles, in preparation for die dicing.

[0033] The width of the scribe line may be set to 20 to 200 μm, for example, 75 to 125 μm, or, for example, 100 μm.

[0034] The test specimen terminals may be fabricated simultaneously with the electronic / integrated circuit of the die, in which case the die area and scribe lines are exposed to the first layer of material in the same process, and the test specimen terminals are insulated from each other in a second process.

[0035] That is, the first layer of the test specimen terminal and the first layer of the stack may be in the same plane.

[0036] Several test specimen terminals, for example, four test specimen terminals, may be arranged next to each other. Their pitch (the distance between them) may match, for example, the pitch of a multi-point probe, so that the second test specimen terminal is adjacent to the first test specimen terminal. The third test specimen terminal may be adjacent to the second test specimen terminal, and the fourth test specimen terminal may be adjacent to the third test specimen terminal. The four test specimen terminals may be arranged linearly with each other to form a row of test specimen terminals.

[0037] The electrically insulating layer provides support for the layers above it and can also be used to embed electrical wiring, i.e., electrical interconnections between different parts of the wafer. Several such metallization layers may be provided for electrical interconnections throughout the wafer.

[0038] The electrical wiring, e.g., the first conductive path and the second conductive path, may be fabricated as copper lines deposited on the electrically insulating layer during fabrication of the wafer, and then the conductive paths may be embedded by further depositing material from the electrically insulating layer.

[0039] Interlayer electrical connections may be made by vertical (vertical) vias extending from one layer to another, i.e., vias that are vertical when the wafer is on a horizontal (lateral) surface. That is, a first via may interconnect the first conductive path and the first test specimen terminal. Such vias may be made of tungsten, copper, copper nitride, tantalum, tantalum nitride, cobalt, or ruthenium. Two or more separate vias may be used to establish the vertical portion of the conductive path, thereby interconnecting the test specimen terminal and the stack under test, and the conductive path may have two vertical path portions (one below the test specimen terminal and one below the stack, respectively) and one horizontal portion. Both vertical portions may be composed of multiple vias instead of a single via.

[0040] The electrically insulating layer may be made of an electrically insulating material such that electrical wiring within the layer defines a circuit path and confines electrical current flow to the defined circuit path.

[0041] A circuit may be formed in cooperation with the MTJ stack that conducts a power supply current from a first test specimen terminal to the MTJ stack and a return current to a second test specimen terminal by two conductive paths leading to separate test specimen terminals.

[0042] According to a second aspect of the present invention, the above-mentioned objects and advantages are achieved by a multilayer test specimen for embedded measurement of electrical properties of a multilayer test specimen, the multilayer test specimen comprising: a stack having at least first and second layers and located above an electrical insulating layer; a first test specimen terminal located above the electrical insulating layer for a first connection to a measurement circuit; and a second test specimen terminal located above the electrical insulating layer for a second connection to the measurement circuit, wherein the first test specimen terminal, the second test specimen terminal, and the stack are electrically insulated from each other; and a first conductive path embedded in the electrical insulating layer, electrically interconnecting the first test specimen terminal and the stack; and a second conductive path embedded in the electrical insulating layer, interconnecting the second test specimen terminal and the stack such that a circuit for measuring the electrical properties is formed between the first test specimen terminal and the second test specimen terminal by cooperation of the first conductive path and the second conductive path with the stack.

[0043] The invention will now be described in more detail, by way of example, with reference to the accompanying drawings, in which: [Brief explanation of the drawings]

[0044] [Figure 1] FIG. 1 is a development view of a test specimen. [Figure 2] FIG. 1 shows a test specimen. [Figure 3] 3A and 3B are diagrams showing test specimens, and FIG. 3B is a partially enlarged view of FIG. 3A. [Figure 4] 4A and 4B are diagrams showing test specimens, and FIG. 4B is a partially enlarged view of FIG. 4A. DETAILED DESCRIPTION OF THE INVENTION

[0045] It should be noted that the present invention may be embodied in forms other than those described below, and should not be construed as being limited to any of the examples described herein. Rather, all examples are provided for the purpose of ensuring that this disclosure is consistent and complete, and will fully convey the technical scope of the present invention to those skilled in the art.

[0046] Like reference numerals refer to like parts throughout, and as such, like elements are not described in detail in connection with the description of each figure.

[0047] Figure 1 shows the developed appearance of the test specimen.

[0048] The test specimen 10 has five layers, the top three of which form a magnetic tunnel junction (MTJ), or MTJ stack.

[0049] The test specimen may comprise a semiconductor wafer having at least two conductive layers and a tunneling electrically insulating layer sandwiched therebetween, such as an MTJ.

[0050] The top layer 12 of the MTJ stack may or may not contain ferromagnetic material, but is electrically conductive.

[0051] The magnetization direction of the upper layer is variable.

[0052] The middle layer 14 is sandwiched between the upper and lower layers 16 of the MTJ stack.

[0053] The intermediate layer is a thin electrical insulator, the thickness of which is not so great that electrons cannot tunnel through it; ie, the intermediate layer is a tunneling barrier layer.

[0054] The underlayer 16 may also contain ferromagnetic material but is electrically conductive.

[0055] Alternatively, the magnetization of the upper layer may be permanent and the magnetic moment of the lower layer may be variable, or both layers may have their magnetic moments variable in direction.

[0056] The resistance of the stack when a cross-linking potential is applied to it can depend on whether the magnetizations of the top and bottom layers are parallel or antiparallel, with the tunneling barrier being lower when the magnetizations are parallel than when the magnetizations are antiparallel.

[0057] The top layer is depicted as having a flat top surface, and the layers are generally depicted as being parallel to one another.

[0058] The stack may have two or more conductive layers and a barrier, with several electrical properties being measured.

[0059] Additionally, the layers of the test specimen may have functions other than those associated with the MRAM cell, such as having only two layers in the stack, whose purpose is to act as a sensor.

[0060] 1, the three-layer stack is shown as seven islands: six small islands adjacent to each other on one row and one isolated large island (e.g., a test island that constitutes an MTJ stack 28 for MRAM or sensor purposes), as a result of etching the stack layers so that the islands are electrically isolated from each other, i.e., so that the islands are not electrically connected to each other.

[0061] An electrical insulator made of an oxide material or other material may be created in the area where these layers have been removed, so that the spaces between the islands and the spaces between the island-MTJ stacks are filled with the electrical insulating material.

[0062] The six small islands constitute six test specimen terminals, the purpose of which is to provide landing pads, such as first landing pad 26; on first landing pad 26 is an exposed surface 30, which is a first landing area, and is not covered by any other layer, except that it may be covered by a thin oxide layer.

[0063] The test specimen terminals may be of any in-plane shape. Although a rectangular shape / area is shown in Figure 1, the shape may also be circular, oval, elliptical, polygonal or irregular.

[0064] Each landing area of ​​each landing pad is for landing a probe tip, and by contacting the probe tip with the landing area, electrical signals can be injected into the landing pad or electrical measurement signals can be picked up during a measurement routine. Thus, terminals for probes and for performing probe measurements are provided on the test specimen.

[0065] Instead of using probes, the test specimen may be inserted into the measurement device if the test specimen terminal positions are aligned with fixed positions of the measurement terminals when the test specimen is properly positioned within the measurement device.

[0066] The large island 28 may closely resemble that of the MRAM cell that needs to be tested, specifically, one or more electrical characteristics of its MTJ stack.

[0067] Below the MTJ stack is a fourth layer that constitutes the first electrically insulating layer 18, a layer that is not intended to allow current to flow freely through it without controlling the current path.

[0068] Below the fourth electrically insulating layer is a fifth layer that constitutes the second electrically insulating layer 24.

[0069] The first and second electrical insulating layers may be formed as a single electrical insulating layer.

[0070] The first electrically insulating layer has vias, for example first vias 22, that run through the layer in the thickness direction.

[0071] A via is drawn underneath each of the six islands that make up an island row.

[0072] Six vias, such as second via 34, are also shown below the large island, all of which come into contact with the bottom surface of the bottom layer of the MTJ stack.

[0073] Within the second electrically insulating layer are six copper layers, i.e., copper deposited during one of the manufacturing steps (although conductive materials other than copper may also be used).

[0074] The copper lanes form conductive paths, for example, first conductive paths 24 .

[0075] With regard to the electrical connection between the terminal and the individual portion of the test specimen desired to be tested, vias may be contemplated to be omitted. For example, if the test specimen terminal and the test island are adjacent, electrical connection only needs to be established beneath the isolated / etched portion of the test specimen.

[0076] Conductive tracks run parallel to the layers, each of which interconnects the vias associated with one of the landing pads with one of the vias in contact with the MTJ stack.

[0077] One of the electrically insulating layers may be used for electrical connections to control electronics, such as a switch, etc. The switch itself may be located in a sixth layer, for example a layer below the electrically insulating layer.

[0078] The landing pads do not necessarily have to be made up of three MTJ layers, but can instead be semiconductor material formed, e.g., deposited, as islands on the first electrically insulating layer, so that electrical signals from the probe tip are transmitted to vias that contact the individual landing pads from below.

[0079] Figure 2 shows the test specimen.

[0080] The test specimen in Figure 2 corresponds to the test specimen mentioned in connection with Figure 1, but with the probe already positioned above the test specimen.

[0081] The specimen shown is in an unexpanded state, with the vias and traces underneath the top three layers shown in dashed lines.

[0082] The probe has six cantilever arms extending parallel to one another, each of which has a probe tip, for example first probe tip 32, at the end.

[0083] Each probe tip is brought into contact with the landing area of ​​a corresponding landing pad, for example, first probe tip 32 is brought into contact with first landing pad 26 which is contacted from below by first via 22.

[0084] Since this is a contact for measuring electrical properties, this contact is one in which electrical contact is made between the probe tip and the landing pad; that is, the probe tip can penetrate into the oxide layer that often forms on the landing pad so that electrical contact can be established.

[0085] The probe tip can be allowed to penetrate the landing pad by a small distance rather than simply resting on the surface that makes up the landing area.

[0086] The first conductive path extends from the first via to the MTJ stack 28, ie, to a point below the MTJ stack.

[0087] The vias and conductive tracks complete a circuit path from one probe tip to another, allowing current to be injected into the circuit path and conducted into the MTJ stack and on to the second probe tip.

[0088] Four of the cantilever arms are for four-point measurement (four-terminal sensing): two for current injection and two for voltage measurement.

[0089] A fifth cantilever arm may be used for distance measurement, thereby controlling the probe tip-to-landing pad distance during probe tip landing.

[0090] Figure 3a shows the test specimen.

[0091] The test specimen in FIG. 3a corresponds to the test specimen mentioned in connection with FIG. 1, but is shown in cross section across a via leading to the MTJ stack to be tested.

[0092] FIG. 3b shows an enlarged view of one of the vias in FIG. 3a, ie, a portion of the test specimen shown in FIG. 3a.

[0093] This close-up view reveals the top layer 12, middle layer 14, and bottom layer 16 of the MTJ stack. A second via 34 extends vertically from the first conductive path 24 to the bottom layer 16 of the MTJ stack 28.

[0094] Figure 4a shows the test specimen.

[0095] The specimen in Figure 4a corresponds to the specimen mentioned in connection with Figure 1, but is a cross section through one of the conductive paths, and the cross section is along a plane perpendicular to the cross section of Figure 3b.

[0096] FIG. 4b shows an enlarged view of one of the vias in FIG. 4a, ie, a portion of the test specimen shown in FIG. 4a.

[0097] The enlarged view reveals the top layer 12, middle layer 14 and bottom layer 16 of the MTJ stack.

[0098] A second via 34 extends vertically from the first conductive path 24 to the bottom layer 16 of the MTJ stack 28 .

[0099] The conductive path 24 extends between the first via 22 and the second via 34 .

[0100] Below is a list of reference numbers used in the detailed description of the invention and in the drawings referenced in the detailed description of the invention. [Explanation of symbols]

[0101] 10 test specimen, 12 upper layer, 14 middle layer, 16 lower layer, 18 first electrical insulating layer, 20 second electrical insulating layer, 22 first via, 24 first conductive path, 26 first landing pad, 28 MTJ stack, 30 first landing area, 32 probe tip, 34 second via.

Claims

1. 1. A method for measuring electrical properties of a multilayer test specimen, comprising: providing a multilayer specimen having a stack with a first layer, a second layer and a tunneling barrier, the stack being above an electrically insulating layer; a first test specimen terminal above the electrical insulating layer for a first connection with a measurement circuit; providing a second test specimen terminal above the electrical insulating layer for a second connection with the measurement circuit; a test island having a function of a magnetoresistive random access memory and comprising an MTJ stack is provided; the first test specimen terminal, the second test specimen terminal, and the test island are provided as islands protruding from the electrical insulating layer and spaced apart from one another by etching a stack including the first layer, the second layer, and the one tunneling barrier around the first test specimen terminal, the second test specimen terminal, and the test island; a first conductive path embedded in the electrical insulating layer, the first conductive path electrically interconnecting the first test specimen terminal and the test island; and a second conductive path embedded in the electrical insulating layer, the second conductive path electrically interconnecting the second test specimen terminal and the test island; Furthermore, preparing the measurement circuit having a first measurement terminal and a second measurement terminal; contacting the first measurement terminal with the first test specimen terminal; contacting the second measurement terminal with the second test specimen terminal; and The method includes measuring the electrical characteristics of the test island with the measurement circuitry.

2. 2. The method of claim 1, wherein said multilayer specimen is a semiconductor wafer for said magnetoresistive random access memory.

3. 2. The method of claim 1, wherein the test island comprises a magnetic tunnel junction.

4. 2. The method of claim 1, wherein the first layer is a ferromagnetic sheet.

5. 2. The method of claim 1, wherein the second layer is a ferromagnetic sheet.

6. 2. The method of claim 1, wherein the test island comprises an intermediate layer sandwiched between the first and second layers, the intermediate layer comprising the tunneling barrier.

7. 7. The method of claim 6, wherein the intermediate layer is an electrical insulator for tunneling electrons between the first layer and the second layer.

8. 2. The method of claim 1, wherein said test islands of said multi-layer test specimen have three layers.

9. 2. The method of claim 1, wherein the first conductive path extends planarly within the electrically insulating layer.

10. 2. The method according to claim 1, further comprising providing a first via between said first test specimen terminal and said first conductive path.

11. 11. The method of claim 10, further comprising providing a second via between the island under test and the first conductive path.

12. 2. The method of claim 1, providing a test probe having a first probe tip of the first measurement terminal and a second probe tip of the second measurement terminal; contacting the first probe tip with the first test specimen terminal; and contacting the second probe tip with the second test specimen terminal;

13. A multilayer specimen for measuring electrical properties of the multilayer specimen, an electrical insulating layer; a test island located above the electrical insulating layer, having a function of a magnetoresistive random access memory, and constituting an MTJ stack; a first test specimen terminal above the electrical insulating layer for a first connection to a measurement circuit; a second test specimen terminal for a second connection with the measurement circuit and above the electrical insulating layer; Equipped with the first test specimen terminal, the second test specimen terminal, and the test island each have a first layer, a second layer, and one tunneling barrier, and are provided as islands protruding from the electrical insulating layer and spaced apart from each other by etching a stack including the first layer, the second layer, and the one tunneling barrier around them; Furthermore, a first conductive path embedded in the electrical insulating layer, the first conductive path electrically interconnecting the first test specimen terminal and the test island; a second conductive path embedded in the electrical insulating layer, interconnecting the second test specimen terminal and the test island such that the first and second conductive paths cooperate with the test island to form a circuit for measuring the electrical characteristic between the first test specimen terminal and the second test specimen terminal; A multi-layered test specimen comprising:

Images