Gate drive circuit

Abstract

A gate drive circuit (201) includes: a PNP transistor (Q1) having an emitter connected to a gate of a driven transistor (Q) and a collector connected to a ground application terminal; a capacitor (C1) having a first end connected to a base of the PNP transistor and a second end connected to the ground application terminal; a base-emitter resistor (R1) having a first end connected to the emitter of the PNP transistor and a second end connected to the base of the PNP transistor; an electric charge supplying portion (201A) configured to be capable of supplying electric charge to the gate of the driven transistor; an electric charge extracting portion (201B) configured to be capable of extracting electric charge from the gate of the driven transistor; a charging portion (201C) configured to be capable of charging the capacitor when electric charge is supplied to the driven transistor by the electric charge supplying portion; and a discharging portion (201D) configured to be capable of discharging the capacitor when electric charge is extracted from the gate of the driven transistor by the electric charge extracting portion.

Description

[Technical Field]

[0001] The present disclosure relates to gate drive circuits. [Background technology]

[0002] Conventionally, gate drive circuits that drive the gate of a transistor to be driven are known to have a Miller clamp function (see, for example, Patent Document 1). In the Miller clamp function, a Miller clamp transistor is provided that is connected to the gate of the transistor to be driven. By turning on the Miller clamp transistor when the transistor to be driven is in an off state, it becomes possible to extract charge from the gate of the transistor to be driven via the Miller clamp transistor. This makes it possible to prevent the gate voltage of the transistor to be driven from rising, thereby preventing the transistor to be driven from being turned on erroneously (false on). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2012-257421 Summary of the Invention [Problem to be solved by the invention]

[0004] However, when a Miller clamp transistor is built into an IC package as in Patent Document 1, the IC package is relatively large, and therefore the length of the wiring outside the IC package for connecting the Miller clamp transistor to the gate of the driven transistor becomes long. This increases the impedance of the wiring, and there is a risk that when the gate voltage of the driven transistor in the off state increases, the effect of the Miller clamp transistor in suppressing the increase in gate voltage will be reduced.

[0005] An object of the present disclosure is to provide a gate drive circuit that can improve the effect of suppressing erroneous turn-on of a driven transistor. [Means for solving the problem]

[0006] The gate drive circuit according to the present disclosure comprises: a PNP transistor having an emitter connected to the gate of the driven transistor and a collector connected to the application terminal of ground; a capacitor having a first end connected to the base of the PNP transistor and a second end connected to the application end of the ground; a base-emitter resistor having a first end connected to the emitter of the PNP transistor and a second end connected to the base of the PNP transistor; a charge supply unit configured to be able to supply charge to the gate of the transistor to be driven; a charge extraction unit configured to extract charges from the gate of the transistor to be driven; a charging unit configured to charge the capacitor when the charge supply unit supplies charge to the gate of the transistor to be driven; a discharge unit configured to discharge the capacitor when the charge extraction unit extracts charge from the gate of the transistor to be driven; The configuration has the following. [Effects of the Invention]

[0007] The gate drive circuit according to the present disclosure can improve the effect of suppressing erroneous turn-on of the driven transistor. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a diagram illustrating an example of a transistor driving system. [Figure 2] FIG. 2 is a diagram showing the configuration of a gate drive circuit according to a comparative example. [Figure 3]FIG. 3 is a diagram showing the configuration of the gate drive circuit according to the first embodiment. [Figure 4A] FIG. 4A is a diagram showing an operation when an NMOS transistor is turned on in the first embodiment. [Figure 4B] FIG. 4B is a diagram showing an operation when the NMOS transistor is turned off in the first embodiment. [Figure 5] FIG. 5 is a diagram showing the configuration of a transistor driving system used in the simulation. [Figure 6A] FIG. 6A is a diagram showing an example of a signal waveform obtained as a result of a simulation. [Figure 6B] FIG. 6B is a diagram showing an example of a signal waveform obtained as a result of the simulation. [Figure 7] FIG. 7 is a diagram showing the configuration of a gate drive circuit according to the second embodiment. [Figure 8] FIG. 8 is a diagram showing the operation when the NMOS transistor is turned on in the second embodiment. [Figure 9] FIG. 9 is a diagram showing the configuration of a gate drive circuit according to the third embodiment. [Figure 10A] FIG. 10A is a diagram showing an operation when an NMOS transistor is turned on in the third embodiment. [Figure 10B] FIG. 10B is a diagram showing an operation when the NMOS transistor is turned off in the third embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] Exemplary embodiments of the present disclosure will now be described with reference to the drawings.

[0010] <1. Transistor drive system> Figure 1 shows an example of a transistor driving system. The transistor driving system 100 shown in Figure 1 includes a high-side transistor QH and a low-side transistor QL, which are transistors to be driven, a high-side gate driving circuit GH, and a low-side gate driving circuit GL. The high-side gate driving circuit GH drives the gate of the high-side transistor QH. The low-side gate driving circuit GL drives the gate of the low-side transistor QL.

[0011] The high-side transistor QH and the low-side transistor QL are configured by NMOS transistors. The drain of the high-side transistor QH is connected to the application terminal of the power supply voltage HVdc. The power supply voltage HVdc is a DC voltage. The source of the high-side transistor QH is connected to the drain of the low-side transistor QL at node Nsw. The source of the low-side transistor QL is connected to the application terminal of the ground PGND. The power supply voltage HVdc is referenced to the ground PGND.

[0012] The high-side transistor QH and the low-side transistor QL are each, for example, a metal-oxide-semiconductor field-effect transistor (MOSFET) made of a semiconductor material such as SiC, GaN, Si, etc. Alternatively, for example, the high-side transistor QH and the low-side transistor QL may each be an insulated gate bipolar transistor (IGBT).

[0013] The high-side transistor QH and the low-side transistor QL are switched complementarily by the high-side gate drive circuit GH and the low-side gate drive circuit GL, respectively, so that a switching voltage Vsw is generated at the node Nsw.

[0014] The configurations of the high-side gate drive circuit GH and the low-side gate drive circuit GL will be described later.

[0015] <2. Comparative Example> Before describing the embodiments of the present disclosure, a comparative example will be described for comparison with the embodiments of the present disclosure. Figure 2 is a diagram showing the configuration of a gate drive circuit 20 according to the comparative example. As shown in Figure 2, the gate drive circuit 20 is a circuit for driving the gate of an NMOS transistor Q.

[0016] The NMOS transistor Q is the transistor to be driven and corresponds to either the high-side transistor QH or the low-side transistor QL shown in FIG. 1. That is, the gate drive circuit 20 corresponds to either the high-side gate drive circuit GH or the low-side gate drive circuit GL. Therefore, both the high-side gate drive circuit GH and the low-side gate drive circuit GL can have the same configuration as that shown in FIG. 2.

[0017] The gate drive circuit 20 includes a gate driver 10, a resistor R20, and a capacitor C20. The gate driver 10 is an IC package (semiconductor package) that integrates the internal configuration shown in Fig. 2. The resistor R20 and the capacitor C20 are each discrete elements that are externally attached to the gate driver 10.

[0018] The gate driver 10 has a primary side circuit 1, a secondary side circuit 2, and an isolation transformer 3. The gate driver 10 also has external terminals (lead terminals) for establishing electrical connection with the outside, namely, a GND1 terminal, a VCC1 terminal, an INA terminal, an INB terminal, a GND2 terminal, a VCC2 terminal, an OUT terminal, and an MC terminal.

[0019] The primary side circuit 1 has a first Schmitt trigger 11, a second Schmitt trigger 12, an AND circuit 13, a pulse generator 14, and a first UVLO (Under Voltage Lock Out) unit 15.

[0020] The secondary circuit 2 has a logic unit 21, a PMOS transistor 22, an NMOS transistor 23, a Miller clamp MOS transistor 24, a comparator 25, a second UVLO unit 26, and an OVP (overvoltage protection) unit 27.

[0021] The isolation transformer 3 is provided to connect the primary circuit 1 and the secondary circuit 2. The isolation transformer 3 transmits signals from the primary circuit 1 to the secondary circuit 2 while insulating the primary circuit 1 from the secondary circuit 2.

[0022] The first UVLO unit 15 monitors the power supply voltage Vcc1 applied to the VCC1 terminal, and shuts down the primary side circuit 1 when the power supply voltage Vcc1 falls below a predetermined voltage.

[0023] The first Schmitt trigger 11 transmits a first input signal In1 externally input to an INA terminal to a first input terminal of the AND circuit 13. The second Schmitt trigger 12 transmits a second input signal In2 externally input to an INB terminal to a second input terminal of the AND circuit 13.

[0024] The AND circuit 13 performs a logical AND operation on the signal level input to the first input terminal and the inverted level of the signal level input to the second input terminal. Therefore, when the first input signal In1 is low and the second input signal In2 is low, or when the first input signal In1 is low and the second input signal In2 is high, or when the first input signal In1 is high and the second input signal In2 is high, the output of the AND circuit 13 is low. When the first input signal In1 is high and the second input signal In2 is low, the output of the AND circuit 13 is high.

[0025] Triggered by the fall of the output of AND circuit 13 from high level to low level, pulse generator 14 generates a pulse having a narrower width than the output of AND circuit 13 and outputs it to the primary side of isolation transformer 3. A change in current due to the pulse supplied to the primary side of isolation transformer 3 generates a current on the secondary side of isolation transformer 3, which is supplied to logic unit 21. In this case, a high-level signal is output from logic unit 21 and input to the gate of PMOS transistor 22 and the gate of NMOS transistor 23.

[0026] Here, the PMOS transistor 22 and the NMOS transistor 23 are connected in series between the power supply voltage Vcc2 applied to the VCC2 terminal and the second ground GND2 applied to the GND2 terminal to form a switching arm. Specifically, the source of the PMOS transistor 22 is connected to the terminal to which the power supply voltage Vcc2 is applied. The drain of the PMOS transistor 22 is connected to the drain of the NMOS transistor 23 at a node N2. The source of the NMOS transistor 23 is connected to the terminal to which the second ground GND2 is applied.

[0027] A node N1, to which the gate of the PMOS transistor 22 and the gate of the NMOS transistor 23 are connected, is connected to the output terminal of the logic section 21.

[0028] The node N2 is connected to the OUT terminal. One end of a discharge resistor R20 is externally connected to the OUT terminal. The other end of the discharge resistor R20 is connected to the gate of an NMOS transistor Q. The source of the NMOS transistor Q is externally connected to the GND2 terminal. Note that the second ground GND2, which serves as the reference potential of the secondary circuit 2, is different from the first ground GND1, which is applied to the GND1 terminal and serves as the reference potential of the primary circuit 1.

[0029] Here, when a high-level signal is applied to node N1 from logic unit 21 as described above, PMOS transistor 22 is turned off, NMOS transistor 23 is turned on, and the voltage of the OUT terminal becomes second ground GND2 (low level), which turns NMOS transistor Q off.

[0030] Meanwhile, the pulse generator 14 is triggered by the rise of the output of the AND circuit 13 from low level to high level to generate a pulse narrower than the output of the AND circuit 13 and output it to the primary side of the isolation transformer 3. A change in current due to the pulse supplied to the primary side of the isolation transformer 3 generates a current on the secondary side of the isolation transformer 3, which is supplied to the logic unit 21. In this case, a low-level signal is output from the logic unit 21 and applied to node N1.

[0031] In this case, the PMOS transistor 22 is turned on, the NMOS transistor 23 is turned off, and the voltage at the OUT terminal becomes the power supply voltage Vcc2 (high level), which causes the NMOS transistor Q to be turned on.

[0032] The transistor to be driven by the gate driver 10 may be configured as an IGBT instead of the NMOS transistor Q. In this case, the other end of the resistor R20 is connected to the gate of the IGBT, and the GND2 terminal is connected to the emitter of the IGBT.

[0033] The second UVLO unit 26 monitors the power supply voltage Vcc2 applied to the VCC2 terminal, and when the power supply voltage Vcc2 falls below a predetermined voltage, shuts down the secondary-side circuit 2. The OVP unit 27 is a circuit that detects overvoltage of the power supply voltage Vcc2.

[0034] The mirror clamp MOS transistor 24 is an NMOS transistor for a mirror clamp function that can prevent the gate voltage of the NMOS transistor Q from rising and causing the NMOS transistor Q to be erroneously turned on when the NMOS transistor Q is in an off state.

[0035] In the high-side transistor QH and the low-side transistor QL (FIG. 1), when one of the driven transistors is turned on while the other is off, the gate voltage of the other driven transistor may rise. For example, if the low-side transistor QL is turned on while the high-side transistor QH is off, current flows toward the low-side transistor QL via the gate-drain parasitic capacitance of the high-side transistor QH, the NMOS transistor 23 of the gate driver 10 (FIG. 2), and the line to the second ground GND2. In this case, the gate voltage of the high-side transistor QH rises due to the parasitic inductance in the line to the second ground GND2. This rise in gate voltage may cause the high-side transistor QH to be falsely turned on. The same applies to false-on when the low-side transistor QL is off. The Miller clamp MOS transistor 24 of the gate driver 10 is provided to suppress such false-on of the driven transistor.

[0036] The drain of the Miller clamp MOS transistor 24 is connected to the MC terminal. The gate of the NMOS transistor Q is externally connected to the MC terminal. The source of the Miller clamp MOS transistor 24 is connected to the GND2 terminal. The gate of the Miller clamp MOS transistor 24 is driven by the logic unit 21.

[0037] The inverting input terminal (-) of the comparator 25 is connected to the MC terminal. The non-inverting input terminal (+) of the comparator 25 is connected to the terminal to which the reference voltage REF is applied. This allows the comparator 25 to compare the voltage of the MC terminal, i.e., the gate voltage of the NMOS transistor Q, with the reference voltage REF and output the comparison result to the logic unit 21.

[0038] To explain the operation of the Miller clamp function, when the signal output from the logic unit 21 to node N1 switches from low to high, the voltage at the OUT terminal switches from high to low. At this time, charge is extracted from the gate of NMOS transistor Q via resistor R20, causing the gate voltage of NMOS transistor Q to begin to drop, turning NMOS transistor Q off. When the gate voltage of NMOS transistor Q (i.e., the voltage at the MC terminal) falls below reference voltage REF, the output of comparator 25 switches to high. This causes the logic unit 21 to output a high signal to the gate of Miller clamp MOS transistor 24, turning it on. Therefore, even if the gate voltage of NMOS transistor Q, which is in the off state, attempts to rise, charge is extracted from the gate of NMOS transistor Q via Miller clamp MOS transistor 24, preventing the gate voltage of NMOS transistor Q from rising. This prevents erroneous turn-on of NMOS transistor Q.

[0039] When the logic unit 21 switches the voltage at the OUT terminal from low level to high level and turns on the NMOS transistor Q, the logic unit 21 turns off the Miller clamp MOS transistor 24.

[0040] However, in the gate drive circuit 20 according to this comparative example, the gate driver 10 incorporating the Miller clamp MOS transistor 24 is housed in a relatively large IC package, which requires a long wiring length connecting the MC terminal and the gate of the NMOS transistor Q. This increases the impedance of the wiring, which may reduce the effectiveness of the Miller clamp MOS transistor 24 in suppressing the rise in gate voltage when the gate voltage of the NMOS transistor Q tends to rise in the off state.

[0041] Furthermore, the gate drive circuit 20 according to the comparative example has a problem in that it is necessary to provide the gate driver 10 with a detection terminal (MC terminal) for detecting the gate voltage of the NMOS transistor Q.

[0042] 3. First Embodiment Here, a first embodiment of the present disclosure will be described.

[0043] <3-1. Gate drive circuit configuration> 3 is a diagram showing the configuration of a gate drive circuit 201 according to the first embodiment. The gate drive circuit 201 drives the gate of an NMOS transistor Q, which is a transistor to be driven. As in the comparative example described above, the NMOS transistor Q corresponds to either the high-side transistor QH or the low-side transistor QL shown in FIG. 1. Therefore, the gate drive circuit 201 corresponds to either the high-side gate drive circuit GH or the low-side gate drive circuit GL.

[0044] 3, the gate drive circuit 201 includes a gate driver 10, a PNP transistor Q1, a high-side NPN transistor Q2, a low-side PNP transistor Q3, a base-emitter resistor R1, a discharge resistor R2, an on-resistance Ron, an off-resistance Roff, a charging resistor R3, and a backflow prevention diode D1. The PNP transistor Q1, the high-side NPN transistor Q2, the low-side PNP transistor Q3, the base-emitter resistor R1, the discharge resistor R2, the on-resistance Ron, the off-resistance Roff, the charging resistor R3, and the backflow prevention diode D1 are each discrete elements external to the gate driver 10. The PNP transistor and NPN transistor are bipolar transistors.

[0045] The configuration of the gate driver 10 is the same as that of the comparative example described above. The collector of the high-side NPN transistor Q2 is connected to the terminal to which the power supply voltage Vcc2 is applied. The emitter of the high-side NPN transistor Q2 is connected to one end of the on-resistor Ron at a node N11. The other end of the on-resistor Ron is connected to the gate of the NMOS transistor Q.

[0046] The emitter of the low-side PNP transistor Q3 is connected to one end of the turn-off resistor Roff at a node N15. The other end of the turn-off resistor Roff is connected to the other end of the turn-on resistor Ron at a node N12. The collector of the low-side PNP transistor Q3 is connected to the GND2 terminal, i.e., the application terminal of the second ground GND2. The base of the high-side NPN transistor Q2 and the base of the low-side PNP transistor Q3 are commonly connected to the OUT terminal.

[0047] The PNP transistor Q1 is provided for the Miller clamp function. The emitter of the PNP transistor Q1 is connected to the gate of the NMOS transistor Q at a node N14. The collector of the PNP transistor Q1 is connected to the application terminal of the second ground GND2.

[0048] The base of PNP transistor Q1 is connected to one end of capacitor C1 at node N17. One end of base-emitter resistor R1 is connected to node N13. The other end of base-emitter resistor R1 is connected to node N17. One end of discharge resistor R2 is connected to node N17. The other end of discharge resistor R2 is connected to node N15.

[0049] One end of the charging resistor R3 is connected to the node N11. The other end of the charging resistor R3 is connected to the anode of the backflow prevention diode D1. The cathode of the backflow prevention diode D1 is connected to the node N17 and the node N16.

[0050] As shown in FIG. 3, the MC terminal of the gate driver 10 is not externally connected and is not used.

[0051] As described above, the gate drive circuit 201 according to this embodiment can be configured with resistors, capacitors, bipolar transistors, and diodes to form an external circuit for the gate driver 10, thereby reducing costs and footprint. Furthermore, the circuit configuration is not complicated. Furthermore, the use of a current-driven PNP transistor Q1 as the Miller clamp transistor makes the circuit more resistant to noise.

[0052] <3-2. Gate drive operation> The operation of driving the gate of the NMOS transistor Q by the gate drive circuit 201 configured as above will be described below.

[0053] Here, the gate drive circuit 201 has, as functional sections, a charge supply section 201A, a charge extraction section 201B, a charging section 201C, and a discharging section 201D.

[0054] The charge supply unit 201A has a high-side NPN transistor Q2 and an ON resistor Ron, and has the function of supplying charge to the gate of the NMOS transistor Q to turn the NMOS transistor Q on.

[0055] The charge extractor 201B has a low-side PNP transistor Q3 and an off resistor Roff, and has the function of extracting charge from the gate of the NMOS transistor Q to turn off the NMOS transistor Q.

[0056] The charging unit 201C has a high-side NPN transistor Q2, a charging resistor R3, and a backflow prevention diode D1, and has the function of charging the capacitor C1 when the charge supply unit 201A supplies charge to the gate of the NMOS transistor Q.

[0057] The discharge unit 201D has a low-side PNP transistor Q3 and a discharge resistor R2, and has the function of discharging the capacitor C1 when the charge extractor 201B extracts charge from the gate of the NMOS transistor Q.

[0058] First, the operation when turning on NMOS transistor Q will be described with reference to FIG. 4A. When gate driver 10 switches the voltage at the OUT terminal from low to high, high-side NPN transistor Q2 turns on and low-side PNP transistor Q3 turns off. As a result, as shown by the solid line in FIG. 4A, current flows from the application terminal of power supply voltage Vcc2 through high-side NPN transistor Q2 and on-resistor Ron to the gate of NMOS transistor Q. In other words, charge supply unit 201A supplies charge to the gate of NMOS transistor Q. Therefore, the gate voltage of NMOS transistor Q begins to rise, turning on NMOS transistor Q.

[0059] 4A, a current flows from the application terminal of the power supply voltage Vcc2 through the node N11, the charging resistor R3, and the backflow prevention diode D1 to the capacitor C1. That is, the charging unit 201C charges the capacitor C1.

[0060] The resistance of the on-resistor Ron is set to be larger than the resistance of the charging resistor R3. For example, Ron has a resistance three times that of R3. This allows the capacitor C1 to be charged quickly, rapidly increasing the base voltage of the PNP transistor Q1 and turning the PNP transistor Q1 off. This prevents the PNP transistor Q1 from turning on and causing a through current to flow through the PNP transistor Q1.

[0061] Next, the operation when turning off the NMOS transistor Q will be described with reference to FIG. 4B. When the gate driver 10 switches the voltage at the OUT terminal from high to low, the high-side NPN transistor Q2 turns off and the low-side PNP transistor Q3 turns on. As a result, as shown by the solid line in FIG. 4B, a current flows from the gate of the NMOS transistor Q through the off resistor Roff and the low-side PNP transistor Q3, and charge is extracted from the gate of the NMOS transistor Q. In other words, the charge extraction unit 201B extracts charge from the gate of the NMOS transistor Q. Therefore, the gate voltage of the NMOS transistor Q begins to decrease, and the NMOS transistor Q is turned off.

[0062] At this time, as shown by the dashed line in FIG. 4B, current flows from capacitor C1 through a path via discharge resistor R2 and low-side PNP transistor Q3. That is, discharge unit 201D discharges capacitor C1. At this time, the delay circuit consisting of discharge resistor R2 and capacitor C1 delays the drop in the base voltage of PNP transistor Q1. Therefore, PNP transistor Q1 is prevented from being turned on until the gate voltage of NMOS transistor Q has sufficiently dropped, thereby suppressing heat generation due to the current flowing through PNP transistor Q1. After PNP transistor Q1 is turned on, the drop in the gate voltage of NMOS transistor Q turns PNP transistor Q1 off. That is, when NMOS transistor Q is off, PNP transistor Q1 is off.

[0063] In addition, when capacitor C1 is discharged, backflow prevention diode D1 prevents charge from being supplied from capacitor C1 to the gate of NMOS transistor Q via node N16, charging resistor R3, node N11, and on-resistor Ron, which would otherwise hinder the turn-off of NMOS transistor Q.

[0064] <3-3. Miller clamp operation> Next, we will explain the Miller clamp operation performed by the gate drive circuit 201. If the gate voltage of NMOS transistor Q rises while NMOS transistor Q is off, the gate voltage is divided by base-emitter resistor R1 and discharge resistor R2, generating a voltage across base-emitter resistor R1. That is, the voltage generated across the base-emitter of PNP transistor Q1 generates a base current flowing from the emitter to the base of PNP transistor Q1, turning on PNP transistor Q1. As a result, charge is extracted from the gate of NMOS transistor Q via PNP transistor Q1, preventing the gate voltage of NMOS transistor Q from rising. This prevents erroneous turning on of NMOS transistor Q.

[0065] As described above, in this embodiment, the PNP transistor Q1 is used as the Miller clamp transistor. Because a small IC package can be used for the PNP transistor Q1, the PNP transistor Q1 can be placed as close as possible to the NMOS transistor Q. This shortens the length of the wiring connecting the gates of the PNP transistor Q1 and the NMOS transistor Q, improving the effect of suppressing an increase in the gate voltage of the NMOS transistor Q. In other words, the effect of suppressing erroneous turn-on of the NMOS transistor Q is improved.

[0066] 3, the MC terminal of the gate driver 10 is not used, so it is possible to use a gate driver that does not have a detection terminal for detecting the gate voltage of the NMOS transistor Q.

[0067] <3-4. Operation Simulation> Here, a simulation performed to verify the effectiveness of this embodiment will be described. FIG. 5 shows the configuration of a transistor drive system that was the subject of the simulation. The configuration shown in FIG. 5 is the same as the configuration shown in FIG. 1, except that a constant current source IC is placed between the drain and source of the high-side transistor QH. Furthermore, each of the high-side gate drive circuit GH and the low-side gate drive circuit GL shown in FIG. 5 includes a circuit with a configuration similar to that of the circuit externally attached to the gate driver 10 shown in FIG. 3.

[0068] The signal waveforms resulting from the simulation are shown in Figures 6A and 6B. From the top to bottom, both Figures 6A and 6B show the waveforms of the drain current ID_L flowing through the low-side transistor QL, the drain-source voltage VDS_L of the low-side transistor QL, the gate-source voltage VGS_H of the high-side transistor QH, and the gate-source voltage VGS_L of the low-side transistor QL. In Figures 6A and 6B, the solid lines show the simulation results using the circuit of this embodiment (i.e., with a Miller clamp function), and the dashed lines show the simulation results without the Miller clamp function.

[0069] In FIG. 6A, after a dead time DT during which both the high-side transistor QH and the low-side transistor QL are off, the gate-source voltage VDS_L of the low-side transistor QL rises, turning on the low-side transistor QL. At this time, as can be seen by comparing the solid line and dashed line of the gate-source voltage VGS_H of the high-side transistor QH in FIG. 6A, this embodiment successfully suppresses the rise in the gate-source voltage VGS_H. This indicates that the Miller clamp function of the PNP transistor Q1 is functioning effectively. As a result, as shown in FIG. 6A, the rise in the drain current ID_L flowing through the low-side transistor QL during the rising edge is suppressed.

[0070] 6B shows how charge extraction unit 201B extracts charge from the gate of low-side transistor QL, causing the gate-source voltage VGS_L of low-side transistor QL to drop and turn off low-side transistor QL. At this time, capacitor C1 is discharged by discharge unit 201D, but the delay caused by capacitor C1 and discharge resistor R2 keeps PNP transistor Q1 off, preventing a short circuit between the gate-source voltage VGS_L and ground PGND. In other words, heat generation by PNP transistor Q1 is suppressed.

[0071] <3-5. Determining circuit constants> An example of a method for designing circuit constants in the circuit configuration according to this embodiment shown in Fig. 3 will be described below. The circuit constants are determined in the order of C1 → R2 → R3 → R1.

[0072] First, C1 is determined. For example, C1 is determined so as to satisfy the following formula (1). C1 <Cgs / 10 (1) Note that Cgs is the parasitic capacitance between the gate and source of the NMOS transistor Q.

[0073] Next, regarding C1 and R2 that constitute a circuit that delays the turn-on of the PNP transistor Q1 when the NMOS transistor Q is turned off, R2 is determined so as to satisfy the following formula (2). Roff×Cgs≦R2×C1 (2)

[0074] Next, R3 is determined so as to satisfy the following equation (3) in order to quickly charge the capacitor C1 and turn off the PNP transistor Q1 when the NMOS transistor Q is turned on. Ron×Cgs>R3×C1 (3)

[0075] Next, when the gate voltage of the NMOS transistor Q in the off state tries to rise, R1 is determined so as to satisfy the following equation (4) in order to ensure the base-emitter voltage of the PNP transistor Q1 and turn on the PNP transistor Q1. R1>100×R2 (4)

[0076] 4. Second Embodiment Next, a second embodiment of the present disclosure will be described. Fig. 7 is a diagram showing the configuration of a gate drive circuit 202 according to the second embodiment. The gate drive circuit 202 shown in Fig. 7 differs from the first embodiment (Fig. 3) in that it does not include a charging resistor R3 and a backflow prevention diode D1, but instead includes an emitter-connected diode D2.

[0077] More specifically, the anode of the emitter-connected diode D2 is connected to the emitter of the high-side NPN transistor Q2. The cathode of the emitter-connected diode D2 is connected to the emitter of the low-side PNP transistor Q3. In this gate drive circuit 202, unlike the first embodiment, the charging unit 201C includes a high-side NPN transistor Q2, an emitter-connected diode D2, and a charge / discharge resistor R2. The emitter-connected diode D2 also functions as a backflow prevention diode.

[0078] Here, the operation of the NMOS transistor Q in the gate drive circuit 202 when it is turned on will be described with reference to FIG. 8. When the voltage at the OUT terminal switches from low to high, the high-side NPN transistor Q2 is turned on and the low-side PNP transistor Q3 is turned off. As a result, as in the first embodiment, charge is supplied to the gate of the NMOS transistor Q by the charge supply unit 201A, as shown by the solid line in FIG.

[0079] At this time, current flows into capacitor C1 from the application terminal of power supply voltage Vcc2 via high-side NPN transistor Q2, emitter-connected diode D2, and charge / discharge resistor R2, as shown by the dashed line in Fig. 8. That is, charging unit 201C has high-side NPN transistor Q2, emitter-connected diode D2, and charge / discharge resistor R2, and capacitor C1 is charged by charging unit 201C.

[0080] Furthermore, when the NMOS transistor Q is turned off, the capacitor C1 is discharged by the discharge unit 201D, as in the first embodiment. That is, in the second embodiment, both charging and discharging of the capacitor C1 are performed via the common charge / discharge resistor R2. Therefore, the first embodiment has separate resistors R3 and R2 for charging and discharging, making it easier to design the resistance values. However, the second embodiment has a reduced number of components because it only requires the emitter-connected diode D2 instead of the charging resistor R3 and the backflow prevention diode D1.

[0081] 5. Third Embodiment Next, a third embodiment of the present disclosure will be described. Fig. 9 is a diagram showing the configuration of a gate drive circuit 203 according to the third embodiment.

[0082] The gate drive circuit 203 shown in Figure 9 includes a gate driver Dr, an on / off resistor R11, a base-emitter resistor R12, a charging resistor R13, a backflow prevention diode D11, a capacitor C11, and a PNP transistor Q1. The gate driver Dr is an IC package and includes a high-side NPN transistor Q4 and a low-side PNP transistor Q5. The gate driver Dr also has external terminals: a VCC2 terminal, an OUT terminal, and a GND2 terminal. The resistors R11 to R13, the backflow prevention diode D11, the capacitor C11, and the PNP transistor Q1 are each discrete elements externally attached to the gate driver Dr.

[0083] The collector of the high-side NPN transistor Q4 is connected to the VCC2 terminal. The VCC2 terminal is connected to the terminal to which the power supply voltage Vcc2 is applied. The emitter of the high-side NPN transistor Q4 is connected to the emitter of the low-side PNP transistor Q5 at node N20. The collector of the low-side PNP transistor Q5 is connected to the GND2 terminal.

[0084] The base-emitter resistor R12, the capacitor C11, and the PNP transistor Q1 shown in FIG. 9 correspond to the base-emitter resistor R1, the capacitor C1, and the PNP transistor Q1 shown in FIG. 3, respectively.

[0085] The node N20 is connected to the OUT terminal, which is connected to one end of an on / off resistor R11 at a node N21. The other end of the on / off resistor R11 is connected to one end of a base-emitter resistor R12 at a node N22 and to the emitter of a PNP transistor Q1 at a node N23.

[0086] One end of the charging resistor R13 is connected to a node N21. The other end of the charging resistor R13 is connected to the anode of a backflow prevention diode D11. The cathode of the backflow prevention diode D11 is connected to a node N24 at which the other end of the base-emitter resistor R12 and one end of the capacitor C11 are connected.

[0087] 10A and 10B, the operation of the gate drive circuit 203 having such a configuration will be described. Here, the gate drive circuit 203 has a charge supply unit 203A, a charge extraction unit 203B, a charging unit 203C, and a discharging unit 203D.

[0088] The charge supply unit 203A has a high-side NPN transistor Q4 and an on / off resistor R11. The charge extraction unit 203B has a low-side PNP transistor Q5 and an on / off resistor R11. The charging unit 203C has a high-side NPN transistor Q4, a charging resistor R13, and a backflow prevention diode D11. The discharging unit 203D has a base-emitter resistor R12, an on / off resistor R11, and a low-side PNP transistor Q5.

[0089] In the gate driver Dr, when the base signal B applied to the bases of the high-side NPN transistor Q4 and the low-side PNP transistor Q5 is switched from low to high, the high-side NPN transistor Q4 is turned on and the low-side PNP transistor Q5 is turned off. As a result, as shown by the solid line in FIG. 10A, current flows from the power supply voltage Vcc2 application terminal through the high-side NPN transistor Q4 and the on / off resistor R11 to the gate of the NMOS transistor Q. In other words, charge is supplied to the gate of the NMOS transistor Q by the charge supply unit 203A. This turns on the NMOS transistor Q.

[0090] 10A, charge is supplied to capacitor C11 from the application terminal of power supply voltage Vcc2 via high-side NPN transistor Q4, charging resistor R13, and backflow prevention diode D11. That is, capacitor C11 is charged by charging unit 203C.

[0091] Furthermore, when base signal B is switched from high to low, high-side NPN transistor Q4 is turned off and low-side PNP transistor Q5 is turned on. As a result, as shown by the solid line in FIG. 10B, charge is extracted from the gate of NMOS transistor Q via on / off resistor R11 and low-side PNP transistor Q5. That is, charge is extracted from the gate of NMOS transistor Q by charge extraction unit 203B. As a result, NMOS transistor Q is turned off.

[0092] 10B, charge is extracted from capacitor C11 via base-emitter resistor R12, on / off resistor R11, and low-side PNP transistor Q5. That is, capacitor C11 is discharged by discharge unit 203D, and the combined resistance of base-emitter resistor R12 and on / off resistor R11 functions as a discharge resistor.

[0093] As described above, the third embodiment makes it possible to use a gate driver Dr including a high-side NPN transistor Q4 and a low-side PNP transistor Q5 whose emitters are commonly connected at node N20. However, in the third embodiment, current flows through the path passing through the on / off resistor R11 both when the NMOS transistor Q is turned on and when it is turned off. In contrast, the first and second embodiments (FIGS. 3 and 7) use a high-side NPN transistor Q2 and a low-side PNP transistor Q3 whose emitters are not commonly connected, so that current flows through the path passing through the on resistor Ron when turned on and through the off resistor Roff when turned off. Therefore, the first and second embodiments make it easier to design the resistance values.

[0094] <6. Notes> As described above, for example, a gate drive circuit (201) according to one embodiment of the present disclosure includes a PNP transistor (Q1) having an emitter connected to the gate of a driven transistor (Q) and a collector connected to a ground application terminal; a capacitor (C1) having a first end connected to the base of the PNP transistor and a second end connected to the application end of the ground; a base-emitter resistor (R1) having a first end connected to the emitter of the PNP transistor and a second end connected to the base of the PNP transistor; a charge supply unit (201A) configured to be able to supply charge to the gate of the transistor to be driven; a charge extraction section (201B) configured to be able to extract charges from the gate of the transistor to be driven; a charging unit (201C) configured to be able to charge the capacitor when the charge supply unit supplies charge to the gate of the transistor to be driven; and a discharge section (201D) configured to be able to discharge the capacitor when the charge extraction section extracts charge from the gate of the transistor to be driven (first configuration).

[0095] In addition, in the first configuration, the charge supply unit (201A) may have an on-resistor (Ron) arranged in a path for supplying charge, and the charging unit (201C) may have a charging resistor (R3) arranged in a path for charging, and the charging resistor may have a resistance value smaller than that of the on-resistor (second configuration).

[0096] In the second configuration, the resistance value R3 of the charging resistor may satisfy the following formula (third configuration). Ron×Cgs>R3×C1 where Ron is the resistance value of the on-resistor, C1 is the capacitance value of the capacitor, and Cgs is the capacitance value of the parasitic capacitance between the gate and source of the transistor to be driven.

[0097] In the second or third configuration, the charging section (201C) may have a backflow prevention diode (D1) arranged in a path along which charging is performed (fourth configuration).

[0098] In any of the first to fourth configurations, the discharge section (201D) may have a discharge resistor (R2) arranged in a path along which discharge occurs (fifth configuration).

[0099] In addition, in the fifth configuration, the charge extraction section (201B) may have an off resistor (Roff) arranged in a path for extracting charge, and the resistance value R2 of the discharge resistor may be configured to satisfy the following formula (sixth configuration). Roff×Cgs≦R2×C1 where Roff is the resistance value of the off resistor, C1 is the capacitance value of the capacitor, and Cgs is the capacitance value of the parasitic capacitance between the gate and source of the transistor to be driven.

[0100] In the fifth or sixth configuration, the resistance value R1 of the base-emitter resistor (R1) may satisfy the following formula (seventh configuration). R1>100×R2 where R2 is the resistance value of the discharge resistor

[0101] In any of the first to seventh configurations, the capacitance value C1 of the capacitor (C1) may satisfy the following formula (eighth configuration). C1 <Cgs / 10 where Cgs is the capacitance value of the parasitic capacitance between the gate and source of the transistor to be driven.

[0102] In any one of the first to eighth configurations, a high-side NPN transistor (Q2) having a collector connected to an application terminal of a power supply voltage (Vcc2); an on-resistor (Ron) having a first end connected to the emitter of the high-side NPN transistor and a second end connected to the gate of the driven transistor; a low-side PNP transistor (Q3) having a collector connected to the ground application terminal; a turn-off resistor (Roff) having a first end connected to the emitter of the low-side PNP transistor and a second end connected to the gate of the driven transistor; and The on-resistor and the off-resistor may be separate (ninth configuration).

[0103] In the ninth configuration, the charging unit (201C) includes a charging resistor (R3) having a first terminal connected to a first node (N11) to which the emitter of the high-side NPN transistor (Q2) and a first terminal of the on-resistor are connected, and a second terminal connected to a first terminal of the capacitor (C1), The discharge unit (201D) may be configured to include a discharge resistor (R2) having a first terminal connected to a second node (N15) to which the emitter of the low-side PNP transistor (Q3) and the first terminal of the off resistor (Roff) are connected, and a second terminal connected to the first terminal of the capacitor (tenth configuration).

[0104] In addition, in the above-mentioned tenth configuration, the charging unit (201C) may be configured to have a backflow prevention diode (D1) arranged between the first node (N11) and the first end of the capacitor (C1) (eleventh configuration).

[0105] In the ninth configuration, an emitter-connected diode (D2) having an anode connected to the emitter of the high-side NPN transistor (Q2) and a cathode connected to the emitter of the low-side PNP transistor (Q3); A charging / discharging resistor (R2) having a first end connected to a third node to which the emitter of the low-side PNP transistor and the first end of the off resistor (Roff) are connected, and a second end connected to the first end of the capacitor (C1) may be configured (twelfth configuration).

[0106] In any one of the first to eighth configurations, a high-side NPN transistor (Q4) having a collector connected to an application terminal of a power supply voltage (Vcc2); a low-side PNP transistor (Q5) having a collector connected to the ground application terminal; an on / off resistor (R11) having a first end connected to a fourth node (N20) to which the emitter of the high-side NPN transistor and the emitter of the low-side PNP transistor are connected, and a second end connected to the gate of the driven transistor (Q); and The charging unit (203C) includes a charging resistor (R13) having a first terminal connected to a fifth node (N21) to which the fourth node and a first terminal of the on / off resistor are connected, and a second terminal connected to a first terminal of the capacitor (C11); The discharge section (203D) may have a configuration including the base-emitter resistor (R12) and the on / off resistor (thirteenth configuration).

[0107] In addition, in the thirteenth configuration, the charging unit (203C) may be configured to have a backflow prevention diode (D11) arranged between the fifth node (N21) and the first end of the capacitor (C11) (fourteenth configuration).

[0108] Furthermore, in any of the first to fourteenth configurations, a configuration may be adopted in which a gate driver (10) configured to be able to drive the charge supply unit (201A), the charge extraction unit (201B), the charging unit (201C), and the discharging unit (201D) is provided (a fifteenth configuration).

[0109] In the fifteenth configuration, the gate driver (10) may not have a detection terminal for detecting the gate voltage of the transistor (Q) to be driven (sixteenth configuration).

[0110] A transistor driving system (100) according to an embodiment of the present disclosure includes a high-side transistor (QH) and a low-side transistor (QL), which are transistors to be driven, and a gate drive circuit (201) having any one of the first to sixteenth configurations, which is a separate circuit configured to be able to drive the gate of the high-side transistor and the gate of the low-side transistor, respectively. [Industrial Applicability]

[0111] The present disclosure can be used, for example, to drive the gate of a MOS transistor or the like. [Explanation of symbols]

[0112] 1 Primary side circuit 2 Secondary circuit 3. Isolation transformer 10 Gate Drivers 11 First Schmitt trigger 12 Second Schmitt Trigger 13 AND Circuit 14 Pulse Generator 15 1st UVLO section 20 Gate drive circuit 21 Logic Section 22 PMOS transistors 23 NMOS transistor 24 Miller clamp MOS transistor 25 Comparator 26 2nd UVLO section 27 OVP section 100 Transistor Drive System 201~203 Gate drive circuit 201A Charge supply section 201B Charge extractor 201C charging part 201D Discharge section 203A Charge supply section 203B Charge extractor 203C charging part 203D Discharge section C1 capacitor C11 capacitor C20 capacitor D1 Reverse current prevention diode D11 Reverse current prevention diode D2 Emitter-connected diode Dr Gate driver GH High-side gate drive circuit GL Low-side gate drive circuit IC constant current source Q NMOS transistor Q1 PNP transistor Q2 High-side NPN transistor Q3 Low-side PNP transistor Q4 High-side NPN transistor Q5 Low-side PNP transistor QH High-side transistor QL low-side transistor R1 Base-emitter resistor R11 On / off resistor R12 Base-emitter resistor R13 Charging resistor R2 Discharge resistor R20 resistor R3 Charging resistor Roff Off resistor Ron ON resistance

Claims

1. a PNP transistor having an emitter connected to the gate of the driven transistor and a collector connected to a ground application terminal; a capacitor having a first end connected to the base of the PNP transistor and a second end connected to the ground application end; a base-emitter resistor having a first end connected to the emitter of the PNP transistor and a second end connected to the base of the PNP transistor; a high-side NPN transistor having a collector connected to an application terminal of a power supply voltage; an on-resistor having a first end connected to the emitter of the high-side NPN transistor and a second end connected to the gate of the driven transistor; a low-side PNP transistor having a collector connected to the ground application terminal; an off resistor having a first end connected to the emitter of the low-side PNP transistor and a second end connected to the gate of the driven transistor, the off resistor being separate from the on resistor; a discharge resistor connected between the first end of the capacitor and the emitter of the low-side PNP transistor; a charging resistor connected between the emitter of the high-side NPN transistor and a first end of the capacitor; a charge supply unit configured to be able to supply charge to the gate of the transistor to be driven; a charge extraction unit configured to extract charges from the gate of the transistor to be driven; a charging unit configured to charge the capacitor when the charge supply unit supplies charge to the gate of the transistor to be driven; a discharge unit configured to discharge the capacitor when the charge extraction unit extracts charge from the gate of the transistor to be driven; and the charge supply unit includes the high-side NPN transistor and the on-resistor, the charge extraction unit includes the low-side PNP transistor and the turn-off resistor, the charging unit includes the high-side NPN transistor and the charging resistor, the discharge unit includes the low-side PNP transistor and the discharge resistor, the discharge resistor also serves as a voltage dividing resistor that divides the gate voltage of the driven transistor together with the base-emitter resistor to generate a voltage across the base-emitter resistor.

2. The gate drive circuit according to claim 1 , wherein the charging resistor has a resistance smaller than that of the on-resistor.

3. 3. The gate drive circuit according to claim 1, wherein a resistance value R3 of the charging resistor satisfies the following formula: Ron × Cgs > R3 × C1 where Ron is the resistance value of the ON resistor, C1 is the capacitance value of the capacitor, and Cgs is the capacitance value of the parasitic capacitance between the gate and source of the transistor to be driven.

4. 4. The gate drive circuit according to claim 1, wherein the charging section includes a backflow prevention diode disposed in a path for charging.

5. 5. The gate drive circuit according to claim 1, wherein a resistance value R2 of the discharge resistor satisfies the following formula: Roff × Cgs ≦ R2 × C1 where Roff is the resistance value of the turn-off resistor, C1 is the capacitance value of the capacitor, and Cgs is the capacitance value of the parasitic capacitance between the gate and source of the transistor to be driven.

6. 6. The gate drive circuit according to claim 1, wherein a resistance value R1 of the base-emitter resistor satisfies the following formula: R1>100 x R2 where R2 is the resistance value of the discharge resistor

7. 7. The gate drive circuit according to claim 1, wherein a capacitance value C1 of the capacitor satisfies the following formula: C1<Cgs / 10 where Cgs is the capacitance value of the parasitic capacitance between the gate and source of the transistor to be driven.

8. a PNP transistor having an emitter connected to the gate of the driven transistor and a collector connected to a ground application terminal; a capacitor having a first end connected to the base of the PNP transistor and a second end connected to the ground application end; a base-emitter resistor having a first end connected to the emitter of the PNP transistor and a second end connected to the base of the PNP transistor; a high-side NPN transistor having a collector connected to an application terminal of a power supply voltage; an on-resistor having a first end connected to the emitter of the high-side NPN transistor and a second end connected to the gate of the driven transistor; a low-side PNP transistor having a collector connected to the ground application terminal; an off resistor having a first end connected to the emitter of the low-side PNP transistor and a second end connected to the gate of the driven transistor, the off resistor being separate from the on resistor; an emitter-connected diode having an anode connected to the emitter of the high-side NPN transistor and a cathode connected to the emitter of the low-side PNP transistor; a charge / discharge resistor having a first end connected to a node at which the emitter of the low-side PNP transistor and a first end of the turn-off resistor are connected, and a second end connected to a first end of the capacitor; a charge supply unit configured to be able to supply charge to the gate of the transistor to be driven; a charge extraction unit configured to extract charges from the gate of the transistor to be driven; a charging unit configured to charge the capacitor when the charge supply unit supplies charge to the gate of the transistor to be driven; a discharge unit configured to discharge the capacitor when the charge extraction unit extracts charge from the gate of the transistor to be driven; and the charge supply unit includes the high-side NPN transistor and the on-resistor, the charge extraction unit includes the low-side PNP transistor and the turn-off resistor, the charging unit includes the high-side NPN transistor, the emitter-connected diode, and the charging / discharging resistor; the discharge unit includes the low-side PNP transistor and the charge / discharge resistor, the charge / discharge resistor also serves as a voltage dividing resistor that divides the gate voltage of the driven transistor together with the base-emitter resistor to generate a voltage across the base-emitter resistor.

9. 9. The gate drive circuit according to claim 1, further comprising a gate driver configured to be able to drive the charge supply section, the charge extraction section, the charging section, and the discharging section.

10. 10. The gate drive circuit according to claim 9, wherein the gate driver does not have a detection terminal for detecting a gate voltage of a transistor to be driven.

11. a high-side transistor and a low-side transistor, which are transistors to be driven, the gate drive circuit according to any one of claims 1 to 10, which is a separate circuit configured to be able to drive the gate of the high-side transistor and the gate of the low-side transistor, respectively; A transistor drive system comprising:

12. a PNP transistor having an emitter connected to the gate of the driven transistor and a collector connected to a ground application terminal; a capacitor having a first end connected to the base of the PNP transistor and a second end connected to the ground application end; a base-emitter resistor having a first end connected to the emitter of the PNP transistor and a second end connected to the base of the PNP transistor; a high-side NPN transistor having a collector connected to an application terminal of a power supply voltage; an on-resistor having a first end connected to the emitter of the high-side NPN transistor and a second end connected to the gate of the driven transistor; a low-side PNP transistor having a collector connected to the ground application terminal; an off resistor having a first end connected to the emitter of the low-side PNP transistor and a second end connected to the gate of the driven transistor, the off resistor being separate from the on resistor; a discharge resistor connected between the first end of the capacitor and the emitter of the low-side PNP transistor; a charging resistor connected between the emitter of the high-side NPN transistor and a first end of the capacitor; a charge supply unit configured to be able to supply charge to the gate of the transistor to be driven; a charge extraction unit configured to extract charges from the gate of the transistor to be driven; a charging unit configured to charge the capacitor when the charge supply unit supplies charge to the gate of the transistor to be driven; a discharge unit configured to discharge the capacitor when the charge extraction unit extracts charge from the gate of the transistor to be driven; and the charge supply unit includes the high-side NPN transistor and the on-resistor, the charge extraction unit includes the low-side PNP transistor and the turn-off resistor, the charging unit includes the high-side NPN transistor and the charging resistor, the discharge unit includes the low-side PNP transistor and the discharge resistor, A gate drive circuit, wherein the resistance value R2 of the discharge resistor satisfies the following formula: Roff × Cgs ≦ R2 × C1 where Roff is the resistance value of the turn-off resistor, C1 is the capacitance value of the capacitor, and Cgs is the capacitance value of the parasitic capacitance between the gate and source of the transistor to be driven.

13. a PNP transistor having an emitter connected to the gate of the driven transistor and a collector connected to a ground application terminal; a capacitor having a first end connected to the base of the PNP transistor and a second end connected to the ground application end; a base-emitter resistor having a first end connected to the emitter of the PNP transistor and a second end connected to the base of the PNP transistor; a high-side NPN transistor having a collector connected to an application terminal of a power supply voltage; an on-resistor having a first end connected to the emitter of the high-side NPN transistor and a second end connected to the gate of the driven transistor; a low-side PNP transistor having a collector connected to the ground application terminal; an off resistor having a first end connected to the emitter of the low-side PNP transistor and a second end connected to the gate of the driven transistor, the off resistor being separate from the on resistor; a discharge resistor connected between the first end of the capacitor and the emitter of the low-side PNP transistor; a charging resistor connected between the emitter of the high-side NPN transistor and a first end of the capacitor; a charge supply unit configured to be able to supply charge to the gate of the transistor to be driven; a charge extraction unit configured to extract charges from the gate of the transistor to be driven; a charging unit configured to charge the capacitor when the charge supply unit supplies charge to the gate of the transistor to be driven; a discharge unit configured to discharge the capacitor when the charge extraction unit extracts charge from the gate of the transistor to be driven; and the charge supply unit includes the high-side NPN transistor and the on-resistor, the charge extraction unit includes the low-side PNP transistor and the turn-off resistor, the charging unit includes the high-side NPN transistor and the charging resistor, the discharge unit includes the low-side PNP transistor and the discharge resistor, A gate drive circuit, wherein the resistance value R1 of the base-emitter resistor satisfies the following formula: R1>100 x R2 where R2 is the resistance value of the discharge resistor

14. a PNP transistor having an emitter connected to the gate of the driven transistor and a collector connected to a ground application terminal; a capacitor having a first end connected to the base of the PNP transistor and a second end connected to the ground application end; a base-emitter resistor having a first end connected to the emitter of the PNP transistor and a second end connected to the base of the PNP transistor; a high-side NPN transistor having a collector connected to an application terminal of a power supply voltage; an on-resistor having a first end connected to the emitter of the high-side NPN transistor and a second end connected to the gate of the driven transistor; a low-side PNP transistor having a collector connected to the ground application terminal; an off resistor having a first end connected to the emitter of the low-side PNP transistor and a second end connected to the gate of the driven transistor, the off resistor being separate from the on resistor; a discharge resistor connected between the first end of the capacitor and the emitter of the low-side PNP transistor; a charging resistor connected between the emitter of the high-side NPN transistor and a first end of the capacitor; a charge supply unit configured to be able to supply charge to the gate of the transistor to be driven; a charge extraction unit configured to extract charges from the gate of the transistor to be driven; a charging unit configured to charge the capacitor when the charge supply unit supplies charge to the gate of the transistor to be driven; a discharge unit configured to discharge the capacitor when the charge extraction unit extracts charge from the gate of the transistor to be driven; and the charge supply unit includes the high-side NPN transistor and the on-resistor, the charge extraction unit includes the low-side PNP transistor and the turn-off resistor, the charging unit includes the high-side NPN transistor and the charging resistor, the discharge unit includes the low-side PNP transistor and the discharge resistor, A gate drive circuit, wherein the capacitance value C1 of the capacitor satisfies the following formula: C1<Cgs / 10 where Cgs is the capacitance value of the parasitic capacitance between the gate and source of the transistor to be driven.

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