Area shielding within a package of a microelectronic device

Abstract

The microelectronic device may include a substrate, a first chip mounted on the substrate, and a second chip mounted on the substrate. A plurality of pillars are disposed between the first chip and the second chip, with a first end of each pillar of the plurality of pillars located adjacent to the substrate. The spacing between the plurality of pillars is at least equal to a distance sufficient to block electromagnetic interference (EMI) and / or radio frequency interference (RFI) between the first chip and the second chip. The microelectronic device may further include a cover covering at least the first chip, the second chip, and the plurality of pillars, with a second end of each pillar of the plurality of pillars located adjacent to at least a trench disposed in the cover.

Description

[Background technology]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims priority to U.S. Patent Application No. 17 / 509,887, filed October 25, 2021, which is a non-provisional application under 35 U.S.C. § 119(e) of U.S. Provisional Patent Application No. 63 / 108,096, filed October 30, 2020, and claims priority to that U.S. Provisional Patent Application, both of which are incorporated by reference herein.

[0002] Microelectronic devices often contain numerous microelectronic elements, e.g., dies or chips. The microelectronic elements may be active or passive. The microelectronic elements need to be protected from electromagnetic interference (EMI) and / or radio frequency interference (RFI) that may be caused by other microelectronic elements within the microelectronic device.

[0003] One technique for providing EMI and / or RFI protection to microelectronic elements includes conductive traces disposed within a substrate of a microelectronic device package. Wires may extend from the conductive traces between the microelectronic elements and the conductive traces and / or the wires may be connected to ground. The wires may be arranged as a fence around individual microelectronic elements to isolate the microelectronic elements from other microelectronic elements for EMI and / or RFI shielding.

[0004] Another technique for providing EMI and / or RFI protection to microelectronic elements includes solid conductive walls that may be formed between and / or around individual microelectronic elements to isolate the microelectronic elements from other microelectronic elements for EMI and / or RFI shielding, which may be comprised of a conductive material that engages conductive traces in the substrate of the microelectronic device package to ground the conductive wall.

[0005] When using the first-mentioned technique, the "wire" technique can be time-consuming to produce a microelectronic device package. In addition, the wires can be fragile and thus can even bend and break easily. This adds significant cost and time to fabricating a microelectronic device. When using the second "wall" technique, the walls extend all the way to the conductive traces. Thus, when the microelectronic device is encapsulated, e.g., when a cover is formed, the encapsulation material cannot flow through the walls. This can cause unbalanced pressure during molding, which can ultimately result in encapsulation defects, such as voids, unfilled areas, etc. This also adds significant cost and time to fabricating a microelectronic device.

[0006] Furthermore, if the die is wire bonded onto the substrate, adding a wire fence at the same time may not be a problem for the overall manufacturing process, since the process involves the same wire bond process. However, if flip chip interconnects are used during the manufacturing process, switching to a wire bonder to stitch wires and provide EMI and / or RFI protection may create problems. For example, the need for a bonder for the flip chip process may require extra steps or tooling, since wire bonds may not otherwise be involved. Summary of the Invention

[0007] According to one aspect of the present invention, there is provided a microelectronic device comprising: a substrate; a first chip mounted on the substrate; and a plurality of pillars disposed between the first chip and the second chip, wherein a first end of each of the plurality of pillars is located adjacent to the substrate; a spacing between each of the plurality of pillars is equal to or less than a distance sufficient to block one or more of (i) electromagnetic interference (EMI) or (ii) radio frequency interference (RFI) between the first chip and the second chip; and a cover covering at least the first chip, the second chip, and the plurality of pillars, wherein a second end of each of the plurality of pillars is located adjacent to a trench disposed in at least the cover.

[0008] According to another aspect of the present invention, there is provided a microelectronic device having a substrate with a first region, a second region, and a third region located between the first and second regions, the substrate having (i) a surface and (ii) a ground plane, the microelectronic device including at least one first microelectronic element located on the surface of the first region, at least one second microelectronic element located on the surface of the second region, a conductive element exposed at a surface of the substrate in the third region and coupled to the ground plane, a plurality of conductive posts disposed in the third region, the conductive posts having (i) a first end coupled to the conductive element and (ii) a second end opposite the first end, and at least one conductive post extending from the surface of the substrate. and a conductive encapsulation layer filling spaces between some of the conductive posts, the some of the conductive posts being separated from one another by a dielectric encapsulation layer, the dielectric encapsulation layer having a first portion located at a first height above a surface overlying a first region of the substrate, a second portion located at a second height above a surface overlying a second region of the substrate, and a third portion located at a third height above a surface overlying a third region of the substrate, the third height being lower than the first height and the second height, and second ends of the plurality of conductive posts being located adjacent to at least the third portion, the microelectronic device further comprising a conductive material located within at least the third portion of the dielectric encapsulation layer.

[0009] According to another aspect of the invention, there is provided a method, the method including providing a substrate having a plurality of pillars and one of (i) a conductive trace or (ii) a plurality of conductive pads, wherein a first end of each pillar of the plurality of pillars is coupled to one of the (i) the conductive trace or (ii) a corresponding conductive pad of the plurality of conductive pads, the method further including attaching a first chip to the substrate adjacent a first side of the plurality of pillars and attaching a second chip to the substrate adjacent a second side of the plurality of pillars, the second side being opposite the first side, The method further includes the steps of providing a cover by applying an epoxy molding compound over at least the first chip, the second chip, and the plurality of pillars; forming a trench in the cover; and filling the trench with a conductive material, wherein a second end of each pillar of the plurality of pillars is located at least adjacent to the trench formed in the cover, and wherein a spacing between the plurality of pillars is at least equal to a distance sufficient to block one or more of (i) electromagnetic interference (EMI) or (ii) radio frequency interference (RFI) between the first chip and the chips in stage 2.

[0010] A detailed description is provided below with reference to the accompanying figures. In the figures, the left-most digit(s) of a reference number identifies the figure in which the reference number first appears. The use of the same reference number in different figures indicates similar or identical items. The systems shown in the accompanying figures are not drawn to scale, and components in the figures may be shown to scale differently. [Brief explanation of the drawings]

[0011] [Figure 1A] 1A-1C are diagrams illustrating an example of a microelectronic device during various stages of manufacture. [Figure 1B] 1A-1C are schematic diagrams illustrating an example of a microelectronic device during different stages of manufacture in various forms. [Figure 1C]1A-1C are schematic diagrams illustrating an example of a microelectronic device during different stages of manufacture in various forms. [Figure 1D] 1A-1C are schematic diagrams illustrating an example of a microelectronic device during different stages of manufacture in various forms. [Figure 1E] 1A-1C are schematic diagrams illustrating an example of a microelectronic device during different stages of manufacture in various forms. [Figure 1F] 1A-1C are schematic diagrams illustrating an example of a microelectronic device during different stages of manufacture in various forms. [Figure 2] 1A-1F are flow diagrams of exemplary methods for fabricating microelectronic devices, such as the microelectronic devices of FIGS. 1A-1F, in accordance with various aspects. DETAILED DESCRIPTION OF THE INVENTION

[0012] Overview

[0013] This disclosure relates to an exemplary technique for shielding regions of a microelectronic device package (or the entire package) from EMI and / or RFI, where these regions contain microelectronic elements. Such a technique provides a plurality of pillars of conductive material that are coupled to exposed conductive traces in a substrate of the microelectronic device. The conductive pillars separate a first die from a second die to provide EMI and / or RFI shielding between the two dies.

[0014] According to various embodiments, a microelectronic device may include a substrate. The substrate may have conductive elements in the form of conductive traces of a conductive material exposed within a surface of the substrate, the conductive traces being in contact with a ground plane. In various embodiments, the substrate may have conductive elements in the form of a row of pads (instead of conductive traces) of a conductive material exposed within a surface of the substrate, the row of pads being in contact with a ground plane. In various embodiments, the ground plane may be replaced by one or more ground vias. Pillars or posts may extend linearly in a row from the conductive trace (or row of pads), with a first end of each pillar located adjacent to the substrate and in contact with the conductive trace. In various embodiments, the first ends of the pillars may be integral with the conductive trace (or pads in the row of pads). The pillars may be made of a conductive material. In various embodiments, the conductive material of the pillars is the same as the conductive material of the conductive trace (or row of pads). In another embodiment, the conductive material of the pillar and the conductive trace (or column pad) are different conductive materials, whereby the pillar is grounded by the conductive trace.

[0015] One or more microelectronic elements, e.g., dies or chips, may be disposed on each side of the pillar. For example, a first die may be disposed on a first side of a row of pillars, and a second die may be disposed on an opposite side of the row of pillars. The dies may be bonded to the substrate by a wire bonding process or may be flip-chip attached to the substrate. In various embodiments, the pillars may be disposed such that they surround or at least substantially surround the die. For example, pillars may be disposed around the first die and pillars may be disposed around the second die. In various embodiments, three or more dies may be provided in the microelectronic device.

[0016] After the die is attached to the substrate, an encapsulation step may be performed to provide a cover for the microelectronic device. The encapsulation step may include encapsulating a component including the first and second die or molding such a component onto the substrate. Due to the spacing between the pillars, molding material can flow between the pillars and around the component on the substrate. Thus, the component including the pillars on the substrate is encapsulated during the encapsulation process.

[0017] In some embodiments, after encapsulation, a trench may be provided in the cover of the microelectronic device, for example, by forming the trench in the cover using a saw, laser, water jet, etc. In other embodiments, fins may be utilized during the encapsulation step, in which case the fins may be removed after the encapsulation step, thereby forming the trench.

[0018] After forming the trench, the trench may be filled with a conductive material, and a coating or layer of the conductive material may be applied to at least the top surface of the cover, e.g., the outer surface of the cover. In some embodiments, the coating or layer of the conductive material may extend over the sides of the cover. In some embodiments, the conductive material in the trench and the conductive coating on the top and possibly the sides of the cover are the same material. In other embodiments, the conductive material in the trench and the conductive coating on the top and possibly the sides of the cover are different conductive materials.

[0019] In embodiments, the conductive material in the trench can extend to the second end of each pillar to provide flexible-in-package-shielding (FIPS), e.g., the second end is located opposite (away from) the first end of each pillar that engages the conductive trace. In some embodiments, the conductive material in the trench, e.g., a bottom surface of the conductive material, can engage one or more of the tops, e.g., the second ends, of the pillars. In other embodiments, the conductive material in the trench, e.g., a bottom surface of the conductive material, can not engage the tops, e.g., the second ends, of one or more of the pillars.

[0020] Thus, the conductive material in the pillars and trenches provides EMI and / or RFI protection between dies located on opposite sides of the column pillars. In various embodiments, the spacing between the pillars is at least equal to a distance sufficient to block electromagnetic interference between two dies, e.g., a first die located on one side of the column pillar and a second die located on the opposite side of the column pillar. In various embodiments, the spacing between the pillars is less than a distance sufficient to block electromagnetic interference between the first and second dies, i.e., the spacing between the pillars is less than the maximum distance that enables the pillars to block electromagnetic interference between the first and second dies. In various embodiments, the spacing between the pillars may be in the range of 5 micrometers to 50 micrometers. Additionally, in various embodiments, the spacing between the first and second dies is in the range of 100 microns to 2000 microns. Also, in various embodiments, the column pillars are integral with, e.g., part of, the conductive traces. In other embodiments, the pillars are formed on, eg, coupled to, the conductive traces.

[0021] In various embodiments, the conductive traces and columnar pillars may be formed during the substrate formation process. Thus, a substrate may be provided by a substrate manufacturer with pre-formed conductive traces and pre-formed pillars. Die bonding (and other component placement) and encapsulation processes may then be performed on such a provided substrate.

[0022] Utilizing the techniques provided herein in manufacturing microelectronic devices reduces processing time when forming trenches because the trenches do not extend as deeply into the cover of prior art microelectronic devices, resulting in cost savings. Additionally, in some embodiments, the trenches may not be filled with a separate conductive filler. Instead, a conductive paint on the trenches can be utilized. Additionally, the techniques provided herein provide better shielding protection to the top of the package cover than spaced wires.

[0023] Additionally, the trench does not extend all the way to the substrate, thereby not exposing the substrate, which can result in improved reliability of the microelectronic device and reduced moisture ingress. Furthermore, because the trench does not extend all the way to the substrate, the microelectronic device can have higher mechanical robustness, resulting in less cracking of the packaging / thin substrate, which is typically caused by bending.

[0024] Also, in embodiments, the pillars can be formed using established circuit board batch processes, resulting in time and cost savings. Furthermore, using the techniques described herein, wire stitching is eliminated and the pillars are physically more stable than wires, resulting in higher assembly yields and additional cost savings.

[0025] Additionally, the techniques described herein provide flexible trench fabrication shapes and placement locations for flexible-in-package shielding (FIPS). For example, pillars and trenches do not necessarily need to be straight, but rather only need to be shaped and / or placed to provide EMI and RFI shielding between microelectronic elements. Thus, the microelectronic device has flexibility in terms of internal die / passive-to-die / passive shielding against EMI and / or RFI, as well as external shielding from other components. Therefore, the package design and layout of the microelectronic device can dictate the placement of pillars and trenches. Additionally, utilizing a fin process during fabrication of the encapsulant cover can limit excess trench fabrication, such as cutting through the encapsulant to create the trenches, thereby saving time and / or materials.

[0026] FIG. 1A schematically illustrates a substrate 102 for a microelectronic device 100. The substrate 102 may have conductive traces 104 made of a conductive material exposed within the surface of the substrate 102, with the conductive traces 104 in contact with a ground plane (not shown) of the substrate 102. In various embodiments, the conductive traces 104 may be replaced by an array of conductive pads (not shown) made of a conductive material exposed within the surface of the substrate 102, with the array of conductive pads in contact with the ground plane (not shown) of the substrate 102. A row of pillars or posts 106 may extend linearly from the conductive traces 104. The pillars 106 may be made of a conductive material. By way of example, the conductive material of the conductive traces 104 and pillars 106 may include copper and its alloys. In various embodiments, the conductive material of the pillars 106 is the same as the conductive material of the conductive traces 104. However, in other embodiments, the pillars 106 and the conductive traces 104 may be made of different conductive materials. Thus, the pillars 106 are grounded by the conductive traces 104 through the ground plane. In embodiments, the conductive traces 104 and the array of pillars 106 may be formed during the substrate formation process. Thus, the substrate 102 may be provided by a substrate manufacturer with pre-formed conductive traces 104 and pre-formed pillars 106.

[0027] 1B schematically illustrates a substrate 102 with two dies 108a, 108b, e.g., microelectronic devices or chips, disposed on opposite sides of a pillar 106. The dies or chips 108a, 108b may be active or passive components. For example, a first die 108a may be disposed on a first side of the column of pillars 106, and a second die 108b may be disposed on the opposite side of the column of pillars 106. The dies 108a, 108b may be coupled to the substrate 102 by a wire bonding process or may be flip-chip attached to the substrate 102. In various embodiments, the pillars 106 may be disposed such that they surround or at least substantially surround one or both dies 108a, 108b; for example, the pillars 106 may be disposed similar to a fence. For example, pillars 106 may be disposed around a first die 108a, and pillars 106 may be disposed around a second die 108b. In embodiments, three or more dies 108 may be provided in the microelectronic device 100.

[0028] 1C, after the dies 108a, 108b are attached to the substrate 102, an encapsulation step may be performed to provide a covering in the form of a dielectric encapsulation layer 110 for the microelectronic device 100. The encapsulation step may include encapsulating or molding the components, including the first and second dies 108a, 108b, on the substrate 102 with a dielectric encapsulation material, for example, epoxy molding compound (EMC). Thus, the components, including the pillars 106, on the substrate 102 are encapsulated within the dielectric encapsulation layer during the encapsulation process.

[0029] 1D , in some embodiments, a trench may be provided in the cover of the microelectronic device after encapsulation; for example, trenches 112 may be formed in the cover using a saw, laser, water jet, or the like. In other embodiments, fins 114 may be utilized during the encapsulation step. In such embodiments, fins 114 may be removed after the encapsulation step, thereby forming trenches 112. When fins 114 are utilized, the spacing between pillars 106 allows the molding material to flow more easily between pillars 106 and around components on substrate 102.

[0030] 1E, after forming the trench 112, the trench 112 may be filled with a conductive material 116. A coating 118 of the conductive material 116 may be deposited on at least the top surface of the cover 110. In some embodiments, filling the trench 112 with the conductive material 116 and / or coating the cover 110 may be accomplished with conductive paint. In embodiments, the conductive material 116 may be provided within the trench 112 and / or as a coating 118 using a different deposition technique. In embodiments, the coating 118 of the conductive material 116 may extend onto the sides 120 of the cover 110. In embodiments, the conductive material 116 within the trench 112 and / or the conductive coating 118 on the top and possibly sides 120 of the cover 110 are the same material. In other embodiments, the conductive material 116 in the trench 112 and / or the conductive coating 118 on the top and possibly sides 120 of the cover 110 are different conductive materials.

[0031] 1F, in embodiments, the conductive material 116 in the trench 112 may extend to the pillars 106 to provide flexible-in-package shielding (FIPS). In some embodiments, the conductive material 116 in the trench 112 may not engage the pillars 106. In other embodiments, the conductive material 116 filling the trench 112 may engage the tops 122 of the pillars 106. Thus, the dielectric encapsulation layer 110 has a first portion 124 located at a first height H1 above a surface located above a first region of the substrate 102, including the first die 108a (not shown in FIG. 1F), a second portion 126 located at a second height H2 above a surface located above a second region of the substrate 102, including the second die 108b (not shown in FIG. 1F), and a third portion located at a third height H3 above a surface located above a third region of the substrate 102, including pillars 106, e.g., trenches 112 filled with conductive material 116. As can be seen in FIG. 1F, the third height H3 is less than the first height H1 and the second height H2.

[0032] Thus, the pillars 106, the conductive material 116 in the trenches 112, and / or the coating 118 of conductive material 116 on at least the top surface of the cover 110 form an interconnection combination that provides a Faraday cage, which provides EMI and / or RFI protection between the dies 108 a, 108 b located on opposite sides of the column of pillars 106. The coating 118 of conductive material 116 can also provide external shielding for the microelectronic device 100.

[0033] In some embodiments, the spacing between the pillars 106 is at least equal to a distance sufficient to block electromagnetic interference between two dies, e.g., a first die 108a disposed on one side of the pillar array and a second die 108b disposed on the opposite side of the pillar array. In some embodiments, the spacing between the pillars 106 is less than a distance sufficient to block electromagnetic interference between the first die 108a and the second die 108b. In some embodiments, the spacing between the pillars 106 may be in the range of 5 micrometers to 50 micrometers. Additionally, in some embodiments, the spacing between the first die 108a and the second die 108b is in the range of 100 microns to 2000 microns. Also, in some embodiments, the array of pillars 106 is integral with, e.g., part of, the conductive trace 104. In other embodiments, the pillars 106 are formed on, e.g., coupled to, the conductive trace 104.

[0034] Thus, as described above, utilizing the techniques provided herein in fabricating a microelectronic device, such as microelectronic device 100, reduces processing time in forming trench 112 because trench 112 does not extend as deeply into cover 110 as in prior art microelectronic devices, resulting in cost savings. Additionally, in some embodiments, trench 112 may not be filled with a separate conductive filler. Instead, conductive paint on trench 112 may be used to provide conductive material 116 on the top surface of cover 110 with the conductive paint, and possibly on sides 120 of cover 110.

[0035] Additionally, the trench 112 does not extend all the way to the substrate 102, thereby not exposing the substrate 102, which can result in improved reliability and reduced moisture ingress for the microelectronic device 100. Furthermore, because the trench 112 does not extend all the way to the substrate 102, improved mechanical robustness for the microelectronic device 100 can be achieved, resulting in less cracking of the packaging / thin substrate that is typically caused by bending.

[0036] Also, in various embodiments, the pillars 106 can be formed using established circuit board batch processes, resulting in time and cost savings. Furthermore, using the techniques described herein, wire stitching is eliminated, and the pillars 106 are more physically stable than wire, resulting in higher assembly yields and additional cost savings. Additionally, the techniques provided herein provide better shielding protection to the top of the cover 110 than stitched wire.

[0037] Additionally, the techniques described herein provide flexible trench fabrication shapes and placement locations for flexible-in-package shielding (FIPS). For example, pillars 106 and trenches 112 do not necessarily need to be straight, but rather only need to be shaped and / or placed to provide EMI and RFI shielding between microelectronic elements. Thus, the microelectronic device is flexible in terms of internal die / passive-to-die / passive shielding against EMI and / or RFI, as well as external shielding from other components. Therefore, the package design and layout of the microelectronic device can dictate the placement of pillars 106 and trenches 112. Additionally, utilizing a fin process during fabrication of encapsulating cover 110 can limit excess trench fabrication, such as cutting through the encapsulant to create trenches 112, thereby saving time and / or materials.

[0038] 2 is a flow diagram of an exemplary method 200 of fabricating a microelectronic device, such as microelectronic device 100. In the flow diagram, the operations of method 200 are shown as individual blocks.

[0039] Block 202 includes providing a substrate having a plurality of pillars and one of (i) a conductive trace or (ii) a plurality of conductive pads, wherein a first end of each pillar of the plurality of pillars is coupled to one of the (i) conductive trace or (ii) a corresponding conductive pad of the plurality of conductive pads. For example, the substrate may be substantially the same as substrate 102 having conductive traces 104 and pillars 106.

[0040] In block 204, a first die is attached to the substrate adjacent to a first side of the pillar. For example, a first die 108a may be attached to the substrate 102 adjacent to a first side of the pillar 106.

[0041] Block 206 includes attaching a second die to the substrate adjacent to a second side of the plurality of pillars, the second side being opposite the first side. For example, a second die 108b may be attached to the substrate 102 on a second side of the pillars 106.

[0042] In block 208, an epoxy molding compound is applied over at least the first chip, the second chip, and the plurality of pillars to provide a cover. For example, an encapsulation step may be performed to provide cover 110.

[0043] In block 210, a trench is formed in the cover, wherein a second end of each pillar of the plurality of pillars is located at least adjacent to the trench formed in the cover, and the spacing between the plurality of pillars is at least equal to a distance sufficient to block one or more of (i) electromagnetic interference (EMI) or (ii) radio frequency interference (RFI) between the first chip and the second chip. For example, trench 112 may be formed in cover 110. In some embodiments, trench 112 may be formed in cover 110 using fins 114 during performance of block 208, and thus step 210 may not be performed in such embodiments.

[0044] In block 212, the trenches may be filled with a conductive material. For example, the trenches 112 may be filled with the conductive material 116 such that the pillars 106, the conductive material 116 in the trenches 112, and / or the coating 118 of the conductive material 116 on at least the top surface of the cover 110 form an interconnected combination that provides a Faraday cage, which provides EMI and / or RFI protection between the dies 108 a, 108 b disposed on opposite sides of the column of pillars 106.

[0045] Although the present invention has been described with reference to specific embodiments and configurations, it should be understood that the scope of the present invention is not limited to these specific embodiments and configurations. Since other modifications and variations that can be made to suit particular operating requirements and environments will be apparent to those skilled in the art, the present invention should not be construed as being limited to the embodiments and configurations selected for purposes of disclosure, and the present invention includes all changes and variations that do not depart from the true spirit and scope of the present invention.

[0046] Although the present application describes aspects and embodiments that include particular structural features and / or methodological acts, it should be understood that the claims are not necessarily limited to the particular features or acts described. Rather, the particular features and acts are merely illustrative of some of the aspects and embodiments that fall within the scope of the invention as defined by the claims of the present application.

Claims

1. 1. A microelectronic device comprising: a substrate; a first chip mounted on the substrate and a second chip mounted on the substrate; a plurality of pillars disposed between the first chip and the second chip, a first end of each of the plurality of pillars being located adjacent to the substrate, and a spacing between each of the plurality of pillars being at least equal to a distance sufficient to block one or more of (i) electromagnetic interference (EMI) or (ii) radio frequency interference (RFI) between the first chip and the second chip; the individual pillars of the plurality of pillars are arranged based on one or more frequencies associated with interference between the first chip and the second chip; the plurality of pillars are positioned to substantially shield interference at one or more frequencies between the first chip and the second chip; a cover covering at least the first chip, the second chip, and the plurality of pillars, wherein a second end of each pillar of the plurality of pillars is located adjacent to a trench provided in at least the cover.

2. the trench is filled with a conductive material; The microelectronic device of claim 1 , wherein the second end of each pillar of the plurality of pillars engages a bottom surface of the conductive material.

3. The microelectronic device of claim 2 , wherein an outer surface of the cover includes the layer of conductive material.

4. The microelectronic device of claim 1 , wherein the cover extends to the substrate.

5. 10. The microelectronic device of claim 1, wherein the first end of each pillar of the plurality of pillars is coupled to one of (i) a conductive trace or (ii) a corresponding conductive pad of a plurality of conductive pads exposed at a surface of the substrate.

6. 6. The microelectronic device of claim 5, wherein the first end of each pillar is integral with one of (i) the conductive trace or (ii) the corresponding conductive pad of the plurality of conductive pads.

7. The microelectronic device of claim 1 , wherein the cover material extends between the plurality of pillars.

8. The microelectronic device of claim 1 , wherein each pillar of the plurality of pillars is linearly aligned between the first chip and the second chip.

9. The microelectronic device of claim 1 , wherein the spacing between individual pillars of the plurality of pillars is in the range of 5 micrometers to 50 micrometers.

10. The microelectronic device of claim 1 , wherein the spacing between the first tip and the second tip is in the range of 100 microns to 2000 microns.

11. 1. A microelectronic device comprising: a substrate having a first region, a second region, and a third region located between the first region and the second region, the substrate having (i) a surface and (ii) a ground plane; at least one first microelectronic element located on the surface of the first region; at least one second microelectronic element located on the surface of the second region; a conductive element exposed at the surface of the substrate in the third region and coupled to the ground plane; a plurality of conductive posts disposed within the third region, the conductive posts having (i) a first end coupled to the conductive element and (ii) a second end opposite the first end; each conductive post of the plurality of conductive posts is positioned based on one or more frequencies associated with interference between the at least one first microelectronic element and the at least one second microelectronic element; the plurality of conductive posts are positioned to substantially shield interference at one or more frequencies between the at least one first microelectronic element and the at least one second microelectronic element; a dielectric encapsulation layer extending from the surface of the substrate and filling spaces between some of the plurality of conductive posts, the some of the conductive posts being separated from one another by the dielectric encapsulation layer, the dielectric encapsulation layer having a first portion located at a first height above the surface overlying the first region of the substrate, a second portion located at a second height above the surface overlying the second region of the substrate, and a third portion located at a third height above the surface overlying the third region of the substrate, the third height being lower than the first height and the second height, and the second ends of the plurality of conductive posts being located adjacent to at least the third portion; The microelectronic device has a conductive material located within at least the third portion of the dielectric encapsulation layer.

12. The microelectronic device of claim 11 , wherein the interconnected combination of the ground plane, the conductive material, and the plurality of conductive posts layers defines a Faraday cage.

13. 12. The microelectronic device of claim 11, wherein the spacing between the plurality of conductive posts is at least equal to a distance sufficient to block one or more of (i) electromagnetic interference (EMI) or (ii) radio frequency interference (RFI) between the at least one first microelectronic element and the at least one second microelectronic element.

14. The microelectronic device of claim 11 , wherein the first ends of the plurality of conductive posts are coupled to the conductive element.

15. The microelectronic device of claim 14 , wherein the first ends of the plurality of conductive posts are integral with the conductive element.

16. The microelectronic device of claim 11 , wherein the plurality of conductive posts are linearly arranged between the at least one first microelectronic element and the at least one second microelectronic element.

17. 1. A method comprising: providing a substrate having a plurality of pillars and one of (i) a conductive trace or (ii) a plurality of conductive pads, wherein a first end of each pillar of the plurality of pillars is coupled to one of (i) the conductive trace or (ii) a corresponding conductive pad of the plurality of conductive pads; attaching a first chip to the substrate adjacent a first side of the plurality of pillars; attaching a second chip to the substrate adjacent to a second side of the plurality of pillars, the second side being opposite the first side; providing an epoxy molding compound over at least the first chip, the second chip, and the plurality of pillars to provide a cover; forming a trench in the cover; filling the trench with a conductive material; a second end of each pillar of the plurality of pillars positioned adjacent to at least the trench formed in the cover; a spacing between the plurality of pillars at least equal to a distance sufficient to block one or more of (i) electromagnetic interference (EMI) or (ii) radio frequency interference (RFI) between the first chip and the second chip; individual pillars of the plurality of pillars are arranged in a preselected manner with respect to one or more frequencies associated with interference between the first chip and the second chip; The method, wherein the plurality of pillars are positioned to substantially shield interference at one or more frequencies between the first chip and the second chip.

18. providing the substrate having the conductive traces and the plurality of pillars; providing the substrate; The method of claim 17 , further comprising forming the plurality of pillars and one of (i) the conductive traces or (ii) the plurality of conductive pads.

19. 20. The method of claim 18, wherein the first end of each pillar is integral with one of (i) the conductive trace or (ii) the corresponding conductive pad of the plurality of conductive pads.

20. The step of forming the trench comprises: placing fins within the cover during the step of providing the epoxy molding compound; The method of claim 17 further comprising removing the fin to provide the trench.

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