Charge pump circuit and driving device

Abstract

To provide a charge pump circuit that raises voltage with high efficiency, and a driving device.SOLUTION: A charge pump circuit in an embodiment includes a first capacitor having a first end to which a first voltage is supplied, a second capacitor having a first end to which a first pulse signal is supplied and a second end connected to a first node, a third capacitor having a first end to which the first pulse signal is supplied, a first transistor having a first end connected to a second end of the first capacitor and a second end connected to the first node, a second transistor having a first end connected to the first end of the first capacitor and a second end connected to the first node, and a first circuit having a first input end connected to the first node, a second input end connected to a second end of the third capacitor, a first output end connected to a gate of the first transistor, and a second output end connected to a gate of the second transistor.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] FIELD Embodiments of the present invention relate to a charge pump circuit and a driving device. [Background technology]

[0002] 2. Description of the Related Art A drive device for driving a motor or the like that handles a large current, and a charge pump circuit for generating a voltage higher than a power supply voltage in the drive device, are known. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] U.S. Patent No. 6,608,505 [Patent Document 2] Japanese Patent Application Publication No. 10-242834 Summary of the Invention [Problem to be solved by the invention]

[0004] A charge pump circuit and a drive device for boosting voltage with high efficiency are provided. [Means for solving the problem]

[0005] A charge pump circuit according to an embodiment includes a first capacitor, a second capacitor, a third capacitor, a first transistor, a second transistor, and a first circuit. The first capacitor has a first terminal to which a first voltage is supplied. The second capacitor has a first terminal to which a first pulse signal is supplied and a second terminal connected to a first node. The third capacitor has a first terminal to which the first pulse signal is supplied. The first transistor has a first terminal connected to the second terminal of the first capacitor and a second terminal connected to the first node. The second transistor has a first terminal connected to the first terminal of the first capacitor and a second terminal connected to the first node. The first circuit has a first input terminal connected to the first node, a second input terminal connected to the second terminal of the third capacitor, a first output terminal connected to a gate of the first transistor, and a second output terminal connected to a gate of the second transistor. and controlling a voltage supplied to each of the gates of the first transistor and the second transistor based on the first pulse signal. . [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a block diagram showing an example of the configuration of a motor drive system including a drive device according to an embodiment. [Figure 2] FIG. 2 is a circuit diagram showing an example of the configuration of a charge pump circuit of the drive device according to the embodiment. [Figure 3] FIG. 4 is a waveform diagram showing an example of a boosting operation in a charge pump circuit of the driving device according to the embodiment. [Figure 4] FIG. 4 is a waveform diagram showing an example of a boosting operation when a clock signal rises in the charge pump circuit of the drive device according to the embodiment. [Figure 5] 5A and 5B are diagrams showing an example of a boosting operation when a clock signal rises in a charge pump circuit of the driving device according to the embodiment. [Figure 6] FIG. 4 is a waveform diagram showing an example of a boosting operation when a clock signal falls in the charge pump circuit of the drive device according to the embodiment. [Figure 7] 5A and 5B are diagrams showing an example of a boosting operation when a clock signal falls in a charge pump circuit of the driving device according to the embodiment. [Figure 8] FIG. 10 is a circuit diagram showing an example of the configuration of a charge pump circuit of a driving device according to a modified example. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, embodiments will be described with reference to the drawings. In the following description, components having substantially the same functions and configurations will be designated by the same reference numerals. When elements having similar configurations are to be particularly distinguished from one another, different letters or numbers may be added to the end of the same reference numerals.

[0008] 1. Configuration 1.1 Drive unit 1 is a block diagram showing an example of the configuration of a motor drive system including a drive device according to an embodiment. The motor drive system 1 includes a control unit 2, a drive device 3, and a motor 4. The motor drive system 1 is an application that executes a predetermined operation using torque obtained from the motor 4.

[0009] The control unit 2 controls the entire motor drive system 1. The control unit 2 includes, for example, a processor and a memory. The processor of the control unit 2 generates control signals based on a program stored in advance in the memory, and controls the drive device 3.

[0010] The driving device 3 is, for example, an IC (Integrated Circuit) chip that functions as a motor controller driver (MCD). The driving device 3 drives the motor 4 in accordance with a control signal from the control unit 2. Specifically, the driving device 3 has a built-in charge pump circuit 10. The charge pump circuit 10 is a voltage generating circuit that generates a voltage used to drive the motor 4. The charge pump circuit 10 is also called a boost circuit. The driving device 3 drives the motor 4 using the voltage generated by the charge pump circuit 10.

[0011] 1.2 Charge pump circuit Next, the configuration of the charge pump circuit of the drive device according to the embodiment will be described below. Fig. 2 is a circuit diagram showing an example of the configuration of the charge pump circuit of the drive device according to the embodiment.

[0012] The charge pump circuit 10 is a synchronous rectification circuit and includes a plurality of power supplies E, a clock generator CK, a plurality of inverters IV, a plurality of capacitors C, a plurality of non-conjunction circuits NOR, a plurality of non-conjunction circuits NAND, a plurality of transistors Tr, and an output terminal P. The plurality of power supplies E include power supplies E1 and E2.

[0013] The plurality of inverters IV include inverters IV1, IV2, IV3, IV4, IV5, IV6, IV7, IV8, IV9, IV10, IV11, and IV12. The plurality of capacitors C include capacitors C1, C2, C3, C4, and C5. The plurality of NOR circuits NOR include NOR circuits NOR1 and NOR2. The plurality of NAND circuits NAND include NAND circuits NAND1 and NAND2. The plurality of transistors Tr include transistors Tr1, Tr2, Tr3, and Tr4. The transistors Tr1 and Tr3 are P-type metal-oxide-semiconductor transistors (MOS). The transistors Tr2 and Tr4 are N-type MOS transistors.

[0014] The power supply E1 is a logic power supply. The power supply E1 outputs a voltage VDD relative to the ground GND. The voltage VDD drives a plurality of inverters IV, a plurality of non-OR circuits NOR, and a plurality of non-AND circuits NAND.

[0015] The clock generator CK generates a clock signal CLK. The clock signal CLK is, for example, a pulse signal. In accordance with the period of the clock signal CLK, the charge pump circuit 10 performs a boost operation to boost the voltage output to the output terminal P. Specifically, the voltage output to the output terminal P is boosted in accordance with the rising and falling edges of the clock signal CLK. The boost operation will be described in detail later.

[0016] A first voltage input terminal of each of the inverters IV1, IV2, IV3, IV4, IV5, IV6, and IV7 is connected to ground GND. A second voltage input terminal of each of the inverters IV1, IV2, IV3, IV4, IV5, IV6, and IV7 is supplied with voltage VDD. As a result, each of the inverters IV1, IV2, IV3, IV4, IV5, IV6, and IV7 is configured to output voltage VDD as an "H" level from its signal output terminal and a ground GND voltage (e.g., 0 V) ​​as an "L" level.

[0017] A clock signal CLK is input to a signal input terminal of the inverter IV1. A signal output terminal of the inverter IV1 is connected to the signal input terminals of the inverters IV2 and IV3. A signal output terminal of the inverter IV2 is connected to a first terminal of the capacitor C1. A signal output terminal of the inverter IV3 is connected to a first terminal of the capacitor C3.

[0018] A clock signal CLK is input to a signal input terminal of the inverter IV4. A signal output terminal of the inverter IV4 is connected to a signal input terminal of the inverter IV5. A signal output terminal of the inverter IV5 is connected to signal input terminals of the inverters IV6 and IV7. A signal output terminal of the inverter IV6 is connected to a first terminal of the capacitor C2. A signal output terminal of the inverter IV7 is connected to a first terminal of the capacitor C4.

[0019] A second end of the capacitor C1 is connected to the node N1. A second end of the capacitor C2 is connected to the node N2. A second end of the capacitor C3 is connected to the node N3. A second end of the capacitor C4 is connected to the node N4.

[0020] The power supply E2 is a motor power supply. The power supply E2 outputs a voltage VM relative to the ground GND. The voltage VM is used to boost the voltage transferred to the output terminal P. The voltage VM is supplied to a node N5.

[0021] The first voltage input terminals of the inverters IV7, IV8, IV9, IV10, IV11, and IV12, the NOR circuits NOR1 and NOR2, and the NAND circuits NAND1 and NAND2, and the first terminal of the capacitor C5 are connected to the node NOUT. The second voltage input terminals of the inverters IV7, IV8, IV9, IV10, IV11, and IV11, the NOR circuits NOR1 and NOR2, and the NAND circuits NAND1 and NAND2, and the second terminal of the capacitor C5 are connected to the node N5. As a result, the inverters IV7, IV8, IV9, IV10, IV11, and IV12, the NOR circuits NOR1 and NOR2, and the NAND circuits NAND1 and NAND2 are configured to output the voltage of the node NOUT as a "H" level from their signal output terminals and the voltage VM of the node N5 as a "L" level.

[0022] The signal input terminal of the inverter IV7 is connected to the node N1, the signal output terminal of the inverter IV7 is connected to the signal input terminals of the inverters IV8 and IV9, and the signal output terminal of the inverter IV8 is connected to the node N3.

[0023] A first input terminal of each of the NOR circuit NOR1 and the NAND circuit NAND1 is connected to a node N3. A second input terminal of each of the NOR circuit NOR1 and the NAND circuit NAND1 is connected to a signal output terminal of an inverter IV9. That is, the NOR circuit NOR1 outputs a "L" level signal from its signal output terminal unless the voltage of the node N3 and the voltage of the signal output terminal of the inverter IV9 are both "L" level. When the voltage of the node N3 and the voltage of the signal output terminal of the inverter IV9 are both "L" level, the NOR circuit NOR1 outputs a "H" level signal from its signal output terminal.

[0024] The source of the transistor Tr1 is connected to the node NOUT, the drain of the transistor Tr1 is connected to the node N1, and the gate of the transistor Tr1 is connected to the signal output terminal of the NAND circuit NAND1 via the node GIN1.

[0025] The source of the transistor Tr2 is connected to the node N5, the drain of the transistor Tr2 is connected to the node N1, and the gate of the transistor Tr2 is connected to the signal output terminal of the NOR circuit NOR1 via the node GIN2.

[0026] In this way, the inverters IV7, IV8, and IV9, the NOR circuit NOR1, and the NAND circuit NAND1 function to control the voltages supplied to the gates of the transistors Tr1 and Tr2. The inverters IV7, IV8, and IV9, the NOR circuit NOR1, and the NAND circuit NAND1 are also referred to as the gate control circuit GCa. The gate control circuit GCa is configured to allow a period during which the transistors Tr1 and Tr2 are both turned off, but to prevent a period during which the transistors Tr1 and Tr2 are both turned on.

[0027] The signal input terminal of the inverter IV10 is connected to the node N2, the signal output terminal of the inverter IV10 is connected to the signal input terminals of the inverters IV11 and IV12, and the signal output terminal of the inverter IV11 is connected to the node N4.

[0028] The first input terminals of the NOR circuit NOR2 and the NAND circuit NAND2 are connected to the node N4, and the second input terminals of the NOR circuit NOR2 and the NAND circuit NAND2 are connected to the signal output terminal of the inverter IV12.

[0029] The source of the transistor Tr3 is connected to the node NOUT, the drain of the transistor Tr3 is connected to the node N2, and the gate of the transistor Tr3 is connected to the signal output terminal of the NAND circuit NAND2 via the node GIN3.

[0030] The source of the transistor Tr4 is connected to the node N5, the drain of the transistor Tr4 is connected to the node N2, and the gate of the transistor Tr4 is connected to the signal output terminal of the NOR circuit NOR2 via the node GIN4.

[0031] The output terminal P is connected to the node NOUT. The output terminal P outputs the voltage boosted by the boosting operation of the charge pump circuit 10 to the outside of the charge pump circuit 10 in the driving device 3.

[0032] In the above configuration, the pair of transistors Tr1 and Tr2 and the pair of transistors Tr3 and Tr4 function as rectifying elements. Capacitors C1 and C2 function as pumping capacitors. Capacitors C3 and C4 function as level shift capacitors arranged in parallel with capacitors C1 and C2, respectively. Power supply E1, clock generator CK, and inverters IV1, IV2, IV3, IV4, IV5, IV6, and IV7 function as drive circuits for the pumping capacitors.

[0033] In addition, inverters IV10, IV11, and IV12, NOR circuit NOR2, and NAND circuit NAND2 function to control the voltages supplied to the gates of transistors Tr3 and Tr4. Inverters IV10, IV11, and IV12, NOR circuit NOR2, and NAND circuit NAND2 are also referred to as a gate control circuit GCb. Gate control circuit GCb is configured to allow a period during which transistors Tr3 and Tr4 are simultaneously turned off, but to prevent a period during which transistors Tr3 and Tr4 are simultaneously turned on.

[0034] 2. Operation 2.1 Overview of boost operation First, the boost operation will be outlined.

[0035] 3 is a waveform diagram showing an example of a boosting operation in the charge pump circuit of the driving device according to the embodiment, which illustrates the time variations of the clock signal CLK and the voltages of the nodes NOUT, GIN1, GIN2, GIN3, and GIN4.

[0036] 3, the clock signal CLK periodically changes between the “H” level and the “L” level with a period D. The voltage at the node NOUT gradually increases from the voltage VM in response to the rising and falling edges of the clock signal CLK, and gradually approaches the voltage VOUT.

[0037] The voltage VOUT is, for example, the sum of the voltages VM and VDD minus the sum of the drain-source voltages of transistors Tr1 and Tr2, or the sum of the drain-source voltages of transistors Tr3 and Tr4. In other words, if the sum of the drain-source voltages of transistors Tr1 and Tr2 and the sum of the drain-source voltages of transistors Tr3 and Tr4 are approximately equal to 2Vds, the voltage VOUT can be (VDD+VM-2Vds).

[0038] The voltages of nodes GIN1 and GIN2 each transition from the "H" level to the "L" level in response to the rising edge of the clock signal CLK (e.g., time T10 in FIG. 3). The voltages of nodes GIN1 and GIN2 each transition from the "L" level to the "H" level in response to the falling edge of the clock signal CLK (e.g., time T20 in FIG. 3). While the clock signal CLK is at the "H" level, the voltages of nodes GIN1 and GIN2 are gradually boosted from voltage VM with each repetition of the cycle of the clock signal CLK, and gradually approach voltage VOUT.

[0039] Meanwhile, the voltages of nodes GIN3 and GIN4 each transition from the "L" level to the "H" level in response to the rising edge of the clock signal CLK (for example, time T10 in FIG. 3). The voltages of nodes GIN3 and GIN4 each transition from the "H" level to the "L" level in response to the falling edge of the clock signal CLK (for example, time T20 in FIG. 3). Then, while the clock signal CLK is at the "H" level, the voltages of nodes GIN3 and GIN4 are gradually boosted from voltage VM with each repetition of the cycle of the clock signal CLK, and gradually approach voltage VOUT.

[0040] 2.2 Details of boost operation at rising edge of clock signal Next, the boosting operation at the rising edge of the clock signal will be described in detail.

[0041] Fig. 4 is a waveform diagram showing an example of a boost operation when a clock signal rises in a charge pump circuit of a drive device according to an embodiment. Fig. 5 is a diagram showing an example of a boost operation when a clock signal rises in a charge pump circuit of a drive device according to an embodiment. Figs. 4 and 5 correspond to time T10 and the vicinity thereof in Fig. 3.

[0042] Until time T10, the clock signal CLK is at the "L" level.

[0043] Accordingly, the first terminals of the capacitors C1 and C3 are grounded to ground GND. At this time, the voltages of the nodes N1 and N3 are both at "L" level. Therefore, the signal level output from the NAND circuit NAND1 to the node GIN1 and the signal level output from the NOR circuit NOR1 to the node GIN2 are both at "H" level. Therefore, the transistor Tr1 is in an off state and the transistor Tr2 is in an on state. Then, the node N1 is connected to the node N5 via the transistor Tr2, and the voltage VM is supplied to the second terminal of the capacitor C1.

[0044] Furthermore, voltage VDD is supplied to the first ends of capacitors C2 and C4. At this time, the voltages of nodes N2 and N4 are both at "H" level. Therefore, the signal level output from NAND circuit NAND2 to node GIN3 and the signal level output from NOR circuit NOR2 to node GIN4 are both at "L" level. Therefore, transistor Tr3 is in an ON state and transistor Tr4 is in an OFF state. Then, since node N2 is connected to node NOUT via transistor Tr3, capacitor C5 is charged by capacitor C2.

[0045] At time T10, the clock signal CLK rises from the "L" level to the "H" level.

[0046] Accordingly, the supply of voltage VDD to the first terminals of capacitors C1 and C3 begins. As a result, the voltage at node N3 changes from the "L" level to the "H" level. Meanwhile, because node N1 is connected to node N5, the voltage change at node N1 lags behind node N3. As a result, the voltage at node N1 is maintained at the "L" level. Therefore, the signal level output from the NAND circuit NAND1 to node GIN1 is maintained at the "H" level. The signal level output from the NOR circuit NOR1 to node GIN2 changes from the "H" level to the "L" level. Therefore, both transistors Tr1 and Tr2 are turned off.

[0047] The second terminals of the capacitors C2 and C4 are connected to the ground GND. Accordingly, the voltage at the node N4 changes from the "H" level to the "L" level. Meanwhile, since the node N2 is connected to the node NOUT, the voltage change at the node N2 lags behind the node N4. As a result, the voltage at the node N2 is maintained at the "H" level. Therefore, the signal level output from the NAND circuit NAND2 to the node GIN3 changes from the "L" level to the "H" level. The signal level output from the NOR circuit NOR2 to the node GIN4 is maintained at the "L" level. Therefore, both the transistors Tr3 and Tr4 are turned off.

[0048] At time T11, the voltage at the node N1 rises to the "H" level, and the voltage at the node N2 drops to the "L" level.

[0049] As a result, the level of the signal output from the NAND circuit NAND1 to the node GIN1 changes from the "H" level to the "L" level. The level of the signal output from the NOR circuit NOR1 to the node GIN2 is maintained at the "L" level. As a result, the transistor Tr2 remains in the off state, while the transistor Tr1 is turned on. Then, the node N1 is connected to the node NOUT via the transistor Tr1, and the capacitor C5 starts to be charged by the capacitor C1.

[0050] Furthermore, the level of the signal output from the NAND circuit NAND2 to the node GIN3 is maintained at the “H” level. The level of the signal output from the NOR circuit NOR2 to the node GIN4 changes from the “L” level to the “H” level. As a result, the transistor Tr3 remains in the off state, while the transistor Tr4 is turned on. Then, the node N2 is connected to the node N5 via the transistor Tr4, and the voltage VM is supplied to the second end of the capacitor C2.

[0051] By operating as described above, at the rising edge of the clock signal CLK, the state transitions from one in which transistor Tr1 is off and transistor Tr2 is on to one in which both transistors Tr1 and Tr2 are off, to one in which transistor Tr1 is on and transistor Tr2 is off. Similarly, at the rising edge of the clock signal CLK, the state transitions from one in which transistor Tr3 is on and transistor Tr4 is off to one in which both transistors Tr3 and Tr4 are off, to one in which transistor Tr3 is off and transistor Tr4 is on.

[0052] 2.3 Details of boost operation at the falling edge of the clock signal Next, the boosting operation at the falling edge of the clock signal will be described in detail.

[0053] Fig. 6 is a waveform diagram showing an example of a boost operation when a clock signal falls in a charge pump circuit of a drive device according to an embodiment. Fig. 7 is a diagram showing an example of a boost operation when a clock signal falls in a charge pump circuit of a drive device according to an embodiment. Figs. 6 and 7 correspond to time T20 and its vicinity in Fig. 3.

[0054] Until time T20, the clock signal CLK is at the "H" level.

[0055] Accordingly, the voltage VDD is supplied to the first terminals of the capacitors C1 and C3. At this time, the voltages of the nodes N1 and N3 are both at the "H" level. Therefore, the signal level output from the NAND circuit NAND1 to the node GIN1 and the signal level output from the NOR circuit NOR1 to the node GIN2 are both at the "L" level. Therefore, the transistor Tr1 is in the ON state, and the transistor Tr2 is in the OFF state. Then, the node N1 is connected to the node NOUT via the transistor Tr1, so that the capacitor C5 is charged by the capacitor C1.

[0056] The first terminals of the capacitors C2 and C4 are connected to ground GND. At this time, the voltages of the nodes N2 and N4 are both at the "L" level. Therefore, the signal level output from the NAND circuit NAND2 to the node GIN3 and the signal level output from the NOR circuit NOR2 to the node GIN4 are both at the "H" level. Therefore, the transistor Tr3 is in the off state, and the transistor Tr4 is in the on state. The node N2 is connected to the node N5 via the transistor Tr4, so that the voltage VM is supplied to the second terminal of the capacitor C2.

[0057] At time T20, the clock signal CLK falls from the "H" level to the "L" level.

[0058] As a result, the second ends of the capacitors C1 and C3 are grounded to ground GND. The voltage at node N3 changes from "H" level to "L" level. Meanwhile, because node N1 is connected to node NOUT, the voltage change at node N1 lags behind node N3. As a result, the voltage at node N1 is maintained at "H" level. Therefore, the signal level output from the NAND circuit NAND1 to node GIN1 changes from "L" level to "H" level. The signal level output from the NOR circuit NOR1 to node GIN3 is maintained at "L" level. Therefore, both transistors Tr1 and Tr2 are turned off.

[0059] Furthermore, the supply of voltage VDD to the first ends of capacitors C2 and C4 begins. As a result, the voltage at node N4 changes from the "L" level to the "H" level. On the other hand, since node N2 is connected to node N5, the voltage change at node N2 lags behind node N4. As a result, the voltage at node N2 is maintained at the "L" level. Therefore, the signal level output from the NAND circuit NAND2 to node GIN3 is maintained at the "H" level. The signal level output from the NOR circuit NOR2 to node GIN4 changes from the "H" level to the "L" level. Therefore, both transistors Tr3 and Tr4 are turned off.

[0060] At time T21, the voltage at the node N1 drops to the "L" level, and the voltage at the node N2 rises to the "H" level.

[0061] Accordingly, the level of the signal output from the NAND circuit NAND1 to the node GIN1 is maintained at the "H" level. The level of the signal output from the NOR circuit NOR1 to the node GIN2 changes from the "L" level to the "H" level. As a result, the transistor Tr1 remains in the off state, while the transistor Tr2 is turned on. Then, the node N1 is connected to the node N5 via the transistor Tr2, and the voltage VM is supplied to the second end of the capacitor C1.

[0062] Furthermore, the level of the signal output from the NAND circuit NAND2 to the node GIN3 changes from the "H" level to the "L" level. The level of the signal output from the NOR circuit NOR2 to the node GIN4 is maintained at the "L" level. As a result, the transistor Tr4 remains in the off state, and the transistor Tr3 is turned on. Then, the node N2 is connected to the node NOUT via the transistor Tr3, and the capacitor C5 starts to be charged by the capacitor C2.

[0063] By operating as described above, at the falling edge of the clock signal CLK, the state where transistor Tr1 is on and transistor Tr2 is off transitions to a state where both transistors Tr1 and Tr2 are off, followed by a state where transistor Tr1 is off and transistor Tr2 is on. Similarly, at the falling edge of the clock signal CLK, the state where transistor Tr3 is off and transistor Tr4 is on transitions to a state where both transistors Tr3 and Tr4 are off, followed by a state where transistor Tr3 is on and transistor Tr4 is off.

[0064] 3. Effects of the embodiment According to the embodiment, the gate control circuit GCa receives the voltage at node N1 as an output state signal for transistors Tr1 and Tr2 serving as rectifying elements, and receives the voltage at node N3 as an input signal from the drive circuit for the pump-up capacitor. Based on these two types of signals, the gate control circuit GCa can distinguish between a state in which both transistors Tr1 and Tr2 are off, a state in which one of transistors Tr1 and Tr2 is on and the other is off, and a state in which both transistors Tr1 and Tr2 are on. Therefore, the gate control circuit GCa can transition from a state in which transistor Tr1 is on and transistor Tr2 is off to a state in which transistors Tr1 and Tr2 are off, via a state in which both transistors Tr1 and Tr2 are off, to a state in which transistor Tr1 is off and transistor Tr2 is on. The gate control circuit GCa can transition from a state in which transistor Tr1 is off and transistor Tr2 is on to a state in which transistors Tr1 and Tr2 are off, via a state in which both transistors Tr1 and Tr2 are off, to a state in which transistor Tr1 is on and transistor Tr2 is off. Therefore, the through current that occurs when both the transistors Tr1 and Tr2 are turned on can be suppressed, and the voltage VOUT output from the output terminal P can be prevented from decreasing due to the through current.

[0065] The gate control circuit GCb also receives the voltage at node N2 as an output state signal for the rectifying transistors Tr3 and Tr4, and receives the voltage at node N4 as an input signal from the drive circuit for the pump-up capacitor. Based on these two signals, the gate control circuit GCb can distinguish between a state in which both transistors Tr3 and Tr4 are off, a state in which one of the transistors Tr3 and Tr4 is on and the other is off, and a state in which both transistors Tr3 and Tr4 are on. Therefore, the gate control circuit GCb can transition from a state in which transistor Tr3 is on and transistor Tr4 is off to a state in which both transistors Tr3 and Tr4 are off, and then to a state in which transistor Tr3 is off and transistor Tr4 is on. The gate control circuit GCb can transition from a state in which transistor Tr3 is off and transistor Tr4 is on to a state in which both transistors Tr3 and Tr4 are off, and finally to a state in which transistor Tr3 is on and transistor Tr4 is off. Therefore, the through current that occurs when both the transistors Tr3 and Tr4 are turned on can be suppressed, and the voltage VOUT output from the output terminal P can be prevented from decreasing due to the through current.

[0066] Specifically, the gate control circuit GCa includes a NAND circuit NAND1 having an output terminal connected to the gate of transistor Tr1 and a NOR circuit NOR1 having an output terminal connected to the gate of transistor Tr2. The gate control circuit GCb includes a NAND circuit NAND2 having an output terminal connected to the gate of transistor Tr3 and a NOR circuit NOR2 having an output terminal connected to the gate of transistor Tr4. This allows the configuration to fulfill the functions of the gate control circuits GCa and GCb while minimizing the number of MOS transistors used. This reduces the packaging area of ​​the charge pump circuit 10. Therefore, the charge pump circuit 10 can be built into the drive device 3.

[0067] 4. Variations In the above-described embodiment, the charge pump circuit 10 is described as having a logic power supply and a motor power supply, but this is not limiting. The charge pump circuit 10 may also be configured to have a single power supply that is used as both the logic power supply and the motor power supply. The following mainly describes configurations and operations that differ from the embodiment. Explanations of configurations and operations that are equivalent to those of the embodiment will be omitted as appropriate.

[0068] 8 is a circuit diagram showing an example of the configuration of a charge pump circuit of a driving device according to a modified example. As shown in FIG. 8, the charge pump circuit 10 may include one power supply E1'.

[0069] Power supply E1' is a power supply used both as a logic power supply and a motor power supply. Power supply E1' outputs a voltage VDD relative to ground GND. Power supply E1' supplies voltage VDD to the second voltage input terminals of inverters IV1, IV2, IV3, IV4, IV5, IV6, and IV7. Power supply E1' also supplies voltage VDD to the first terminal of capacitor C5 via node N5.

[0070] With the above configuration, as in the embodiment, it is possible to prevent the voltage VOUT output from the output terminal P from decreasing due to the through current.

[0071] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, as well as within the scope of the invention described in the claims and their equivalents. [Explanation of symbols]

[0072] 1...Motor drive system 2...Control unit 3...Driver 4...Motor 10...Charge pump circuit E1,E1',E2...Power supply CK: Clock generator IV1,IV2,IV3,IV4,IV5,IV6,IV7,IV8,IV9,IV10,IV11,IV12...Inverter C1, C2, C3, C4, C5...capacitors NOR1, NOR2...Negative OR circuit NAND1, NAND2...NAND circuit Tr1, Tr2, Tr3, Tr4...Transistors P...Output end

Claims

1. a first capacitor having a first end to which a first voltage is applied; a second capacitor having a first end to which the first pulse signal is supplied and a second end connected to the first node; a third capacitor having a first end to which the first pulse signal is supplied; a first transistor having a first end connected to the second end of the first capacitor and a second end connected to the first node; a second transistor having a first end connected to the first end of the first capacitor and a second end connected to the first node; a first circuit having a first input terminal connected to the first node, a second input terminal connected to the second terminal of the third capacitor, a first output terminal connected to the gate of the first transistor, and a second output terminal connected to the gate of the second transistor, and configured to control a voltage supplied to each of the gates of the first transistor and the second transistor based on the first pulse signal; Equipped with Charge pump circuit.

2. the first circuit includes a first NAND circuit and a first NOR circuit; The first NAND circuit a first input terminal connected to the first node; a second input terminal connected to the second terminal of the third capacitor; an output terminal connected to the gate of the first transistor; and The first NOR circuit a first input terminal connected to the first node; a second input terminal connected to the second terminal of the third capacitor; an output terminal connected to the gate of the second transistor; having 2. The charge pump circuit according to claim 1.

3. the first transistor is a P-type MOS transistor, the second transistor is an N-type MOS transistor; 2. The charge pump circuit according to claim 1.

4. a first end of each of the first transistor and the second transistor is a source; the second terminal of each of the first transistor and the second transistor is a drain.

4. The charge pump circuit according to claim 3.

5. a fourth capacitor having a first end to which a second pulse signal obtained by inverting the first pulse signal is supplied and a second end connected to a second node; a fifth capacitor having a first end to which the second pulse signal is supplied; a third transistor having a first end connected to the second end of the first capacitor and a second end connected to the second node; a fourth transistor having a first end connected to the first end of the first capacitor and a second end connected to the second node; a second circuit having a first input terminal connected to the second node, a second input terminal connected to the second terminal of the fifth capacitor, a first output terminal connected to the gate of the third transistor, and a second output terminal connected to the gate of the fourth transistor; Further comprising:

2. The charge pump circuit according to claim 1.

6. the first circuit includes a first NAND circuit and a first NOR circuit; The first NAND circuit a first input terminal connected to the first node; a second input terminal connected to the second terminal of the third capacitor; an output terminal connected to the gate of the first transistor; and The first NOR circuit a first input terminal connected to the first node; a second input terminal connected to the second terminal of the third capacitor; an output terminal connected to the gate of the second transistor; and the second circuit includes a second NAND circuit and a second NOR circuit; The second NAND circuit a first input connected to the second node; a second input terminal connected to the second terminal of the fifth capacitor; an output terminal connected to the gate of the third transistor; and The second NOR circuit a first input connected to the second node; a second input terminal connected to the second terminal of the fifth capacitor; an output terminal connected to the gate of the fourth transistor; having 6. The charge pump circuit according to claim 5.

7. the first transistor and the third transistor are P-type MOS transistors, the second transistor and the fourth transistor are N-type MOS transistors; 6. The charge pump circuit according to claim 5.

8. a first end of each of the first transistor, the second transistor, the third transistor, and the fourth transistor is a source; a second terminal of each of the first transistor, the second transistor, the third transistor, and the fourth transistor is a drain; 8. The charge pump circuit according to claim 7.

9. an output terminal connected to the second terminal of the first capacitor; 9. The charge pump circuit according to claim 1.

10. The charge pump circuit of claim 9, The voltage at the output terminal is used to drive an external motor. Drive unit.

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