Wiring structure and manufacturing method thereof

Abstract

To provide an advanced wiring structure and a manufacturing method for the same for overcoming disadvantages of conventional techniques and making efficient connections possible.SOLUTION: The wiring structure includes a first dielectric layer, a first conductive layer, a conductor pillar, an upper dielectric layer, and an upper conductive layer. The first dielectric layer is arranged on a first terminal of a device. The first conductive layer is arranged on the first dielectric layer. The conductive pillar is connected to the first terminal. The upper dielectric layer is arranged on the first conductive layer. The upper conductive layer is arranged on the upper dielectric layer. The conductor pillar is connected to the upper conductive layer but is disconnected from the first conductive layer.SELECTED DRAWING: Figure 1H(2)

Description

[Technical Field]

[0001] FIELD OF THE DISCLOSURE The present disclosure relates generally to semiconductor structures and methods for their manufacture, and more particularly to interconnect structures and methods for their manufacture. [Background technology]

[0002] Modern integrated circuit chips connect numerous transistors on a single die using a multi-wire interconnect system. The first interconnect layer, M1, connects the gate level (gate) of MOSFET devices to the diffusion level (commonly referred to as diffusion) for the source and drain regions. To facilitate signal transmission, a second interconnect layer, M2, is required without increasing the die size. To connect M2 to M1, a structure, Via1, is formed using a certain conductive material. Thus, a vertical structure can be formed through the contact (Con) connection from the diffusion to M1, i.e., "Diffusion-Contact-M1." Similarly, another structure can be formed, connecting the gate to M1 with a contact structure, called "Gate-Contact-M1." If a connection structure is required, such as connecting the M1 interconnect to the M2 interconnect through Via1, it will be called "M1-Via1-M2." A more complex interconnect structure from the gate level to the M2 interconnect can be described as "Gate-Contact-M1-Via1-M2." Furthermore, the stacked wiring system may have an "M1-Via1-M2-Via2-M3-Via4-M4..." structure.

[0003] Until now, state-of-the-art wiring systems have prevented, for example, a gate from directly connecting to M2 without bypassing the M1 structure. As a result, the required space between one M1 wire and another can increase die size, and in some cases, this wiring connection can hinder the intended efficient connection beyond the M1 region using M2 directly. Furthermore, there is no way to form a self-aligned structure between Via1 and the contact, while both Via1 and the contact are connected to their own wiring systems. Summary of the Invention [Problem to be solved by the invention]

[0004] Therefore, there is a need to provide an advanced wiring structure and method for fabricating the same to overcome the shortcomings of the prior art. [Means for solving the problem]

[0005] One embodiment of the present disclosure provides a wiring structure, the wiring structure including a first dielectric layer, a first conductive layer, a conductor pillar, an upper dielectric layer, and an upper conductive layer. The first dielectric layer is disposed over a first terminal of a device. The first conductive layer is disposed over the first dielectric layer. The conductor pillar is connected to the first terminal. The upper dielectric layer is disposed over the first conductive layer. The upper conductive layer is disposed over the upper dielectric layer. The conductor pillar connects to the upper conductive layer but disconnects it from the first conductive layer.

[0006] In one aspect of the present disclosure, the conductor pillar includes a first conductor pillar portion and a second conductor pillar portion, the first conductor pillar portion being surrounded by a first dielectric layer and the second conductor pillar portion being surrounded by an upper dielectric layer.

[0007] In another aspect of the present disclosure, the first conductor pillar portion is formed using the silicon region of the first terminal as a base, and the second conductor pillar portion is formed using the first conductor pillar portion as a base.

[0008] In another aspect of the present disclosure, the device is a transistor and the first terminal of the device is a gate terminal, the gate terminal including a gate dielectric layer, a gate conductive layer on the gate dielectric layer, and a silicon region on the gate conductive layer.

[0009] In another aspect of the present disclosure, the silicon region is a polycrystalline silicon region or an amorphous silicon region.

[0010] In another aspect of the present disclosure, a first conductor pillar portion is formed by selective epitaxial growth on a base of a polycrystalline silicon region or an amorphous silicon region, and a second conductor pillar portion is formed by selective epitaxial growth on a base of the first conductor pillar portion.

[0011] In another aspect of the disclosure, the device is a transistor and the first terminal of the device is a drain terminal.

[0012] In another aspect of the present disclosure, the top surface of the conductor pillar is higher than the top surface of the upper dielectric layer.

[0013] Another embodiment of the present disclosure provides a method for manufacturing an interconnect structure, the method comprising the steps of: forming a first dielectric layer over a first terminal of a device; forming a conductor pillar connecting to the first terminal; forming a first conductive layer over the first dielectric layer; forming an upper dielectric layer over the first conductive layer; forming an upper conductive layer over the upper dielectric layer; and forming the conductor pillar connecting to the upper conductive layer but disconnecting from the first conductive layer.

[0014] In one embodiment of the present disclosure, the conductor pillar includes a first conductor pillar portion and a second conductor pillar portion, and the process of forming the conductor pillar includes the following steps: first, forming an opening hole in a first dielectric layer to expose a silicon region of a first terminal; second, forming the first conductor pillar portion on the silicon region of the first terminal by first selective epitaxial growth; and then forming the second conductor pillar portion on the first conductor pillar by second selective epitaxial growth.

[0015] In another aspect of the present disclosure, before the step of forming the second conductor pillar portion, the manufacturing method further includes the step of forming a first dielectric underlayer on the first dielectric layer, wherein an upper surface of the first dielectric underlayer has substantially the same level as an upper surface of the first conductor pillar portion.

[0016] In another aspect of the present disclosure, the width of the aperture hole is equal to the minimum feature size.

[0017] In another aspect of the present disclosure, the first conductor pillar portion and the second conductor pillar portion are both heavily doped silicon pillar portions.

[0018] In another aspect of the present disclosure, forming a first conductive layer includes depositing a first conductive material on a first dielectric layer, depositing a second dielectric underlayer on the first conductive material, and patterning the first conductive material and the second dielectric underlayer to form a first conductive layer, defining an opening through the first conductive layer and the second dielectric underlayer, with a conductor pillar passing through the opening.

[0019] In another embodiment of the present disclosure, the step of forming the upper dielectric layer includes the steps of: first, disposing an upper dielectric material over the first dielectric underlayer to fill the hollow opening, and then etching back the upper dielectric material so that the upper surface of the upper dielectric layer is lower than the upper surface of the conductor pillar.

[0020] In another aspect of the present disclosure, the width of the opening hollow is greater than the minimum feature size.

[0021] Yet another embodiment of the present disclosure provides an interconnect structure, the interconnect structure including a first dielectric layer, a first dielectric underlayer, a conductor pillar, and a first conductive layer. The first dielectric layer is disposed over a first terminal of a device. The first dielectric underlayer is disposed over the first dielectric layer. The conductor pillar is connected to the first terminal. The first conductive layer is disposed over the first dielectric underlayer and connected to the conductor pillar. The device is a transistor, and the first terminal of the device is a gate terminal including a gate dielectric layer, a gate conductive layer on the gate dielectric layer, and a silicon region on the gate conductive layer, and the conductor pillar is connected to the silicon region of the gate terminal.

[0022] In one embodiment of the present disclosure, the top surface of the conductor pillar is substantially flush with the top surface of the first dielectric underlayer.

[0023] In another aspect of the present disclosure, the conductor pillar includes a tungsten pillar and a TiN layer surrounding the tungsten pillar.

[0024] In another aspect of the present disclosure, the width of the conductor pillar is equal to the minimum feature size.

[0025] In another embodiment of the present disclosure, the device further includes a second terminal that functions as a drain terminal, and the wiring structure further includes another conductor pillar and another first conductive layer, the another conductor pillar connected to the drain terminal, and the another first conductive layer disposed on the first dielectric underlayer and connected to the another conductor pillar.

[0026] Yet another embodiment of the present disclosure provides a method for manufacturing an interconnect structure, the method comprising the steps of: forming a first dielectric layer over a first terminal and a second terminal of a device; forming a first silicon pillar through the first dielectric layer and connecting to the first terminal; and simultaneously forming a second silicon pillar through the first dielectric layer and connecting to the second terminal.

[0027] In another aspect of the present disclosure, both the first silicon pillar and the second silicon pillar comprise heavily doped silicon, and the method further comprises simultaneously forming a first connecting underlayer connected to the first silicon pillar and forming a second connecting underlayer connected to the second silicon pillar.

[0028] In another aspect of the present disclosure, the manufacturing method further includes replacing the first silicon pillar with a first conductor pillar and replacing the second silicon pillar with a second conductor pillar, wherein the first conductor pillar is connected to a first terminal and the second conductor pillar is connected to a second terminal.

[0029] In another aspect of the present disclosure, the manufacturing method further includes simultaneously forming a first connection underlayer connected to the first conductor pillar and forming a second connection underlayer connected to the second conductor pillar.

[0030] In another aspect of the present disclosure, the manufacturing method further includes forming a first dielectric underlayer on the first dielectric layer, and planarizing the first dielectric underlayer, the first silicon pillar, and the second silicon pillar so that an upper surface of the first dielectric underlayer is substantially at the same level as an upper surface of the first silicon pillar and an upper surface of the second silicon pillar.

[0031] In another embodiment of the present disclosure, the process of forming the first and second silicon pillars includes the steps of: first, forming an opening hole in a first dielectric layer to expose a silicon region of the first terminal and a silicon region of the second terminal; then, by selective epitaxial growth, forming the first silicon pillar on the silicon region of the first terminal and simultaneously forming the second silicon pillar on the silicon region of the second terminal.

[0032] Yet another embodiment of the present disclosure provides an interconnect structure, the interconnect structure including a first dielectric layer, a conductor pillar, a first heavily doped silicon pillar, and a first conductive layer. The first dielectric layer is disposed over a first terminal of a device. The conductor pillar is connected to the first terminal. The first heavily doped silicon pillar is disposed over the conductor pillar. The first conductive layer is disposed over the first dielectric layer and connected to the heavily doped silicon pillar.

[0033] In another aspect of the present disclosure, the wiring structure further includes a first dielectric liner layer on the first dielectric layer, and the first heavily doped silicon pillar is surrounded by the first dielectric liner layer.

[0034] In another aspect of the present disclosure, the conductor pillar includes a tungsten pillar and a TiN layer surrounding the tungsten pillar.

[0035] In another aspect of the present disclosure, the wiring structure further includes a heavily doped silicon side pillar disposed on the first heavily doped silicon pillar and connected to the first metal layer.

[0036] Yet another embodiment of the present disclosure provides a method for manufacturing an interconnect structure, the method comprising the steps of: forming a first dielectric layer over a first terminal of a device; forming a silicon pillar connected to the first terminal; replacing the silicon pillar with a conductor pillar and connecting the conductor pillar to the first terminal; replacing an upper portion of the conductor pillar with a first heavily doped silicon pillar; and forming a first conductive layer connected to the first heavily doped silicon pillar.

[0037] In another embodiment of the present disclosure, before the step of replacing the silicon pillar, the manufacturing method further includes the steps of: first, forming a first dielectric underlayer on the first dielectric layer, and then patterning the first dielectric layer and the silicon pillar so that the top surface of the first dielectric underlayer is substantially flush with the top surface of the silicon pillar.

[0038] In another aspect of the present disclosure, forming the silicon pillar includes forming an opening hole in the first dielectric layer to expose the silicon region of the first terminal, and forming the silicon pillar on the silicon region of the first terminal by selective epitaxial growth.

[0039] In another embodiment of the present disclosure, the conductor pillar includes a tungsten pillar and a TiN layer, and the process of replacing the silicon pillar with the conductor pillar includes the following steps: first, removing the silicon pillar to expose an opening hole, then forming a TiN layer in the opening hole, and then forming the tungsten pillar so as to be surrounded by the TiN layer.

[0040] In another aspect of the present disclosure, the manufacturing method further includes forming a side pillar on the first heavily doped silicon pillar and connecting to the first metal layer, the side pillar comprising a heavily doped silicon material.

[0041] Yet another embodiment of the present disclosure provides a wiring structure, the wiring structure including a first dielectric layer, a first conductor pillar, a first heavily doped silicon pillar, a first conductive layer, and a second conductor pillar. The first conductor pillar is surrounded by the first dielectric layer. The first heavily doped silicon pillar is disposed on the first conductor pillar. The first conductive layer is disposed on the first dielectric layer. The second conductor pillar is disposed on the first heavily doped silicon pillar and connected to the first conductive layer.

[0042] In another aspect of the present disclosure, the first conductor pillar, the first heavily doped silicon pillar, and the second conductor pillar are vertically self-aligned.

[0043] In another embodiment of the present disclosure, each of the first conductor pillar and the second conductor pillar includes a tungsten pillar and a TiN layer surrounding the tungsten pillar.

[0044] In another aspect of the present disclosure, the wiring structure further includes a first dielectric underlayer over the first dielectric layer and below the first conductive layer, and the first heavily doped silicon pillar is surrounded by the first dielectric underlayer.

[0045] In another aspect of the present disclosure, the wiring structure further includes a second highly doped silicon pillar on the second conductor pillar.

[0046] In another aspect of the present disclosure, the wiring structure further includes a second dielectric liner layer over the first conductive layer, and the second heavily doped silicon pillar is surrounded by the second dielectric liner layer.

[0047] Yet another embodiment of the present disclosure provides a wiring structure, the wiring structure including a lower conductive layer, a first conductor pillar, a first heavily doped silicon pillar, a lower dielectric layer, an upper conductive layer, and a second conductor pillar. The first conductor pillar is surrounded by and connected to the lower conductive layer. The first heavily doped silicon pillar is disposed on the first conductor pillar. The lower dielectric layer is disposed on the lower connection layer. The upper conductive layer is disposed on the lower dielectric layer. The second conductor pillar is disposed on the first heavily doped silicon pillar and surrounded by the upper conductive layer. The second conductor pillar is connected to the upper conductive layer.

[0048] In another aspect of the present disclosure, the first conductor pillar, the first heavily doped silicon pillar, and the second conductor pillar are vertically self-aligned.

[0049] In another aspect of the present disclosure, the wiring structure further includes a lower dielectric liner layer between the lower dielectric layer and the lower conductive layer, and the first heavily doped silicon pillar is surrounded by the lower dielectric liner layer.

[0050] In another aspect of the present disclosure, the wiring structure further includes a second highly doped silicon pillar on the second conductor pillar.

[0051] In another aspect of the present disclosure, the wiring structure further includes an upper dielectric liner layer over the upper conductive layer, and the second heavily doped silicon pillar is surrounded by the upper dielectric liner layer.

[0052] Yet another embodiment of the present disclosure provides a wiring structure, the wiring structure including: a first dielectric layer on a first conductive terminal; a first conductive layer on the first dielectric layer; a conductor pillar penetrating the first dielectric layer and connected to the first conductive terminal; an upper dielectric layer on the first conductive layer; and an upper conductive layer on the upper dielectric layer, wherein the conductor pillar penetrates the upper dielectric layer and connects to the upper conductive layer, but the conductor pillar is not electrically connected to the first conductive layer.

[0053] In another aspect of the present disclosure, the wiring structure further comprises a plurality of intermediate conductive layers between the first conductive layer and the upper conductive layer, each of the intermediate conductive layers being vertically shifted relative to one another, and no conductor pillar electrically connecting the plurality of intermediate conductive layers.

[0054] In another aspect of the present disclosure, the conductor pillar comprises a first conductor pillar portion and a second conductor pillar portion, the first conductor pillar portion being surrounded by a first dielectric layer and the second conductor pillar portion being surrounded by an upper dielectric layer.

[0055] In another aspect of the present disclosure, the first conductor pillar portion is formed based on a seed region of the first conductive terminal, and the second conductor pillar portion is formed based on the seed region of the first conductor pillar portion.

[0056] In another aspect of the present disclosure, the seed region of the first conductive terminal is composed of polycrystalline silicon or amorphous silicon.

[0057] In another aspect of the present disclosure, the first conductor pillar portion is formed by selective epitaxial growth based on polycrystalline silicon or amorphous silicon of the first conductive terminal.

[0058] In another aspect of the present disclosure, the first conductive terminal is a gate terminal of a semiconductor transistor in a semiconductor substrate, the gate terminal comprising a gate dielectric layer, a gate metal layer on the gate dielectric layer, and a silicon region on the gate metal layer.

[0059] In another aspect of the present disclosure, the first conductive terminal is a gate terminal of a semiconductor transistor in the semiconductor substrate, the gate terminal comprising a gate dielectric layer and a gate polysilicon layer on the gate dielectric layer.

[0060] In another aspect of the present disclosure, the first conductive terminal is a drain or source terminal of a semiconductor transistor.

[0061] In another aspect of the present disclosure, the first conductive terminal is a lower conductive layer on a semiconductor transistor in a semiconductor substrate, the lower conductive layer comprising a metal region and a seed region electrically coupled to the metal region.

[0062] In another aspect of the present disclosure, the seed region of the lower conductive layer is composed of heavily doped silicon.

[0063] Yet another embodiment of the present disclosure provides a wiring structure, the wiring structure including: a semiconductor transistor formed based on a semiconductor substrate, the semiconductor transistor having a gate terminal and a drain terminal; a first conductor pillar provided on the semiconductor transistor and extending upward; a seed pillar provided on the first conductor pillar and electrically connected to the first conductor pillar; a second conductor pillar provided on the seed pillar and extending upward; and an upper conductive layer provided on the second conductor pillar and electrically connected to the second conductor pillar, wherein the seed pillar is sandwiched between the first conductor pillar and the second conductor pillar.

[0064] In another aspect of the present disclosure, the seed pillar is composed of heavily doped silicon.

[0065] In another aspect of the present disclosure, the first conductor pillar is electrically connected to the gate terminal or the drain terminal of the transistor.

[0066] In another aspect of the present disclosure, the wiring structure further comprises a lower conductive layer above the semiconductor transistor and below the upper conductive layer, the lower conductive layer being electrically insulated from the first conductor pillar and the second conductor pillar.

[0067] In another aspect of the present disclosure, the wiring structure further comprises a lower conductive layer above the semiconductor transistor and below the upper conductive layer, the lower conductive layer electrically connected to the first conductor pillar.

[0068] In another aspect of the present disclosure, the wiring structure further comprises an intermediate conductive layer between the lower conductive layer and the upper conductive layer, the intermediate conductive layer being electrically insulated from the first conductor pillar and the second conductor pillar.

[0069] Yet another embodiment of the present disclosure is to provide a wiring structure, the wiring structure including: a first dielectric layer on a first conductive terminal; a conductor pillar penetrating the first dielectric layer and connected to the first conductive terminal; a seed pillar disposed on the conductor pillar and electrically connected to the conductor pillar; and a first conductive layer disposed on the first dielectric layer and electrically connected to the seed pillar.

[0070] In another aspect of the present disclosure, the wiring structure further comprises a side pillar disposed on the seed pillar and electrically connected to the first conductive layer.

[0071] In another embodiment of the present disclosure, the seed pillar or the side pillar is made of heavily doped silicon, the side pillar is selectively grown using the seed pillar as a base, and the first conductive layer is made of metal.

[0072] In another aspect of the present disclosure, the first dielectric layer includes a dielectric underlayer, the seed pillar is surrounded by the dielectric underlayer, the top surface of the seed pillar is aligned with the top surface of the dielectric underlayer, and the top surface of the side pillar is higher than the top surface of the dielectric underlayer.

[0073] In another aspect of the present disclosure, the first conductive terminal is a lower conductive layer on a semiconductor transistor in a semiconductor substrate, the lower conductive layer comprising a metal region and a seed region electrically coupled to the metal region.

[0074] In another aspect of the present disclosure, the seed region of the lower conductive layer is composed of heavily doped silicon.

[0075] In another aspect of the present disclosure, the first conductive terminal is a gate terminal of a semiconductor transistor in a semiconductor substrate, the gate terminal comprising a gate dielectric layer, a gate metal layer on the gate dielectric layer, and a seed region on the gate metal layer.

[0076] In another aspect of the present disclosure, the seed region of the gate terminal is composed of heavily doped silicon.

[0077] Yet another embodiment of the present disclosure provides an interconnect structure, the interconnect structure including: a first dielectric layer on a gate terminal of a semiconductor transistor formed on a semiconductor substrate; a conductor pillar penetrating the first dielectric layer and connected to the gate terminal; and a first conductive layer provided on the first dielectric layer and electrically connected to the conductor pillar, wherein the gate terminal comprises the gate dielectric layer and a seed region on the gate dielectric layer.

[0078] In another aspect of the present disclosure, the conductor pillar is selectively grown based on the seed region of the gate terminal.

[0079] In another aspect of the present disclosure, the conductor pillars are composed of heavily doped silicon.

[0080] In another aspect of the present disclosure, the gate terminal further comprises a gate metal layer between the gate dielectric layer and the seed region.

[0081] In another aspect of the present disclosure, the wiring structure further comprises a seed pillar on the conductor pillar, the seed pillar electrically connected to the conductor pillar and the first conductive layer.

[0082] In another aspect of the present disclosure, the conductor pillar comprises a tungsten pillar and a TiN layer surrounding the tungsten pillar.

[0083] Yet another embodiment of the present disclosure provides a wiring structure, the wiring structure comprising: a semiconductor transistor formed based on a semiconductor substrate, the semiconductor transistor having a gate terminal and a drain terminal; a first conductor pillar provided on the semiconductor transistor and extending upward, the first conductor pillar having a first seed region; and a second conductor pillar provided on the first conductor pillar and extending upward, the second conductor pillar having a second seed region, the second conductor pillar having a bottom surface self-aligned with the top surface of the first conductor pillar.

[0084] In another aspect of the present disclosure, the first conductor pillar is composed of heavily doped silicon and the first seed region is an uppermost region of heavily doped silicon.

[0085] In another aspect of the present disclosure, the first conductor pillar further comprises a first tungsten pillar and a first TiN layer surrounding the first tungsten pillar, and the first seed region is composed of heavily doped silicon and is present on the first tungsten pillar.

[0086] In another aspect of the present disclosure, the bottom surface of the second conductor pillar is self-aligned with the top surface of the first seed region.

[0087] In another aspect of the present disclosure, a wiring structure includes a third conductor pillar disposed on the second conductor pillar and extending upward, the third conductor pillar including a third seed region, the second conductor pillar further including a second tungsten pillar and a second TiN layer surrounding the second tungsten pillar, the second seed region being composed of heavily doped silicon and located in the second tungsten pillar, and the bottom surface of the third conductor pillar being self-aligned with the top surface of the second seed region.

[0088] In another aspect of the present disclosure, the wiring structure further comprises a lower conductive layer over the semiconductor transistor and an upper conductive layer over the lower conductive layer, wherein the first conductor pillar is electrically connected to a gate terminal or a drain terminal of the semiconductor transistor, the third conductor pillar is electrically connected to the upper conductive layer, and the lower conductive layer is electrically insulated from the first conductor pillar, the second conductor pillar, and the third conductor pillar.

[0089] In another aspect of the present disclosure, the wiring structure further comprises a lower conductive layer above the semiconductor transistor, an upper conductive layer above the lower conductive layer, and an intermediate conductive layer between the lower conductive layer and the upper conductive layer, wherein the first conductor pillar is electrically connected to the lower conductive layer and the third conductor pillar is electrically connected to the upper conductive layer, and the intermediate conductive layer is electrically insulated from the first conductor pillar, the second conductor pillar, and the third conductor pillar.

[0090] Thus, the exemplary embodiments significantly improve the interconnect structure and wiring between devices to form an efficient interconnect system on a die for completing an integrated circuit. The first exemplary embodiment allows either gate regions or diffusion (source / drain) regions to be directly connected to the M2 wiring layer in a self-aligned manner without the transition layer M1 through a single vertical conductive plug consisting of Contact A and Via 1A, respectively, formed in the construction phase of Contact and Via 1 at another location on the same die. This embodiment can also be applied to allow the M1 wiring or conductive layer to be directly connected to the MX wiring layer (without the transition conductive layers M2, M3, ... MX-1) in a self-aligned manner through a single vertical conductive or conductor plug.

[0091] Another exemplary embodiment is a landing pad created by a vertical conductor pillar connecting either the gate or the diffusion region, respectively, to a plane that is effectively created for landing the metal M1 wiring layer, thereby avoiding the contact material having to go through a very rough surface topography inside the contact hole region, which has a high aspect ratio of depth to opening hole.

[0092] Another exemplary embodiment is that M1 can be connected to the contact in a self-aligned manner without the need for a mask or design that provides an extra M1 boundary between the M1 width and the contact width.

[0093] Another exemplary embodiment is to form Via 1 precisely on the top surface of the contact in a self-aligned manner (similarly Via 2 above Via 1 can also be precisely self-aligned with each other, and then Via 3 above Via 2), while all layers M1, M2, etc. retain their respective connection functions and complete individual wiring under Via 1 and the contact with the smallest footprint area, and the benefit can be extended to all via layers from top to bottom. The present invention discloses a method to self-align from the bottom wiring layer to the upper wiring layer and realize vertical connection between them, which is different from the conventional method of aligning from the upper wiring layer to the bottom wiring layer. [Brief explanation of the drawings]

[0094] These and other aspects of the present disclosure will be better understood from a reading of the following detailed description of the preferred, but non-limiting, embodiment(s), which is / are described below with reference to the accompanying drawings.

[0095] [Figure 1A(1)] 1A-1C are a series of top and cross-sectional views illustrating a method of manufacturing a device having a transistor structure according to an embodiment of the present disclosure. [Figure 1A(2)] 1A-1C are a series of top and cross-sectional views illustrating a method of manufacturing a device having a transistor structure according to an embodiment of the present disclosure. [Figure 1A(3)] 1A-1C are a series of top and cross-sectional views illustrating a method of manufacturing a device having a transistor structure according to an embodiment of the present disclosure. [Figure 1B(1)] 1A-1C are a series of top and cross-sectional views illustrating a method of manufacturing a device having a transistor structure according to an embodiment of the present disclosure. [Figure 1B(2)]1A-1C are a series of top and cross-sectional views illustrating a method of manufacturing a device having a transistor structure according to an embodiment of the present disclosure. [Figure 1B(3)] 1A-1C are a series of top and cross-sectional views illustrating a method of manufacturing a device having a transistor structure according to an embodiment of the present disclosure. [Figure 1C(1)] 1A-1C are a series of top and cross-sectional views illustrating a method of manufacturing a device having a transistor structure according to an embodiment of the present disclosure. [Figure 1C(2)] 1A-1C are a series of top and cross-sectional views illustrating a method of manufacturing a device having a transistor structure according to an embodiment of the present disclosure. [Figure 1C(3)] 1A-1C are a series of top and cross-sectional views illustrating a method of manufacturing a device having a transistor structure according to an embodiment of the present disclosure. [Figure 1D(1)] 1A-1C are a series of top and cross-sectional views illustrating a method of manufacturing a device having a transistor structure according to an embodiment of the present disclosure. [Figure 1D(2)] 1A-1C are a series of top and cross-sectional views illustrating a method of manufacturing a device having a transistor structure according to an embodiment of the present disclosure. [Figure 1D(3)] 1A-1C are a series of top and cross-sectional views illustrating a method of manufacturing a device having a transistor structure according to an embodiment of the present disclosure. [Figure 1E(1)] 1A-1C are a series of top and cross-sectional views illustrating a method of manufacturing a device having a transistor structure according to an embodiment of the present disclosure. [Figure 1E(2)] 1A-1C are a series of top and cross-sectional views illustrating a method of manufacturing a device having a transistor structure according to an embodiment of the present disclosure. [Figure 1E(3)] 1A-1C are a series of top and cross-sectional views illustrating a method of manufacturing a device having a transistor structure according to an embodiment of the present disclosure. [Figure 1F(1)] 1A-1C are a series of top and cross-sectional views illustrating a method of manufacturing a device having a transistor structure according to an embodiment of the present disclosure. [Figure 1F(2)] 1A-1C are a series of top and cross-sectional views illustrating a method of manufacturing a device having a transistor structure according to an embodiment of the present disclosure. [Figure 1F(3)] 1A-1C are a series of top and cross-sectional views illustrating a method of manufacturing a device having a transistor structure according to an embodiment of the present disclosure. [Figure 1G(1)] 1A-1C are a series of top and cross-sectional views illustrating a method of manufacturing a device having a transistor structure according to an embodiment of the present disclosure. [Figure 1G(2)] 1A-1C are a series of top and cross-sectional views illustrating a method of manufacturing a device having a transistor structure according to an embodiment of the present disclosure. [Figure 1G(3)] 1A-1C are a series of top and cross-sectional views illustrating a method of manufacturing a device having a transistor structure according to an embodiment of the present disclosure. [Figure 1H(1)] 1A-1C are a series of top and cross-sectional views illustrating a method of manufacturing a device having a transistor structure according to an embodiment of the present disclosure. [Figure 1H(2)] 1A-1C are a series of top and cross-sectional views illustrating a method of manufacturing a device having a transistor structure according to an embodiment of the present disclosure. [Figure 1H(3)] 1A-1C are a series of top and cross-sectional views illustrating a method of manufacturing a device having a transistor structure according to an embodiment of the present disclosure. [Figure 2A(1)] 1A-1C are a series of top and cross-sectional views illustrating a manufacturing method for forming a device having a transistor structure according to another embodiment of the present disclosure. [Figure 2A(2)] 1A-1C are a series of top and cross-sectional views illustrating a manufacturing method for forming a device having a transistor structure according to another embodiment of the present disclosure. [Figure 2A(3)] 1A-1C are a series of top and cross-sectional views illustrating a manufacturing method for forming a device having a transistor structure according to another embodiment of the present disclosure. [Figure 2B(1)]1A-1C are a series of top and cross-sectional views illustrating a manufacturing method for forming a device having a transistor structure according to another embodiment of the present disclosure. [Figure 2B(2)] 1A-1C are a series of top and cross-sectional views illustrating a manufacturing method for forming a device having a transistor structure according to another embodiment of the present disclosure. [Figure 2B(3)] 1A-1C are a series of top and cross-sectional views illustrating a manufacturing method for forming a device having a transistor structure according to another embodiment of the present disclosure. [Figure 2C(1)] 1A-1C are a series of top and cross-sectional views illustrating a manufacturing method for forming a device having a transistor structure according to another embodiment of the present disclosure. [Figure 2C(2)] 1A-1C are a series of top and cross-sectional views illustrating a manufacturing method for forming a device having a transistor structure according to another embodiment of the present disclosure. [Figure 2C(3)] 1A-1C are a series of top and cross-sectional views illustrating a manufacturing method for forming a device having a transistor structure according to another embodiment of the present disclosure. [Figure 3A(1)] 10A-10C are a series of top and cross-sectional views illustrating a manufacturing method for forming another device having a transistor structure according to yet another embodiment of the present disclosure. [Figure 3A(2)] 10A-10C are a series of top and cross-sectional views illustrating a manufacturing method for forming another device having a transistor structure according to yet another embodiment of the present disclosure. [Figure 3A(3)] 10A-10C are a series of top and cross-sectional views illustrating a manufacturing method for forming another device having a transistor structure according to yet another embodiment of the present disclosure. [Figure 3B(1)] 10A-10C are a series of top and cross-sectional views illustrating a manufacturing method for forming another device having a transistor structure according to yet another embodiment of the present disclosure. [Figure 3B(2)] 10A-10C are a series of top and cross-sectional views illustrating a manufacturing method for forming another device having a transistor structure according to yet another embodiment of the present disclosure. [Figure 3B(3)]10A-10C are a series of top and cross-sectional views illustrating a manufacturing method for forming another device having a transistor structure according to yet another embodiment of the present disclosure. [Figure 4A(1)] 10A-10C are a series of top and cross-sectional views illustrating a manufacturing method for forming another device having a transistor structure according to yet another embodiment of the present disclosure. [Figure 4A(2)] 10A-10C are a series of top and cross-sectional views illustrating a manufacturing method for forming another device having a transistor structure according to yet another embodiment of the present disclosure. [Figure 4A(3)] 10A-10C are a series of top and cross-sectional views illustrating a manufacturing method for forming another device having a transistor structure according to yet another embodiment of the present disclosure. [Figure 4B(1)] 10A-10C are a series of top and cross-sectional views illustrating a manufacturing method for forming another device having a transistor structure according to yet another embodiment of the present disclosure. [Figure 4B(2)] 10A-10C are a series of top and cross-sectional views illustrating a manufacturing method for forming another device having a transistor structure according to yet another embodiment of the present disclosure. [Figure 4B(3)] 10A-10C are a series of top and cross-sectional views illustrating a manufacturing method for forming another device having a transistor structure according to yet another embodiment of the present disclosure. [Figure 5(1)] 10A-10C are top and cross-sectional views illustrating a manufacturing method for forming another device having a transistor structure according to yet another embodiment of the present disclosure. [Figure 5(2)] 10A-10C are top and cross-sectional views illustrating a manufacturing method for forming another device having a transistor structure according to yet another embodiment of the present disclosure. [Figure 5(3)] 10A-10C are top and cross-sectional views illustrating a manufacturing method for forming another device having a transistor structure according to yet another embodiment of the present disclosure. [Figure 6A(1)] 10A-10C are a series of top and cross-sectional views illustrating a manufacturing method for forming another device having a transistor structure according to yet another embodiment of the present disclosure. [Figure 6A(2)]10A-10C are a series of top and cross-sectional views illustrating a manufacturing method for forming another device having a transistor structure according to yet another embodiment of the present disclosure. [Figure 6A(3)] 10A-10C are a series of top and cross-sectional views illustrating a manufacturing method for forming another device having a transistor structure according to yet another embodiment of the present disclosure. [Figure 6B(1)] 10A-10C are a series of top and cross-sectional views illustrating a manufacturing method for forming another device having a transistor structure according to yet another embodiment of the present disclosure. [Figure 6B(2)] 10A-10C are a series of top and cross-sectional views illustrating a manufacturing method for forming another device having a transistor structure according to yet another embodiment of the present disclosure. [Figure 6B(3)] 10A-10C are a series of top and cross-sectional views illustrating a manufacturing method for forming another device having a transistor structure according to yet another embodiment of the present disclosure. [Figure 6B(4)] 10A-10C are a series of top and cross-sectional views illustrating a manufacturing method for forming another device having a transistor structure according to yet another embodiment of the present disclosure. [Figure 6B(5)] 10A-10C are a series of top and cross-sectional views illustrating a manufacturing method for forming another device having a transistor structure according to yet another embodiment of the present disclosure. [Figure 6C(1)] 10A-10C are a series of top and cross-sectional views illustrating a manufacturing method for forming another device having a transistor structure according to yet another embodiment of the present disclosure. [Figure 6C(2)] 10A-10C are a series of top and cross-sectional views illustrating a manufacturing method for forming another device having a transistor structure according to yet another embodiment of the present disclosure. [Figure 6C(3)] 10A-10C are a series of top and cross-sectional views illustrating a manufacturing method for forming another device having a transistor structure according to yet another embodiment of the present disclosure. [Figure 7A(1)] 10A-10C are a series of top and cross-sectional views illustrating a manufacturing method for forming another device having a transistor structure according to yet another embodiment of the present disclosure. [Figure 7A(2)]10A-10C are a series of top and cross-sectional views illustrating a manufacturing method for forming another device having a transistor structure according to yet another embodiment of the present disclosure. [Figure 7A(3)] 10A-10C are a series of top and cross-sectional views illustrating a manufacturing method for forming another device having a transistor structure according to yet another embodiment of the present disclosure. [Figure 7B(1)] 10A-10C are a series of top and cross-sectional views illustrating a manufacturing method for forming another device having a transistor structure according to yet another embodiment of the present disclosure. [Figure 7B(2)] 10A-10C are a series of top and cross-sectional views illustrating a manufacturing method for forming another device having a transistor structure according to yet another embodiment of the present disclosure. [Figure 7B(3)] 10A-10C are a series of top and cross-sectional views illustrating a manufacturing method for forming another device having a transistor structure according to yet another embodiment of the present disclosure. [Figure 7B(4)] 10A-10C are a series of top and cross-sectional views illustrating a manufacturing method for forming another device having a transistor structure according to yet another embodiment of the present disclosure. [Figure 7B(5)] 10A-10C are a series of top and cross-sectional views illustrating a manufacturing method for forming another device having a transistor structure according to yet another embodiment of the present disclosure. [Figure 7C(1)] 10A-10C are a series of top and cross-sectional views illustrating a manufacturing method for forming another device having a transistor structure according to yet another embodiment of the present disclosure. [Figure 7C(2)] 10A-10C are a series of top and cross-sectional views illustrating a manufacturing method for forming another device having a transistor structure according to yet another embodiment of the present disclosure. [Figure 7C(3)] 10A-10C are a series of top and cross-sectional views illustrating a manufacturing method for forming another device having a transistor structure according to yet another embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0096] The present disclosure provides wiring structures and methods for fabricating the same. These and other aspects of the disclosure will become better understood from the following detailed description of preferred, but non-limiting, embodiment(s), as described below with reference to the accompanying drawings.

[0097] Several embodiments of the present disclosure are disclosed below with reference to the accompanying drawings. However, the structures and contents disclosed in the embodiments are for the purpose of illustration and description only, and the scope of protection of the present disclosure is not limited to the embodiments. It should be noted that the present disclosure does not illustrate all possible embodiments, and a person skilled in the art of the present disclosure would be able to make appropriate modifications or changes based on the specifications disclosed below to meet actual needs without departing from the spirit of the present disclosure. The present disclosure is also applicable to other embodiments not disclosed herein.

[0098] The following embodiments will be described by forming an interconnect structure of the device 10. In some embodiments of the present disclosure, the transistor structure 100 taken as an example may be an NMOS transistor, which can be similarly derived as a PMOS transistor structure, except that it has materials that are doped or formed in the opposite direction as opposed to the materials of the NMOS transistor.

[0099] Embodiment 1 According to one embodiment of the present disclosure, a method for forming a device 10 having a transistor structure 100 includes the following steps. Step S11: Form a first dielectric layer on a first terminal of the device. Step S12: A conductor pillar connected to the first terminal is formed. Step S121: An opening hole is formed in the first dielectric layer to expose the silicon region of the first terminal. Step S122: A first conductive pillar portion is formed on the silicon region of the first terminal by first selective epitaxial growth. Step S123: A first dielectric underlayer is formed on the first dielectric layer, and the upper surface of the first dielectric underlayer has substantially the same level as the upper surface of the first conductor pillar portion (e.g., is planarized by a CMP process or an etching process). Step S124: A second conductor pillar portion is formed on the first conductor pillar by second selective epitaxial growth. Step S13: Form a first conductive layer on the first dielectric layer. Step S131: Deposit a first conductive material on the first dielectric layer. Step S132: Depositing a second dielectric underlayer on the first conductive material. Step S133: The first conductive material and the second dielectric underlayer are patterned to form a first conductive layer, and an opening hollow is defined through the first conductive layer and the second dielectric underlayer, and the conductive pillar penetrates the opening hollow. Step S14: Form at least one upper dielectric layer on the first conductive layer. Step S141: Depositing an upper dielectric material to cover the first dielectric underlayer and fill the opening hollow. Step S142: Etch back the upper dielectric material so that the top surface of the upper dielectric layer is lower than the top surface of the conductor pillar. Step S15: Form an upper conductive layer on the upper dielectric layer, and the conductor pillar connects to the upper conductive layer but is disconnected from the first conductive layer.

[0100] See step S11: forming a first dielectric layer 120 on a first conductive terminal (gate, drain or source) of the device 10. Figure 1A(1) is a top view illustrating the structure after forming the first dielectric layer 120 on a transistor structure 100 previously formed in a semiconductor substrate 101, according to one embodiment of the present disclosure. Figure 1A(2) is a cross-sectional view taken along the cutting line C1A1 depicted in Figure 1A(1). Figure 1A(3) is a cross-sectional view taken along the cutting line C1A2 depicted in Figure 1A(1).

[0101] In this embodiment, a semiconductor substrate 101 includes a silicon layer, such as a polycrystalline silicon layer or an amorphous silicon layer. As shown in FIGS. 1A(1) to 1A(3), a transistor structure 100 is formed in an active region of the silicon layer defined by a shallow trench isolator (STI) 105. The transistor structure 100 has a gate terminal 102 formed on the active region, a transistor channel region 103 formed in the active region below the gate terminal 102, and source / drain regions 104 formed in the active region and adjacent to the transistor channel region 103.

[0102] The gate terminal 102 includes a gate dielectric layer 102a, a gate conductive layer 102b formed on the gate dielectric layer 102a, and a silicon region 102c formed on the gate conductive layer 102b. In some embodiments of the present disclosure, the gate dielectric layer 102a may be composed of an oxide or a low-k dielectric, the gate conductive layer 102b may be composed of a metal (but is not limited in this respect), and the silicon region 102c may be composed of polycrystalline silicon or amorphous silicon. In some embodiments, the gate terminal 102 further includes a capping layer (e.g., a nitride layer) on an upper surface of the silicon region 102c and at least one spacer (e.g., including a nitride spacer 102s1 and a thermal oxide spacer 102s2) on sidewalls of the gate dielectric layer 102a, the gate conductive layer 102b, and the silicon region 102c. The top surface portion of silicon region 102 c can serve as exposed top surface portion 11 , and exposed top surface portion 12 can be the drain terminal of source / drain region 104 .

[0103] A first dielectric layer 120 is formed on the semiconductor substrate 101 to at least cover the active area of ​​the transistor structure 100, including the gate terminal 102 and the source / drain regions 104 and the STI 105. In some embodiments of the present disclosure, the first dielectric layer 120 is composed of an oxide or a low-k dielectric.

[0104] See step S12: forming a conductor pillar (e.g., the first conductor pillar 130A) connected to the exposed upper surface portion 11. In this embodiment, the formation of the conductor pillar (e.g., the first conductor pillar 130A) includes the following steps: First, a plurality of opening holes (opening holes 107a and 107b) are formed in the first dielectric layer 120 to expose the upper surface portion of the silicon 102c region (see step S121).

[0105] Figure 1B(1) is a top view showing the structure after forming the opening holes 107a and 107b in the first dielectric layer 120 according to one embodiment of the present disclosure. Figure 1B(2) is a cross-sectional view taken along the cutting line C1B1 depicted in Figure 1B(1). Figure 1B(2) is a cross-sectional view taken along the cutting line C1B2 depicted in Figure 1B(1).

[0106] In some embodiments, the opening holes 107a and 107b are formed by partially removing the first dielectric layer 120 through a photolithography process to expose a portion of the silicon region 102c (which serves as the exposed top surface portion or first terminal 11) and a silicon region of the drain terminal of the source / drain region 104 (which serves as the exposed top surface portion or second terminal 12). In one embodiment, the first terminal 11 and the second terminal 12 are the uppermost regions of the gate terminal and the source / drain terminal, respectively. In one example, each of the opening holes 107a and 107b can be sized equal to a minimum feature size (e.g., a critical size of the transistor structure 100 of the device 10). Of course, the size of the opening holes 107a, 107b may be larger than the minimum feature size.

[0107] 1B(1)-1B(3), the gate (i.e., gate terminal 102) and diffusion regions (i.e., source / drain regions 104) of a transistor structure 100 (e.g., a MOSFET) are exposed through openings 107a and 107b, respectively, surrounded by an insulator (e.g., a first dielectric layer 120). The bottoms of openings 107a and 107b (i.e., exposed top surface portions 11 and 12) are made of either polycrystalline / amorphous silicon or highly doped crystalline silicon with high conductivity.

[0108] A method for forming a plurality of opening holes 107a and 107b over the gate (i.e., gate terminal 102) and diffusion (i.e., source / drain regions 104) regions has been previously disclosed in U.S. Application No. 17 / 468,683 (titled "TRANSISTOR STRUCTURE WITH METAL INTERCONNECTION DIRECTLY CONNECTING GATE AND DRAIN / SOURCE REGIONS"), filed on September 8, 2021 by the same inventor as the present invention. The entire contents of the aforementioned U.S. application are incorporated herein by reference.

[0109] See step S122: By selective epitaxial growth (SEG), a first conductor pillar portion (or a first sub-conductor pillar portion) 131a is formed on the silicon region 102c of the exposed upper surface portion 11 (exposed through the opening hole 107a), and simultaneously, a third conductor pillar portion (or a third sub-conductor pillar portion) 131b is formed on the silicon region of the exposed upper surface portion 12 (the drain terminal of the source / drain region 104) exposed through the opening hole 107b by the same SEG. FIG. 1C(1) is a top view showing the structure after the first conductor pillar portion 131a and the third conductor pillar portion 131b are formed in the opening holes 107a and 107b, respectively, according to one embodiment of the present disclosure. FIG. 1C(2) is a cross-sectional view taken along the cutting line C1C1 depicted in FIG. 1C(1). 1C(2) is a cross-sectional view taken along the cutting line C1C2 drawn in FIG. 1C(1). The exposed silicon region 102c of the gate terminal and the exposed silicon region of the source / drain terminal are seed regions for growing seed-based pillars by selective epitaxial growth (SEG) technique.

[0110] In this embodiment, SEG (or selective atomic layer deposition) is used to grow heavily doped conductive silicon plugs (or conductor pillars) based on the exposed top surface portion 11 and the exposed top surface portion 12 to form the first conductor pillar portion 131a and the third conductor pillar portion 131b. Here, the first conductor pillar portion 131a and the third conductor pillar portion 131b each have a top surface 131t that is higher than the top of the first dielectric layer 120.

[0111] Then, a first dielectric underlayer 140 is formed on the first dielectric layer 120, so that the upper surface 140s of the first dielectric underlayer 140 is substantially flush with the upper surfaces 131t of the first conductor pillar portion 131a and the third conductor pillar portion 131b (see step S123). FIG. 1D(1) is a top view showing a structure after the first dielectric underlayer 140 is formed on the first dielectric layer 120 according to an embodiment of the present disclosure. FIG. 1D(2) is a cross-sectional view taken along the cutting line C1D1 depicted in FIG. 1D(1). FIG. 1D(3) is a cross-sectional view taken along the cutting line C1D2 depicted in FIG. 1C(1). Here, the upper surface 140s of the formed first dielectric underlayer 140 is substantially flush with the upper surfaces 131t of the first conductor pillar portion 131a and the third conductor pillar portion 131b.

[0112] In some embodiments, forming the first dielectric underlayer 140 may include the following steps: depositing a dielectric material (not shown), such as silicon oxide, silicon nitride, a low-k dielectric, or other suitable material, on the first dielectric layer 120 to cover the top surfaces 131t of the first and third conductor pillar portions 131a and 131b; and performing a planarization process, such as a chemical mechanical polishing (CMP) process or an etch-back process, using the top surfaces 131t of the first and third conductor pillar portions 131a and 131b as a stop layer to remove portions of the dielectric material and expose the top surfaces 131t of the first and third conductor pillar portions 131a and 131b. The "exposed heads" of the first and third conductor pillar portions 131a and 131b (the exposed top surfaces 131t of the first and third conductor pillar portions 131a and 131b) can be used as landing pads in a subsequent process for forming a wiring structure. Furthermore, each of the first and third conductor pillar portions 131a and 131b has a seed region or seed pillar in its upper portion, which can be used for subsequent selective epitaxial growth.

[0113] Next, a second conductor pillar portion (or a second sub-conductor pillar portion) 132a is formed on the first conductor pillar portion 131a by second selective epitaxial growth (see step S123), and simultaneously, a fourth conductor pillar portion (or a fourth sub-conductor pillar portion) 132b is formed on the third conductor pillar portion 131b. FIG. 1E(1) is a top view showing a structure after the second conductor pillar portion 132a and the fourth conductor pillar portion 132b are formed on the first conductor pillar portion 131a and the third conductor pillar portion 131b according to an embodiment of the present disclosure. FIG. 1E(2) is a cross-sectional view taken along the cutting line C1E1 in FIG. 1E(1). FIG. 1E(3) is a cross-sectional view taken along the cutting line C1E2 in FIG. 1E(1).

[0114] In some embodiments of the present disclosure, the process for forming the second conductor pillar portion 132a and the fourth conductor pillar portion 132b can be (but is not limited to) the same as the process for forming the first conductor pillar portion 131a and the third conductor pillar portion 131b. In this embodiment, the second conductor pillar portion 132a and the fourth conductor pillar portion 132b can be heavily doped conductive silicon plugs grown from the upper surfaces 131t of the first conductor pillar portion 131a and the third conductor pillar portion 131b by SEG and extending upward beyond the upper surface 140s of the first dielectric underlayer 140. The second conductor pillar portion 132a and the fourth conductor pillar portion 132b have dopant concentrations different from (or the same as) those of the first conductor pillar portion 131a and the third conductor pillar portion 131b. The first conductor pillar portion 131a and the second conductor pillar portion 132a together form the first conductor pillar portion 130A, and the third conductor pillar portion 131b and the fourth conductor pillar portion 132b together form the second conductor pillar portion 130B.

[0115] See step S13: forming a first conductive layer 150 on the first dielectric layer. Figure 1F(1) is a top view illustrating the structure after forming the first conductive layer 150 on the first dielectric layer 120 according to one embodiment of the present disclosure. Figure 1F(2) is a cross-sectional view taken along the cutting line C1F1 depicted in Figure 1F(1). Figure 1F(3) is a cross-sectional view taken along the cutting line C1F2 depicted in Figure 1F(1).

[0116] In this embodiment, the formation of the first conductive layer 150 includes the following steps: A first conductive material (not shown), such as copper (Cu), aluminum (Al), tungsten (W), or other suitable conductive material, may be deposited on the upper surface 140s of the first dielectric underlayer 140 on the first dielectric layer (see step S131). Subsequently, a second dielectric underlayer 160 is deposited on the first conductive material (see step S132). The first conductive material and the second dielectric underlayer 160 are patterned to form the first conductive layer 150, defining an open hollow 109 that passes through the first conductive layer 150 and the second dielectric underlayer 160, and the first conductor pillar 130A penetrates the open hollow 109 without contacting the first conductive layer 150 and the second dielectric underlayer 160 (see step S133).

[0117] In some embodiments of the present disclosure, the first conductive layer 150 and the second dielectric liner layer 160 can be formed before forming the second conductor pillar portion 132 a and the fourth conductor pillar portion 132 b. In this case, the open hollow 109 can be defined by an etching process that passes through the first conductive layer 150 and the second dielectric liner layer 160 to expose the top surfaces 131 t of the first conductor pillar portion 131 a and the third conductor pillar portion 131 b before forming the second conductor pillar portion 132 a and the fourth conductor pillar portion 132 b.

[0118] See step S14: forming at least one upper dielectric layer 170 on the first conductive layer 150. FIG. 1G(1) is a top view illustrating the structure after forming the upper dielectric layer 170 on the first conductive layer 150 according to one embodiment of the present disclosure. FIG. 1G(2) is a cross-sectional view taken along the cutting line C1G1 depicted in FIG. 1G(1). FIG. 1G(3) is a cross-sectional view taken along the cutting line C1G2 depicted in FIG. 1G(1).

[0119] In this embodiment, the formation of the upper dielectric layer 170 includes the following steps. First, at least one layer of upper dielectric material (not shown) is deposited to cover the second dielectric underlayer 160 and the first dielectric underlayer 140 (portions of the upper surfaces 140s exposed from the hollow openings 109) to fill the hollow openings 109 (see step S141). Then, the upper dielectric material is etched back so that the upper surface 170s of the upper dielectric layer 170 is lower than the upper surfaces 130t of the first conductor pillars 130A and the second conductor pillars 130B (see step S142).

[0120] See step S15: forming an upper conductive layer 180 on the upper dielectric layer 170; the first conductor pillar 130A connects to the upper conductive layer 180 but is disconnected from the first conductive layer 150. FIG. 1H(1) is a top view illustrating the structure after forming the conductive layer 180 on the upper dielectric layer 170 according to one embodiment of the present disclosure. FIG. 1H(2) is a cross-sectional view taken along the cutting line C1H1 depicted in FIG. 1H(1). FIG. 1H(3) is a cross-sectional view taken along the cutting line C1H2 depicted in FIG. 1H(1).

[0121] In some embodiments of the present disclosure, the process for forming the upper conductive layer 180 may be the same as or different from the process for forming the first conductive layer 150 .

[0122] After a series of downstream process steps are performed, the device 10 can be implemented. As described above, the exposed silicon region 102c of the gate terminal and the exposed silicon region of the source / drain terminals each serve as a seed region for growing a pillar based on the seed region by selective epitaxial growth (SEG). Furthermore, each of the first conductor pillar portion 131a and the third conductor pillar portion 131b also has a seed region or seed pillar in its upper portion, which can be used for subsequent selective epitaxial growth. In addition, this embodiment also allows the M1 wiring (a type of conductive terminal) or conductive layer to be directly connected to the MX wiring layer in a self-aligned manner through a single vertical conductive or conductive plug (without connecting to the transition conductive layers M2, M3, ..., MX-1) if the upper portion of the conductive terminal has a seed region or seed pillar and the conductive pillar portion is configured according to the selective epitaxial growth technique. It should be noted that the seed portion or seed pillar is not limited to silicon, but may be any material that can be used as a seed configured for subsequent selective epitaxial growth.

[0123] 1E(3) as an example, the second conductor pillar portion 132a is grown upward by the SEG method using the seed region or seed pillar of the first conductor pillar portion 131a as a base. Since the area of ​​the seed region is the area of ​​the top surface of the first conductor pillar portion 131a, the area of ​​the bottom surface of the second conductor pillar portion 132a is the same (or substantially the same) as the area of ​​the top surface of the first conductor pillar portion 131a, and self-alignment between the first conductor pillar portion 131a and the second conductor pillar portion 132a is easily achieved.

[0124] Embodiment 2 According to one embodiment of the present disclosure, a method for forming a device 20 having a transistor structure 200 includes the following steps. Step S21: A first dielectric layer is formed on the first terminal and the second terminal of the device. Step S22: At the same time, a first silicon pillar is formed through the first dielectric layer and connected to the first terminal, and a second silicon pillar is formed through the first dielectric layer and connected to the second terminal. Step S221: An opening hole is formed in the first dielectric layer to expose the silicon region of the first terminal and the silicon region of the second terminal. In step S222, a first silicon pillar is simultaneously formed on the silicon region of the first terminal by selective epitaxial growth, and a second silicon pillar is simultaneously formed on the silicon region of the second terminal by selective epitaxial growth. Step S23: A first conductive layer is formed on the first dielectric underlayer.

[0125] See step S21: A first dielectric layer 120 is formed on the first terminal 21 and the second terminal 22 of the device 20. In one embodiment, the first terminal 21 and the second terminal 22 are the uppermost regions of the gate terminal and the source / drain terminal, respectively. FIG. 2A(1) is a top view illustrating the structure after forming the first dielectric layer 220 on a transistor structure 200 pre-formed in a semiconductor substrate 201, according to one embodiment of the present disclosure. FIG. 2A(2) is a cross-sectional view taken along the cutting line C2A1 depicted in FIG. 2A(1). FIG. 2A(3) is a cross-sectional view taken along the cutting line C2A2 depicted in FIG. 2A(1).

[0126] In this embodiment, a semiconductor substrate 201 includes a silicon layer, such as a polycrystalline silicon layer or an amorphous silicon layer. As shown in Figures 2A(1) to 2A(3), a transistor structure 200 is formed in an active region of the silicon layer defined by an STI 205. The transistor structure 200 has a gate terminal 202 formed on the active region, a transistor channel region 203 formed in the active region below the gate terminal 202, and source / drain regions 204 formed in the active region and adjacent to the transistor channel region 203.

[0127] The gate terminal 202 includes a gate dielectric layer 202a, a gate conductive layer 202b formed on the gate dielectric layer 202a, a silicon region 202c formed on the gate conductive layer 202b, a capping layer (e.g., a nitride layer) covering an upper surface of the silicon region 202c, and at least one spacer (e.g., a nitride spacer 202s1 and a thermal oxide spacer 202s2) covering sidewalls of the gate dielectric layer 202a, the gate conductive layer 202b, and the silicon region 202c. The upper surface portion of the silicon region 202c can function as a first terminal 21, and the second terminal 22 can be a drain terminal of the source / drain region 204.

[0128] A first dielectric layer 220 is formed on the semiconductor substrate 201 to at least cover the active region including the gate terminal 202 and the source / drain regions 204 and the STI 205 .

[0129] See step S22: simultaneously form a first silicon pillar 231a through the first dielectric layer 220 and connected to the first terminal 21, and form a second silicon pillar 231b through the first dielectric layer 220 and connected to the second terminal 22. FIG. 2B(1) is a top view showing the structure after the first silicon pillar 231a and the second silicon pillar 231b are formed according to one embodiment of the present disclosure. FIG. 2B(2) is a cross-sectional view taken along the cutting line C2B1 depicted in FIG. 2B(1). FIG. 2B(3) is a cross-sectional view taken along the cutting line C2B2 depicted in FIG. 2B(1). The silicon pillars can be made of heavily doped silicon to obtain higher conductivity.

[0130] In this embodiment, the formation of the first silicon pillar 231a and the second silicon pillar 231b includes the following steps: First, a plurality of opening holes (such as opening holes 207a and 207b) are formed in the first dielectric layer 220 to expose the upper surface portion of the silicon region 202c of the first terminal 21 and the drain terminal of the source / drain region 204 that functions as the second terminal 22 (see step S221).

[0131] Next, referring to step S222, a first silicon pillar 231a is formed by SEG on the silicon region 202c of the first terminal 21 exposed from the opening 207a, and a second silicon pillar 231b is simultaneously formed by the same SEG on the silicon region 202c of the second terminal 22 exposed from the opening 207b. Here, each of the first silicon pillar 231a and the second silicon pillar 231b has an upper surface 231t that is higher than the upper surface of the first dielectric layer 220.

[0132] In some embodiments, a first dielectric liner 240 is then formed on the first dielectric layer 220 such that the upper surface 240s of the first dielectric liner 240 is substantially flush with the upper surfaces 203t of the first silicon pillar 231a and the second silicon pillar 231b, and the first dielectric liner is planarized.

[0133] See step S23: forming a first conductive layer 250 on the first dielectric liner layer 240. Figure 2C(1) is a top view illustrating the structure after the first conductive layer 250 is formed on the first dielectric liner layer 240 according to one embodiment of the present disclosure. Figure 2C(2) is a cross-sectional view taken along the cutting line C2C1 depicted in Figure 2C(1). Figure 2C(3) is a cross-sectional view taken along the cutting line C2C2 depicted in Figure 2C(1).

[0134] In this embodiment, the first conductive layer 250 is a patterned metal layer and includes a first metal underlayer 250a and a second metal underlayer 250b that function as connecting lines placed on the upper surfaces 203t of the first silicon pillar 231a and the second silicon pillar 231b, respectively.

[0135] Additionally, the exposed heads (top surfaces 230t of the first and second conductor pillars 230A and 230B) can be used as landing pads for connecting M1 (first conductive layer 250) to the conductor pillars (first and second conductor pillars 230A and 230B) and facilitating contact with both the gate (first terminal 21) and the diffusion region (second terminal 22), respectively. Because there is no need to worry about etching the oxide layer or dielectric associated with this contact hole, there is no need to create a metal M1 pad that would be large enough to cover the openings of the holes (opening holes 207a and 207b).

[0136] After a series of downstream processing steps have been performed, the formation of device 20 can be implemented.

[0137] Embodiment 3 According to one embodiment of the present disclosure, a method for forming a device 30 having a transistor structure 200 includes the following steps. Step S31: A first dielectric layer is formed on the first terminal and the second terminal of the device. Step S32: Simultaneously, a first silicon pillar is formed through the first dielectric layer and connected to the first terminal, and a second silicon pillar is formed through the first dielectric layer and connected to the second terminal. Step S321: An opening hole is formed in the first dielectric layer to expose the silicon region of the first terminal and the silicon region of the second terminal. Step S322: Simultaneously, a first silicon pillar is formed on the silicon region of the first terminal and a second silicon pillar is formed on the silicon region of the second terminal by selective epitaxial growth. Step S33: The first silicon pillar is replaced with a first conductor pillar, and the second silicon pillar is replaced with a second conductor pillar. Step S34: A first conductive layer is formed on the first dielectric underlayer.

[0138] The structure of device 30 and its manufacturing method are similar to those of device 20. The difference between the two is that device 30 uses first conductor pillars 330A and second conductor pillars 330B instead of first silicon pillars 231a and second silicon pillars 231b. Steps S31 to S32 for forming device 30 are the same as steps S21 to S22 for forming device 20, so the detailed procedures and materials applied thereby will not be redundantly described here, and the same elements in the embodiments will be denoted by the same reference numerals. The process for forming device 30 will be described starting from step S33.

[0139] See step S33: Replace the first silicon pillar 231a with the first conductor pillar 330A, and replace the second silicon pillar 231b with the second conductor pillar 330B. FIG. 3A(1) is a top view showing the structure after the first conductor pillar 330A and the second conductor pillar 330B are formed according to one embodiment of the present disclosure. FIG. 3A(2) is a cross-sectional view taken along the cutting line C3A1 depicted in FIG. 3A(1). FIG. 3A(3) is a cross-sectional view taken along the cutting line C3A2 depicted in FIG. 3A(1).

[0140] In this embodiment, replacing the first silicon pillar 231a and the second silicon pillar 231b includes the following steps: First, the first silicon pillar 231a and the second silicon pillar 231b are removed by a selective etching technique to expose the silicon region 202c of the first terminal 21 and the drain terminal of the source / drain region 204, which functions as the second terminal 22, from the opening holes 207a and 207b, respectively.

[0141] Subsequently, a metal plugging process is performed to form a titanium nitride (TiN) layer 330n on the sidewalls and bottom surfaces of the openings 207a and 207b. Next, metallic tungsten is deposited on the upper surface 240s of the first dielectric underlayer 240 to fill the openings 207a and 207b. Subsequently, a CMP process or an etching-back process is performed to remove the tungsten metal portion disposed on the upper surface 240s of the first dielectric underlayer 240, thereby forming two tungsten pillars 330w surrounded by the TiN layer 330n in the openings 207a and 207b, respectively.

[0142] Here, the tungsten pillar 330w and a portion of the TiN layer 330n are both disposed within the opening 207a and together form the first conductor pillar 330A. The tungsten pillar 330w and a portion of the TiN layer 330n are both disposed within the opening 207b and together form the second conductor pillar 330B. The first conductor pillar 330A and the second conductor pillar 330B each have a top surface 330t that is substantially coplanar with the top surface 240s of the first dielectric underlayer 240.

[0143] See step S34: forming a first conductive layer 350 on the first dielectric liner layer 240. Figure 3B(1) is a top view illustrating the structure after the first conductive layer 350 is formed on the first dielectric liner layer 240 according to one embodiment of the present disclosure. Figure 3B(2) is a cross-sectional view taken along the cutting line C3B1 depicted in Figure 3B(1). Figure 3B(3) is a cross-sectional view taken along the cutting line C3B2 depicted in Figure 3B(1).

[0144] In this embodiment, the first conductive layer 350 is a patterned metal layer and includes a first metal underlayer 350a and a second metal underlayer 350b that function as connecting lines placed on the upper surfaces 330t of the first conductor pillar 330A and the second conductor pillar 330B, respectively.

[0145] After a series of downstream process steps have been performed, formation of device 30 can be carried out.

[0146] Embodiment 4 According to one embodiment of the present disclosure, a method for forming a device 40 having a transistor structure 200 includes the following steps. Step S41: Form a first dielectric layer on the first terminal and the second terminal of the device. Step S42: Simultaneously, a first silicon pillar is formed through the first dielectric layer and connected to the first terminal, and a second silicon pillar is formed through the first dielectric layer and connected to the second terminal. Step S43: The first silicon pillar is replaced with a first conductor pillar, and the second silicon pillar is replaced with a second conductor pillar. Step S44: At the same time, a first highly doped silicon pillar is formed on the first conductor pillar, and a second highly doped silicon pillar is formed on the second conductor pillar. Step S45: A first conductive layer is formed on the first dielectric underlayer.

[0147] The structure of device 40 and its manufacturing method are similar to those of device 30. The difference between the two is that device 40 further includes a first heavily doped silicon pillar 410a and a second heavily doped silicon pillar 410b. Steps S41 to S43 for forming device 40 are the same as steps S31 to S33 for forming device 30, so the detailed procedures and materials applied thereby will not be redundantly described here, and the same elements in the embodiments will be denoted by the same reference numerals. The process for forming device 40 will be described starting from step S44.

[0148] See step S44: form a first heavily doped silicon pillar 410a connected to the first conductor pillar 330A, and simultaneously form a second heavily doped silicon pillar 410b connected on the second conductor pillar 330B. Figure 4A(1) is a top view showing the structure after the first heavily doped silicon pillar 410a and the second heavily doped silicon pillar 410b are formed on the first conductor pillar 330A and the second conductor pillar 330B, as depicted in Figure 4A(1), according to one embodiment of the present disclosure. Figure 4A(2) is a cross-sectional view taken along the cutting line C4A1 depicted in Figure 4A(1). Figure 4A(3) is a cross-sectional view taken along the cutting line C4A2 depicted in Figure 4A(1).

[0149] The formation of the first heavily doped silicon pillar 410a and the second heavily doped silicon pillar 410b includes the following steps: removing the upper portions of the two tungsten pillars 330w and the TiN layer 330n formed in the openings 207a and 407b, respectively, by an etching process (e.g., a selective etching technique), and then depositing heavily doped N+ polycrystalline silicon on the first dielectric underlayer 240 to fill the removed upper portions of the two tungsten pillars 330w and the portions of the openings 207a and 207b originally occupied by the TiN layer 330n.

[0150] Next, a CMP process or an etch-back process is performed to remove the heavily doped N+ polycrystalline silicon portion located on the upper surface 240s of the first dielectric underlayer 240, thereby forming a first heavily doped silicon pillar 410a and a second heavily doped silicon pillar 410b in the upper portions of the openings 207a and 207b originally occupied by the upper portions of the tungsten pillar 330w and the TiN layer 330n after removal. Here, the first heavily doped silicon pillar 410a and the second heavily doped silicon pillar 410b are each surrounded by the first dielectric underlayer 240 and have an upper surface 410s that is flush with the upper surface 240s of the first dielectric underlayer 240. Alternatively, the conductor pillar may include a tungsten pillar and a first heavily doped silicon pillar, i.e., the conductor pillar has a seed region or seed pillar in its upper portion.

[0151] See step S45: forming a first conductive layer 450 on the first dielectric liner layer 240. Figure 4B(1) is a top view illustrating the structure after the first conductive layer 450 is formed on the first dielectric liner layer 240 according to one embodiment of the present disclosure. Figure 4B(2) is a cross-sectional view taken along the cutting line C4B1 depicted in Figure 4B(1). Figure 4B(3) is a cross-sectional view taken along the cutting line C4B2 depicted in Figure 4B(1).

[0152] In this embodiment, the first conductive layer 450 is a patterned metal layer and includes a first metal underlayer 350a and a second metal underlayer 450b that function as connecting lines disposed on the top surfaces 410s of the first heavily doped silicon pillar 410a and the second heavily doped silicon pillar 410b, respectively. The exposed top surfaces 410s of the first heavily doped silicon pillar 410a and the second heavily doped silicon pillar 410a can be used as landing pads for M1 (the first conductive layer 450) to connect to the conductive pillars (the first conductive pillar 330A and the second conductive pillar 330B) and facilitate contact with both the gate (the first terminal 21) or the diffusion region (the second terminal 22), respectively.

[0153] After a series of downstream process steps have been performed, formation of device 40 can be carried out.

[0154] Embodiment 5 According to one embodiment of the present disclosure, a method for forming a device 50 having a transistor structure 200 includes the following steps. Step S51: Form a first dielectric layer on the first terminal and the second terminal of the device. Step S52: Simultaneously, a first silicon pillar is formed through the first dielectric layer and connected to the first terminal, and a second silicon pillar is formed through the first dielectric layer and connected to the second terminal. Step S53: The first silicon pillar is replaced with a first conductor pillar, and the second silicon pillar is replaced with a second conductor pillar. Step S54: A first heavily doped silicon pillar is formed on the first conductor pillar, and simultaneously a second heavily doped silicon pillar is formed on the second conductor pillar. Step S55: A first conductive layer is formed on the first dielectric underlayer. Step S56: Highly doped silicon side pillars are formed on the first highly doped silicon pillar and the second highly doped silicon pillar, respectively.

[0155] The structure of device 50 and its manufacturing method are similar to those of device 40. The difference between the two is that device 50 further includes heavily doped silicon side pillars 520 connected to first conductive layer 550. Since steps S51 to S54 for forming device 50 are the same as steps S41 to S44 for forming device 40, the detailed procedures and materials applied thereby will not be redundantly described here, and the same elements of the embodiments will be denoted by the same reference numerals. The process for forming device 50 will be described starting from step S55.

[0156] Figure 5(1) is a top view showing the structure after the first conductive layer 550 and heavily doped silicon side pillars have been formed according to one embodiment of the present disclosure. Figure 5(2) is a cross-sectional view taken along the cutting line C51 depicted in Figure 5(1). Figure 5(3) is a cross-sectional view taken along the cutting line C52 depicted in Figure 5(1).

[0157] Formation of the first conductive layer 550 (see step S55) includes the following steps: First, a patterned metal layer including a first metal underlayer 550a and a second metal underlayer 550b is formed so that the first metal underlayer 550a and the second metal underlayer 550b are disposed on the first heavily doped silicon pillar 410a and the second heavily doped silicon pillar 410b, respectively.

[0158] Next, referring to step S56, a portion of the first metal underlayer 550a and a portion of the second metal underlayer 550b are removed (e.g., by etching) to partially expose the top surfaces 410s of the first highly doped silicon pillar 410a and the second highly doped silicon pillar 410b. Subsequently, SEG is performed using the exposed portions of the top surfaces 410s as a starting point to grow two highly doped silicon side pillars 520 on the first highly doped silicon pillar 410a and the second highly doped silicon pillar 410b, respectively. Here, the two highly doped silicon side pillars 520 are connected to the (vertical) sidewalls of the etched first metal underlayer 550a and the second metal underlayer 550b, respectively.

[0159] Based on this structure, even if the width of the metal conductive layer (e.g., the first metal underlayer 550a or the second metal underlayer 550b) is the same as the width of the underlying contact plug (which may be as small as the minimum feature size), the metal conductive layer may not completely cover the contact (as shown in Figures 5(2) and 5(3)) due to misalignment tolerances in photolithography masking. However, there is no need to worry about the resistance between the metal conductive layer and the contact becoming too high due to insufficient contact area. The invention here further uses SEG to grow some extra heavily doped silicon material (side pillars 520) to attach the vertical walls of the metal conductive layer.

[0160] After a series of downstream process steps have been performed, the formation of device 50 can be carried out.

[0161] Embodiment 6 According to one embodiment of the present disclosure, a method for forming a device 60 having a transistor structure 200 includes the following steps. Step S61: Form a first dielectric layer on the first terminal and / or the second terminal of the device. Step S62: Forming a first silicon pillar through the first dielectric layer and connected to the first terminal, and / or forming a second silicon pillar through the first dielectric layer and connected to the second terminal. Step S63: The first silicon pillar is replaced with a first conductor pillar, and the second silicon pillar is replaced with a second conductor pillar. Step S64: A first heavily doped silicon pillar is formed on the first conductor pillar, and a second heavily doped silicon pillar is formed on the second conductor pillar. Step S65: A first conductive layer is formed on the first dielectric underlayer. Step S66: A third conductor pillar and a fourth conductor pillar are formed on the first heavily doped silicon pillar and the second heavily doped silicon pillar, respectively, so that the first conductive layer surrounds and connects the third conductor pillar and the fourth conductor pillar. Step S67: A third heavily doped silicon pillar is formed on the third conductor pillar, and simultaneously a fourth heavily doped silicon pillar is formed on the fourth conductor pillar.

[0162] The structure of device 60 and its manufacturing method are similar to those of device 40. The difference between the two is that the wiring structure of device 60 can be further extended. Since steps S61 to S64 for forming device 60 are the same as steps S41 to S44 for forming device 40, the detailed procedures and materials applied thereby will not be redundantly described here, and the same elements in the embodiments will be denoted by the same reference numerals. The process for forming device 60 will be described from step S65.

[0163] See step S65: forming a first conductive layer 650 on the first dielectric liner layer 240. Figure 6A(1) is a top view showing the structure after the first conductive layer 650 is formed on the first dielectric liner layer 240. Figure 6A(2) is a cross-sectional view taken along cutting line C6A1 as depicted in Figure 6A(1).

[0164] Prior to the formation of the first conductive layer 650, two undoped silicon pillars 610 are formed on the upper surfaces 410s of the first highly doped silicon pillar 410a and the second highly doped silicon pillar 410b, respectively. In this embodiment, SEG is performed using the upper surfaces 410s of the first highly doped silicon pillar 410a and the second highly doped silicon pillar 410b as bases to grow two undoped silicon pillars 610, each of which has an upper surface 610s higher than the upper surface 240s of the first dielectric underlayer 240.

[0165] Next, a first conductive layer 650 is formed on the first dielectric underlayer 240 to surround and connect the two undoped silicon pillars 610. In this embodiment, the first conductive layer 650 has an upper surface 650s that is lower than the upper surfaces 610s of the two undoped silicon pillars 610. Subsequently, a dielectric underlayer 640 is formed on the upper surface 650s of the first conductive layer 650 to surround and connect the two undoped silicon pillars 610. Here, the upper surface 640s of the second dielectric underlayer 640 is substantially flush with the upper surfaces 610s of the two undoped silicon pillars 610.

[0166] See step S66: forming a third conductor pillar 630A and a fourth conductor pillar 630B on the first heavily doped silicon pillar 410a and the second heavily doped silicon pillar 410b, respectively, such that the first conductive layer 650 surrounds and connects the third conductor pillar 630A and the fourth conductor pillar 630B. FIG. 6B(1) is a top view illustrating a structure after forming the third conductor pillar 630A and the fourth conductor pillar 630B on the first heavily doped silicon pillar 410a and the second heavily doped silicon pillar 410b according to an embodiment of the present disclosure. FIG. 6B(2) is a cross-sectional view taken along the cutting line C6B1 depicted in FIG. 6B(1). FIG. 6B(3) is a cross-sectional view taken along the cutting line C6B2 depicted in FIG. 6B(1).

[0167] In this embodiment, the formation of the third conductor pillar 630A and the fourth conductor pillar 630B includes the following steps: First, the two undoped silicon pillars 610 are removed to form two openings 607a and 607b. Next, a metal plugging process is performed to form a TiN layer 630n on the sidewalls and bottom surfaces of the openings 607a and 607b. Next, metallic tungsten is deposited on the upper surface 640s of the second dielectric underlayer 640 to fill the openings 607a and 607b. After that, a CMP process or an etching-back process is performed to remove the tungsten metal portion disposed on the upper surface 640s of the second dielectric underlayer 640, thereby forming two tungsten pillars 630w surrounded by the TiN layer 630n in the openings 607a and 607b, respectively.

[0168] In another embodiment, in addition to removing the two undoped silicon pillars 610, the first heavily doped silicon pillar 410a and the second heavily doped silicon pillar 410b may also be removed. Next, a metal plug process is performed to form a TiN layer 630n and a tungsten pillar 630w in the opening holes 607a and 607b. Therefore, as shown in FIGS. 6B(4) and 6B(5), the fourth conductive pillar 630B contacts the second conductive pillar 330B, and the third conductive pillar 630A contacts the first conductive pillar 330A. Therefore, the resistance of this pillar-like structure may be low.

[0169] Here, the tungsten pillar 630w and a portion of the TiN layer 630n are both disposed within the opening 607a and together form the third conductor pillar 630A. The tungsten pillar 630w and a portion of the TiN layer 630n are both disposed within the opening 607b and together form the fourth conductor pillar 630B. The third conductor pillar 630A and the fourth conductor pillar 630B each have a top surface 630s that is substantially coplanar with the top surface 640s of the second dielectric underlayer 640.

[0170] See step S67: forming a third heavily doped silicon pillar 660a on the third conductor pillar 630A, and simultaneously forming a fourth heavily doped silicon pillar 660b on the fourth conductor pillar 630B. Figure 6C(1) is a top view illustrating the structure after the third heavily doped silicon pillar 660a and the fourth heavily doped silicon pillar 660b are formed on the third conductor pillar 630A and the fourth conductor pillar 630B according to an embodiment of the present disclosure. Figure 6C(2) is a cross-sectional view taken along the cutting line C6C1 depicted in Figure 6C(1). Figure 6C(3) is a cross-sectional view taken along the cutting line C6C2 depicted in Figure 6C(1).

[0171] The formation of the third highly doped silicon pillar 660a and the fourth highly doped silicon pillar 660b includes the following steps: removing the upper portions of the two tungsten pillars 630w and the TiN layer 630n formed in the openings 607a and 607b, respectively, by an etching process; then, depositing heavily doped N+ polycrystalline silicon on the second dielectric liner 640 to fill the openings 607a and 607b originally occupied by the removed upper portions of the two tungsten pillars 630w and the TiN layer 630n.

[0172] Then, a CMP process or an etch-back process is performed to remove the heavily doped N+ polycrystalline silicon disposed on the upper surface 640s of the second dielectric liner 640, thereby forming a third heavily doped silicon pillar 660a and a fourth heavily doped silicon pillar 660b in the upper portions of the opening holes 607a and 607b, where the third heavily doped silicon pillar 660a and the fourth heavily doped silicon pillar 660b are surrounded by the second dielectric liner 640 and have upper surfaces 660s that are flush with the upper surface 640s of the second dielectric liner 640.

[0173] The first conductive layer 650 and the second dielectric underlayer 640 are then patterned to form a first metal underlayer 650a and a second metal underlayer 650b, respectively, which function as connecting lines surrounding and connecting the third conductor pillar 630A and the fourth conductor pillar 630B, respectively.

[0174] After a series of downstream process steps are performed, the device 60 can be formed. Further, taking Figures 6A(3) and 6C(3) as examples, first, an undoped silicon pillar 610 is grown upward using the SEG method based on the seed region of the first heavily doped silicon pillar 410a (Figure 6A(3)), and then the undoped silicon pillar 610 is replaced with a heavily doped silicon pillar 660a and a third conductor pillar 630A (Figure 6C(3)). Since the area of ​​the seed region is the area of ​​the top surface of the first heavily doped silicon pillar 410a, the area of ​​the bottom surface of the undoped silicon pillar 610 is considered to be the same (or substantially the same) as the area of ​​the top surface of the first heavily doped silicon pillar 410a, and the area of ​​the bottom surface of the third conductor pillar 630A (replacing the undoped silicon pillar 610) is also considered to be the same (or substantially the same) as the area of ​​the top surface of the first heavily doped silicon pillar 410a. Thus, self-alignment between the first heavily doped silicon pillar 410a and the third conductor pillar 630A is easily achieved.

[0175] That is, in other words, as shown in FIG. 6C(3), the lower conductor pillar (combination of 330A and 410a) has a seed region or seed pillar (such as heavily doped silicon pillar 410a) in its upper portion, and the high conductor pillar (combination of 630A and 660a) also has a seed region or seed pillar (such as heavily doped silicon pillar 660a) in its upper portion, and due to the self-alignment disclosed herein, the area of ​​the top surface of the low conductor pillar is the same or substantially the same as the area of ​​the bottom surface of the high conductor pillar.

[0176] Embodiment 7 According to one embodiment of the present disclosure, a method for forming a device 70 having a transistor structure 200 includes the following steps. Step S71: Form a first dielectric layer on the first terminal and the second terminal of the device. Step S72: Form a first silicon pillar through the first dielectric layer and connected to the first terminal, and form a second silicon pillar through the first dielectric layer and connected to the second terminal. Step S73: The first silicon pillar is replaced with a first conductor pillar, and the second silicon pillar is replaced with a second conductor pillar. Step S74: A first heavily doped silicon pillar is formed on the first conductor pillar, and a second heavily doped silicon pillar is formed on the second conductor pillar. Step S75: A first conductive layer is formed on the first dielectric underlayer. Step S76: A third conductor pillar and a fourth conductor pillar are formed on the first heavily doped silicon pillar and the second heavily doped silicon pillar, respectively, so that the first conductive layer surrounds and connects the third conductor pillar and the fourth conductor pillar. Step S77: A third heavily doped silicon pillar is formed on the third conductor pillar, and a fourth heavily doped silicon pillar is formed on the fourth conductor pillar. Step S78: Steps S75 and S77 are repeated.

[0177] The structure of device 70 and its manufacturing method are similar to those of device 60. The difference between the two is that the wiring structure of device 70 can be further extended by repeating steps S75 to S77. Since steps S71 to S77 for forming device 70 are the same as steps S61 to S67 for forming device 60, the detailed procedures and materials applied thereby will not be redundantly described here, and the same elements in the embodiments will be denoted by the same reference numerals. The process for forming device 70 will be described from step S78.

[0178] Figure 7A(1) is a top view illustrating the structure after repeating step S75 to form a second conductive layer 750 on the second dielectric liner layer 640 according to one embodiment of the present disclosure. Figure 7A(2) is a cross-sectional view taken along section line C7A1 depicted in Figure 7A(1). Figure 7A(3) is a cross-sectional view taken along section line C7A2 depicted in Figure 7A(1).

[0179] In this embodiment, prior to the formation of the second conductive layer 750, two undoped silicon pillars 710 are formed on the upper surfaces 660s of the third highly doped silicon pillar 660a and the fourth highly doped silicon pillar 660b, respectively. In this embodiment, SEG is performed using the upper surfaces 660s of the third highly doped silicon pillar 660a and the fourth highly doped silicon pillar 660b as bases, and the two undoped silicon pillars 710 are grown. Subsequently, a second dielectric layer 720 is formed to cover the first dielectric underlayer 240, the second dielectric underlayer 640, and the first conductive layer 650. Here, each of the two undoped silicon pillars 710 has an upper surface 710s that is higher than the upper surface 720s of the second dielectric layer 720.

[0180] Next, a second conductive layer 750 is formed on the second dielectric layer 720 so as to surround and connect these two undoped silicon pillars 710. Subsequently, a third dielectric underlayer 740 is formed on an upper surface 750s of the second conductive layer 750 so as to surround and connect these two undoped silicon pillars 710. Here, the upper surface 740s of the third dielectric underlayer 740 is substantially flush with the upper surfaces 710s of these two undoped silicon pillars 710.

[0181] Figure 7B(1) is a top view illustrating the structure after forming the fifth and sixth conductor pillars 730A and 730B on the third and fourth heavily doped silicon pillars 660a and 660b according to an embodiment of the present disclosure. Figure 7B(2) is a cross-sectional view taken along the cutting line C7B1 depicted in Figure 7B(1). Figure 7B(3) is a cross-sectional view taken along the cutting line C7B2 depicted in Figure 7B(1).

[0182] Similar to step S66 of forming the third conductor pillar 630A and the fourth conductor pillar 630B, the fifth conductor pillar 730A and the sixth conductor pillar 730B are formed by replacing these two undoped silicon pillars 710 with two tungsten pillars 730w surrounded by a TiN layer 730n.

[0183] In this example, similar to FIGS. 6B(4) and 6B(5), in addition to removing the two undoped silicon pillars 710, the first heavily doped silicon pillar 660a and the second heavily doped silicon pillar 660b may also be removed. Next, a metal plug process is performed to form a TiN layer 730n and a tungsten pillar 730w in the opening hole. Therefore, as shown in FIGS. 7B(4) and 7B(5), the fourth conductor pillar 630B contacts the sixth conductor pillar 730B, and the third conductor pillar 630A contacts the fifth conductor pillar 730A. Therefore, the resistance of this structure is low. FIGS. 6B(4), 6B(5), and 7B The structures of (4) and (5) of FIG. 7B can be repeated in the following process to form higher conductor pillars in other levels of metal layers.

[0184] Figure 7C(1) is a top view illustrating the structure after a fifth heavily doped silicon pillar 760a and a sixth heavily doped silicon pillar 760b are formed on the fifth conductor pillar 730A and the sixth conductor pillar 730B according to one embodiment of the present disclosure. Figure 7C(2) is a cross-sectional view taken along section line C7C1 depicted in Figure 7C(1). Figure 7C(3) is a cross-sectional view taken along section line C6C2 depicted in Figure 6C(1).

[0185] Similar to step S67 for forming the heavily doped silicon pillar 660a and the fourth heavily doped silicon pillar 660b, the fifth heavily doped silicon pillar 760a and the sixth heavily doped silicon pillar 760b may be formed of heavily doped N+ polycrystalline silicon instead of the upper portions of the fifth conductor pillar 730A and the sixth conductor pillar 730B. Here, the fifth heavily doped silicon pillar 760a and the sixth heavily doped silicon pillar 760b are surrounded by the second conductive layer 750 and the third dielectric liner layer 740 and have upper surfaces 760t that are flush with the upper surface 740s of the third dielectric liner layer 740.

[0186] The second conductive layer 750 and the third dielectric underlayer 740 are then patterned to form a third metal underlayer 750a and a fourth metal underlayer 650b, respectively, which function as connecting lines surrounding and connecting the fifth conductor pillar 730A and the sixth conductor pillar 730B, respectively.

[0187] After a series of downstream process steps are performed, the formation of device 60 can be carried out. In this example, or in other words, as shown in FIG. 7C(3), the aforementioned high conductor pillar (the combination of 630A and 660a) has a seed region or seed pillar (such as heavily doped silicon pillar 660a) on its upper portion, and the high conductor pillar (the combination of 730A and 760a) also has a seed region or seed pillar (such as heavily doped silicon pillar 760a) on its upper side. Due to the self-alignment disclosed herein, the area of ​​the top surface of the high conductor pillar is the same or substantially the same as the area of ​​the bottom surface of the upper conductor pillar. Based on FIGS. 6C(3) and 7C(3), all conductor pillars can be self-aligned from the bottom conductor pillar to the upper or top conductor pillar to achieve vertical connection therebetween, which is different from the conventional alignment method from the upper conductor pillar to the bottom conductor pillar.

[0188] While the present invention has been described by way of example and in terms of preferred embodiments, it is to be understood that the invention is not limited thereto. On the contrary, the invention is intended to cover various modifications and similar arrangements and procedures within the scope of the appended claims, and the claims are to be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements and procedures. [Explanation of symbols]

[0189] 10, 20, 30, 40, 50, 60, 70 devices 21 First terminal 22 Second terminal 120 first dielectric layer 100, 200 transistor structure 101, 201 Semiconductor substrate 102, 202 Gate terminal 103 Transistor channel region 104, 204 source / drain regions 107a, 107b, 207a, 207b opening hole 109 Hollow opening 130A, 230A, 330A First conductor pillar 130B, 230B, 330B Second conductor pillar 140, 240 First dielectric underlayer 150, 250, 350 First conductive layer 160, 640 Second dielectric underlayer 170 Upper dielectric layer 180 Upper conductive layer 330n TiN layer 630A Third Conductor Pillar 630B Fourth conductor pillar 720 second dielectric layer 730A 5th conductor pillar 730B 6th conductor pillar 740 Third dielectric underlayer 750 second conductive layer

Claims

1. A wiring structure, a semiconductor transistor formed on a semiconductor substrate, the semiconductor transistor having a gate terminal and a drain terminal; a first conductor pillar disposed above the semiconductor transistor and extending upward; a first seed pillar made of a semiconductor material provided on an upper surface of the first conductor pillar and electrically connected to the first conductor pillar, wherein the area of ​​a bottom surface of the first seed pillar is the same as or substantially the same as the area of ​​a top surface of the first conductor pillar; a second conductor pillar provided above the first seed pillar and extending upward; an upper conductive layer provided above the second conductor pillar and electrically connected to the second conductor pillar; A wiring structure, wherein the first seed pillar is sandwiched between the first conductor pillar and the second conductor pillar, and the first conductor pillar and the second conductor pillar are not made of a semiconductor material.

2. The wiring structure of claim 1 , wherein the first seed pillar is composed of heavily doped silicon.

3. The wiring structure according to claim 1 , wherein the first conductor pillar is electrically connected to the gate terminal or the drain terminal of the transistor.

4. 4. The wiring structure of claim 3, further comprising a lower conductive layer above the semiconductor transistor and below the upper conductive layer, the lower conductive layer being electrically insulated from the first conductor pillar and the second conductor pillar.

5. 2. The wiring structure of claim 1, further comprising a lower conductive layer above the semiconductor transistor and below the upper conductive layer, the lower conductive layer being electrically connected to the first conductor pillar.

6. 6. The wiring structure of claim 5, further comprising an intermediate conductive layer between the lower conductive layer and the upper conductive layer, the intermediate conductive layer being electrically insulated from the first conductor pillar and the second conductor pillar.

7. The wiring structure of claim 1 , wherein a bottom surface of the second conductor pillar is self-aligned to the top surface of the first conductor pillar.

8. a laterally extending metal layer contacting only a portion of the top surface of the second conductor pillar; 8. The wiring structure of claim 7, wherein a semiconductor side pillar is formed based on another portion of the top surface of the second conductor pillar and laterally contacts the metal layer, and the portion of the top surface of the second conductor pillar is different from the other portion of the top surface of the second conductor pillar.

9. 2. The wiring structure of claim 1, wherein the first conductor pillar further comprises a first tungsten pillar and a first TiN layer surrounding the first tungsten pillar, and the first seed pillar is made of heavily doped silicon and is located on the first tungsten pillar.

10. The wiring structure of claim 9 , wherein a bottom surface of the second conductor pillar is self-aligned with a top surface of the first seed pillar.

11. a third conductor pillar provided above the second conductor pillar and extending upward, the second conductor pillar and the third conductor pillar sandwiching the second seed pillar; the second conductor pillar further comprises a second tungsten pillar and a second TiN layer surrounding the second tungsten pillar, the second seed pillar is made of heavily doped silicon and is provided on the second tungsten pillar, The wiring structure of claim 10 , wherein a bottom surface of the third conductor pillar is self-aligned with a top surface of the second seed pillar.

12. a lower conductive layer disposed above the semiconductor transistor, the upper conductive layer being located above the lower conductive layer; 12. The wiring structure of claim 11, wherein the first conductor pillar is electrically connected to the gate terminal or the drain terminal of the semiconductor transistor, the third conductor pillar is electrically connected to the upper conductive layer, and the lower conductive layer is electrically insulated from the first conductor pillar, the second conductor pillar, and the third conductor pillar.

13. a lower conductive layer provided above the semiconductor transistor and below the upper conductive layer; an intermediate conductive layer disposed between the lower conductive layer and the upper conductive layer; 12. The wiring structure of claim 11, wherein the first conductor pillar is electrically connected to the lower conductive layer, the third conductor pillar is electrically connected to the upper conductive layer, and the intermediate conductive layer is electrically insulated from the first conductor pillar, the second conductor pillar, and the third conductor pillar.

14. The wiring structure according to claim 1 , wherein the area of ​​the bottom surface of the second conductor pillar is the same as or substantially the same as the area of ​​the top surface of the first conductor pillar.

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