Ohmic contacts for multichannel FETs.

Abstract

The ohmic contacts (10, 12) of the multi-channel (20) FET (14) include a plurality of slit-shaped recesses (16) in a wafer (18) in which the multi-channel FET resides, each recess having a depth at least equal to that of the lowest channel layer. Ohmic metal (22) in and on the sidewalls (40, 42) of each recess provides an ohmic contact to each of the multi-channel layers. An ohmic metal contact layer on the upper surface of the wafer may be provided, filled with ohmic metal and continuous with the outer edge of each recess, and above and in contact with the ohmic metal in each recess. This ohmic contact typically serves as the source and / or drain contact of the multi-channel FET. The use of a regrowth material to form the ohmic contacts to the multi-channel FET is further described, with the regrowth material preferably having a corrugated structure.

Description

[Technical Field]

[0001] Government Rights

[0001] This invention was made with government support under FA8650-18-C-7807 awarded by DARPA DREAM. The government has certain rights in this invention.

[0002] This invention relates generally to ohmic contacts, and more particularly to ohmic contacts in multiple channel field effect transistors (FETs). [Background technology]

[0003]

[0003] In recent years, field-effect transistors (FETs) with multi-channel (stacked) structures have attracted attention for their ability to increase current density and reduce on-resistance in power amplifier and power switch applications. For single-channel FETs, conventional alloyed ohmic contacts are formed by annealing stacks of thin metal layers (e.g., Ti / Al / Mo / Au for GaN FETs and AuGe / Ni / Au for GaAs / InGaAs FETs), with the submerged metal forming an ohmic contact to the channel layer. However, this method does not work well for multi-channel FET structures, where the distance between the upper semiconductor surface and the stacked channel is greater, because the alloyed metal does not reach the deep channel. This results in high contact resistance for multi-channel transistors.

[0004] "Regrown" ohmic contacts are another technique used to form low resistance ohmic contacts. Laterally regrown n-type ohmic contacts on a single 2DEG channel are used. + Low ohmic contact resistance has been demonstrated in GaN, however, contact resistance in multi-channel FETs can be higher than desired. Summary of the Invention [Means for solving the problem]

[0005] An ohmic contact for a multi-channel FET is presented. In one possible embodiment, the ohmic contact includes a plurality of slit-shaped recesses in a wafer in which the multi-channel FET resides, each recess having a depth at least equal to the depth of the FET's lowest channel layer. The recesses are aligned linearly with one another, with the recess lines oriented perpendicular to the direction of current flow between the FET's source and drain. Ohmic metal in and on the sidewalls of each slit-shaped recess provides an ohmic contact to each of the multiple channel layers. The sidewalls are preferably sloped, with the sidewall angle being between 45° and 90°.

[0006] Each of the slit-shaped recesses has an inner edge, through which current flows to or from the inner edge, and an outer edge. In a preferred embodiment, a line connection recess is provided that is continuous with the outer edge of each of the slit-shaped recesses. Ohmic metal is further deposited in the line connection recess such that the ohmic metal interconnects the slit-shaped recesses and the line connection recesses with the multiple channel layer.

[0007]

[0007] The ohmic contact may further include an ohmic metal contact layer on the upper surface of the wafer, above and in contact with the ohmic metal within each of the recesses forming the recess line, and above the linear connection recess (if present).

[0008]

[0008] The ohmic contacts typically serve as source and / or drain contacts of a multi-channel FET. The FET may be, for example, a GaN FET with ohmic metallurgy including Ti, Al, Mo, and / or Au. Another example is a GaAs / InGaAs FET with ohmic metallurgy including AuGe, Ni, and / or Au. Additional examples are provided below.

[0009] These and other features, aspects, and advantages of the present invention will become better understood with reference to the drawings, description, and claims that follow. [Brief explanation of the drawings]

[0010] [Figure 1] FIG. 1 is a perspective view of one embodiment of a multi-channel FET using ohmic contacts according to the present invention. [Figure 2]

[0011] FIG. 10 is a perspective view of another possible embodiment of a multi-channel FET using thin ohmic contacts according to the present invention. [Figure 3]

[0012] FIG. 3A is a perspective view of one embodiment of a multi-channel FET using ohmic contacts according to the present invention and depicting cross-sectional lines AA' and BB' at the recess.

[0013] Figure 3B is a possible cross-sectional view of the recess resulting from section lines A-A' and B-B' in Figure 3A. Figure 3C is a possible cross-sectional view of the recess resulting from section lines A-A' and B-B' in Figure 3A. [Figure 4]

[0014] Figures 4A and 4B are plan views of possible embodiments of a multi-channel FET using ohmic contacts according to the present invention, showing potential current paths between the contacts. [Figure 5]

[0015] FIG. 5A is a plan view of one possible embodiment of a multi-channel FET using ohmic contacts according to the present invention.

[0016] FIG. 5B is a plan view of another possible embodiment of a multi-channel FET using ohmic contacts according to the present invention. [Figure 6]

[0017] FIG. 6A is a perspective view of one embodiment of a multi-channel FET using regrown ohmic contacts according to the present invention.

[0018] FIG. 6B is a perspective view of another possible embodiment of a multi-channel FET using regrown ohmic contacts according to the present invention. [Figure 7]

[0019] 1 is a flow chart illustrating one possible set of steps for forming an ohmic contact using slit-shaped recesses in accordance with the present invention. [Figure 8]

[0020] 1 is a flowchart illustrating one possible set of steps for forming an ohmic contact using regrowth material in accordance with the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0011]

[0021] As an overview, in one possible embodiment, the present ohmic contacts, intended for use with FETs having multiple (stacked) channel structures, are formed by recess etching small slit patterns prior to ohmic metal deposition. The recesses are made deeper than the depth of the lower channel layer. Ohmic metal is deposited directly onto the sidewalls of each recess, thereby forming simultaneous contacts to each channel. The length, width, and shape of the slit structures are preferably optimized based on the sheet resistance of the material and the lateral contact resistance between the metal and the channel, so that the overall contact resistance is minimized.

[0012]

[0022] Similar concepts are further described that apply to more recent regrown ohmic contact techniques, in which a regrown material forms ohmic contact with the sidewalls of multiple channels. As described herein, the regrown material preferably has a corrugated structure, which increases the contact area by increasing the contact periphery in two dimensions, thereby reducing the effective contact resistance. The length, width, and shape of the corrugated structure are preferably optimized based on the sheet resistance of the material and the lateral contact resistance between the metal and the channel, so that the overall contact resistance is minimized.

[0013]

[0023] One possible embodiment of the "slit pattern" approach is illustrated in FIG. 1, in which ohmic contacts 10, 12 (source and drain) are provided to a multi-channel FET 14. Each ohmic contact comprises multiple slit-shaped recesses 16 in a wafer 18 in which the multi-channel FET resides. Each recess 16 has a depth at least equal to the depth of the FET's lowermost channel layer 20, and the recesses are aligned in lines with one another. The recess lines are oriented perpendicular to the direction of current flow between the FET's source and drain. Ohmic metal (not numbered) is in and on the sidewalls of each of the slit-shaped recesses so that an ohmic contact is made to each of the multiple channel layers, and contacts to the channel layers are made laterally. The width and pitch of the slits are preferably selected to optimize material conductivity and interface resistance.

[0014]

[0024] The ohmic contact may further include an ohmic metal contact layer 22 on the top surface of wafer 18 above and in contact with the ohmic metal in each of the recesses 16. The ohmic metal contact layer 22 has an inner edge 24 and an outer edge 26, and the lines of recesses 16 are preferably spaced apart from the inner edge 24 of the ohmic metal contact layer by a distance ≧0 μm such that each of the recesses is completely overlapped (covered) by the ohmic metal contact layer.

[0015]

[0025] The ohmic metal contact layer 22 has an associated width W1 defined as the distance between the inner edge 24 and the outer edge 26. Each of the recesses 16 also has an associated common width W2 defined in the same direction as W1. The minimum value of W1 is preferably equal to W2. W1 may be more than or equal to W2, as illustrated in FIG. 1. Alternatively, the ohmic metal contact layer 32 may be relatively thin, and width W1 may be equal to or approximately equal to W2, as illustrated in FIG. 2.

[0016]

[0026] Figure 3A shows a multi-channel FET 14 as described herein, and the cross-sectional views shown in Figures 3B and 3C (taken along section lines A-A' and B-B') illustrate possible shapes of sidewalls 40, 42 of recess 16. As shown in Figure 3A, sidewalls 40, 42 can be vertical. However, in Figure 3B, sidewalls 40, 42 are sloped, with the angle of the sidewalls preferably being between 45° and 90°.

[0017]

[0027] When configured as shown in FIG. 1, a current path 50 is formed between the ohmic contacts 10 and 12, as shown in FIG. 4A—with the slit-shaped recesses 16 described above. Another possible embodiment is shown in FIG. 4B. As before, slit-shaped recesses 60 are formed. In addition, line-shaped connection recesses 62 are formed, contiguous with the outer edges of each of the slit-shaped recesses 60. Ohmic metal fills both the line-shaped connection recesses 62 and the recesses 60, such that the slit-shaped recesses and line-shaped connection recesses of each ohmic contact are interconnected with multiple channel layers. Here, in addition to the current path 50, an additional current path 64 is provided between the line-shaped connection recesses 60.

[0018]

[0028] It should be noted that at least two different embodiments are possible for ohmic contacts having line-shaped connecting recesses as shown in FIG. 4B. For example, in the configuration shown in FIG. 5A, an ohmic contact layer 66 is above and in contact with the ohmic metal in each of the recesses 60 and 62. As before, the line of recesses 60 is preferably spaced from the inner edge 68 of the ohmic metal contact layer by a distance ≧0 μm so that each of the recesses is completely covered by the ohmic metal contact layer 66. Alternatively, as shown in FIG. 5B, no ohmic metal contact layer is provided above the recesses 60 and 62.

[0019]

[0029] The ohmic contacts can be used with multi-channel FETs made from a variety of materials. For example, the multi-channel FET can be an n-type AlGaN / GaN FET, where suitable ohmic metals include Ti, Al, Mo, and / or Au, and for p-type AlGaN / GaN FETs, suitable ohmic metals include Pd, Ni, Pt, and / or Au. As another example, the multi-channel FET can be a GaAs / InGaAs FET, where suitable ohmic metals include AuGe, Ni, and / or Au. Another example is an AlGa2O3 / Ga2O3 FET, where suitable ohmic metals include Ti and Au. In general, the ohmic metal should be selected to provide the desired contact resistance, which is typically determined empirically.

[0020]

[0030] It should be noted that while multi-channel FETs are described as the primary application of the present ohmic contacts, those skilled in the art may find application more generally with any FET having one or more channel layers. For example, ohmic contacts may be useful in FETs having a single thick channel layer, such as a bulk channel (instead of a 2DEG), uniformly doped with n-type or p-type dopants, where a conventional alloyed ohmic contact from the top surface may not reach the entire channel layer. MESFETs are an example.

[0021]

[0031] A similar approach can be applied to more recent "regrowth" ohmic contact technology, where rather than forming the contact by depositing metal, e.g., n +Regrowth material, such as GaN, is deposited directly onto the sidewalls of the multi-channel FET using, for example, MBE or MOCVD. This is illustrated in Figures 6A and 6B. In Figure 6A, ohmic source and drain contacts 70, 72 are formed on a multi-channel FET 74 using regrowth material 76 on a wafer 78 on which the multi-channel FET resides. The regrowth material 76 laterally contacts the sidewalls of each channel layer 79 of the multi-channel FET.

[0022]

[0032] A preferred embodiment using this concept is shown in Figure 6B. Here, regrowth material 82 is perpendicular to the top surface of wafer 86 on which the FET resides and has an inner edge 84 that contacts the sidewall of each channel layer 88, with inner edge 84 having a corrugated shape. The corrugated structure increases the total contact perimeter in two dimensions, resulting in reduced contact resistance per transistor gate width. The length, width, and shape of the corrugated structure are preferably optimized based on the sheet resistance of the material and the lateral contact resistance between the regrowth material and the channel, so that the overall contact resistance is minimized.

[0023]

[0033] Examples of suitable regrowth materials for various FET types follow. - n-type AlGaN / GaN FET: n+GaN - p-type AlGaN / GaN FET: p+GaN - n-type AlGaO3 / Ga2O3FET: n+Ga2O3

[0034] As discussed above for the slit-shaped recess approach, the regrowth material approach described herein may find application more generally with any FET having one channel layer or multiple channel layers.

[0024]

[0035] Both the "slit" and "regrowth" approaches significantly reduce the contact resistance to the multiple channels compared to prior art methods by (1) simultaneously contacting the multiple channels directly with ohmic metal or regrowth material, and (2) increasing the contact perimeter by introducing slit / corrugation structures.

[0025]

[0036] One possible method for forming ohmic contacts using slit-shaped recesses as described herein is shown in FIG. 7. In step 90, slit-shaped recesses are etched into a wafer in which multiple-channel FETs are being fabricated. Each recess is etched to a depth at least equal to the depth of the FET's lowest channel layer. The recesses are aligned with one another in lines, with the lines of the recesses oriented perpendicular to the direction of current flow between the FET's source and drain. In step 92, ohmic metal is deposited in and on the sidewalls of each of the slit-shaped recesses so that an ohmic contact is formed to each of the multiple channel layers.

[0026]

[0037] Optionally, in step 94, line connection recesses contiguous with the outer edges of each of the slit-shaped recesses (as illustrated in FIGS. 4B, 5A, and 5B) are etched. Once the line connection recesses are etched, ohmic metal is further deposited in the line connection recesses (step 96), such that the ohmic metal interconnects the slit-shaped recesses and the line connection recesses with the multiple channel layers.

[0027]

[0038] Another optional step is shown in step 98, in which an ohmic metal contact layer is deposited on the upper surface of the wafer above and in contact with the ohmic metal in each of the recesses (as illustrated in Figures 1 and 2). According to the present invention, either step 94 / 96 or step 98 may be performed, both may be performed, or neither may be performed.

[0028]

[0039] The etching step is preferably performed by a dry etch, such as a reactive ion etch (RIE) or an inductively coupled plasma etch (ICP-RIE). The ohmic metal depositing step preferably includes sequentially evaporating or sputtering the ohmic metal in one process step. As noted above, the sidewalls of the recess may be sloped, with the angle of the sidewalls being between 45° and 90°. The etching and metal deposition steps are preferably performed before the gate of the FET is formed.

[0029]

[0040] One possible method of forming ohmic contacts using regrowth materials as described herein is shown in Figure 8. In step 100, a multi-channel FET is etched to expose the sidewalls of each channel layer. In step 102, e.g., n + A regrowth material, such as GaN, is directly deposited such that the regrowth material laterally contacts each sidewall of the channel layer. Optionally (and preferably), the inner edges of the regrowth material are given a corrugated shape in step 104. As mentioned above, the regrowth material is preferably deposited using MBE or MOVCD.

[0030]

[0041] The present ohmic contacts of multi-channel FETs can be used in numerous applications, such as power amplifier MMICs with high output power, low noise amplifier MMICs with high linearity, RF switch MMICs with low insertion loss and high isolation, and power switch transistors with low dynamic on-resistance and breakdown voltage are just a few possible applications.

[0031]

[0042] The embodiments of the invention described herein are illustrative, and numerous modifications, variations, and rearrangements can be readily envisioned to achieve substantially equivalent results, all of which are intended to be encompassed within the spirit and scope of the invention as defined in the appended claims.

Claims

1. An ohmic contact of a FET, a regrowth material on a wafer on which a FET is present, the FET having one or more channel layers, the regrowth material laterally contacting a sidewall of each channel layer of the FET; Including, The ohmic contact, wherein the regrowth material is perpendicular to the top surface of the wafer and has an inner edge that contacts a sidewall of the channel layer, the inner edge having a corrugated shape.

2. An ohmic contact for a multi-channel FET, comprising: a regrowth material on the wafer on which the multi-channel FET is located, the regrowth material laterally contacting a sidewall of each channel layer of the multi-channel FET; Including, The ohmic contact, wherein the regrown material has an inner edge that is normal to the top surface of the wafer and contacts a sidewall of the channel layer, the inner edge having a corrugated shape.

3. The multi-channel FET is an n-type AlGaN / GaN FET, and the regrown material is n ＋ GaN, or the multi-channel FET is a p-type AlGaN / GaN FET and the regrown material is p ＋ GaN, or the multi-channel FET is n-type AlGaO ３ / Ga ２ O ３ FET, wherein the regrown material is n+Ga ２ O ３ 3. The ohmic contact of claim 2, wherein:

4. 1. A method for forming an ohmic contact for a multi-channel FET, comprising: Etching the layers of the multi-channel FET to expose the sidewalls of each channel layer; depositing regrowth material directly such that the material laterally contacts the sidewalls of each of the channel layers; Including, The method wherein the regrowth material has an inner edge that is normal to the top surface of the wafer and contacts the sidewall, the inner edge having a corrugated shape.

5. 5. The method of claim 4, wherein the step of directly depositing is performed using MBE or MOVCD.

6. The multi-channel FET is an n-type AlGaN / GaN FET, and the regrown material is n ＋ GaN, or the multi-channel FET is a p-type AlGaN / GaN FET and the regrown material is p ＋ GaN, or the multi-channel FET is n-type AlGaO ３ / Ga ２ O ３ FET, wherein the regrown material is n+Ga ２ O ３ The method of claim 4, wherein

Images