Structural and material engineering methods for improving the signal-to-noise ratio of optoelectronic devices

Abstract

A method for fabricating a semiconductor device includes forming an interconnect structure on a front side of a sensor substrate, thinning the sensor substrate from a back side of the sensor substrate, etching trenches in the sensor substrate, pre-cleaning the exposed surface of the sensor substrate, epitaxially growing a charge layer directly on the pre-cleaned exposed surface of the sensor substrate, and forming isolation structures in the etched trenches.

Description

[Technical Field]

[0001]

[0001] The embodiments described herein relate generally to optoelectronic devices, and more particularly to image sensors having an epitaxially grown charge layer on the surface of the pixels to improve the signal-to-noise ratio of the image sensor. [Background technology]

[0002]

[0002] Complementary metal-oxide semiconductor (CMOS) image sensors (CIS) are widely used in a variety of applications, such as digital cameras and mobile phones. A CIS uses an array of pixels, such as photodiodes, photogate detectors, or phototransistors, to collect light projected onto a semiconductor substrate and convert the collected light energy into an electrical signal that can be used in an appropriate application. One type of CIS, a backside-illuminated (BSI) CIS, typically has a silicon substrate with an array of pixels formed therein to sense and record the intensity of light incident on the substrate from the backside, and some circuitry and input / output adjacent to the array of pixels to provide an operating environment for the pixels and direct external communication with the pixels. During device processing, such as etching, polishing, or any other material removal process, the backside surface of the substrate (i.e., the surface of the pixels) can be damaged, leaving dangling bonds and / or defect centers. Charge carriers generated from these dangling bonds and / or defect centers can result in the formation of noise in the electrical signal within the array of pixels.

[0003]

[0003] Conventional methods for suppressing noise generation include passivating the backside surface of a substrate by adding a charge layer (i.e., a layer containing charge carriers) near the backside surface. The charge carriers in the charge layer recombine with charge carriers originating from dangling bonds and / or defect centers. The charge layer can be formed by injecting a desired type of charge (i.e., a positive or negative charge opposite to the charge carriers originating from dangling bonds and / or defect centers) into the substrate. Alternatively, the charge layer can be formed by adding a dielectric material on the backside surface of the substrate that has a charge type opposite to the desired type, such that the desired type of charge is induced in the substrate near the backside. A buffer oxide layer can be inserted between the backside surface of the substrate and the dielectric material for charge separation between the charge carriers in the dielectric layer and the induced charge carriers in the substrate near the surface.

[0004]

[0004] However, recent demands for high aspect ratio trench isolation (i.e., pixels separated from each other by high aspect ratio trenches) and deeper pixels with higher signal-to-noise ratios present challenges for conventional methods. Charge layers formed by conventional methods may not provide enough charge carriers to passivate the surface of the substrate at reasonable manufacturing costs and design requirements. Furthermore, charge layers formed by implantation may not have good coverage for the sidewalls of high aspect ratio trenches. Charge layers formed by thick dielectric layers to better passivate induced charge carriers may also have a high absorption coefficient, which can result in a reduction in signal from an array of pixels.

[0005]

[0005] Therefore, there is a need in the art for an improved method for passivating damaged backside surfaces of BSI CIS devices, as well as any damaged surfaces due to etching and / or polishing, and more generally, for an improved structure of BSI CIS devices, which method can also be implemented in frontside-illuminated (FSI) CIS, providing similar benefits as BSI CIS. Summary of the Invention

[0006]

[0006] In one embodiment, a method for manufacturing a semiconductor device includes forming an interconnect structure on a front side of a sensor substrate, thinning the sensor substrate from a back side of the sensor substrate, etching a trench in the sensor substrate, pre-cleaning the exposed surface of the sensor substrate, epitaxially growing a charge layer directly on the pre-cleaned exposed surface of the sensor substrate, and forming an isolation structure in the etched trench.

[0007]

[0007] In another embodiment, a method for manufacturing a semiconductor device includes epitaxially growing a layer to be epitaxially grown directly on a surface of a handle substrate, epitaxially growing a semiconductor layer directly on the charge layer, injecting dopants into the semiconductor layer, etching trenches in the semiconductor layer, forming isolation structures in the etched trenches, forming interconnect structures on the semiconductor layer, and removing the handle substrate from the epitaxially grown layer.

[0008]

[0008] In yet another embodiment, the image sensor includes a sensor substrate having a front side and a back side, a plurality of pixels formed in the sensor substrate on the back side, a plurality of isolation structures formed in the sensor substrate, wherein the plurality of pixels are separated from one another by one of the plurality of isolation structures, an interconnect structure covering the front side of the sensor substrate, and a charge layer epitaxially grown directly on the surface of the plurality of pixels on the back side of the sensor substrate.

[0009]

[0009] Implementations of the present disclosure, briefly summarized above and described in more detail below, can be understood by reference to exemplary implementations of the present disclosure illustrated in the accompanying drawings. It should be noted, however, that because the present disclosure may admit of other equally effective implementations, the accompanying drawings depict only typical implementations of the present disclosure and therefore should not be considered as limiting the scope of the present disclosure. [Brief explanation of the drawings]

[0010] [Figure 1] 1 is a cross-sectional view of a fabricated backside illuminated (BSI) image sensor device according to a first embodiment of the present disclosure. [Figure 2] FIG. 4 is a cross-sectional view of a fabricated backside illuminated (BSI) image sensor device according to a second embodiment of the present disclosure. [Figure 3] 1 is a flow diagram of a method for manufacturing an image sensor device, such as a backside illuminated (BSI) image sensor, according to a first embodiment of the present disclosure. [Figure 4A-E] 1A-1C illustrate schematic diagrams of intermediate steps performed in a method for manufacturing an image sensor device, such as a backside illuminated (BSI) image sensor, according to a first embodiment of the present disclosure. [Figure 5] 4 is a flow diagram of a method for manufacturing an image sensor device, such as a backside illuminated (BSI) image sensor, according to a second embodiment of the present disclosure. [Figure 6A-F] 5A-5C illustrate schematic diagrams of intermediate steps performed in a method for manufacturing an image sensor device, such as a backside illuminated (BSI) image sensor, according to a second embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0011]

[0016] For ease of understanding, the same reference numerals have been used, where possible, to designate identical elements common to the figures. The figures are not drawn to scale and may be simplified for clarity. It is intended that elements and features of one implementation may be beneficially incorporated in other implementations without further description.

[0012]

[0017] The embodiments described herein relate generally to optoelectronic devices, and more particularly to image sensors having an epitaxially grown charge layer on the surface of the pixels to improve the signal-to-noise ratio of the image sensor.

[0013]

[0018] The image sensors described herein include an epitaxially grown charge layer on a sensor substrate on which pixels are formed. The epitaxially grown charge layer conformally covers damaged surfaces of the pixels where unwanted carriers (noise) arise from dangling bonds and / or defect centers generated by the device fabrication process. The epitaxially grown charge layer passivates charge carriers on the surface of the pixels, preventing noise from occurring in the electrical signal converted from light energy within the pixels.

[0014]

[0019] 1 is a cross-sectional view of a fabricated backside illuminated (BSI) image sensor device 100 according to a first embodiment of the present disclosure. The image sensor device 100 may be a charge-coupled device (CCD), a complementary metal-oxide semiconductor (CMOS) image sensor (CIS), an active pixel sensor (APS), or a passive pixel sensor.

[0015]

[0020] The image sensor device 100 includes a sensor substrate 102 having a front side 104 and a back side 106. The sensor substrate 102 may be a photodiode. In some embodiments, the sensor substrate 102 includes a pinned layer photodiode, a photogate, a reset transistor, a source follower transistor, or a transfer transistor. The sensor substrate 102 is operable to detect incident light 110 projected toward the back side 106 of the sensor substrate 102. The sensor substrate 102 absorbs the optical energy of the projected incident light 110, generating electron-hole pairs near the back side 106 of the sensor substrate 102 and inducing mobile charge carriers. The charge carriers diffuse and are detected as an electrical signal near the front side 104 of the sensor substrate 102.

[0016]

[0021] The sensor substrate 102 may be a substrate having a p-type dopant, such as boron, or an n-type dopant, such as phosphorus or arsenic, doped by a suitable implantation process, such as a diffusion process. The substrate may be bulk silicon or any other suitable semiconductor material, such as crystalline germanium, or a compound semiconductor, such as silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, indium arsenide, antimonide, III-V, III-nitride, or a combination thereof. Alternatively, the substrate may be a silicon-on-insulator (SOI) substrate including a semiconductor layer, such as silicon or germanium, formed on an insulator layer, formed using wafer bonding and / or other suitable methods. The insulator layer may be a buried oxide (BOX) layer formed within the semiconductor substrate. The substrate may have any suitable crystal orientation (e.g., (100), (110), (111), or (001) crystal orientation). The thickness of the substrate may range between about 100 microns (μm) and 1000 μm.

[0017]

[0022] An array or grid of pixels 108 is formed in the sensor substrate 102. The pixels 108 may differ from one another, such as having different depths, thicknesses, widths, etc. Although only two pixels 108 are shown in FIG. 1 , any number of pixels 108 may be implemented on the sensor substrate 102. The sensor substrate 102 may further include isolation structures 112 that provide electrical and optical isolation between the pixels 108. The isolation structures 112 may be shallow trench isolation (STI) structures formed from a dielectric material such as silicon oxide or silicon nitride filled in the trenches 114, deep trench isolation (DTI) structures formed from a dielectric or polymetallic material in the trenches 114, or capacitors with air gaps in the trenches 114. The trenches 114 are formed by etching the sensor substrate 102. In some embodiments, the isolation structures 112 include doped isolation features, such as heavily doped n-type or p-type regions. Although only three isolation structures 112 are shown in FIG. 1 , any number of isolation structures can be implemented within the sensor substrate 102 to adequately isolate the pixels 108. The pixels 108 and trenches 114 have depths between about 3 μm and about 10 μm or more. The pixels 108 have widths between about 1.2 μm and about 1.4 μm, which may decrease to about 0.7 μm or less. The isolation structures 112 have widths between about 50 nm and about 300 nm and aspect ratios between 5 and 100, and in some cases even higher.

[0018]

[0023] The image sensor device 100 further includes a charge layer 116 conformally and epitaxially grown directly on the surface of the pixels 108 on the backside 106 of the sensor substrate 102, including the inner walls of the trenches 114. The pixels 108 may include defect centers and a high concentration of dangling bonds near the surface of the pixels 108 on the backside 106 of the sensor substrate 102 due to device processing, such as etching to form the trenches 114 and thinning the sensor substrate 102 from the backside 106. Charge carriers originating from the defect centers and dangling bonds that cause noise in the electrical signals converted from light energy in the array of pixels 108 are passivated (i.e., recombined) by the charge carriers formed in the charge layer 116, thereby reducing noise in the electrical signals. The charge layer 116 may include boron-doped silicon (Si:B), boron-doped silicon germanium (SiGe:B), boron-doped germanium (Ge:B), or a combination thereof. In some embodiments, the charge layer 116 is formed from carbon-doped silicon (Si:C). In addition to providing charge carriers, the carbon-doped silicon blocks metal diffusion from the front side 104 of the sensor substrate 102. A charge layer 116 formed from silicon germanium (SiGe), germanium (Ge), or carbon-doped silicon (Si:C) on a sensor substrate 102 formed from doped silicon induces tension at the interface with the sensor substrate 102 due to lattice mismatch, resulting in the indirect bandgap of silicon being modified to a direct bandgap, thereby improving the generation of electron-hole pairs and, therefore, the electrical signal. The thickness of the charge layer 116 may be between approximately 5 nm and 50 nm. Such an epitaxial charge layer can also function as an extension of the pixel area, increasing the thickness to more than 50 nm depending on the integration density. The density of charge carriers formed in the charge layer 116 is 1×10 18 / cm 3 and 5×10 21 / cm 3 It may be between.

[0019]

[0024] The image sensor device 100 may further include an interconnect structure 118 formed on the front side 104 of the sensor substrate 102. The interconnect structure 118 may include multiple patterned dielectric and conductive layers that provide interconnections (e.g., wiring) between various doped features, circuits, and inputs / outputs of the image sensor device 100. The interconnect structure 118 may include, for example, an interlayer dielectric (ILD), a multilayer interconnect (MLI) structure including contacts, vias, and metal lines. The MLI structure may include aluminum interconnects formed from aluminum / silicon / copper alloys, titanium, titanium nitride, tungsten, polysilicon, metal silicides, or combinations thereof. Alternatively, the MLI structure may include copper multilayer interconnects formed from copper alloys, titanium, titanium nitride, tantalum, tantalum nitride, tungsten, polysilicon, metal silicides, or combinations thereof.

[0020]

[0025] 2 is a cross-sectional view of the back side of a fabricated backside illuminated (BSI) image sensor device 200 according to a second embodiment of the present disclosure. In the following description, components that are substantially the same as those in the first embodiment will be designated by the same reference numerals, and descriptions of duplicated components may be omitted.

[0021]

[0026] The image sensor device 200 includes a sensor substrate 102 having a front side 104 and a back side 106 .

[0022]

[0027] An array or grid of pixels 108 is formed on the sensor substrate 102. The sensor substrate 102 may further include isolation structures 212 that provide electrical and optical isolation between the pixels 108. The isolation structures 212 may be shallow trench isolation (STI) structures formed from a dielectric material such as silicon oxide or silicon nitride filled in trenches 214, deep trench isolation (DTI) structures formed from a dielectric or polymetallic material filled in the trenches 214, or capacitors with air gaps in the trenches 214. The trenches 214 are formed by etching the sensor substrate 102. In some embodiments, the isolation structures 212 include doped isolation features, such as heavily doped n-type or p-type regions. Although only three isolation structures 212 are shown in FIG. 2 , any number of isolation structures may be implemented in the sensor substrate 102 to provide appropriate isolation for the pixels 108.

[0023]

[0028] The image sensor device 200 includes an epitaxially grown layer 216 (hereinafter referred to as "epilayer") directly disposed on top of the pixels 108 on the backside 106 of the sensor substrate 102. The epilayer 216 may be formed from boron-doped silicon (Si:B), boron-doped silicon germanium (SiGe:B), boron-doped germanium (Ge:B), or carbon-doped silicon (Si:C). The image sensor device 200 further includes a charge layer 218 covering the epilayer 216 and the inner walls of the trenches 214. In some embodiments, the charge layer 218 includes boron-doped silicon (Si:B), boron-doped silicon germanium (SiGe:B), boron-doped germanium (Ge:B), or carbon-doped silicon (Si:C) epitaxially grown on the exposed surface of the sensor substrate 102 at the backside 106. In some embodiments, the charge layer 218 is formed by adding a dielectric material to the exposed surface of the sensor substrate 102 on the backside 106 that has a charge of the opposite type to the desired type, thereby inducing a charge of the desired type into the substrate near the backside 106.

[0024]

[0029] 3 is a flow diagram of a method 300 for manufacturing an image sensor device 100, such as a back-illuminated (BSI) image sensor, according to a first embodiment of the present disclosure. Figures 4A to 4E schematically illustrate intermediate steps performed in the method 300.

[0025]

[0030] In block 302 of method 300, a sensor substrate 102 is provided or fabricated, as shown in FIG. 4A. The sensor substrate 102 may be a photodiode formed from a substrate having a p-type dopant, such as boron, or an n-type dopant, such as phosphorus or arsenic, doped by a suitable implantation process, such as a diffusion process. The substrate may be bulk silicon or any other suitable semiconductor material, such as crystalline germanium, or a compound semiconductor, such as silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, gallium phosphide, indium arsenide, indium phosphide, indium arsenide, indium antimonide, III-V, III-nitride, or a combination thereof. Alternatively, the substrate may be a silicon-on-insulator (SOI) substrate including a semiconductor layer, such as silicon or germanium, formed on an insulator layer, formed using wafer bonding and / or other suitable methods. The insulator layer may be a buried oxide (BOX) layer formed within the semiconductor substrate. The substrate may have any suitable crystal orientation (e.g., (100), (110), (111), or (001) crystal orientation). The thickness of the substrate may range between about 100 microns (μm) and 1000 μm.

[0026]

[0031] 4B, an interconnect structure 118 is formed on the front side 104 of the sensor substrate 102. The interconnect structure 118 may include multiple patterned dielectric and conductive layers that provide interconnections (e.g., wiring) between various doped features, circuits, and inputs / outputs of the image sensor device 100. The interconnect structure 118 may include, for example, an interlayer dielectric (ILD), a multilayer interconnect (MLI) structure including contacts, vias, and metal lines. The MLI structure may include aluminum interconnects formed from aluminum / silicon / copper alloys, titanium, titanium nitride, tungsten, polysilicon, metal silicides, or combinations thereof. The aluminum interconnects may be formed by a process such as physical vapor deposition (PVD) (or sputtering), chemical vapor deposition (CVD), atomic layer deposition (ALD), photolithography, etching to pattern conductive materials for vertical connections (e.g., vias / contacts) and horizontal connections (e.g., conductive lines), or a combination thereof. Alternatively, the MLI structure may include copper multi-layer interconnects formed from copper alloys, titanium, titanium nitride, tantalum, tantalum nitride, tungsten, polysilicon, metal silicides, or a combination thereof. The copper wiring structure may be formed by a process such as CVD, sputtering, plating, or other suitable process.

[0027]

[0032] In block 306 of the method 300, the sensor substrate 102 is flipped over and thinned from the backside 106, as shown in FIG. 4C . The sensor substrate 102 is thinned so that charge carriers induced near the backside 106 of the sensor substrate 102 diffuse to the frontside 104. The thinning process can include mechanical grinding and chemical thinning. The mechanical grinding process first removes a substantial amount of substrate material from the sensor substrate 102, and then the chemical thinning process applies an etching chemical to the backside 106 of the sensor substrate 102 to further thin the sensor substrate 102 to a desired thickness. If the sensor substrate 102 is an SOI type, an incorporated buried oxide layer (BOX) can function as an etch stop layer. The desired thickness of the sensor substrate 102 can vary between approximately 3 μm and approximately 10 μm depending on the application type and design requirements of the image sensor device.

[0028]

[0033] In block 308 of the method 300, trenches 114 are etched into the sensor substrate 102 from the backside 106. Each pixel 108 is defined between two adjacent trenches 114, forming an array or grid of pixels 108. The pixels 108 may differ from one another, having different depths, thicknesses, widths, etc. Although only two pixels 108 and three trenches 114 are shown in FIG. 4D , any number of pixels 108 or trenches 114 may be implemented in the sensor substrate 102. The pixels 108 and trenches 114 have depths between about 3 μm and about 10 μm. The pixels 108 have widths between about 0.7 μm and about 2.5 μm, which may decrease to about 0.5 μm. The trenches 114 have widths between about 50 nm and about 300 nm and an aspect ratio between 50 and 100.

[0029]

[0034] At block 310 of the method 300, the exposed surface of the sensor substrate 102 on the backside 106 is pre-cleaned to remove organic materials, native oxides such as carbon dioxide, and other impurities to improve the performance of the image sensor device 100. The cleaning solution may include a mixture of HO-HSO and / or wet oxidation, dry oxidation, and aqueous HF (hydrofluoric acid). The cleaned surface of the sensor substrate 102 may be dried in a dryer to remove any residual liquid or particles. In some embodiments, the pre-cleaning process is performed at a low temperature of about 450° C. or less.

[0030]

[0035] 4E, a charge layer 116 is epitaxially grown on exposed surfaces of the sensor substrate 102 on the backside 106, including the interior walls of the trenches 114 (i.e., the exposed surfaces of the pixels 108). The charge layer 116 may be formed from boron-doped silicon (Si:B), boron-doped silicon germanium (SiGe:B), boron-doped germanium (Ge:B), or carbon-doped silicon (Si:C). The epitaxial growth of the charge layer 116 is achieved by supplying a source gas including a silicon source (e.g., SiH4 or SiHCl3) and a dopant, such as a boron compound (e.g., diborane, B2H6), at a low temperature (e.g., below about 450°C), thereby protecting the metal interconnects on the front side of the wafer and ensuring that the dopants implanted in the sensor substrate 102 do not migrate or become deactivated within the sensor substrate 102, which could damage the sensor substrate 102. Due to the nature of the epitaxial growth, the charge layer 116 passivates dangling bonds on exposed surfaces and conformally covers the surfaces of the pixels 108 on the backside 106, including the inner walls of the trenches 114. Charge carriers are activated from the dopants (e.g., boron) as the charge layer 116 is epitaxially grown, without the need for an activation anneal as is required to activate charges from implanted dopants. The density of activated charge carriers from dopants (e.g., boron) in charge layer 116 is 1×10 18 / cm 3 and 5×10 21 / cm 3The charge carriers activated in the charge layer 116 passivate (i.e., recombine) the charge carriers induced in defect centers and dangling bonds near the surface of the pixel 108, including the inner walls of the trench 114. These defect centers and dangling bonds are generated by device processing, such as the thinning process of block 306 and the etching process of block 308. The thickness of the charge layer 116 may be between approximately 5 nm and 50 nm. The charge layer 116 provides the same function as an etch stop layer as the BOX in the SOI type, in addition to other functions such as passivation, stress engineering, and bandpass filtering. In both the SOI type of the handle substrate 602 and the charge layer 116, the total thickness variation (TTV) is determined by the deposition process instead of the removal process.

[0031]

[0036] In block 314 of the method 300, the isolation structures 112 are formed by filling the trenches 114 with a dielectric material, such as silicon oxide or silicon nitride, or a polymetallic material, or by forming a capacitor with an air gap, as shown in FIG. 1. In some embodiments, the isolation structures 112 may include heavily doped n-type or p-type regions. The isolation structures 112 provide electrical and optical isolation between the pixels 108.

[0032]

[0037] It should be noted that the above-described specific exemplary embodiments are merely some possible examples of methods for manufacturing a semiconductor device having an integrated circuit according to the present disclosure, and do not limit the possible configurations or specifications of a liquid ejection device according to the present disclosure. For example, the present method may be applied to manufacturing other semiconductor devices, such as solar cells. Furthermore, the order of the blocks of the method 300 may be permuted, and some of the blocks of the method 300 may be repeated or omitted. The trench 114 may be etched from the front side 104 of the sensor substrate 102.

[0033]

[0038] 5 is a flow diagram of a method 500 for manufacturing an image sensor device 200, such as a back-illuminated (BSI) image sensor, according to a second embodiment of the present disclosure. FIGS. 6A to 6E schematically illustrate intermediate steps performed in the method 500. In the following description, components that are substantially the same as those in the first embodiment will be designated by the same reference numerals, and descriptions of duplicated components may be omitted. Furthermore, the method 500 according to the second embodiment may be combined with the method 300 according to the first embodiment.

[0034]

[0039] 6A, a layer 216 is epitaxially grown on a handle substrate 602. The epitaxially grown layer 216 (hereinafter referred to as "epi layer") may or may not contain a charge. The handle substrate 602 may be a silicon wafer, a Ge wafer, an SOI wafer, a III-V wafer with a p-type dopant such as boron or an n-type dopant such as phosphorus or arsenic, or may be intrinsic. The epi layer 216 may include boron-doped silicon (Si:B), boron-doped silicon germanium (SiGe:B), boron-doped germanium (Ge:B), or carbon-doped silicon (Si:C). The epitaxial growth of epilayer 216 is performed by supplying a source gas containing a silicon source (e.g., SiH4 or SiHCl3) and a dopant, such as a boron compound (e.g., diborane, B2H6), at a temperature between about 500° C. and about 900° C. The density of activated charge carriers from the dopant (e.g., boron) in epilayer 216 is about 1×10 17 / cm 3 and 5×10 21 / cm 3 The thickness of the epilayer 216 may be between about 5 nm and 100 nm.

[0035]

[0040] In block 504 of method 500, a semiconductor layer 604 is epitaxially grown on epi layer 216, as shown in FIG. 6B. Semiconductor layer 604 may be a single semiconductor material, such as silicon or germanium, or a compound semiconductor, such as silicon germanium, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide, III-V, III-nitrides, or a combination thereof. Semiconductor layer 604 may be a silicon-on-insulator (SOI) substrate including a semiconductor layer, such as silicon or germanium, formed on an insulator layer using wafer bonding and / or other suitable methods. The insulator layer may be formed from any suitable material, including silicon oxide, sapphire, other suitable insulating materials, and / or combinations thereof. An exemplary insulator layer may be a buried oxide layer (BOX) or an epitaxial oxide / silicon stack. The insulator layer is formed by any suitable process, such as separation by implantation of oxygen (SIMOX), oxidation, deposition, and / or other suitable processes. The substrate may have any suitable crystallographic orientation (e.g., (100), (110), (111), or (001) crystallographic orientation). The thickness of semiconductor layer 604 may range between approximately 100 microns (μm) and 1000 μm.

[0036]

[0041] 6C, a p-type dopant, such as boron, and an n-type dopant, such as phosphorus or arsenic, are doped into the semiconductor layer 604 by a suitable implantation process 606, such as a diffusion or epitaxial process, to form the sensor substrate 102. The front side 104 of the sensor substrate 102 is exposed, and the back side 106 of the sensor substrate 102 is in direct contact with the epi layer 216.

[0037]

[0042] In block 508 of the method 500 , as in block 304 , the interconnect structure 118 is formed on the front side 104 of the sensor substrate 102 .

[0038]

[0043] 6D, the sensor substrate 102 is flipped over and the handle substrate 602 is removed from the epi layer 216. The handle substrate 602 can be removed by grinding, chemical polishing, and wet or dry etching / cleaning. In some embodiments, the epi layer 216 is formed from a material having a different composition than the handle substrate 602, such as SiGeB, SiGeBC, Si:C, Si:B, Si:P, Si:PC, SiAs. Due to different material etch rates between the handle substrate 602 and the epi layer 216, the etching process stops at the epi layer 216.

[0039]

[0044] At block 512 of the method 500, trenches 214 are etched into the sensor substrate 102 from the backside 106. Each pixel 108 is defined between two adjacent trenches 214, forming an array or grid of pixels 108. The pixels 108 may differ from one another, having different depths, thicknesses, widths, etc. Although only two pixels 108 and three trenches 214 are shown in FIG. 6E, any number of pixels 108 or trenches 214 may be implemented in the sensor substrate 102. The trenches 214 have widths between about 50 nm and about 300 nm and aspect ratios between 10 and 100.

[0040]

[0045] 6F, a charge layer 218 is formed on the exposed surface of the sensor substrate 102 at the backside 106, including the interior walls of the trenches 214. In some embodiments, the charge layer 218 comprises boron-doped silicon (Si:B), boron-doped silicon germanium (SiGe:B), boron-doped germanium (Ge:B), or carbon-doped silicon (Si:C), which is epitaxially grown after the exposed surface of the sensor substrate 102 at the backside 106 is pre-cleaned, as in block 310 of the method 300. In some embodiments, the charge layer 218 is formed by adding a dielectric material to the exposed surface of the sensor substrate 102 at the backside 106 that has a charge type opposite to the desired type, thereby inducing the desired type of charge in the substrate near the backside 106.

[0041]

[0046] In block 516 of the method 500, the isolation structures 212 are formed by filling the trenches 214 with a dielectric material, such as silicon oxide or silicon nitride, or a polymetallic material, or by forming a capacitor with an air gap, as shown in FIG. 2. In some embodiments, the isolation structures 212 may include heavily doped n-type or p-type regions. The isolation structures 212 provide electrical and optical isolation between the pixels 108.

[0042]

[0047] It should be noted that the above-described specific exemplary embodiments are merely some possible examples of methods for manufacturing a semiconductor device having an integrated circuit according to the present disclosure, and do not limit the possible configurations or specifications of a liquid ejection device according to the present disclosure. For example, the present method may be applied to manufacturing other semiconductor devices, such as solar cells. Furthermore, the order of the blocks of the method 500 may be permuted, and some of the blocks of the method 500 may be repeated or omitted. The trench 214 may be etched from the front side 104 of the sensor substrate 102.

[0043]

[0048] In the exemplary embodiments described above, an image sensor and a method for fabricating the image sensor are provided for reducing noise in electrical signals converted from light energy in an array of pixels. An epitaxially grown charge layer in the image sensor provides a high concentration of charge carriers and passivates excess charge carriers generated at the surface of the pixels in the image sensor. The epitaxially grown charge layer can provide additional functions, such as an etch stop layer in the fabrication process or a getter to prevent metal diffusion within the image sensor, stress to tune the material bandgap / work function near the sensor surface, and / or isolation between signal and noise.

[0044]

[0049] While specific embodiments have been described, these embodiments are presented by way of example only and are not intended to limit the scope of the present invention. Indeed, the novel embodiments described herein may be embodied in a variety of other forms. Furthermore, various omissions, substitutions, and changes may be made in the form of the embodiments described herein without departing from the spirit of the present invention. The accompanying claims and their equivalents are intended to cover such forms or modifications within the scope and spirit of the present invention.

Claims

1. 1. A method for manufacturing a semiconductor device, comprising: forming an interconnect structure comprising a plurality of patterned dielectric and conductive layers on a front side of the sensor substrate; thinning the sensor substrate from a backside of the sensor substrate; thinning the sensor substrate and then etching a trench into the backside of the sensor substrate; pre-cleaning the exposed backside surface of the sensor substrate after etching the trench; epitaxially growing a charge layer directly onto the exposed pre-cleaned surface of the backside of the sensor substrate; forming an isolation structure in the etched trench after epitaxially growing the charge layer; Including, The method, wherein the charge layer comprises a material selected from boron-doped silicon, boron-doped silicon germanium, and boron-doped germanium.

2. The method of claim 1 , wherein the sensor substrate is a silicon photodiode.

3. The density of charge carriers in the charge layer is 1×10 １８ / cm ３ and 5 x 10 ２１ / cm ３ The method of claim 1 , wherein

4. The method of claim 1 , wherein the charge layer has a thickness between 5 nm and 50 nm.

5. The method of claim 1 , wherein the epitaxial growth of the charge layer is performed at a temperature of 450° C. or less.

6. The method of claim 1 , wherein the isolation structure comprises a dielectric material selected from silicon oxide and silicon nitride.

7. 1. A method for manufacturing a semiconductor device, comprising: epitaxially growing a layer directly on the surface of a handle substrate; epitaxially growing a semiconductor layer directly on the epitaxially grown layer, the semiconductor layer having a first side in direct contact with the epitaxially grown layer and a second side opposite the first side; injecting dopants into the semiconductor layer; forming an interconnect structure comprising a plurality of patterned dielectric and conductive layers on the second side of the semiconductor layer; removing the handle substrate from the epitaxially grown layers; removing the handle substrate and then etching a trench into the semiconductor layer from the first side; After etching the trench, epitaxially growing a charge layer directly on the etched surface; forming an isolation structure in the etched trench after epitaxially growing the charge layer; Including, The method, wherein the charge layer comprises a material selected from boron-doped silicon, boron-doped silicon germanium, and boron-doped germanium.

8. the semiconductor layer comprises silicon; the dopant comprises boron, phosphorus, or arsenide; The method of claim 7 , wherein the isolation structure comprises a dielectric material selected from silicon oxide and silicon nitride.

9. The density of charge carriers in the epitaxially grown layer is 1×10 １７ / cm ３ and 5 x 10 ２１ / cm ３ The method of claim 7, wherein 10. The method of claim 7, wherein the epitaxially grown layer has a thickness between 5 nm and 100 nm.

11. The method of claim 7, wherein the epitaxial growth of the epitaxially grown layer is performed at a temperature between 500°C and 900°C.

12. An image sensor, a sensor substrate having a front side and a back side; a plurality of pixels formed in the sensor substrate at the backside; a plurality of isolation structures formed in the sensor substrate, the plurality of pixels being separated from one another by one of the plurality of isolation structures; an interconnect structure overlying the front side of the sensor substrate, the interconnect structure including a plurality of patterned dielectric and conductive layers; and a charge layer epitaxially grown directly on the backside of the sensor substrate on the surfaces of the pixels and the areas between the pixels; Equipped with The image sensor, wherein the charge layer comprises a material selected from boron-doped silicon, boron-doped silicon germanium, and boron-doped germanium.

13. The image sensor of claim 12 , wherein the sensor substrate is a silicon photodiode.

14. The density of charge carriers in the charge layer is 1×10 １８ / cm ３ and 5 x 10 ２１ / cm ３ 13. The image sensor of claim 12, wherein:

15. The image sensor of claim 12 , wherein the charge layer has a thickness between 5 nm and 50 nm.

16. The image sensor of claim 12 , wherein the plurality of isolation structures comprises a silicon-containing dielectric material.

17. 13. The image sensor of claim 12, wherein each of the plurality of isolation structures has a width-to-depth aspect ratio of between 50 and 100.

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