Drive circuit, voltage converter, and control method thereof

Abstract

A drive circuit, a voltage converter, and a control method thereof are provided. [Solution] A drive circuit generates first and second control signals and provides them to respective control electrodes of first and second power semiconductor elements connected in parallel. The range of the safe operating area of ​​the first power semiconductor element is greater than the range of the safe operating area of ​​the second power semiconductor element. The drive circuit includes a time delay circuit, a control logic circuit, and a buffer. The time delay circuit compares the voltage level of the second control signal with a first reference voltage or compares the drain-source voltage of the first power semiconductor element with a second reference voltage, and generates a first voltage based on the comparison result. The first and second reference voltages are related to the temperatures of the first and second power semiconductor elements. The control logic circuit generates a logic signal based on the first voltage. The buffer generates the first or second control signal based on the logic signal.

Description

[Technical Field]

[0001] The present invention relates to a voltage converter, and more particularly to a drive circuit, a voltage converter and a control method thereof. [Background technology]

[0002] To realize a voltage converter with higher withstand voltage, a method of connecting the two power semiconductor elements of the upper and lower bridge sections in a cascode configuration is known. However, the use of a cascode configuration increases the conduction resistance, resulting in poor switching efficiency. Summary of the Invention

[0003] SUMMARY OF THE INVENTION An object of the present invention is to propose a driving circuit for generating a first control signal and a second control signal and providing the first and second control signals to control electrodes of a first power semiconductor element and a second power semiconductor element connected in parallel to each other in a voltage converter, where the range of the safe operating area of ​​the first power semiconductor element is greater than the range of the safe operating area of ​​the second power semiconductor element, the driving circuit including: a first time delay circuit for performing a first comparison operation to compare a voltage level of the second control signal with a first reference voltage and generate a corresponding first comparison result, or to compare a drain-source voltage of the first power semiconductor element with a second reference voltage and generate a corresponding second comparison result, and to generate a first voltage based on the first comparison result or the second comparison result, the first and second reference voltages being related to temperatures of the first and second power semiconductor elements; a control logic circuit coupled to the first time delay circuit and generating a first logic signal based on the first voltage; and a first buffer coupled to the control logic circuit and generating one of the first and second control signals based on the first logic signal.

[0004] An object of the present invention is to further propose a voltage converter including: a first power semiconductor element having a control electrode for receiving a first control signal; a second power semiconductor element connected in parallel to the first power semiconductor element and having a control electrode for receiving a second control signal, the second power semiconductor element having a safe operating area range smaller than that of the first power semiconductor element; a first time delay circuit performing a first comparison operation to compare a voltage level of the second control signal with a first reference voltage and generate a corresponding first comparison result, or to compare a first drain-source voltage of the first power semiconductor element with a second reference voltage and generate a corresponding second comparison result, and to generate a first voltage based on the first or second comparison result, wherein the first and second reference voltages are related to first temperatures of the first and second power semiconductor elements; a control logic circuit coupled to the first time delay circuit and for generating a first logic signal based on the first voltage and the pulse width modulated signal; and a first buffer coupled to the control logic circuit and for generating one of the first and second control signals based on the first logic signal.

[0005] An object of the present invention is to further propose a control method for a voltage converter, which is used to generate a first control signal and a second control signal to be respectively provided to a control electrode of a first power semiconductor element and a control electrode of a second power semiconductor element connected in parallel to each other in a voltage converter, wherein the range of the safe operating area of ​​the first power semiconductor element is greater than that of the second power semiconductor element, the control method comprising: receiving a pulse width modulated signal; performing a first comparison operation to compare a voltage level of the second control signal with a first reference voltage and generate a corresponding first comparison result, or to compare a drain-source voltage of the first power semiconductor element with a second reference voltage and generate a corresponding second comparison result, wherein the first and second reference voltages are related to temperatures of the first and second power semiconductor elements; generating a first voltage based on the first comparison result or the second comparison result; generating a first logic signal based on the first voltage; and buffering the first logic signal to generate one of the first and second control signals.

[0006] In order to make the above features and advantages of the present invention more clearly comprehensible, the following detailed description, taken in conjunction with the accompanying drawings, particularly illustrates the embodiments of the present invention. [Brief explanation of the drawings]

[0007] A better understanding of the present invention can be obtained from the following detailed description taken in conjunction with the accompanying drawings. Note that, in accordance with standard industry practice, the features are not drawn to scale. In fact, the dimensions of the features may be arbitrarily increased or decreased for clarity of discussion. [Figure 1] FIG. 2 is a circuit diagram of a voltage converter according to an embodiment of the present invention. [Figure 2] 4 is a signal timing chart of a voltage converter according to an embodiment of the present invention. [Figure 3] FIG. 2 is an exemplary circuit diagram of a control logic circuit according to an embodiment of the present invention. [Figure 4A] FIG. 2 is an exemplary circuit diagram of a temperature sensor and a time delay circuit according to an embodiment of the present invention. [Figure 4B] 1 is an exemplary circuit diagram of a time delay circuit according to an embodiment of the present invention; [Figure 5] 4 is a signal timing chart during the conduction stage of the upper bridge portion of the voltage converter according to an embodiment of the present invention; [Figure 6A] FIG. 2 is an exemplary circuit diagram of a temperature sensor and a time delay circuit according to an embodiment of the present invention. [Figure 6B] 1 is an exemplary circuit diagram of a time delay circuit according to an embodiment of the present invention; [Figure 7] 4 is a signal timing chart at the disconnection stage of the upper bridge portion of the voltage converter according to an embodiment of the present invention; [Figure 8] FIG. 2 is another exemplary circuit diagram of a time delay circuit according to an embodiment of the present invention. [Figure 9] FIG. 2 is another exemplary circuit diagram of a time delay circuit according to an embodiment of the present invention. [Figure 10A] FIG. 2 is an exemplary circuit diagram of a temperature sensor and a time delay circuit according to an embodiment of the present invention. [Figure 10B]1 is an exemplary circuit diagram of a time delay circuit according to an embodiment of the present invention; [Figure 11A] FIG. 2 is an exemplary circuit diagram of a temperature sensor and a time delay circuit according to an embodiment of the present invention. [Figure 11B] 1 is an exemplary circuit diagram of a time delay circuit according to an embodiment of the present invention; [Figure 12] FIG. 2 is another exemplary circuit diagram of a time delay circuit according to an embodiment of the present invention. [Figure 13] FIG. 2 is another exemplary circuit diagram of a time delay circuit according to an embodiment of the present invention. [Figure 14] FIG. 2 is a circuit diagram of a voltage converter according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0008] Below, embodiments of the present invention will be discussed in detail. However, as will be understood, the embodiments provide many applicable concepts that can be implemented in a variety of specific contexts. The discussed and disclosed embodiments are for illustrative purposes only and are not intended to limit the scope of the present invention. As used herein, terms such as "first," "second," etc., do not imply any particular order or ranking, but are used only to distinguish between elements or operations described with the same technical terminology.

[0009] FIG. 1 is a circuit diagram of a voltage converter 1 according to an embodiment of the present invention. In the embodiment of FIG. 1, the voltage converter 1 is a buck converter. The voltage converter 1 includes temperature sensors 122 and 162, time delay circuits 120, 140, 160, and 180, a control logic circuit 220, a buffer BF, power semiconductor devices NM1 to NM4, an inductor L, and an output capacitor Cout. The power semiconductor devices NM1 and NM2 form an upper bridge portion of the voltage converter 1, and the power semiconductor devices NM3 and NM4 form a lower bridge portion of the voltage converter 1.

[0010] The temperature sensor 122 is located adjacent to the power semiconductor elements NM1 and NM2, thereby sensing the temperature of the power semiconductor elements NM1 and NM2 (i.e., the temperature of the upper bridge portion) and outputting a sensed voltage Vtemp1 corresponding to the temperature (i.e., the sensed voltage Vtemp1 indicates the temperature of the power semiconductor elements NM1 and NM2). In this embodiment, as the temperatures of the power semiconductor elements NM1 and NM2 increase, the sensed voltage Vtemp1 increases accordingly. For example, different voltage values ​​of the sensed voltage Vtemp1 correspond to different temperature values ​​or temperature ranges of the power semiconductor elements NM1 and NM2. The temperature sensor 162 is located adjacent to the power semiconductor elements NM3 and NM4, thereby sensing the temperature of the power semiconductor elements NM3 and NM4 (i.e., the temperature of the lower bridge portion) and outputting a sensed voltage Vtemp2 corresponding to the temperature (i.e., the sensed voltage Vtemp2 indicates the temperature of the power semiconductor elements NM3 and NM4). In this embodiment, as the temperatures of the power semiconductor elements NM3 and NM4 increase, the sensed voltage Vtemp2 increases accordingly. For example, different voltage values ​​of the sense voltage Vtemp2 correspond to different temperature values ​​or different temperature ranges of the power semiconductor elements NM3 and NM4.

[0011] Time delay circuits 140 and 120 are coupled to temperature sensor 122 to receive sense voltage Vtemp1 from temperature sensor 122 and provide or generate voltages VG1 and VG2, respectively, based on sense voltage Vtemp1. Time delay circuits 180 and 160 are coupled to temperature sensor 162 to receive sense voltage Vtemp2 from temperature sensor 162 and provide voltages VG3 and VG4, respectively, based on sense voltage Vtemp2. ​​As can be seen from the above, time delay circuits 140, 120, 180, and 160 are used to provide voltages VG1, VG2, VG3, and VG4, respectively.

[0012] The control logic circuit 220 receives a pulse-width modulation (PWM) signal SPWM and is coupled to the time delay circuits 120, 140, 160, and 180 to receive voltages VG1, VG2, VG3, and VG4, respectively. As shown in FIG. 1, the control logic circuit 220 provides or generates logic signals SG1-SG4 based on the PWM signal SPWM and the voltages VG1-VG4. The buffer BF buffers the logic signals SG1-SG4. Specifically, the signal strengths of the logic signals SG1-SG4 are enhanced (driving capabilities are enhanced) by the buffer BF. The enhanced logic signals SG1, SG2, SG3, and SG4 are referred to as control signals SG10, SG20, SG30, and SG40, respectively. In other words, the control signals SG10, SG20, SG30, and SG40 are obtained by processing the logic signals SG1, SG2, SG3, and SG4 by the buffer BF (i.e., the control signals SG10, SG20, SG30, and SG40 are derived from the logic signals SG1, SG2, SG3, and SG4, respectively). The buffer BF provides the control signals SG10, SG20, SG30, and SG40 to the gates (also called control electrodes) G1, G2, G3, and G4 of the power semiconductor elements NM1, NM2, NM3, and NM4, respectively, to control or determine the conductive / non-conductive (ON / OFF) states of the power semiconductor elements NM1, NM2, NM3, and NM4, respectively. 1, temperature sensors 122 and 162, time delay circuits 120, 140, 160, and 180, buffer BF, and control logic circuit 220 comprise driver circuit 100, which is used to provide or generate control signals SG10, SG20, SG30, and SG40 to drive power semiconductor devices NM1, NM2, NM3, and NM4, respectively. In another embodiment, driver circuit 100 comprises time delay circuits 120, 140, 160, and 180, buffer BF, and control logic circuit 220, and temperature sensors 122 and 162 are external to driver circuit 100.

[0013] The PWM signal SPWM is a signal provided by a previous circuit (not shown in FIG. 1). The PWM signal SPWM can be switched or converted between a high voltage level and a low voltage level. The PWM signal SPWM switched or converted to a high voltage level instructs the voltage converter 1 to perform a conductive operation on its upper bridge section (i.e., power semiconductor devices NM1 and NM2), and at this time, the upper bridge section charges the output capacitor Cout through the inductor L. The PWM signal SPWM switched or converted to a low voltage level instructs the voltage converter 1 to perform a conductive operation on the lower bridge section (i.e., power semiconductor devices NM3 and NM4), and at this time, the lower bridge section discharges the output capacitor Cout through the inductor L. By charging and discharging the output capacitor Cout, the voltage converter 1 generates the output voltage VOUT.

[0014] In the voltage converter 1, the power semiconductor device NM1 is connected in parallel with the power semiconductor device NM2, so that the power semiconductor devices NM1 and NM2 have a common drain D1 and a common source S1. In an embodiment of the present invention, the safe operation area (SOA) of the power semiconductor device NM1 is larger than that of the power semiconductor device NM2, so that the power semiconductor device NM1 has a higher withstand voltage than the power semiconductor device NM2. In an embodiment of the present invention, the power semiconductor devices NM1 and NM2 are metal oxide semiconductor field effect transistors (MOSFETs), but the present invention is not limited thereto.

[0015] In the voltage converter 1, the power semiconductor element NM3 is connected in parallel with the power semiconductor element NM4, so that the power semiconductor elements NM3 and NM4 share a common drain D3 and a common source S3. In the embodiment of the present invention, the safe operating area (SOA) of the power semiconductor element NM3 is larger than that of the power semiconductor element NM4, so that the power semiconductor element NM3 has a higher withstand voltage than the power semiconductor element NM4. In the embodiment of the present invention, the power semiconductor elements NM3 and NM4 are metal oxide semiconductor field effect transistors, but the present invention is not limited thereto. See FIG. 1. The source S1 and the drain D3 are the same electrode point, and the source S3 is coupled to ground GND.

[0016] In known voltage converters, two power semiconductor devices in the upper bridge section (the same applies to the lower bridge section, and no further explanation will be given) are connected in a cascode configuration to increase the withstand voltage. However, adopting a cascode configuration increases the on-resistance of the upper bridge section, thereby reducing the switching efficiency of the upper bridge section. In contrast, in the present invention, the two power semiconductor devices in the upper bridge section (the same applies to the lower bridge section, and no further explanation will be given) are connected in parallel, significantly reducing the on-resistance. Compared to the known voltage converter, the voltage converter of the present invention can achieve a lower on-resistance using the same chip area, while also achieving a voltage converter with a similarly high withstand voltage, making it suitable for high-voltage voltage conversion applications. Because the on-resistance is small, the on-resistance loss is small and the switching efficiency is high. On the other hand, as can be seen, assuming that the on-resistance of the known voltage converter and the voltage converter of the present invention are the same, the voltage converter of the present invention can be realized using a smaller chip area, resulting in a higher cost advantage.

[0017] Specifically, the voltage converter of the present invention achieves a large safe operating area (SOA) range by connecting two power semiconductor devices in parallel in the upper bridge section and the lower bridge section, each with a different safe operating area range, thereby reducing the conduction resistance, power loss during switching, and chip area usage, and further increasing overall efficiency and enabling use at low cost.

[0018] It should be noted that in order for the voltage converter 1 to operate normally, the power semiconductor elements NM1 and NM2 in the upper bridge portion and the power semiconductor elements NM3 and NM4 in the lower bridge portion must be turned on and off in a specific order of priority, as will be explained below.

[0019] FIG. 2 is a signal timing diagram of a voltage converter 1 according to an embodiment of the present invention. As shown in FIG. 2, time periods t1, t2, and t3 are processes for turning on the upper bridge portion of the voltage converter 1 (i.e., power semiconductor devices NM1 and NM2). At the start of time period t1, the PWM signal SPWM is switched or converted from a low voltage level to a high voltage level, indicating that the upper bridge portion of the voltage converter 1 is about to be turned on. At the same time, the logic signal SG4 is converted from a high voltage level to a low voltage level, indicating that the corresponding buffer BF is blocking the power semiconductor device NM4. At the start of time period t2, the logic signal SG3 is converted from a high voltage level to a low voltage level, indicating that the corresponding buffer BF is blocking the power semiconductor device NM4. At the start of time period t3 (i.e., time T1), the logic signal SG1 is converted from a low voltage level to a high voltage level, indicating that the corresponding buffer BF is blocking the power semiconductor device NM1. Then, at the end of time period t3 (ie, time T2), logic signal SG2 is converted from a low voltage level to a high voltage level, causing power semiconductor device NM2 to become conductive via the corresponding buffer BF.

[0020] Specifically, the lower bridge section of voltage converter 1 must be turned off before the upper bridge section of voltage converter 1 is turned on. In this embodiment of the present invention, because the safe operating area of ​​power semiconductor device NM3 is greater than that of power semiconductor device NM4, the turn-off time of power semiconductor device NM3 must be later than the turn-off time of power semiconductor device NM4, thereby reducing the avalanche multiplication effect of the MOSFET. Specifically, the turn-off time of power semiconductor device NM3 must be later than the turn-off time of power semiconductor device NM4 to reach the optimal timing point for turning off the lower bridge section and ensure that power semiconductor devices NM3 and NM4 are within their nominal operating areas without being damaged. Therefore, as shown in FIG. 2, power semiconductor device NM4 is turned off before the start of time period t1, and power semiconductor device NM3 is turned off at the start of time period t2.

[0021] In addition, to ensure that voltage converter 1 can operate normally, a time delay (i.e., time period t2) is required to turn on the upper bridge portion of voltage converter 1 after turning off the lower bridge portion of voltage converter 1, thereby avoiding turning on the upper bridge portion when the lower bridge portion is not turned off. Thus, as shown in Figure 2, after turning off power semiconductor device NM3 at the start of time period t2, there is a time delay (i.e., time period t2), and then turning on power semiconductor device NM1 at the start of time period t3 (i.e., time T1).

[0022] After the lower bridge portion of voltage converter 1 is cut off, the upper bridge portion of voltage converter 1 is turned on. In this embodiment of the present invention, the safe operating area (SOA) of power semiconductor device NM1 is greater than that of power semiconductor device NM2. Therefore, the turn-on time of power semiconductor device NM1 must be earlier than the turn-on time of power semiconductor device NM2 to reach the optimal timing point for turning on the upper bridge portion and ensure that power semiconductor devices NM1 and NM2 are within their normal operating ranges without being damaged. Therefore, as shown in Figure 2, power semiconductor device NM1 is turned on before the start of time period t3, and power semiconductor device NM2 is turned on at the end of time period t3.

[0023] As shown in FIG. 2, time periods t4, t5, and t6 are the process of turning on the lower bridge portion of voltage converter 1 (i.e., power semiconductor devices NM3 and NM4). At the start of time period t4 (i.e., time T3), PWM signal SPWM is converted from a high voltage level to a low voltage level, indicating that the lower bridge portion of voltage converter 1 is about to begin conducting. At the same time, logic signal SG2 is converted from a high voltage level to a low voltage level, thereby turning off power semiconductor device NM2 via the corresponding buffer BF. At the start of time period t5 (i.e., time T4), logic signal SG1 is converted from a high voltage level to a low voltage level, thereby turning off power semiconductor device NM1 via the corresponding buffer BF. At the start of time period t6, logic signal SG3 is converted from a low voltage level to a high voltage level, thereby turning on power semiconductor device NM3 via the corresponding buffer BF. At the end of time period t6, logic signal SG4 is converted from a low voltage level to a high voltage level, thereby turning on power semiconductor device NM4 via the corresponding buffer BF.

[0024] Specifically, the upper bridge section of voltage converter 1 must be turned off before the lower bridge section of voltage converter 1 is turned on. In this embodiment of the present invention, because the safe operating area of ​​power semiconductor device NM1 is greater than that of power semiconductor device NM2, the turn-off time of power semiconductor device NM1 must be later than the turn-off time of power semiconductor device NM2, thereby reducing the avalanche multiplication effect of the MOSFET. Specifically, the turn-off time of power semiconductor device NM1 must be later than the turn-off time of power semiconductor device NM2 to reach the optimal timing point for turning off the upper bridge section and ensure that power semiconductor devices NM1 and NM2 are within their normal operating ranges. Therefore, as shown in FIG. 2 , power semiconductor device NM2 is turned off before the start of time period t4, and power semiconductor device NM1 is turned off at the start of time period t5.

[0025] In addition, to ensure that the voltage converter 1 can operate normally, a time delay (i.e., time period t5) is required to turn on the lower bridge portion of the voltage converter 1 after turning off the upper bridge portion of the voltage converter 1, thereby avoiding turning on the lower bridge portion when the upper bridge portion is not turned off. Thus, as shown in Figure 2, after turning off power semiconductor device NM1 at the start of time period t5 (i.e., time T4), there is a time delay (i.e., time period t5), and then turning on power semiconductor device NM3 at the start of time period t6.

[0026] After the upper bridge portion of voltage converter 1 is cut off, the lower bridge portion of voltage converter 1 is made conductive. In this embodiment of the present invention, because the safe operating area of ​​power semiconductor device NM3 is greater than that of power semiconductor device NM4, the conduction point of power semiconductor device NM3 must be made earlier than the conduction point of power semiconductor device NM4, thereby ensuring that power semiconductor device NM4 is within its normal operating range when it is made conductive, reaches the optimal timing point for making the lower bridge portion conductive, and ensures that power semiconductor devices NM3 and NM4 are within their normal operating ranges. Therefore, as shown in Figure 2, power semiconductor device NM3 is made conductive before the start of time period t6, and power semiconductor device NM4 is made conductive at the end of time period t6.

[0027] FIG. 3 is an exemplary circuit diagram of a control logic circuit 220 according to an embodiment of the present invention. The control logic circuit 220 includes AND gates AND1 through AND4, OR gates OR1 and OR2, and delays DL1 and DL2. The AND gate AND1 receives the PWM signal SPWM, an inverted signal of the logic signal SG3 (as shown in FIG. 3, the logic signal SG3 is received by the AND gate AND1 after passing through an inverter), and an inverted signal of the logic signal SG4. The input terminal of the OR gate OR1 is coupled to the output terminal of the AND gate AND1 via the delay DL1 (i.e., this input terminal of the OR gate OR1 is coupled to the output terminal of the AND gate AND1), and its other input terminal receives a voltage VG1, whereby the OR gate OR1 outputs the logic signal SG1 based on the voltage VG1. In other words, the control logic circuit 220 provides the logic signal SG1 based on the voltage VG1, the logic signals SG3 and SG4, and the PWM signal SPWM. The delay DL1 provides a delay time. In one embodiment, the length of the delay time provided by delay unit DL1 is equal to the length of time period t2 in FIG. 2, so time period t2 is also referred to as the delay time. AND gate AND2 receives the inverted signal of PWM signal SPWM, the inverted signal of logic signal SG1, and the inverted signal of logic signal SG2. An input terminal of OR gate OR2 is coupled to the output terminal of AND gate AND2 via delay unit DL2 (i.e., this input terminal of OR gate OR2 is coupled to the output terminal of AND gate AND2), and another input terminal thereof receives voltage VG3, so that OR gate OR2 outputs logic signal SG3 based on voltage VG3, logic signals SG1 and SG2, and PWM signal SPWM. Delay unit DL2 provides the delay time. In one embodiment, the length of the delay time provided by delay unit DL2 is equal to the length of time period t5 in FIG. 2, so time period t5 is also referred to as the delay time. The AND gate AND3 receives the PWM signal SPWM and the voltage VG2 and outputs the logic signal SG2 based thereon (in other words, the control logic circuit 220 provides the logic signal SG2 based on the PWM signal SPWM and the voltage VG2).The AND gate AND4 receives the inverted signal of the PWM signal SPWM and the voltage VG4 and outputs the logic signal SG4 based thereon (in other words, the control logic circuit 220 provides the logic signal SG4 based on the PWM signal SPWM and the voltage VG4).

[0028] 4A is an exemplary circuit diagram of a temperature sensor 122 and a time delay circuit 120 according to an embodiment of the present invention. As shown in FIG. 4A, the time delay circuit 120 receives a sensed voltage Vtemp1 from the temperature sensor 122. The time delay circuit 120 generates a reference voltage Vds1_adj based on the sensed voltage Vtemp1, compares the reference voltage Vds1_adj with a drain-source voltage VDS1 of the power semiconductor device NM1 (i.e., the voltage difference between the drain D1 and the source S1 in FIG. 1) to generate a comparison result, and outputs a voltage VG2 based on the comparison result.

[0029] 4A, the time delay circuit 120 includes a current source ITH1, a resistor Rds1_adj, and a comparator CMP1. The current source ITH1 is serially coupled with the resistor Rds1_adj between the system voltage VDD and ground GND. The positive input terminal (+) of the comparator CMP1 is coupled to the node between the current source ITH1 and the resistor Rds1_adj to receive a reference voltage Vds1_adj, and the negative input terminal (-) of the comparator CMP1 receives the drain-source voltage VDS1. The comparator CMP1 performs a comparison operation between the reference voltage Vds1_adj and the drain-source voltage VDS1. When the reference voltage Vds1_adj is greater than the drain-source voltage VDS1, the voltage VG2 output or generated at its output terminal by the comparator CMP1 based on the comparison result is a high voltage level. When the reference voltage Vds1_adj is smaller than the drain-source voltage VDS1, the voltage VG2 output or generated at its output terminal by the comparator CMP1 based on the comparison result is at a low voltage level.

[0030] As shown in FIG. 4A, resistor Rds1_adj receives sense voltage Vtemp1. In the embodiment of FIG. 4A, resistor Rds1_adj is a voltage-controlled element (i.e., a voltage-controlled resistor) that is responsive to sense voltage Vtemp1. As sense voltage Vtemp1 increases, the resistance of resistor Rds1_adj increases accordingly. The current output by current source ITH1 does not change with changes in temperature. In other words, since sense voltage Vtemp1 increases as the temperature of power semiconductor devices NM1 and NM2 increases, the resistance of resistor Rds1_adj increases as the temperature of power semiconductor devices NM1 and NM2 increases. Thus, reference voltage Vds1_adj increases as the temperature of power semiconductor devices NM1 and NM2 increases.

[0031] FIG. 5 is a signal timing chart showing the conduction stage of the upper bridge portion of the voltage converter 1 according to an embodiment of the present invention. Hereinafter, the detailed process of the conduction stage of the upper bridge portion of the voltage converter 1 will be further described with reference to FIGS. 1 to 4A and 5. First, before time T1, the logic signals SG1 and SG2 are all at a low voltage level (as shown in FIG. 2), and accordingly, the control signals SG10 and SG20 generated by the buffer BF are at a low voltage level (as shown in FIG. 5). As shown in FIG. 1, the control signals SG10 and SG20 are provided to the gate G1 of the power semiconductor device NM1 and the gate G2 of the power semiconductor device NM2, respectively, thereby turning off the power semiconductor devices NM1 and NM2.

[0032] Then, at time T1, the logic signal SG1 is converted from a low voltage level to a high voltage level (as shown in FIG. 2), which causes the control signal SG10 to be converted from a low voltage level to a high voltage level (as shown in FIG. 5), so that the high voltage level control signal SG10 turns on the power semiconductor element NM1.

[0033] After time T1, power semiconductor device NM1 becomes conductive, and thus the drain-source voltage VDS1 of power semiconductor device NM1 gradually decreases (as shown in FIG. 5). As shown in FIG. 4A, the temperatures of power semiconductor devices NM1 and NM2 gradually increase due to the conduction of power semiconductor device NM1, which in turn causes the reference voltage Vds1_adj to gradually increase. By time T2, the drain-source voltage VDS1 of power semiconductor device NM1 is already smaller than the reference voltage Vds1_adj (as shown in FIG. 5), and the voltage VG2 output by comparator CMP1 is accordingly converted from a low voltage level to a high voltage level. As can be seen from FIG. 2, at time T2, the PWM signal SPWM is at a high voltage level. Therefore, by the operation of AND gate AND3 in FIG. 3, the logic signal SG2 is switched to a high voltage level at time T2, and thus the control signal SG20 is also at a high voltage level, causing power semiconductor device NM2 to become conductive.

[0034] Specifically, the time delay circuit 120 controls the reference voltage Vds1_adj within the safe operating range of the power semiconductor element NM2, thereby ensuring that the drain-source voltage VDS1 when the power semiconductor element NM2 is turned on is also within the safe operating range of the power semiconductor element NM2, thereby ensuring that the power semiconductor elements NM1 and NM2 are within their normal operating ranges.

[0035] In the present invention, the time delay circuit 120 dynamically adjusts the time delay (i.e., time period t3) between the conduction time of power semiconductor device NM2 (i.e., time T2) and the conduction time of power semiconductor device NM1 (i.e., time T1) according to the temperatures of power semiconductor devices NM1 and NM2. In other words, the time delay is not a fixed length. Specifically, the upper bridge portion of the voltage converter 1 of the present invention has a mechanism for automatically adjusting the conduction delay by dynamically adjusting its conduction delay according to different temperatures to reach the optimal timing point for turning on the upper bridge portion.

[0036] Based on the above, the reference voltage Vds1_adj is related to the temperature of the power semiconductor devices NM1 and NM2. Specifically, the reference voltage Vds1_adj increases as the temperature of the power semiconductor devices NM1 and NM2 increases, and is controlled within the safe operating area of ​​the power semiconductor device NM2. In general, the safe operating area of ​​a power semiconductor device changes with temperature and / or process variations during its operation.

[0037] Therefore, in another embodiment of the present invention (e.g., the embodiment of FIG. 4B ), the voltage converter 1 may be coupled to or may include a memory that stores a look-up table. The memory may be provided in the drive circuit 100, for example, in the control logic circuit 220. The look-up table includes a plurality of different preset sense voltage values ​​as indexes and a plurality of different preset reference voltage values ​​as output values. The plurality of different preset sense voltages correspond to different temperature values ​​or different temperature ranges of the power semiconductor device, while the plurality of different preset reference voltages correspond to different safe operating area ranges of the power semiconductor device. In the look-up table, the plurality of different preset sense voltage values ​​may respectively correspond to the plurality of different preset reference voltage values, i.e., may respectively correspond to different safe operating area ranges, or at least two of the different preset sense voltage values ​​may correspond to the same preset reference voltage value, i.e., may correspond to the same safe operating area range.

[0038] See FIG. 4B. In some embodiments, the time delay circuit 120 includes only the comparator CMP1, but does not include the current source ITH1 and the resistor Rds1_adj of the embodiment of FIG. 4A. The positive input terminal (+) of the comparator CMP1 receives the reference voltage Vds1_adj, and the negative input terminal (−) thereof receives the drain-source voltage VDS1. The voltage converter 1 (or the drive circuit 100 or the control logic circuit 220) looks up the lookup table in the memory based on the value of the sense voltage Vtemp1 generated by the temperature sensor 122 (which corresponds to one preset sense voltage value in the lookup table) to obtain the corresponding preset reference voltage value as the reference voltage Vds1_adj. As can be seen from the above, the reference voltage Vds1_adj in FIG. 4B increases as the temperatures of the power semiconductor devices NM1 and NM2 increase, and corresponds to the range of the safe operating area of ​​the power semiconductor device NM2 at the temperatures of the power semiconductor devices NM1 and NM2.

[0039] See Figures 1, 2, 4B, and 5. At time T1, logic signal SG1 transitions from a low voltage level to a high voltage level (as shown in Figure 2), and control signal SG10 transitions accordingly from a low voltage level to a high voltage level (as shown in Figure 5), thereby turning on power semiconductor device NM1. In response to the conduction of power semiconductor device NM1, drain-source voltage VDS1 of power semiconductor device NM1 gradually decreases (as shown in Figure 5). Note that, as shown in Figure 4B, the temperatures of power semiconductor devices NM1 and NM2 gradually increase due to the conduction of power semiconductor device NM1, which causes reference voltage Vds1_adj to gradually increase. By time T2, drain-source voltage VDS1 is already smaller than reference voltage Vds1_adj (as shown in Figure 5), and voltage VG2 output by comparator CMP1 transitions accordingly from a low voltage level to a high voltage level. As can be seen from Figure 2, at time T2, PWM signal SPWM is at a high voltage level. 3, logic signal SG2 is switched to a high voltage level at time T2, so that control signal SG20 is also at a high voltage level, causing power semiconductor device NM2 to be turned on. In this way, time delay circuit 120 dynamically adjusts the time delay (i.e., time period t3) between the turn-on time of power semiconductor device NM2 (i.e., time T2) and the turn-on time of power semiconductor device NM1 (i.e., time T1) according to the temperatures of power semiconductor devices NM1 and NM2.

[0040] 6A is an exemplary circuit diagram of the temperature sensor 122 and the time delay circuit 140 according to an embodiment of the present invention. As shown in FIG. 6A, the time delay circuit 140 receives a sensed voltage Vtemp1 from the temperature sensor 122 and a control signal SG20. The time delay circuit 140 generates a reference voltage Vgs2_adj based on the sensed voltage Vtemp1, compares the voltage levels of the reference voltage Vgs2_adj and the control signal SG20 to generate a comparison result, and outputs a voltage VG1 based on the comparison result.

[0041] 6A, the time delay circuit 140 includes a current source ITH2, a resistor Rgs2_adj, and a comparator CMP2. The current source ITH2 is serially coupled with the resistor Rgs2_adj between the system voltage VDD and ground GND. The negative input terminal (-) of the comparator CMP2 is coupled to the node between the current source ITH2 and the resistor Rgs2_adj to receive the reference voltage Vgs2_adj, and the positive input terminal (+) of the comparator CMP2 receives the control signal SG20. The comparator CMP2 performs a comparison between the voltage level of the control signal SG20 and the reference voltage Vgs2_adj. If the voltage level of the control signal SG20 is greater than the reference voltage Vgs2_adj, the voltage VG1 output or generated by the comparator CMP2 at its output terminal based on the comparison result is a high voltage level. When the voltage level of the control signal SG20 is lower than the reference voltage Vgs2_adj, the voltage VG1 output or generated at the output terminal of the comparator CMP2 based on the comparison result is at a low voltage level.

[0042] As shown in FIG. 6A, resistor Rgs2_adj receives sense voltage Vtemp1. In the embodiment of FIG. 6A, resistor Rgs2_adj is a voltage-controlled element (i.e., a voltage-controlled resistor) that responds to sense voltage Vtemp1. As sense voltage Vtemp1 decreases, the resistance of resistor Rgs2_adj increases accordingly. The current output by current source ITH2 does not change with changes in temperature. In other words, since sense voltage Vtemp1 decreases as the temperature of power semiconductor elements NM1 and NM2 decreases, the resistance of resistor Rgs2_adj increases as the temperature of power semiconductor elements NM1 and NM2 decreases. Thus, reference voltage Vgs2_adj increases as the temperature of power semiconductor elements NM1 and NM2 decreases.

[0043] FIG. 7 is a signal timing chart showing the shut-off step of the upper bridge portion of the voltage converter 1 according to an embodiment of the present invention. Hereinafter, the detailed process of the shut-off step of the upper bridge portion of the voltage converter 1 will be further described with reference to FIGS. 1 to 3, 6A, and 7. First, before time T3, the logic signals SG1 and SG2 are all at a high voltage level (as shown in FIG. 2), and the control signals SG10 and SG20 generated by the buffer BF accordingly are at a high voltage level (as shown in FIG. 7). As shown in FIG. 1, the control signals SG10 and SG20 are provided to the gate G1 of the power semiconductor device NM1 and the gate G2 of the power semiconductor device NM2, respectively, thereby turning on the power semiconductor devices NM1 and NM2.

[0044] Then, at time T3, the logic signal SG2 is converted from a high voltage level to a low voltage level (as shown in FIG. 2), which causes the control signal SG20 to gradually decrease from a high voltage level to a low voltage level (as shown in FIG. 7), so that the control signal SG20 gradually shuts off the power semiconductor element NM2.

[0045] Also, after time T3, power semiconductor device NM2 is gradually shut down, and the temperatures of power semiconductor devices NM1 and NM2 gradually decrease as power semiconductor device NM2 is gradually shut down, causing reference voltage Vgs2_adj to gradually increase. By time T4, the voltage level of control signal SG20 is already smaller than reference voltage Vgs2_adj (as shown in FIG. 7), and voltage VG1 output by comparator CMP2 is accordingly converted from a high voltage level to a low voltage level. As can be seen from FIG. 2, at time T4, PWM signal SPWM is at a low voltage level. Therefore, by operation of AND gate AND1 and OR gate OR1 in FIG. 3, logic signal SG1 is switched from a high voltage level to a low voltage level at time T4, which in turn causes control signal SG10 to gradually decrease from a high voltage level to a low voltage level (as shown in FIG. 7), thereby gradually shutting down power semiconductor device NM1.

[0046] Specifically, the time delay circuit 140 controls the reference voltage Vgs2_adj within the off-operation range of the power semiconductor device NM2. The time delay circuit 140 also dynamically adjusts the shutdown delay of the power semiconductor device NM1 to ensure that the power semiconductor device NM2 has already been shut off, and then shuts off the power semiconductor device NM1. In this way, the power semiconductor devices NM1 and NM2 can be maintained within their normal operating ranges without being damaged.

[0047] In the present invention, the time delay circuit 140 dynamically adjusts the time delay (i.e., time period t4) between the cut-off time of power semiconductor device NM1 (i.e., time T4) and the cut-off time of power semiconductor device NM2 (i.e., time T3) according to the temperatures of power semiconductor devices NM1 and NM2. In other words, the time delay is not a fixed length. Specifically, the upper bridge portion of the voltage converter 1 of the present invention has a mechanism for automatically adjusting the cut-off delay by dynamically adjusting the cut-off delay according to different temperatures to reach the optimal timing point for cutting off the upper bridge portion.

[0048] Based on the above, the reference voltage Vgs2_adj is generated by the current source ITH2 and the resistor Rgs2_adj based on the sense voltage Vtemp1 and is related to the temperature of the power semiconductor devices NM1 and NM2. Specifically, the reference voltage Vgs2_adj increases as the temperature of the power semiconductor devices NM1 and NM2 decreases. In another embodiment, the reference voltage Vgs2_adj represents the threshold voltage (Vth) of the power semiconductor device NM2. Generally, the threshold voltage of a power semiconductor device changes with temperature and / or process variations during its operation.

[0049] In another embodiment of the present invention, the voltage converter 1 may be coupled to or may include a memory that stores a look-up table. The memory may be provided in the drive circuit 100, for example, in the control logic circuit 220. The look-up table includes a plurality of different preset sense voltage values ​​as indexes and a plurality of different preset reference voltage values ​​as output values. The plurality of different preset sense voltages correspond to different temperature values ​​or different temperature ranges of the power semiconductor device, while the plurality of different preset reference voltages correspond to different threshold voltages of the power semiconductor device. In the look-up table, the plurality of different preset sense voltage values ​​may each correspond to the plurality of different preset reference voltage values, i.e., different threshold voltages, or at least two of the different preset sense voltage values ​​may correspond to the same preset reference voltage value, i.e., the same threshold voltage.

[0050] See FIG. 6B. In some embodiments, the time delay circuit 140 includes only the comparator CMP2 and does not include the current source ITH2 and resistor Rgs2_adj of the embodiment of FIG. 6A. The positive input terminal (+) of the comparator CMP1 receives the control signal SG20, and the negative input terminal (−) receives the reference voltage Vgs2_adj. The voltage converter 1 (or the drive circuit 100 or the control logic circuit 220) looks up the lookup table in the memory based on the value of the sense voltage Vtemp1 generated by the temperature sensor 122 (which corresponds to one preset sense voltage value in the lookup table) to obtain the corresponding preset reference voltage value as the reference voltage Vgs2_adj. As can be seen from the above, the reference voltage Vgs2_adj in FIG. 6B increases as the temperatures of the power semiconductor devices NM1 and NM2 decrease, and corresponds to the threshold voltage of the power semiconductor device NM2 at the temperatures of the power semiconductor devices NM1 and NM2.

[0051] See Figures 1, 2, 6B, and 7. At time points T1 and T3, logic signal SG2 transitions from a high voltage level to a low voltage level (as shown in Figure 2), and control signal SG20 also gradually decreases from a high voltage level to a low voltage level (as shown in Figure 7), gradually shutting down power semiconductor device NM2. In response to power semiconductor device NM2 being gradually shut down, the temperatures of power semiconductor devices NM1 and NM2 gradually decrease as power semiconductor device NM2 is gradually shut down, thereby gradually increasing reference voltage Vgs2_adj. By time point T4, control signal SG20 is already smaller than reference voltage Vgs2_adj (as shown in Figure 7), and voltage VG1 output by comparator CMP2 is accordingly converted from a high voltage level to a low voltage level. As can be seen from Figure 2, at time point T4, PWM signal SPWM is at a low voltage level. 3, logic signal SG1 is switched from a high voltage level to a low voltage level at time T4, which causes control signal SG10 to gradually decrease from a high voltage level to a low voltage level (as shown in FIG. 7), causing control signal SG10 to gradually shut off power semiconductor device NM1. In this way, time delay circuit 140 dynamically adjusts the time delay (i.e., time period t4) between the shut-off time of power semiconductor device NM1 (i.e., time T4) and the shut-off time of power semiconductor device NM2 (i.e., time T3) according to the temperatures of power semiconductor devices NM1 and NM2.

[0052] 8 is another exemplary circuit diagram of a time delay circuit 120 according to an embodiment of the present invention. The time delay circuit 120 of FIG. 8 is similar to the time delay circuit 120 of FIG. 4A, except that the current source ITH1 and the resistor Rds1_adj of the time delay circuit 120 of FIG. 4A are replaced with a current source ITH1_adj and a resistor Rds1 in the time delay circuit 120 of FIG. 8. Specifically, the time delay circuit 120 of FIG. 8 has a similar function to the time delay circuit 120 of FIG. 4A, and therefore the time delay circuit 120 of the embodiment shown in FIG. 1 may be implemented using the time delay circuit 120 of FIG. 8.

[0053] Specifically, as shown in FIG. 8, the current source ITH1_adj has a resistor Rds1 serially coupled between the system voltage VDD and ground GND, and receives a sense voltage Vtemp1. In the embodiment of FIG. 8, the current source ITH1_adj is a voltage-controlled element (i.e., a voltage-controlled current source) responsive to the sense voltage Vtemp1. As the sense voltage Vtemp1 increases, the current of the current source ITH1_adj increases accordingly. The resistance of the resistor Rds1 does not change with temperature. In other words, the sense voltage Vtemp1 increases as the temperature of the power semiconductor devices NM1 and NM2 increases, and therefore the current output by the current source ITH1_adj also increases as the temperature of the power semiconductor devices NM1 and NM2 increases. Thus, the reference voltage Vds1_adj increases as the temperature of the power semiconductor devices NM1 and NM2 increases.

[0054] 9 is another exemplary circuit diagram of a time delay circuit 140 according to an embodiment of the present invention. The time delay circuit 140 of FIG. 9 is similar to the time delay circuit 140 of FIG. 6A, except that the current source ITH2 and the resistor Rgs2_adj of the time delay circuit 140 of FIG. 6A are replaced with a current source ITH2_adj and a resistor Rgs2 in the time delay circuit 140 of FIG. 9. Specifically, since the time delay circuit 140 of FIG. 9 has a similar function to the time delay circuit 140 of FIG. 6A, the time delay circuit 140 of the embodiment shown in FIG. 1 may be realized using the time delay circuit 140 of FIG. 9.

[0055] Specifically, as shown in FIG. 9 , the current source ITH2_adj has a resistor Rgs2 serially coupled between the system voltage VDD and ground GND, and the current source ITH2_adj receives a sense voltage Vtemp1. In the embodiment of FIG. 9 , the current source ITH2_adj is a voltage-controlled element (i.e., a voltage-controlled current source) responsive to the sense voltage Vtemp1. As the sense voltage Vtemp1 decreases, the current of the current source ITH2_adj increases accordingly. The resistance of the resistor Rgs2 does not change with temperature. In other words, the sense voltage Vtemp1 decreases as the temperature of the power semiconductor devices NM1 and NM2 decreases, and therefore the current output by the current source ITH2_adj also increases as the temperature of the power semiconductor devices NM1 and NM2 decreases. Thus, the reference voltage Vgs2_adj increases as the temperature of the power semiconductor devices NM1 and NM2 decreases.

[0056] 10A is an exemplary circuit diagram of a temperature sensor 162 and a time delay circuit 160 according to an embodiment of the present invention. As shown in FIG. 10A, the time delay circuit 160 receives a sensed voltage Vtemp2 from the temperature sensor 162. The time delay circuit 160 generates a reference voltage Vds3_adj based on the sensed voltage Vtemp2, compares the reference voltage Vds3_adj with a drain-source voltage VDS3 of the power semiconductor device NM3 (i.e., the voltage difference between the drain D3 and the source S3 in FIG. 1) to generate a comparison result, and outputs a voltage VG4 based on the comparison result.

[0057] 10A, the time delay circuit 160 includes a current source ITH3, a resistor Rds3_adj, and a comparator CMP3. The current source ITH3 is serially coupled with the resistor Rds3_adj between the system voltage VDD and ground GND. The positive input terminal (+) of the comparator CMP3 is coupled to a node between the current source ITH3 and the resistor Rds3_adj to receive a reference voltage Vds3_adj, and the negative input terminal (-) of the comparator CMP3 receives the drain-source voltage VDS3 of the power semiconductor device NM3. The comparator CMP3 performs a comparison operation between the reference voltage Vds3_adj and the drain-source voltage VDS3. If the reference voltage Vds3_adj is greater than the drain-source voltage VDS3, the voltage VG4 output or generated by the comparator CMP3 at its output terminal based on the comparison result is a high voltage level. When the reference voltage Vds3_adj is smaller than the drain-source voltage VDS3, the voltage VG4 output or generated at its output terminal by the comparator CMP3 based on the comparison result is at a low voltage level.

[0058] As shown in FIG. 10A, resistor Rds3_adj receives sense voltage Vtemp2. ​​In the embodiment of FIG. 10A, resistor Rds3_adj is a voltage-controlled element (i.e., a voltage-controlled resistor) responsive to sense voltage Vtemp2. ​​As sense voltage Vtemp2 increases, the resistance of resistor Rds3_adj increases accordingly. The current output by current source ITH3 does not change with temperature. In other words, since sense voltage Vtemp2 increases as the temperature of power semiconductor devices NM3 and NM4 increases, the resistance of resistor Rds3_adj also increases as the temperature of power semiconductor devices NM3 and NM4 increases. Thus, reference voltage Vds3_adj increases as the temperature of power semiconductor devices NM3 and NM4 increases. The operational logic of time delay circuit 160 is similar to that of time delay circuit 120 of FIG. 4A, and a detailed description of its operation will be omitted here.

[0059] Based on the above, the reference voltage Vds3_adj is related to the temperature of the power semiconductor devices NM3 and NM4. Specifically, the reference voltage Vds3_adj increases as the temperature of the power semiconductor devices NM3 and NM4 increases, and is controlled within the safe operating area of ​​the power semiconductor device NM2. In general, the safe operating area of ​​a power semiconductor device changes with temperature and / or process variations during its operation.

[0060] Therefore, in another embodiment of the present invention (e.g., the embodiment of FIG. 10B ), the voltage converter 1 may be coupled to or may include a memory that stores a look-up table. The memory may be provided in the drive circuit 100, for example, in the control logic circuit 220. The look-up table includes a plurality of different preset sense voltage values ​​as indexes and a plurality of different preset reference voltage values ​​as output values. The plurality of different preset sense voltages correspond to different temperature values ​​or temperature ranges of the power semiconductor device, while the plurality of different preset reference voltages correspond to different safe operating area ranges of the power semiconductor device.

[0061] See FIG. 10B. In some embodiments, the time delay circuit 160 includes only the comparator CMP3, but does not include the current source ITH3 and resistor Rds3_adj of the embodiment of FIG. 10A. The positive input terminal (+) of the comparator CMP3 receives the reference voltage Vds3_adj, and the negative input terminal (−) thereof receives the drain-source voltage VDS3. The voltage converter 1 (or the drive circuit 100 or the control logic circuit 220) looks up the lookup table in the memory based on the value of the sense voltage Vtemp2 generated by the temperature sensor 162 (which corresponds to one preset sense voltage value in the lookup table) to obtain the corresponding preset reference voltage value as the reference voltage Vds3_adj. The reference voltage Vds3_adj in FIG. 10B increases as the temperatures of the power semiconductor elements NM3 and NM4 increase and corresponds to the range of the safe operating area of ​​the power semiconductor element NM4 at the temperatures of the power semiconductor elements NM3 and NM4. The operation logic of the time delay circuit 160 of Fig. 10B is similar to that of the time delay circuit 120 of Fig. 4B, and a detailed operation description will be omitted here. According to the embodiment of Fig. 10B, the time delay circuit 160 can dynamically adjust the time delay (i.e., time period t6) between the conduction time of the power semiconductor device NM4 and the conduction time of the power semiconductor device NM3 according to the temperatures of the power semiconductor devices NM3 and NM4.

[0062] In some embodiments, when the embodiments of Figures 4B and 10B are employed simultaneously, voltage converter 1 may be coupled to or include a memory that stores a look-up table for obtaining reference voltages Vds1_adj and Vds3_adj.

[0063] 11A is an exemplary circuit diagram of a temperature sensor 162 and a time delay circuit 180 according to an embodiment of the present invention. As shown in FIG. 11A, the time delay circuit 180 receives a sensed voltage Vtemp2 from the temperature sensor 162. The time delay circuit 180 is used to generate a reference voltage Vgs4_adj based on the sensed voltage Vtemp2, compare the reference voltage Vgs4_adj with the voltage level of the control signal SG40 to generate a comparison result, and output a voltage VG3 based on the comparison result.

[0064] 11A, the time delay circuit 180 includes a current source ITH4, a resistor Rgs4_adj, and a comparator CMP4. The current source ITH4 is serially coupled with the resistor Rgs4_adj between the system voltage VDD and ground GND. The negative input terminal (-) of the comparator CMP4 is coupled to the node between the current source ITH4 and the resistor Rgs4_adj to receive the reference voltage Vgs4_adj, and the positive input terminal (+) of the comparator CMP4 receives the reference voltage Vgs4_adj. The comparator CMP4 compares the voltage level of the control signal SG40 with the reference voltage Vgs4_adj. If the voltage level of the control signal SG40 is greater than the reference voltage Vgs4_adj, the voltage VG3 output or generated by the comparator CMP4 at its output terminal based on the comparison result is a high voltage level. When the voltage level of the control signal SG40 is lower than the reference voltage Vgs4_adj, the voltage VG3 output or generated at the output terminal of the comparator CMP4 based on the comparison result is at a low voltage level.

[0065] As shown in FIG. 11A, resistor Rgs4_adj receives sense voltage Vtemp2. ​​In the embodiment of FIG. 11A, resistor Rgs4_adj is a voltage-controlled element (i.e., a voltage-controlled resistor) responsive to sense voltage Vtemp2. ​​As sense voltage Vtemp2 decreases, the resistance of resistor Rgs4_adj increases accordingly. Furthermore, the current output by current source ITH4 does not change with temperature. In other words, since sense voltage Vtemp2 decreases as the temperature of power semiconductor devices NM3 and NM4 decreases, the resistance of resistor Rgs4_adj also increases as the temperature of power semiconductor devices NM3 and NM4 decreases. Thus, reference voltage Vgs4_adj increases as the temperature of power semiconductor devices NM3 and NM4 decreases. The operational logic of time delay circuit 180 is similar to that of time delay circuit 140 of FIG. 6A, and a detailed description of its operation will be omitted here.

[0066] Based on the above, the reference voltage Vgs4_adj is generated by the current source ITH4 and the resistor Rgs4_adj based on the sense voltage Vtemp2 and is related to the temperature of the power semiconductor devices NM3 and NM4. Specifically, the reference voltage Vgs4_adj increases as the temperature of the power semiconductor devices NM3 and NM4 decreases. In another embodiment, the reference voltage Vgs4_adj represents the threshold voltage of the power semiconductor device NM4. Generally, the threshold voltage of a power semiconductor device changes with temperature and / or process variations during its operation.

[0067] In another embodiment of the present invention, the voltage converter 1 may be coupled to or include a memory that stores a look-up table. The memory may be provided in the drive circuit 100, for example, in the control logic circuit 220. The look-up table includes a plurality of different preset sense voltage values ​​as indexes and a plurality of different preset reference voltage values ​​as output values. The plurality of different preset sense voltages correspond to different temperature values ​​or different temperature ranges of the power semiconductor device, while the plurality of different preset reference voltages correspond to different threshold voltages of the power semiconductor device.

[0068] See FIG. 11B. In some embodiments, the time delay circuit 180 includes only the comparator CMP4, but does not include the current source ITH4 and resistor Rgs4_adj of the embodiment of FIG. 11A. The positive input terminal (+) of the comparator CMP4 receives the control signal SG40, and the negative input terminal (−) receives the reference voltage Vgs4_adj. The voltage converter 1 (or the drive circuit 100 or the control logic circuit 220) looks up the lookup table in the memory based on the value of the sense voltage Vtemp2 generated by the temperature sensor 162 (which corresponds to one preset sense voltage value in the lookup table) to obtain the corresponding preset reference voltage value as the reference voltage Vgs4_adj. As can be seen from the above, the reference voltage Vgs4_adj in FIG. 11B increases as the temperatures of the power semiconductor elements NM3 and NM4 decrease, and corresponds to the threshold voltage of the power semiconductor element NM4 at the temperatures of the power semiconductor elements NM3 and NM4. The operation logic of the time delay circuit 180 of Fig. 11B is similar to the operation of the time delay circuit 140 of Fig. 6B, and a detailed operation description will be omitted here. According to the embodiment of Fig. 11B, the time delay circuit 180 can dynamically adjust the time delay (i.e., time period t1) between the cut-off time of the power semiconductor element NM3 and the cut-off time of the power semiconductor element NM4 according to the temperatures of the power semiconductor elements NM3 and NM4.

[0069] In some embodiments, when the embodiments of Figures 6B and 11B are employed simultaneously, voltage converter 1 may be coupled to or include a memory that stores a look-up table for obtaining reference voltages Vgs2_adj and Vgs4_adj.

[0070] In another embodiment, when the embodiments of Figures 4B, 6B, 10B, and 11B are simultaneously employed, the voltage converter 1 may be coupled to or include a memory that stores two lookup tables. One lookup table is used to obtain the reference voltages Vds1_adj and Vds3_adj, and the other lookup table is used to obtain the reference voltages Vgs2_adj and Vgs4_adj. When the embodiments of Figures 4B, 6B, 10B, and 11B are simultaneously employed, the time periods t1, t3, t4, and t6 can be shortened, and the delays DL1 and DL2 of Figure 3 can be omitted, thereby improving the operating efficiency of the voltage converter 1. When the delays DL1 and DL2 of Figure 3 are omitted, the input terminal of the OR gate OR1 is directly coupled to the output terminal of the AND gate AND1, and the input terminal of the OR gate OR2 is directly coupled to the output terminal of the AND gate AND2.

[0071] 12 is another exemplary circuit diagram of a time delay circuit 160 according to an embodiment of the present invention. The time delay circuit 160 of FIG. 12 is similar to the time delay circuit 160 of FIG. 10A, except that the current source ITH3 and the resistor Rds3_adj of the time delay circuit 160 of FIG. 10A are replaced with a current source ITH3_adj and a resistor Rds3 in the time delay circuit 160 of FIG. 12. Specifically, since the time delay circuit 160 of FIG. 12 has a similar function to the time delay circuit 160 of FIG. 10A, the time delay circuit 160 of the embodiment shown in FIG. 1 may be implemented using the time delay circuit 160 of FIG. 12.

[0072] Specifically, as shown in FIG. 12, the current source ITH3_adj has a resistor Rds3 serially coupled between the system voltage VDD and ground GND, and receives a sense voltage Vtemp2. ​​In the embodiment of FIG. 12, the current source ITH3_adj is a voltage-controlled element (i.e., a voltage-controlled current source) responsive to the sense voltage Vtemp2. ​​As the sense voltage Vtemp2 increases, the current of the current source ITH3_adj increases accordingly. The resistance value of the resistor Rds3 does not change with temperature. In other words, since the sense voltage Vtemp2 increases as the temperature of the power semiconductor devices NM3 and NM4 increases, the current output by the current source ITH3_adj also increases as the temperature of the power semiconductor devices NM3 and NM4 increases. Thus, the reference voltage Vds3_adj increases as the temperature of the power semiconductor devices NM3 and NM4 increases.

[0073] 13 is another exemplary circuit diagram of a time delay circuit 180 according to an embodiment of the present invention. The time delay circuit 180 of FIG. 13 is similar to the time delay circuit 180 of FIG. 11A, except that the current source ITH4 and the resistor Rgs4_adj of the time delay circuit 180 of FIG. 11A are replaced with the current source ITH4_adj and the resistor Rgs4 in the time delay circuit 180 of FIG. 13. Specifically, since the time delay circuit 180 of FIG. 13 has a similar function to the time delay circuit 180 of FIG. 11A, the time delay circuit 180 of the embodiment shown in FIG. 1 may be implemented using the time delay circuit 180 of FIG. 13.

[0074] Specifically, as shown in FIG. 13, the current source ITH4_adj has a resistor Rgs4 serially coupled between the system voltage VDD and ground GND, and the current source ITH4_adj receives the sense voltage Vtemp2. ​​In the embodiment of FIG. 13, the current source ITH4_adj is a voltage-controlled element (i.e., a voltage-controlled current source) responsive to the sense voltage Vtemp2. ​​As the sense voltage Vtemp2 decreases, the current of the current source ITH4_adj increases accordingly. The resistance of the resistor Rgs4 does not change with temperature. In other words, the sense voltage Vtemp2 decreases as the temperature of the power semiconductor elements NM3 and NM4 decreases, and therefore the current output by the current source ITH4_adj also increases as the temperature of the power semiconductor elements NM3 and NM4 decreases. Thus, the reference voltage Vgs4_adj increases as the temperature of the power semiconductor elements NM3 and NM4 decreases.

[0075] Below, the detailed process at various stages of voltage converter 1 will be described in detail with reference to Figures 1 through 4A, 6A, 10A, and 11A. Before the start of time period t1, logic signals SG1 and SG2 are at a low voltage level. At the start of time period t1, PWM signal SPWM changes from a low voltage level to a high voltage level, indicating that the upper bridge portion of voltage converter 1 (i.e., power semiconductor devices NM1 and NM2) is about to be turned on. Therefore, the lower bridge portion of voltage converter 1 (i.e., power semiconductor devices NM3 and NM4) must be turned off first. Note that the safe operating area of ​​power semiconductor device NM3 is larger than the safe operating area of ​​power semiconductor device NM4, so power semiconductor device NM3 must be turned off later than power semiconductor device NM4. As can be seen from Figure 3, the inverted signal of PWM signal SPWM received by AND gate AND4 is turned from a high voltage level to a low voltage level, and therefore the logic signal SG4 output by AND gate AND4 is turned from a high voltage level to a low voltage level.

[0076] As described above, at the start of time period t1, logic signal SG4 transitions from a high voltage level to a low voltage level, causing control signal SG40 to gradually decrease from a high voltage level to a low voltage level during time period t1, thereby gradually shutting down power semiconductor device NM4. As power semiconductor device NM4 gradually shuts down, the temperatures of power semiconductor devices NM3 and NM4 gradually decrease, causing reference voltage Vgs4_adj to gradually increase. By the end of time period t1, control signal SG40 is already less than reference voltage Vgs4_adj, causing voltage VG3 output by comparator CMP4 of time delay circuit 180 of FIG. 11A to transition from a high voltage level to a low voltage level. As can be seen from FIG. 2, at the end of time period t1, the PWM signal SPWM is at a high voltage level, so that based on the operation of the AND gate AND2, the delay unit DL2, and the OR gate OR2 in FIG. 3, the logic signal SG3 is converted from a high voltage level to a low voltage level, whereby the control signal SG30 also gradually decreases from a high voltage level to a low voltage level, so that the control signal SG30 gradually turns off the power semiconductor element NM3.

[0077] As described above, at the beginning of time period t2 (i.e., the end of time period t1), logic signal SG3 is converted from a high voltage level to a low voltage level. During time period t2, based on the operation of time delay circuit 140, output voltage VG1 is at a low voltage level, which causes OR gate OR1 to depend on the output signal of AND gate AND1. As logic signal SG3 is converted to a low voltage level by the operation of AND gate AND1 and OR gate OR1 in FIG. 3, logic signal SG1 is converted from a low voltage level to a high voltage level at the end of time period t2, thereby causing power semiconductor device NM1 to conduct. However, since the delay element DL1 is coupled between the AND gate AND1 and the OR gate OR1 (i.e., the input terminal of the OR gate OR1 is coupled to the output terminal of the AND gate AND1 via the delay element DL1), the AND gate AND1 must go through a time period t2 (i.e., the delay time of the delay element DL1) to convert the logic signal SG3 from a high voltage level to a low voltage level, and then convert its output signal from a low voltage level to a high voltage level, and then convert the logic signal SG1 from a low voltage level to a high voltage level.

[0078] Then, during time period t3, because power semiconductor device NM1 is turned on, the drain-source voltage VDS1 of power semiconductor device NM1 gradually decreases and the temperatures of power semiconductor devices NM1 and NM2 rise, causing reference voltage Vds1_adj to gradually increase accordingly, and by the end of time period t3 (time point T2), the drain-source voltage VDS1 of power semiconductor device NM1 is already smaller than reference voltage Vds1_adj, and voltage VG2 output by comparator CMP1 of time delay circuit 120 of Figure 4A is accordingly converted from a low voltage level to a high voltage level. Therefore, by the operation of AND gate AND3 in Figure 3, at the end of time period t3, logic signal SG2 is converted from a low voltage level to a high voltage level, thereby turning on power semiconductor device NM2.

[0079] Then, at the start of time period t4, the PWM signal SPWM is converted from a high voltage level to a low voltage level, indicating that the lower bridge portion of voltage converter 1 (i.e., power semiconductor devices NM3 and NM4) is about to be turned on. Therefore, the upper bridge portion of voltage converter 1 (i.e., power semiconductor devices NM1 and NM2) must be turned off first. Note that the safe operating area of ​​power semiconductor device NM1 is larger than the safe operating area of ​​power semiconductor device NM2, so the turning off of power semiconductor device NM1 must be later than the turning off of power semiconductor device NM2. As can be seen from Figure 3, at this time, the PWM signal SPWM received by AND gate AND3 is converted from a high voltage level to a low voltage level, and therefore the logic signal SG2 output by AND gate AND3 is converted from a high voltage level to a low voltage level.

[0080] As described above, at the start of time period t4 (i.e., time T3), logic signal SG2 transitions from a high voltage level to a low voltage level, which causes control signal SG20 to gradually decrease from a high voltage level to a low voltage level during time period t4. Therefore, control signal SG20 gradually shuts off power semiconductor device NM2. As power semiconductor device NM2 gradually shuts off, the temperatures of power semiconductor devices NM1 and NM2 gradually decrease, which causes reference voltage Vgs2_adj to gradually increase. By the end of time period t4 (i.e., time T4), control signal SG20 is already less than reference voltage Vgs2_adj, and voltage VG1 output by comparator CMP2 of time delay circuit 140 of FIG. 6A transitions from a high voltage level to a low voltage level. As can be seen from FIG. 2, at the end of time period t4, the PWM signal SPWM is at a low voltage level, and therefore, through the operation of the AND gate AND1 and the OR gate OR1 in FIG. 3, the logic signal SG1 is converted from a high voltage level to a low voltage level, and as a result, the control signal SG10 also gradually decreases from a high voltage level to a low voltage level, and therefore the control signal SG10 gradually shuts off the power semiconductor element NM1.

[0081] As described above, at the beginning of time period t5 (i.e., time T4), logic signal SG1 transitions from a high voltage level to a low voltage level. During time period t5, based on the operation of time delay circuit 180, output voltage VG3 is at a low voltage level, which causes OR gate OR2 to depend on the output signal of AND gate AND2. As logic signal SG1 transitions to a low voltage level due to the operation of AND gate AND2 and OR gate OR2 of FIG. 3, logic signal SG3 transitions from a low voltage level to a high voltage level at the end of time period t5, thereby causing power semiconductor device NM3 to conduct. However, since the delay element DL2 is coupled between the AND gate AND2 and the OR gate OR2 (i.e., the input terminal of the OR gate OR2 is coupled to the output terminal of the AND gate AND2 via the delay element DL2), the AND gate AND2 must convert its output signal from a low voltage level to a high voltage level in response to the logic signal SG1 being converted from a high voltage level to a low voltage level, and then must pass through a time period t5 (i.e., the delay time of the delay element DL2) to convert the logic signal SG3 from a low voltage level to a high voltage level.

[0082] Then, during time period t6, because power semiconductor device NM3 is turned on, the drain-source voltage VDS3 of power semiconductor device NM3 gradually decreases and the temperatures of power semiconductor devices NM3 and NM4 rise, causing reference voltage Vds3_adj to gradually increase accordingly, and by the end of time period t6, the drain-source voltage VDS3 of power semiconductor device NM3 is already smaller than reference voltage Vds3_adj, and voltage VG4 output by comparator CMP3 of time delay circuit 160 of Figure 10A is accordingly converted from a low voltage level to a high voltage level. Therefore, by the operation of AND gate AND4 of Figure 3, at the end of time period t6, logic signal SG4 is converted from a low voltage level to a high voltage level, thereby turning on power semiconductor device NM4.

[0083] 14 is a circuit diagram of a voltage converter 14 according to an embodiment of the present invention. The voltage converter 14 is similar to the voltage converter 1 shown in FIG. 1, except that the voltage converter 14 is a boost converter.

[0084] See Figure 14. When the PWM signal SPWM is at a low voltage level, the voltage converter 14 conducts its lower bridge portion (i.e., power semiconductor devices NM3 and NM4), and at this time, current from the system voltage VDD flows through the inductor L to store energy. When the PWM signal SPWM is at a high voltage level, the voltage converter 14 conducts its upper bridge portion (i.e., power semiconductor devices NM1 and NM2), and at this time, current flowing through the inductor L charges the output capacitor Cout through the upper bridge portion, and the voltage converter 14 outputs a voltage Vout based on this.

[0085] The signal timing diagram of the voltage converter 14 is also similar to that shown in FIG. 2, and the exemplary circuit diagram of the control logic circuit 220 of the voltage converter 14 is also similar to that shown in FIG. 3, so the operation process thereof will not be further described here.

[0086] According to the above embodiments, in the control method for a voltage converter of the present invention, the control logic circuit 220 receives the PWM signal SPWM and uses the PWM signal SPWM as a base signal to control the operation of the upper bridge section and the lower bridge section of the voltage converter 1. Hereinafter, the control method of the present invention will be described by taking the operation of controlling the upper bridge section as an example.

[0087] According to the control method of the present invention, the time delay circuit 140 performs a comparison operation to compare the voltage level of the control signal SG20 with the reference voltage Vgs2_adj and generate a corresponding comparison result. The time delay circuit 140 generates the voltage VG1 based on the comparison result. Meanwhile, the time delay circuit 120 performs another comparison operation to compare the drain-source voltage VDS1 of the power semiconductor device NM1 with the reference voltage Vds1_adj and generate a corresponding comparison result. The time delay circuit 140 generates the voltage VG2 based on the comparison result. In this embodiment of the present invention, the reference voltages Vgs2_adj and Vds1_adj are both related to the temperatures of the power semiconductor devices NM1 and NM2. The control logic circuit 220 generates the logic signal SG1 based on the voltage VG1 and the PWM signal SPWM, and generates the logic signal SG2 based on the voltage VG2 and the PWM signal SPWM. The logic signals SG1 and SG2 are buffered by two buffers, respectively, to generate the control signals SG10 and SG20. By providing control signals SG10 and SG20 to the gates (control electrodes) of power semiconductor elements NM1 and NM2, respectively, the timing of their conduction / cutoff is controlled.

[0088] Having outlined the features of several embodiments above, those skilled in the art can better understand aspects of the present invention. It should be understood that those skilled in the art can readily design or modify other processes and structures based on the present invention, thereby achieving the same objectives and / or advantages as those described herein. It should be understood that these equivalent constructions do not depart from the spirit and scope of the present invention, and that various changes, substitutions, and variations can be made therein without departing from the spirit and scope of the present invention. [Explanation of symbols]

[0089] 1, 14: Voltage converter 100: Drive circuit 120, 140, 160, 180: Time delay circuit 122, 162: Temperature sensor 220: Control logic circuit AND1, AND2, AND3, AND4: AND gates BF: Buffer CMP1, CMP2, CMP3, CMP4: Comparators Cout: Output capacitor D1, D3: Drain DL1, DL2: Delay units G1, G2, G3, G4: Gates GND: Ground ITH1, ITH1_adj, ITH2, ITH2_adj, ITH3, ITH3_adj, ITH4, ITH4_adj: Current source L: inductor NM1, NM2, NM3, NM4: Power semiconductor elements OR1, OR2: OR gates Rds1, Rds3, Rds1_adj, Rds3_adj, Rgs2, Rgs4, Rgs2_adj, Rgs4_adj: Resistance S1, S3: Source SG1, SG2, SG3, SG4: Logic signals SG10, SG20, SG30, SG40: Control signals SPWM: Pulse Width Modulation (PWM) signal T1, T2, T3, T4: time points t1, t2, t3, t4, t5, t6: time zone VDD: System voltage VDS1, VDS3: Drain-source voltage Vds1_adj, Vds3_adj, Vgs2_adj, Vgs4_adj: Reference voltages VG1, VG2, VG3, VG4: Voltage VOUT: Output voltage Vtemp1, Vtemp2: Sense voltage

Claims

1. A drive circuit is used to generate a first control signal and a second control signal and to provide the first and second control signals to a control electrode of a first power semiconductor element and a control electrode of a second power semiconductor element connected in parallel to each other in a voltage converter in order to turn on or off a first power semiconductor element and a second power semiconductor element, respectively, wherein a range of a safe operating area of ​​the first power semiconductor element is larger than a range of a safe operating area of ​​the second power semiconductor element, and the first power semiconductor element is turned on earlier than the second power semiconductor element by a first time period and turned off later than the second power semiconductor element by a second time period, a first time delay circuit configured to perform a first comparison operation to compare a voltage level of the second control signal with a first reference voltage and generate a corresponding first comparison result, and to generate a first voltage based on the first comparison result; a second time delay circuit configured to perform a second comparison operation to compare the drain-source voltage of the first power semiconductor device with a second reference voltage and generate a corresponding second comparison result, and to generate a second voltage based on the second comparison result, wherein the first and second reference voltages are related to temperatures of the first and second power semiconductor devices; a control logic circuit coupled to the first time delay circuit and configured to generate a first logic signal based on the first voltage, and further coupled to the second time delay circuit and configured to generate a second logic signal based on the second voltage; a first buffer coupled to the control logic circuit and configured to generate the first control signal based on the first logic signal; a second buffer coupled to the control logic circuit and configured to generate the second control signal based on the second logic signal; The first control signal corresponds to the second time period, and the second control signal corresponds to the first time period.

2. 2. The drive circuit of claim 1, wherein the first reference voltage increases as the temperature of the first and second power semiconductor elements decreases, and the second reference voltage increases as the temperature of the first and second power semiconductor elements increases.

3. 2. The driving circuit of claim 1, wherein the first time delay circuit includes a first current source, a first resistor, and a first comparator, the first current source being series-coupled to the first resistor, the negative input terminal of the first comparator being coupled to a node between the first current source and the first resistor to receive the first reference voltage, the positive input terminal of the first comparator receiving the second control signal, and the first comparator generating the first voltage at its output terminal based on the first comparison result.

4. 4. The drive circuit of claim 3, wherein one of the first resistor and the first current source is a voltage controlled element that receives and responds to a sense voltage, and the sense voltage is indicative of the temperature of the first and second power semiconductor elements.

5. 2. The driving circuit of claim 1, wherein the second time delay circuit includes a second current source, a second resistor, and a second comparator, the second current source being serially coupled to the second resistor, the positive input terminal of the second comparator being coupled to a node between the second current source and the second resistor to receive the second reference voltage, the negative input terminal of the second comparator receiving the drain-source voltage, and the second comparator generating the second voltage at its output terminal based on the second comparison result.

6. 6. The drive circuit of claim 5, wherein one of the second resistor and the second current source is a voltage controlled element that receives and responds to a sense voltage, and the sense voltage is indicative of the temperature of the first and second power semiconductor elements.

7. 2. The drive circuit of claim 1, wherein the first time delay circuit includes a first comparator, a negative input terminal of the first comparator receives the first reference voltage, a positive input terminal of the first comparator receives the second control signal, the first comparator generates the first voltage at its output terminal based on the first comparison result, and the first reference voltage corresponds to a threshold voltage of the second power semiconductor element at the temperature of the first and second power semiconductor elements.

8. 2. The drive circuit of claim 1, wherein the second time delay circuit includes a second comparator, a positive input terminal of the second comparator receives the second reference voltage, a negative input terminal of the second comparator receives the drain-source voltage, the second comparator generates the second voltage at its output terminal based on the second comparison result, and the second reference voltage corresponds to a range of a safe operating area of ​​the second power semiconductor device at the temperature of the first and second power semiconductor devices.

9. A voltage converter comprising: a first power semiconductor element having a control electrode for receiving a first control signal to turn the first power semiconductor element on or off; a second power semiconductor element connected in parallel to the first power semiconductor element and having a control electrode for receiving a second control signal to turn on or off the second power semiconductor element, the second power semiconductor element having a safe operating area smaller than that of the first power semiconductor element, the first power semiconductor element being turned on earlier than the second power semiconductor element during a first time period, and the first power semiconductor element being turned off later than the second power semiconductor element during a second time period; a first time delay circuit configured to perform a first comparison operation to compare a voltage level of the second control signal with a first reference voltage and generate a corresponding first comparison result, and generate a first voltage based on the first comparison result; a second time delay circuit that performs a second comparison operation to compare the first drain-source voltage of the first power semiconductor device with a second reference voltage and generate a corresponding second comparison result, and generates a second voltage based on the second comparison result, the first and second reference voltages being related to first temperatures of the first and second power semiconductor devices; a control logic circuit coupled to the first time delay circuit and configured to generate a first logic signal based on the first voltage and a pulse width modulated signal, and further coupled to the second time delay circuit and configured to generate a second logic signal based on the second voltage and the pulse width modulated signal; a first buffer coupled to the control logic circuit and configured to generate the first control signal based on the first logic signal; a second buffer coupled to the control logic circuit and configured to generate the second control signal based on the second logic signal; The first control signal corresponds to the second time period, and the second control signal corresponds to the first time period.

10. 10. The voltage converter of claim 9, wherein the first time delay circuit includes a first comparator, a negative input terminal of the first comparator receives the first reference voltage, a positive input terminal of the first comparator receives the second control signal, the first comparator generates the first voltage at its output terminal based on the first comparison result, and the first reference voltage increases as the first temperatures of the first and second power semiconductor devices decrease.

11. 11. The voltage converter of claim 10, wherein in response to the second power semiconductor device being turned off based on the second control signal, when the first comparison result indicates that the voltage level of the second control signal is less than the first reference voltage, the first comparator generates the first voltage having a first voltage level, and the first power semiconductor device is turned off based on the first voltage at the first voltage level.

12. 10. The voltage converter of claim 9, wherein the second time delay circuit includes a second comparator, a positive input terminal of the second comparator receives the second reference voltage, a negative input terminal of the second comparator receives the first drain-source voltage, the second comparator generates the second voltage at its output terminal based on the second comparison result, and the second reference voltage increases as the first temperatures of the first and second power semiconductor devices increase.

13. 13. The voltage converter of claim 12, wherein, in response to the first power semiconductor device being made conductive based on the first control signal, when the second comparison result indicates that the first drain-source voltage is smaller than the second reference voltage, the second comparator generates the second voltage having a second voltage level, and the second power semiconductor device is made conductive based on the second voltage at the second voltage level.

14. a third power semiconductor device having a control electrode for receiving a third control signal; a fourth power semiconductor device connected in parallel to the third power semiconductor device and having a control electrode for receiving a fourth control signal, wherein a range of a safe operating area of ​​the third power semiconductor device is greater than a range of a safe operating area of ​​the fourth power semiconductor device, the first and second power semiconductor devices constitute an upper bridge portion of the voltage converter, and the third and fourth power semiconductor devices constitute a lower bridge portion of the voltage converter; a third time delay circuit that performs a third comparison operation to compare the voltage level of the fourth control signal with a third reference voltage and generate a corresponding third comparison result, and generates a third voltage based on the third comparison result; a fourth time delay circuit that performs a fourth comparison operation to compare a second drain-source voltage of the third power semiconductor device with a fourth reference voltage and generate a corresponding fourth comparison result, and generates a fourth voltage based on the fourth comparison result, wherein the third and fourth reference voltages are related to second temperatures of the third and fourth power semiconductor devices, and the control logic circuit is coupled to the third and fourth time delay circuits, and generates a third logic signal based on the third voltage and the pulse width modulation signal, and generates a fourth logic signal based on the fourth voltage and the pulse width modulation signal; a third buffer coupled to the control logic circuit and configured to generate the third control signal based on the third logic signal; a fourth buffer coupled to the control logic circuit and configured to generate the fourth control signal based on the fourth logic signal; The voltage converter of claim 9 further comprising:

15. The control logic circuit a first AND gate receiving the pulse width modulated signal, an inverted signal of the third logic signal, and an inverted signal of the fourth logic signal; a first OR gate coupled to the output terminal of the first AND gate, receiving the first voltage and outputting the first logic signal based thereon; a second AND gate receiving the pulse width modulated signal and the second voltage and outputting the second logic signal based thereon; 15. The voltage converter of claim 14, comprising:

16. The control logic circuit a third AND gate receiving an inverted signal of the pulse width modulated signal, an inverted signal of the first logic signal, and an inverted signal of the second logic signal; a second OR gate coupled to the output terminal of the third AND gate, receiving the third voltage and outputting the third logic signal based thereon; a fourth AND gate receiving an inverted signal of the pulse width modulation signal and the fourth voltage and outputting the fourth logic signal based thereon; 16. The voltage converter of claim 15, comprising:

17. A control method for a voltage converter, the method comprising: generating a first control signal and a second control signal and providing the first control signal and the second control signal to a control electrode of a first power semiconductor element and a control electrode of a second power semiconductor element connected in parallel to each other in a voltage converter in order to turn on or off the first power semiconductor element and the second power semiconductor element, respectively; a range of a safe operating area of ​​the first power semiconductor element is larger than a range of a safe operating area of ​​the second power semiconductor element; and the first power semiconductor element is turned on earlier than the second power semiconductor element by a first time period and turned off later than the second power semiconductor element by a second time period, receiving a pulse width modulated signal; performing a first comparison operation to compare a voltage level of the second control signal with a first reference voltage and generate a corresponding first comparison result, and performing a second comparison operation to compare a drain-source voltage of the first power semiconductor device with a second reference voltage and generate a corresponding second comparison result, wherein the first and second reference voltages are related to temperatures of the first and second power semiconductor devices; generating a first voltage based on the first comparison result and a second voltage based on the second comparison result; generating a first logic signal based on the first voltage and a second logic signal based on the second voltage; buffering the first logic signal to generate the first control signal and buffering the second logic signal to generate the second control signal; wherein the first control signal corresponds to the second time period, and the second control signal corresponds to the first time period.

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