Semiconductor device inspection device, learning device, inference device, and manufacturing method

Abstract

To improve the accuracy of detecting a semiconductor device having a defect that causes element breakdown, compared to electrical characteristic inspection.SOLUTION: A model generation unit 7 generates a trained model that infers data regarding the quality of a first semiconductor device from learning input data including data regarding at least one defect included in a first semiconductor device by machine learning using learning data. An inference data processing unit 10 generates inference input data including data on at least one defect included in a second semiconductor device. An inference unit 11 infers data regarding the quality of the second semiconductor device from the inference input data using the trained model.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to an inspection device, a learning device, an inference device, and a manufacturing method for a semiconductor device. [Background technology]

[0002] In a semiconductor device including a field effect transistor (FET) having a metal oxide semiconductor (MOS) structure on a silicon carbide substrate, if a defect occurs on the silicon carbide substrate, current will concentrate at the defect when power is applied to the semiconductor device. Therefore, the defect may cause element breakdown. To prevent such element breakdown, the semiconductor device manufacturing process requires an inspection process to remove semiconductor devices that may cause element breakdown from products to be shipped.

[0003] For example, Japanese Patent No. 6471421 (Patent Document 1) discloses a semiconductor device inspection method for eliminating semiconductor devices that may cause switching failures. In this inspection method, whether or not a semiconductor device contains a defect is determined based on a characteristic curve showing the input / output characteristics (electrical characteristics) of the semiconductor device, where the voltage is input and the current is output, plotted on a horizontal axis and the current is plotted on a logarithmic scale on a vertical axis. Specifically, a first slope of a line connecting two points in a first section set within an intermediate current section is calculated from a minute current on the characteristic curve. A second slope of a line connecting two points in a second section set within the rated current section of the semiconductor device is calculated from the intermediate current on the characteristic curve, and the first and second slopes are compared. If the first and second slopes do not match, the semiconductor device is determined to contain a defect. If the first and second slopes match, the semiconductor device is determined to contain no defect. This inspection method makes it possible to eliminate semiconductor devices that may cause switching failures while suppressing increases in inspection costs. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Patent No. 6471421 Summary of the Invention [Problem to be solved by the invention]

[0005] In the inspection method disclosed in Patent Document 1, depending on the current measurement resolution of the inspection device, it is possible that the presence or absence of a defect in a semiconductor device may not be reflected as a difference between the first slope and the second slope. In other words, even if a semiconductor device contains a defect that could cause element destruction, the first slope and the second slope of the semiconductor device may match in the inspection results. Even in such a semiconductor device, the current may still be concentrated at the defect when power is applied, causing element destruction. Therefore, it is necessary to increase the measurement resolution of the inspection device and remove the semiconductor device from the inspection process.

[0006] In order to increase the measurement resolution of an inspection device, it is necessary to set the measurement time from input of the input voltage to measurement of the output current to at least one second. However, extending the measurement time for each semiconductor device manufactured in large quantities results in enormous manufacturing costs. Therefore, in an inspection method such as that disclosed in Patent Document 1, which performs electrical characteristic inspections on semiconductor devices, there is a problem in that, due to manufacturing cost limitations, it is not possible to remove semiconductor devices in which the difference between the presence and absence of defects is apparent only in an area smaller than the measurement resolution of the current.

[0007] The present disclosure has been made to solve the above-mentioned problems, and its purpose is to improve the accuracy of detecting semiconductor devices having defects that can cause element destruction compared to electrical characteristic testing. [Means for solving the problem]

[0008] The semiconductor device inspection apparatus according to the present disclosure includes a training data processing unit, a model generation unit, an inference data processing unit, and an inference unit. The training data processing unit identifies at least one defect in the first semiconductor device based on defect data related to defects in the first silicon carbide substrate and positional information on where the first semiconductor device is formed on the first silicon carbide substrate, and generates training data in which training input data including data related to the at least one defect in the first semiconductor device and teacher data including data related to the quality of the first semiconductor device are associated. The model generation unit generates a trained model that infers data related to the quality of the first semiconductor device from the training input data through machine learning using the training data. The inference data processing unit identifies at least one defect in the second semiconductor device based on defect data related to defects in the second silicon carbide substrate and positional information on where the second semiconductor device is formed on the second silicon carbide substrate, and generates inference input data including data related to the at least one defect in the second semiconductor device. The inference unit infers data related to the quality of the second semiconductor device from the inference input data using the trained model.

[0009] A learning device according to the present disclosure includes a training data processing unit and a model generation unit. The training data processing unit identifies at least one defect in the semiconductor device from defect data related to defects occurring in the silicon carbide substrate and position information on where the semiconductor device is formed on the silicon carbide substrate, and generates training data in which input data including data related to the at least one defect in the semiconductor device is associated with training data including data related to the quality of the semiconductor device. The model generation unit generates a trained model that infers data related to the quality of the semiconductor device from the input data through machine learning using the training data.

[0010] The inference device according to the present disclosure includes an inference data processing unit and an inference unit. The inference data processing unit identifies at least one defect in the semiconductor device from defect data related to defects occurring in the silicon carbide substrate and position information on where the semiconductor device is formed on the silicon carbide substrate, and generates inference input data including data related to the at least one defect in the semiconductor device. The inference unit infers data related to the quality of the semiconductor device from the inference input data using a trained model. [Effects of the Invention]

[0011] According to the semiconductor device inspection device, learning device, and inference device of the present disclosure, by using a trained model that infers data regarding the quality of a semiconductor device from input data that includes data regarding at least one defect contained in the semiconductor device, it is possible to improve the accuracy of detecting semiconductor devices that have defects that may cause element destruction compared to electrical characteristic testing. [Brief explanation of the drawings]

[0012] [Figure 1] 1 is a block diagram showing a configuration of an inspection device for a semiconductor device according to a first embodiment. [Figure 2] FIG. 2 is a block diagram showing the configuration of the learning device of FIG. [Figure 3] FIG. 2 is a block diagram showing the configuration of the inference device of FIG. [Figure 4] FIG. 3 is a diagram showing a neural network, which is an example of an inference model to be optimized by the model generation unit of FIG. 2. [Figure 5] 3 is a flowchart showing the flow of a learning process performed in the learning device of FIG. 2. [Figure 6] FIG. 10 is a diagram showing defect data including defects occurring in a silicon carbide substrate. [Figure 7] 7 is a diagram showing manufacturing position information indicating the position where a semiconductor device is formed on the silicon carbide substrate of FIG. 6, superimposed on defect data in association with the defect data. FIG. [Figure 8] FIG. 8 is a diagram showing relative positions of defects in the semiconductor device of FIG. [Figure 9] 9 is a cross-sectional view taken along the line A1-A2 in FIG. 8. [Figure 10] 4 is a flowchart showing the flow of an inference process performed by the inference device and the selection unit of FIG. 3. [Figure 11] 2 is a block diagram showing a hardware configuration of the inspection device for the semiconductor device of FIG. 1. FIG. [Figure 12] FIG. 10 is a block diagram showing a configuration of an inspection device for semiconductor devices according to a first modification of the first embodiment. [Figure 13] FIG. 10 is a block diagram showing a configuration of an inspection device for semiconductor devices according to a second modification of the first embodiment. [Figure 14] FIG. 10 is a block diagram showing a configuration of an inspection device for semiconductor devices according to a third modification of the first embodiment. [Figure 15] FIG. 10 is a block diagram showing an example of the configuration of an inspection device for semiconductor devices according to a fourth modification of the first embodiment. [Figure 16] FIG. 11 is a block diagram showing another example of the configuration of the semiconductor device inspection device according to the fourth modification of the first embodiment. [Figure 17] FIG. 11 is a block diagram showing a configuration of an inspection device for semiconductor devices according to a fifth modification of the first embodiment. [Figure 18] 18 is a flowchart for explaining the flow of processing by the unnecessary data calculation unit in FIG. 17. [Figure 19] FIG. 10 is a block diagram showing the configuration of an inspection device for semiconductor devices according to a second embodiment. [Figure 20] FIG. 20 is a block diagram showing the configuration of the learning device of FIG. [Figure 21] FIG. 20 is a block diagram showing the configuration of the inference device of FIG. 19. [Figure 22] 10 is a histogram of electrical characteristics measured in advance before measuring the short-circuit resistance of a semiconductor device. [Figure 23] 22 is a histogram of short-circuit withstand capability output from the inference unit of FIG. 21. [Figure 24] 21 is a flowchart showing the flow of a learning process performed in the learning device of FIG. 20. [Figure 25]22 is a flowchart showing the flow of inference processing performed by the inference device and the selection unit of FIG. 21. [Figure 26] 10 is a flowchart showing the flow of a method for manufacturing a semiconductor device according to a third embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0013] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. In the drawings, the same or corresponding parts are designated by the same reference numerals, and their description will not be repeated in principle.

[0014] Embodiment 1 In the first embodiment, a case will be described in which the semiconductor device to be inspected is a power semiconductor formed on a silicon carbide substrate. FIG. 1 is a block diagram showing the configuration of a semiconductor device inspection apparatus 100 according to the first embodiment. As shown in FIG. 1, the semiconductor device inspection apparatus 100 includes a teacher data storage unit 6, a learning device 13, and an inference device 14. Note that the learning device 13 and the inference device 14 may each be a device separate from the semiconductor device inspection apparatus 100 and connected to the semiconductor device inspection apparatus 100 via a network, for example. Furthermore, the learning device 13 and the inference device 14 may reside on a cloud server. The teacher data storage unit 6 stores data on pass / fail judgment results, which are the results (pass or fail) of inspection of semiconductor devices to be manufactured (quality-related data).

[0015] FIG. 2 is a block diagram showing the configuration of the learning device 13 of FIG. 1. As shown in FIG. 2, the learning device 13 includes a learning data acquisition unit 4, a learning data processing unit 5, a model generation unit 7, and a trained model storage unit 8. The learning data acquisition unit 4 acquires defect data of a silicon carbide substrate (first silicon carbide substrate) from the defect inspection data storage unit 3, and acquires manufacturing position information of a semiconductor device (first semiconductor device) formed on the silicon carbide substrate from the dimension information storage unit 30. The defect data includes, for example, the type of known defect that commonly occurs on a silicon carbide substrate, such as a micropipe, a triangular defect, or a stacking fault, as well as the size, angle, or occurrence position of the defect. The defect is measured by a silicon carbide substrate defect inspection device 2 and stored in the defect inspection data storage unit 3. The manufacturing position information of the semiconductor device includes information (position information) regarding the position on the silicon carbide substrate where the power semiconductor is formed. The learning data acquisition unit 4 outputs the manufacturing position information and defect data of the semiconductor device to the learning data processing unit 5.

[0016] The training data processing unit 5 identifies at least one defect contained in a semiconductor device to be manufactured using the semiconductor device manufacturing location information and defect data from the training data acquisition unit 4, and associates the manufacturing location information with each of the at least one defect in the defect data. The training data processing unit 5 assigns feature quantities, such as the relative position of each of the at least one defect contained in the semiconductor device, the size of the defect, the type of the defect, and the number of defects classified into that type, to the defect data. The training data processing unit 5 acquires a pass / fail judgment result, which is the inspection result (pass or fail) of the semiconductor device, from the training data storage unit 6, and associates the defect data of the semiconductor device with the pass / fail judgment result. The training data processing unit 5 creates training data including a combination of defect data and pass / fail judgment results (training data). The training data processing unit 5 outputs the training data to the model generation unit 7.

[0017] The model generation unit 7 uses the learning data from the learning data processing unit 5 to learn the relationship between defect data and pass / fail judgment results. The model generation unit 7 generates a trained inference model (trained model) that infers an optimal pass / fail judgment result from the defect data and pass / fail judgment result (teacher data) of the semiconductor device. The inference model uses the defect data (learning input data) processed by the learning data processing unit 5 as input (explanatory variable) and the pass / fail judgment result as output (objective variable). The model generation unit 7 stores the trained model in the trained model storage unit 8. Note that the trained model may be a trained model of another semiconductor device, etc., optimized in an external learning device different from the learning device 13.

[0018] Figure 3 is a block diagram showing the configuration of the inference device 14 of Figure 1. As shown in Figure 3, the inference device 14 includes an inference data acquisition unit 9, an inference data processing unit 10, an inference unit 11, and a determination unit 12. The inference data acquisition unit 9 acquires defect data of the silicon carbide substrate (second silicon carbide substrate) from the defect inspection data storage unit 3, and acquires manufacturing position information of the semiconductor device (second semiconductor device) formed on the silicon carbide substrate from the dimension information storage unit 30. The inference data acquisition unit 9 outputs the manufacturing position information and defect data of the semiconductor device to the inference data processing unit 10.

[0019] The inference data processing unit 10 identifies at least one defect contained in the semiconductor device to be manufactured using the semiconductor device manufacturing location information and defect data from the inference data acquisition unit 9, and associates the manufacturing location information with each of the at least one defect. The inference data processing unit 10 assigns feature quantities, such as the relative position of each of the at least one defect contained in the semiconductor device, the size of the defect, the type of the defect, and the number of defects classified into that type, to the defect data. The inference data processing unit 10 outputs the processed defect data to the inference unit 11.

[0020] The inference unit 11 infers the pass / fail judgment result of the semiconductor device from the defect data using the learned model stored in the learned model storage unit 8. That is, the inference unit 11 inputs the defect data (inference input data) processed by the inference data processing unit 10 into the learned model, and outputs to the judgment unit 12 the pass / fail judgment probability (probability of a good product and probability of a defective product) inferred from the defect data.

[0021] The judgment unit 12 identifies the highest probability among the pass / fail judgment probabilities output from the inference unit 11, judges whether the semiconductor device is a pass or a fail product according to the highest probability, and outputs the judgment result to the sorting unit 23. Note that the judgment method of the judgment unit 12 is not limited to the judgment method of the first embodiment. For example, the judgment method may be a method in which the semiconductor device is judged to be fail unless the pass probability of the semiconductor device is equal to or greater than a certain level, or vice versa, a method in which the pass or fail of the semiconductor device is judged by comparing with a predetermined threshold value.

[0022] The sorting unit 23 uses the judgment result from the judging unit 12 to sort the semiconductor devices into either good products or bad products.

[0023] The machine learning algorithm used by the model generation unit 7 can be a known algorithm such as supervised learning, semi-supervised learning, unsupervised learning, or reinforcement learning. The model generation unit 7 may also perform machine learning according to other known methods such as deep learning, which learns to extract features themselves, or genetic programming, functional logic programming, support vector machines, or GBDT (Gradient Boosting Decision Tree). Below, a machine learning algorithm using a neural network will be described as an example of the machine learning algorithm used by the model generation unit 7.

[0024] The model generation unit 7 learns the relationship between defect data and pass / fail judgment results of semiconductor devices, for example, by so-called supervised learning in accordance with a neural network model. Here, supervised learning refers to a method of using pairs of input and result data (label or correct answer data) as training data to learn the features of the training data and infer results from the input. The neural network is composed of an input layer consisting of multiple neurons, an intermediate layer (hidden layer) consisting of multiple neurons, and an output layer consisting of multiple neurons. The intermediate layer may include one layer, or two or more layers.

[0025] FIG. 4 is a diagram showing a neural network Nw1, which is an example of an inference model to be optimized by the model generation unit 7 of FIG. 2. As shown in FIG. 4, the neural network Nw1 includes an input layer X10, a hidden layer Y10, and an output layer Z10. The input layer X10 includes neurons X11, X12, and X13. The hidden layer Y10 includes neurons Y11 and Y12. The output layer Z10 includes neurons Z11, Z12, and Z13. The input layer X10 and the hidden layer Y10 are fully connected to each other. The hidden layer Y10 and the output layer Z10 are fully connected to each other.

[0026] When multiple inputs are input to neurons X11 to X13 in input layer X10, the values ​​are multiplied by weights w11, w12, w13, w14, w15, and w16, and the result is input to neurons Y11 and Y12 in hidden layer Y10. The outputs from neurons Y11 and Y12 are multiplied by weights w21, w22, w23, w24, w25, and w26, and the result is output from neurons Z11, Z12, and Z13 in output layer Z10. The output results from output layer Z10 vary depending on the values ​​of weights w11 to w16 and w21 to w26.

[0027] The neural network Nw1 learns the relationship between the defect data and the pass / fail judgment results (teacher data) by so-called supervised learning in accordance with learning data created using a combination of the defect data and the pass / fail judgment results of the semiconductor device. That is, the weights and biases of the neural network Nw1 are updated by backpropagation of the error between the defect data input to the input layer and the correct data so that the result output from the output layer approaches the pass / fail judgment result of the correct data.

[0028] 5 is a flowchart showing the flow of the learning process performed in learning device 13 of FIG. 2. FIG. 6 is a diagram showing defect data including defects 15a, 15b, and 15c that have occurred in silicon carbide substrate 16. FIG. 7 is a diagram showing manufacturing position information 18 indicating the position where semiconductor device 17 is formed on silicon carbide substrate 16 of FIG. 6, associated with and superimposed on the defect data of FIG. 6. FIG. 8 is a diagram showing the relative positions of defects 15a and 15c in semiconductor device 17. FIG. 9 is a cross-sectional view taken along line A1-A2 of FIG. 8. In FIGS. 8 and 9, the X-axis, Y-axis, and Z-axis are perpendicular to one another. Below, steps will simply be abbreviated as S.

[0029] Referring primarily to Figure 5 and also to Figure 6, in S101, the learning data acquisition unit 4 acquires defect data of the silicon carbide substrate 16 shown in Figure 6 from the defect inspection data storage unit 3, and also acquires manufacturing location information 18 of the semiconductor device 17 on the grid from the dimension information storage unit 30.

[0030] Referring also to FIG. 7, in S102, the learning data processing unit 5 processes the defect data so as to link the defects 15a-15c acquired by the learning data acquisition unit 4 to the pass / fail judgment result (teacher data) of the semiconductor device 17 via manufacturing location information 18 on the silicon carbide substrate 16 of the semiconductor device 17. Referring also to FIG. 8, in S102, the learning data processing unit 5 adds to the defect data information regarding the relative position of each of the defects 15a-15c, the size of the defect, the type of the defect, and the number of defects classified into that type. That is, the learning data processing unit 5 adds to the defect data information regarding whether each of the defects 15a-15c is located in an invalid region 19 or a gate pad 24 through which almost no current flows when the semiconductor device 17 is energized, or in an effective region 20 through which current flows when the semiconductor device 17 is energized. Furthermore, the learning data processing unit 5 also adds to the defect data the number of each defect type within the same semiconductor device 17. 9, the region on the outer periphery of semiconductor device 17 is defined as an ineffective region 19 where no current flows when power is applied, and the region containing cells on the inner periphery of semiconductor device 17 is defined as an effective region 20 where current flows when power is applied. In addition, in S102, the case where the defect data and the pass / fail judgment result (teaching data) are acquired separately has been described, but it is sufficient that the defect data and the pass / fail judgment result (teaching data) are input in association with each other, and both may be acquired simultaneously.

[0031] In S103, the model generation unit 7 learns the relationship between the defect data and the pass / fail determination results by so-called supervised learning in accordance with the learning data created using a combination of the defect data and the pass / fail determination results (teaching data) output from the learning data processing unit 5, generates a trained model, and proceeds to S104. In S104, the model generation unit 7 stores the trained model in the trained model storage unit 8. Note that the model generation unit 7 may learn the relationship between the defect data and the pass / fail determination results (teaching data) in accordance with the learning data created for multiple semiconductor devices. For example, the learning data may be created from data of semiconductor devices manufactured in the same production lot, during the same period, or from the same ingot, or the like. The learning data may also be created from data of semiconductor devices manufactured in different production lots, during different periods, or from different ingots, etc.

[0032] Fig. 10 is a flowchart showing the flow of the inference process performed by the inference device 14 and the selection unit 23 of Fig. 3. As shown in Fig. 10, in S111, the inference data acquisition unit 9 acquires defect data of the silicon carbide substrate from the defect inspection data storage unit 3, and also acquires manufacturing position information of the semiconductor device from the dimension information storage unit 30.

[0033] In S112, the inference data processing unit 10 identifies at least one defect included in the semiconductor device to be manufactured using the semiconductor device manufacturing location information and defect data output from the inference data acquisition unit 9, and associates the manufacturing location information with each of the at least one defect in the defect data. Furthermore, the inference data processing unit 10 assigns to the defect data feature quantities, namely, the relative position of each of the at least one defect included in the semiconductor device, the size of the defect, the type of the defect, and the number of defects classified into that type.

[0034] In S113, the inference unit 11 inputs the defect data (data for inference) processed in S112 into the learned model stored in the learned model storage unit 8, and obtains the probability of determining whether the semiconductor device is good or bad from the learned model.

[0035] The determining unit 12 selects the highest probability from the pass / fail determination probabilities output from the inferring unit 11 and outputs a determination result indicating whether the semiconductor device is a pass or a fail product.

[0036] In S115, the sorting unit 23 sorts the semiconductor devices using the determination result output in S114. As a result, semiconductor devices that may cause element destruction can be more accurately removed from the finished product.

[0037] It is also possible to add or remove a semiconductor device from which learning data is collected to the inspection targets during the inspection. Furthermore, an inference model that has learned the relationship between defect data and pass / fail judgment results (teaching data) for a certain semiconductor device may be applied to a semiconductor device other than the semiconductor device in question, and the inference model may be updated by re-learning (or additional learning) the relationship between the defect data and pass / fail judgment results for the other semiconductor device.

[0038] FIG. 11 is a block diagram showing the hardware configuration of the semiconductor device inspection apparatus 100 of FIG. 1. As shown in FIG. 11, the inspection apparatus 100 includes a processing circuit 71, a memory 72, and an input / output unit 73. The processing circuit 71 includes a CPU (Central Processing Unit) that executes programs stored in the memory 72. The processing circuit 71 may also include a GPU (Graphics Processing Unit). The functions of the inspection apparatus 100 are realized by software, firmware, or a combination of software and firmware. The software or firmware is written as a program and stored in the memory 72. The processing circuit 71 reads and executes the program stored in the memory 72. The CPU is also called a central processing unit, processing device, arithmetic unit, microprocessor, microcomputer, processor, or DSP (Digital Signal Processor).

[0039] Memory 72 may include non-volatile or volatile semiconductor memory (e.g., RAM (Random Access Memory), ROM (Read Only Memory), flash memory, EPROM (Erasable Programmable Read Only Memory), or EEPROM (Electrically Erasable Programmable Read Only Memory)), as well as magnetic disks, flexible disks, optical disks, compact disks, minidisks, or DVDs (Digital Versatile Discs).

[0040] The memory 72 stores teacher data Ds, a machine learning program Pg1, a testing program Pg2, and an inference model M1. The processing circuit 71 that executes the machine learning program Pg1 corresponds to the learning device 13 in Figure 2. The processing circuit 71 that executes the testing program Pg2 corresponds to the inference device 14 in Figure 3. The memory 72 corresponds to the teacher data storage unit 6 and the trained model storage unit 8 in Figure 1.

[0041] The input / output unit 73 receives operations from the user and outputs processing results to the user. The input / output unit 73 includes, for example, a mouse, a keyboard, a touch panel, a display, and a speaker.

[0042] Variation 1 of Embodiment 1 In the first modification of the first embodiment, a case will be described in which defect data input to a semiconductor device inspection device is image data. By using image data as defect data, the inference model can learn complex features that cannot be determined from low-dimensional data, thereby improving the inference accuracy of the inference model. Furthermore, when a semiconductor device is determined to be defective, the basis for this can be visually confirmed as image data, making it easy to investigate the cause of the defective determination and to plan countermeasures.

[0043] Fig. 12 is a block diagram showing the configuration of a semiconductor device inspection apparatus 100 according to a first modification of the first embodiment. In the configuration shown in Fig. 12, the defect inspection data storage unit 3 in Fig. 1 is replaced with a defect image data storage unit 33. As shown in Fig. 12, the learning data acquisition unit 4 and the inference data acquisition unit 9 acquire defect image data from the defect image data storage unit 33. The configuration other than this is the same as that of the first embodiment, and therefore description thereof will not be repeated.

[0044] Variation 2 of Embodiment 1 The data acquired by the learning data acquiring unit 4 and the inference data acquiring unit 9 is not limited to those in the first embodiment and the first modification. For example, as in the learning data acquiring unit 4 and the inference data acquiring unit 9 of the semiconductor device inspection apparatus 100 according to the second modification of the first embodiment shown in FIG. 13, in addition to the defect inspection data and the manufacturing location information of the semiconductor device, data on the product specifications of the semiconductor device to be manufactured may be acquired from the product specification storage unit 25, and the data may be used for learning and inference. The product specifications include information necessary for designing the semiconductor device, such as the thickness and concentration of the epitaxial layer of the semiconductor device, the thickness of the semiconductor device, the channel concentration, the channel length, and the thickness of the gate oxide film, as well as manufacturing variations thereof.

[0045] Modification 3 of Embodiment 1 The dimension information storage unit 30 and the product specification storage unit 25 do not need to be provided outside the semiconductor device inspection apparatus 100. They may be provided inside the semiconductor device inspection apparatus 100, as in the semiconductor device inspection apparatus 100 according to the third modification of the first embodiment shown in FIG.

[0046] Variation 4 of Embodiment 1 FIG. 15 is a block diagram showing an example of the configuration of a semiconductor device inspection apparatus 100 according to Variation 4 of Embodiment 1. In FIG. 15, in order to emphasize the features of Variation 4 of Embodiment 1, components of the semiconductor device inspection apparatus 100 other than the model generation unit 7, the learned model storage unit 8, and the determination unit 12 are not shown. As shown in FIG. 15, the display device 28 includes a display 281. The operation input device 27 includes a keyboard 271 and a mouse 272. In the semiconductor device inspection apparatus 100, the determination result of the determination unit 12 is displayed on the display device 28. A user can change the determination result displayed on the display device 28 using the operation input device 27. The user can update the learned model by feeding back changes made to the determination result to the model generation unit 7. Note that the display device 28 and the operation input device 27 in FIG. 15 may be formed as an integrated unit, such as a display / operation input device 29 including a touch display 291 shown in FIG. 16.

[0047] Variation 5 of Embodiment 1 FIG. 17 is a block diagram showing the configuration of a semiconductor device inspection apparatus 100 according to a fifth modification of the first embodiment. In FIG. 17, in order to emphasize the features of the fifth modification of the first embodiment, the configuration of the semiconductor device inspection apparatus 100 other than the learning device 13, the teacher data storage unit 6, and the unnecessary data calculation unit 31 is not shown. As shown in FIG. 17, the semiconductor device inspection apparatus 100 further includes an unnecessary data calculation unit 31. The unnecessary data calculation unit 31 extracts unnecessary defect inspection data that does not contribute to the determination by the determination unit of the inference device for the trained model generated by the model generation unit 7, and deletes the unnecessary defect data from the defect inspection data storage unit 3.

[0048] 18 is a flowchart for explaining the processing flow of the unnecessary data calculation unit 31 of FIG. 17. As shown in FIG. 18, in S131, the unnecessary data calculation unit 31 acquires the importance of the defect data used by the model generation unit 7 and proceeds to S132. In S132, the unnecessary data calculation unit 31 determines whether the importance acquired in S131 is higher than a predetermined threshold value. If the importance is higher than the threshold value (YES in S132), the unnecessary data calculation unit 31 proceeds to S134. If the importance is equal to or lower than the threshold value (NO in S132), the unnecessary data calculation unit 31 proceeds to S133. In S133, the unnecessary data calculation unit 31 deletes the defect inspection data corresponding to the importance from the defect inspection data storage unit 3 and proceeds to S134. In S134, the unnecessary data calculation unit 31 determines whether there is any undetermined importance among the importance of the defect data used by the model generation unit 7. If there is an undetermined importance (YES in S134), the unnecessary data calculation unit 31 returns the process to S 131. If there is no undetermined importance (NO in S134), the unnecessary data calculation unit 31 ends the process.

[0049] According to the semiconductor device inspection device 100 relating to variant example 5 of embodiment 1, the amount of data held by the defect inspection data storage unit 3 can be reduced, thereby reducing the computational cost required for machine learning by the model generation unit 7.

[0050] As described above, the semiconductor device inspection devices according to the first embodiment and the first to fifth modifications can improve the accuracy of detecting semiconductor devices having defects that may cause element breakdown compared to electrical characteristic inspection.

[0051] Embodiment 2 In the second embodiment, the semiconductor device to be inspected is a so-called SBD-integrated MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) having an SBD (Schottky Barrier Diode) structure, and a semiconductor device inspection device for inspecting the short-circuit resistance of the semiconductor device will be described. Note that the short-circuit resistance is the time from when the semiconductor device to be inspected shorts to when the semiconductor device is destroyed.

[0052] 19 is a block diagram showing the configuration of a semiconductor device inspection device 200 according to embodiment 2. In the configuration of semiconductor device inspection device 200, the teacher data storage unit 6 and the inference unit 11 in FIG. 1 are replaced with a teacher data storage unit 26 and an inference unit 21, respectively. Data (quality-related data) relating to the short-circuit resistance of semiconductor devices to be manufactured is stored in teacher data storage unit 26.

[0053] Fig. 20 is a block diagram showing the configuration of learning device 13 of Fig. 19. As shown in Fig. 20, learning device 13 includes a learning data acquisition unit 4, a learning data processing unit 5, a model generation unit 7, and a trained model storage unit 8. Learning data acquisition unit 4 performs the same processing as in the first embodiment and outputs manufacturing position information and defect data of the semiconductor device to learning data processing unit 5.

[0054] The learning data processing unit 5 performs the same processing as in the first embodiment, and also acquires the short-circuit tolerance of the semiconductor device to be manufactured from the teacher data storage unit 26 and associates the defect data of the semiconductor device with the short-circuit tolerance. The learning data processing unit 5 creates learning data including a combination of the defect data and the short-circuit tolerance (teacher data). The learning data processing unit 5 outputs the learning data to the model generation unit 7.

[0055] The model generation unit 7 uses the learning data from the learning data processing unit 5 to learn the relationship between defect data and short-circuit withstand capability. The model generation unit 7 generates a trained model that infers the optimum short-circuit withstand capability from the defect data and short-circuit withstand capability (teaching data) of the semiconductor device. The inference model uses the defect data (learning input data) processed by the learning data processing unit 5 as input (explanatory variable) and the short-circuit withstand capability as output (objective variable). The model generation unit 7 stores the trained model in the trained model storage unit 8.

[0056] 21 is a block diagram showing the configuration of the inference device 14 of FIG. 19. As shown in FIG. 21, the inference device 14 includes an inference data acquisition unit 9, an inference data processing unit 10, an inference unit 21, and a determination unit 12. The inference data acquisition unit 9 performs the same processing as in the first embodiment and outputs manufacturing position information and defect data of the semiconductor device to the inference data processing unit 10. The inference data processing unit 10 performs the same processing as in the first embodiment and outputs the processed defect data to the inference unit 21.

[0057] The inference unit 21 infers the short-circuit tolerance of the semiconductor device from the defect data using the learned model stored in the learned model storage unit 8. The inference unit 21 inputs the defect data (inference input data) processed by the inference data processing unit 10 to the learned model, and outputs the short-circuit tolerance inferred from the defect data to the determination unit 12.

[0058] The determination unit 12 determines whether the semiconductor device being inspected is a pass or a fail product based on a predetermined threshold value for the short circuit withstand capability output from the inference unit 11. That is, the determination unit 12 determines the semiconductor device as a pass product when the short circuit withstand capability is equal to or greater than the threshold value, and determines the semiconductor device as a fail product when the short circuit withstand capability is less than the threshold value.

[0059] The sorting unit 23 uses the judgment result from the judging unit 12 to sort the semiconductor devices to be inspected into either good products or bad products.

[0060] FIG. 22 is a histogram of electrical characteristics measured in advance before measuring the short-circuit withstand capability of a semiconductor device. FIG. 23 is a histogram of short-circuit withstand capability output from the inference unit 21 of FIG. 21. In FIGS. 22 and 23, the results of actual short-circuit withstand capability measurements are shown separated into classes in which element breakdown occurred and classes in which no element breakdown occurred. As shown in FIG. 22, the histogram of electrical characteristics includes a mixture of classes in which element breakdown occurs and classes in which element breakdown occurs. Therefore, using the electrical characteristics, it is not possible to accurately classify normal products into those in which element breakdown occurs. On the other hand, as shown in FIG. 23, the histogram of short-circuit withstand capability separates classes in which element breakdown occurs and classes in which element breakdown occurs at the threshold value Wth. Therefore, using the inferred value of short-circuit withstand capability, it is possible to accurately classify semiconductor devices into those in which element breakdown occurs and those in which element breakdown does not occur.

[0061] Fig. 24 is a flowchart showing the flow of the learning process performed in the learning device 13 of Fig. 20. As shown in Fig. 24, in S201, the learning data acquisition unit 4 acquires defect data of the silicon carbide substrate from the defect inspection data storage unit 3, and also acquires manufacturing position information of the semiconductor device on the grid from the semiconductor device dimension information storage unit.

[0062] In S202, the learning data processing unit 5 processes the defect data acquired by the learning data acquisition unit 4 so as to associate the defect data with the short-circuit withstand capability (teaching data) of the semiconductor device via manufacturing position information on the silicon carbide substrate of the semiconductor device. In addition, in S202, the learning data processing unit 5 assigns to the defect data feature quantities, such as the relative position of each of at least one defect included in the semiconductor device, the size of the defect, the type of the defect, and the number of defects classified into that type. Note that, in S202, the case where the defect data and the short-circuit withstand capability (teaching data) are acquired separately has been described, but as long as the defect data and the short-circuit withstand capability (teaching data) of the semiconductor device are input in an associated manner, they may also be acquired simultaneously.

[0063] In S203, the model generation unit 7 learns the relationship between the defect data and the short-circuit withstand capability by so-called supervised learning in accordance with the learning data created based on a combination of the defect data and the short-circuit withstand capability (teaching data) output from the learning data processing unit 5, generates a trained model, and proceeds to S204. In S204, the model generation unit 7 stores the trained model in the trained model storage unit 8. Note that the model generation unit 7 may learn the relationship between the defect data and the short-circuit withstand capability (teaching data) in accordance with the learning data created for multiple semiconductor devices. For example, the learning data may be created from data of semiconductor devices manufactured in the same production lot, during the same period, or from the same ingot, or the like. The learning data may also be created from data of semiconductor devices manufactured in different production lots, during different periods, or from different ingots, etc.

[0064] Fig. 25 is a flowchart showing the flow of the inference process performed by the inference device 14 and the selection unit 23 of Fig. 21. As shown in Fig. 25, in S211, the inference data acquisition unit 9 acquires defect data of the silicon carbide substrate from the defect inspection data storage unit 3, and also acquires manufacturing position information of the semiconductor device from the semiconductor device dimension information storage unit 30.

[0065] In S212, the inference data processing unit 10 identifies at least one defect included in the semiconductor device to be manufactured using the semiconductor device manufacturing location information and defect data output from the inference data acquisition unit 9, and processes the defect data so as to associate the manufacturing location information with each of the at least one defect. Furthermore, the inference data processing unit 10 assigns to the defect data feature quantities, namely, the relative position of each of the at least one defect included in the semiconductor device, the size of the defect, the type of the defect, and the number of defects classified into that type.

[0066] In S213, the inference unit 11 inputs the inference data generated in S212 into the learned model stored in the learned model storage unit 8, and obtains the short-circuit withstand capability of the semiconductor device from the learned model.

[0067] The determining unit 12 determines whether the semiconductor device to be inspected is a good product or a defective product by using a predetermined threshold value for the short circuit resistance output from the inferring unit 11.

[0068] In S215, the sorting unit 23 sorts the semiconductor devices using the determination result output in S214. As a result, semiconductor devices that may cause element destruction can be more accurately removed from the finished product.

[0069] It is also possible to add or remove a semiconductor device from which learning data is collected to the test subjects during the test. Furthermore, an inference model that has learned the relationship between defect data and short-circuit tolerance (teaching data) for a certain semiconductor device may be applied to a semiconductor device other than the semiconductor device in question, and the inference model may be updated by re-learning (or additional learning) the relationship between the defect data and short-circuit tolerance for the other semiconductor device.

[0070] As described above, the semiconductor device inspection device according to the second embodiment can improve the accuracy of detecting semiconductor devices having defects that may cause element breakdown compared to electrical characteristic inspection.

[0071] Embodiment 3 In the third embodiment, a manufacturing method of a semiconductor device will be described using the semiconductor device inspection apparatus described in the first and second embodiments. FIG. 26 is a flowchart showing the flow of the semiconductor device manufacturing method according to the third embodiment. As shown in FIG. 26, in S301, a silicon carbide substrate made of silicon carbide is procured. In S302 following S301, defect data of the silicon carbide substrate (semiconductor wafer) is acquired. In S303 following S302, product specifications of candidate semiconductor devices to be manufactured on the silicon carbide substrate are acquired. In S304 following S303, the semiconductor device inspection apparatus infers a judgment result of the semiconductor device assuming that a semiconductor device having the product specifications is manufactured on the semiconductor wafer, and infers the number of non-defective semiconductor devices and the yield of semiconductor devices obtained from the semiconductor wafer from the inferred judgment result.

[0072] In S305 following S304, it is determined from the inferred yield whether or not to start manufacturing a semiconductor device having the product specifications on the silicon carbide substrate. Whether or not to start manufacturing the semiconductor device is determined, for example, if the inferred yield is equal to or greater than a predetermined threshold value, to start manufacturing, and if the yield is less than the threshold value, to not start manufacturing. If it is determined to start manufacturing the semiconductor device (YES in S305), manufacturing of the semiconductor device is started in S306. If it is determined not to start manufacturing the semiconductor device (NO in S305), it is determined in S307 whether or not there are other candidate product specifications. If there are other candidate product specifications (YES in S307), the process returns to S303. If there are no other candidate product specifications (NO in S307), it is determined in S308 that the silicon carbide substrate will not be used.

[0073] According to the method for manufacturing a semiconductor device according to the third embodiment, it is possible to prevent deviations from the production plan or increases in manufacturing costs due to a small number of non-defective products that will not cause failures being obtained as a result of manufacturing silicon carbide substrates.

[0074] The embodiments disclosed herein are intended to be combined as appropriate within the scope of compatibility. The embodiments disclosed herein should be considered to be illustrative and not restrictive in all respects. The scope of the present disclosure is defined by the claims, not the above description, and is intended to include all modifications within the meaning and scope of the claims. [Explanation of symbols]

[0075] 2 defect inspection device, 3 defect inspection data storage unit, 4 learning data acquisition unit, 5 learning data processing unit, 6, 26 teacher data storage unit, 7 model generation unit, 8 learned model storage unit, 9 inference data acquisition unit, 10 inference data processing unit, 11, 21 inference unit, 12 judgment unit, 13 learning device, 14 inference device, 15a to 15c defects, 16 silicon carbide substrate, 17 semiconductor device, 18 manufacturing location information, 19 invalid area, 20 valid area, 23 sorting unit, 24 gate pad, 25 product specification storage unit, 27 operation input device, 29 display / operation input device, 28 display device, 30 dimension information storage unit, 31 unnecessary data calculation unit, 33 defect image data storage unit, 71 processing circuit, 72 memory, 73 input / output unit, 100, 200 inspection device, 271 keyboard, 272 Mouse, 281 display, 291 touch display, Ds training data, M1 inference model, Nw1 neural network, Pg1 machine learning program, Pg2 inspection program, Wth threshold, X10 input layer, X11~X13, Y11, Y12, Z11~Z13 neurons, Y10 hidden layer, Z10 output layer, w11~w16, w21~w26 weights.

Claims

1. a learning data processing unit that identifies at least one defect included in the first semiconductor device from defect data related to defects included in the first silicon carbide substrate and position information on where a first semiconductor device is formed on the first silicon carbide substrate, and generates learning data in which learning input data including data related to at least one defect included in the first semiconductor device is associated with teacher data including data related to the quality of the first semiconductor device; a model generation unit that generates a trained model that infers data related to the quality of the first semiconductor device from the training input data by machine learning using the training data; an inference data processing unit that identifies at least one defect included in the second semiconductor device from defect data related to defects occurring in the second silicon carbide substrate and position information on where the second semiconductor device is formed on the second silicon carbide substrate, and generates inference input data including data related to the at least one defect included in the second semiconductor device; an inference unit that infers data related to the quality of the second semiconductor device from the inference input data using the trained model, The semiconductor device inspection device, wherein the learning data processing unit adds information about a current flowing at a position of a defect included in the first silicon carbide substrate when the first semiconductor device is energized to the defect data.

2. 2. The semiconductor device inspection device according to claim 1, further comprising a determination unit that determines whether said second semiconductor device is a non-defective product or a defective product using an inference result from said inference unit.

3. the teaching data includes information as to whether the first semiconductor device is a good product or a defective product, 3. The semiconductor device inspection device according to claim 1, wherein the data relating to the quality of the second semiconductor device includes a probability that the second semiconductor device is a non-defective product and a probability that the second semiconductor device is a defective product.

4. the teacher data includes a short-circuit resistance of the first semiconductor device, 3. The semiconductor device inspection device according to claim 1, wherein the data relating to the quality of said second semiconductor device includes a short-circuit resistance of said second semiconductor device.

5. the learning input data includes a relative position of each of at least one defect included in the first semiconductor device, a size of the defect, a type of the defect, and a number of defects classified into the type; The semiconductor device inspection device of any one of claims 1 to 4, wherein the inference input data includes the relative position of each of at least one defect contained in the second semiconductor device, the size of the defect, the type of the defect, and the number of defects classified into that type.

6. A learning data processing unit that identifies at least one defect contained in a first semiconductor device from defect data related to defects contained in a first silicon carbide substrate and position information where a first semiconductor device is formed on the first silicon carbide substrate, and generates learning data that associates learning input data including data related to at least one defect contained in the first semiconductor device with teacher data including data related to the quality of the first semiconductor device; a model generation unit that generates a trained model that infers data related to the quality of the first semiconductor device from the training input data by machine learning using the training data; an inference data processing unit that identifies at least one defect included in the second semiconductor device from defect data related to defects occurring in the second silicon carbide substrate and position information on where the second semiconductor device is formed on the second silicon carbide substrate, and generates inference input data including data related to the at least one defect included in the second semiconductor device; an inference unit that infers data related to the quality of the second semiconductor device from the inference input data using the trained model, the learning input data includes data on product specifications of the first semiconductor device, The inference input data includes data relating to product specifications of the second semiconductor device.

7. 7. The semiconductor device inspection device according to claim 1, wherein defect data relating to defects occurring in each of the first silicon carbide substrate and the second silicon carbide substrate includes image data of defects occurring in the silicon carbide substrate.

8. a learning data processing unit that identifies at least one defect included in the semiconductor device from defect data related to defects occurring in the silicon carbide substrate and position information on where the semiconductor device is formed on the silicon carbide substrate, and generates learning data in which input data including data related to at least one defect included in the semiconductor device is associated with teacher data including data related to the quality of the semiconductor device; a model generation unit that generates a trained model that infers data related to the quality of the semiconductor device from the input data by machine learning using the training data; The learning device, wherein the learning data processing unit adds, to the defect data, information about a current that flows at a position of a defect included in the silicon carbide substrate when the semiconductor device is energized.

9. an inference data processing unit that identifies at least one defect included in the semiconductor device from defect data related to defects occurring in the silicon carbide substrate and position information on where the semiconductor device is formed on the silicon carbide substrate, and generates inference input data including data related to the at least one defect included in the semiconductor device; An inference device comprising: an inference unit that infers data related to the quality of the semiconductor device from the inference input data using a trained model generated by the learning device according to claim 8.

10. acquiring defect data of a silicon carbide substrate and product specifications of a specific semiconductor device formed on the silicon carbide substrate; using a semiconductor device inspection device to estimate, from the defect data, a yield when the specific semiconductor device is manufactured in accordance with the product specifications; and selecting, based on an inference result of the step of inferring the yield, one of starting manufacturing of the specific semiconductor device, predicting a yield of a semiconductor device having product specifications different from the product specifications, and not using the silicon carbide substrate; The semiconductor device inspection device includes: a learning data processing unit that identifies at least one defect included in the first semiconductor device from defect data related to defects included in the first silicon carbide substrate and position information on where a first semiconductor device is formed on the first silicon carbide substrate, and generates learning data in which learning input data including data related to at least one defect included in the first semiconductor device is associated with teacher data including data related to the quality of the first semiconductor device; a model generation unit that generates a trained model that infers data related to the quality of the first semiconductor device from the training input data by machine learning using the training data; an inference data processing unit that identifies at least one defect included in the second semiconductor device from defect data related to defects occurring in the second silicon carbide substrate and position information on where the second semiconductor device is formed on the second silicon carbide substrate, and generates inference input data including data related to the at least one defect included in the second semiconductor device; A method for manufacturing a semiconductor device, comprising: an inference unit that uses the trained model to infer data regarding the quality of the second semiconductor device from the inference input data.

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