semiconductor memory device

Abstract

This invention reduces defective bits such as SILC mode in a semiconductor memory device. [Solution] The semiconductor memory device includes a plurality of memory cells formed on a semiconductor substrate. Each memory cell includes a first floating gate transistor (TFG1), a second floating gate transistor (TFG2), a first erase element, a second erase element, and a memory cell select transistor. The gate of TFG1 is connected to the gate of the first erase element. The gate of TFG2 is connected to the gate of the second erase element. The source of TFG1 is connected to the drain of the memory cell select transistor. The source of TFG2 is connected to the drain of the memory cell select transistor or the drain of TFG1.

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor memory devices. [Background technology]

[0002] Semiconductor memory devices are used in various electronic devices. For example, nonvolatile memory (NVM) is widely used in portable devices and the like.

[0003] Generally, NVM is classified into multi-time programmable (MTP) memory and one-time programmable (OTP) memory. MTP memory can be read multiple times and written multiple times. Also, OTP does not require an erase operation, but MTP does.

[0004] As a type of NVM, single-poly NVM has been proposed, which can eliminate additional manufacturing processes. In single-poly NVM, a charge storage floating gate is formed with a single layer of polysilicon. Since single-poly NVM can be fabricated using the usual CMOS (Complementary Metal Oxide Semiconductor) manufacturing process, it is used as an embedded memory in microcontrollers and other devices. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Publication No. 2023-89475 Summary of the Invention [Problem to be solved by the invention]

[0006] The nonvolatile memory with the above configuration includes a transistor with a floating gate (FG) as its gate electrode. Nonvolatile data is stored by utilizing the difference in the transistor current depending on whether or not charge is stored in the floating gate (FG).

[0007] In such memory devices, if the gate oxide becomes thinner due to demands for miniaturization or if defects occur in the gate oxide, the charge stored in the floating gate can escape. This is known as the SILC (Stress-Induced Leakage Current) mode. When this occurs, the correct memory state cannot be maintained, resulting in a defective bit. This defect occurs with an extremely low probability, and the retention time is often not very temperature-dependent. This makes screening difficult, and even the repair of defective bits through screening is difficult. Furthermore, the number of defective bits tends to increase with retention time. Projected for 10 years from now, the chip failure rate will be around 1000 ppm, posing a reliability issue.

[0008] In view of the above, an object of the present disclosure is to reduce the number of defective bits caused by defects such as SILC mode in a semiconductor memory device. [Means for solving the problem]

[0009] The semiconductor memory device of the present disclosure includes a plurality of memory cells formed on a semiconductor substrate. Each memory cell includes a first floating gate transistor, a second floating gate transistor, a first erase element, a second erase element, and a memory cell select transistor. The gate of the first floating gate transistor is electrically connected to the gate of the first erase element. The gate of the second floating gate transistor is electrically connected to the gate of the second erase element. The source of the first floating gate transistor is electrically connected to the drain of the memory cell select transistor. The source of the second floating gate transistor is electrically connected to the drain of the memory cell select transistor or the drain of the first floating gate transistor. [Effects of the Invention]

[0010] According to the semiconductor memory device of the present disclosure, one memory cell is stored using multiple floating gate transistors provided in each memory cell, so that even if a SILC mode defect occurs in one floating gate transistor, the memory cell can maintain correct storage, thereby reducing bit defects. [Brief explanation of the drawings]

[0011] [Figure 1] FIG. 1 is a diagram showing a circuit configuration of an exemplary semiconductor memory device according to the first embodiment. [Figure 2] FIG. 2 is a plan view illustrating the layout of the semiconductor memory device of FIG. [Figure 3] FIG. 3 is a diagram showing the bit error rate over time in the semiconductor memory device of the first embodiment. [Figure 4] FIG. 4 is a diagram showing the bit error rate over time in the semiconductor memory device of the comparative example. [Figure 5] FIG. 5 is a plan view illustrating a layout of a semiconductor memory device according to a modification of the first embodiment. [Figure 6]FIG. 6 is a diagram showing a circuit configuration of an exemplary semiconductor memory device according to the second embodiment. [Figure 7] FIG. 7 is a plan view illustrating the layout of the semiconductor memory device of FIG. [Figure 8] FIG. 8 is a diagram showing a circuit configuration of an exemplary semiconductor memory device according to the third embodiment. [Figure 9] FIG. 9 is a plan view illustrating the layout of the semiconductor memory device of FIG. DETAILED DESCRIPTION OF THE INVENTION

[0012] Hereinafter, embodiments will be described with reference to the accompanying drawings. The following description is merely an example and is not intended to be limiting. Furthermore, modifications can be made as appropriate within the scope of the present invention.

[0013] (First embodiment) A first embodiment of the present disclosure will be described with reference to the drawings. Fig. 1 is a diagram showing a circuit configuration of an exemplary semiconductor memory device according to the first embodiment. Fig. 2 is a plan view showing an example layout of the semiconductor memory device of this embodiment.

[0014] The circuit configuration will be described with reference to Fig. 1. Fig. 1 shows a circuit corresponding to one memory cell 50. The memory cell 50 includes a memory cell select gate section 10, a program element section 20, an erase element section 30, and an assist element section 40.

[0015] The program element unit 20 has a configuration in which a transistor TFG1 (floating gate transistor) having a first floating gate FG1 as a gate node and a transistor TFG2 having a second floating gate FG2 as a gate node are connected in parallel. That is, the sources of the transistors TFG1 and TFG2 are connected to each other and the drains are connected to each other.

[0016] The source side of transistors TFG1 and TFG2 is connected to the drain of a select transistor TSG1 provided in the select gate unit 10, and the drain side is connected to a bit line BL. The source side of select transistor TSG1 is connected to a source signal SL (ground voltage VSS), and the gate of select transistor TSG1 is connected to a select gate signal SG.

[0017] The erase element section 30 includes erase elements TER1 and TER2. The erase element TER1 includes a first erase gate and a first erase element impurity region provided on a semiconductor substrate. The erase element TER2 includes a second erase gate and a second erase element impurity region provided on a semiconductor substrate.

[0018] The floating gate FG1 is connected to the gate of the erase element TER1, and the floating gate FG2 is connected to the gate of the erase element TER2. The node of the first erase element impurity region of the erase element TER1 and the node of the second erase element impurity region of the erase element TER2 are connected to the erase node ER. The erase elements TER1 and TER2 are charge control elements that control the charges in the floating gates FG1 and FG2, and erase the information stored in the program element section 20.

[0019] The assist element section 40 includes assist elements TAS1 and TAS2. The assist element TAS1 includes a first assist gate and a first assist element impurity region provided on a semiconductor substrate. The assist element TAS2 includes a second assist gate and a second assist element impurity region provided on a semiconductor substrate.

[0020] The floating gate FG1 is connected to the assist element TAS1, and the floating gate FG2 is connected to the assist element TAS2. The assist elements TAS1 and TAS2 are potential control elements that control the potentials of the floating gates FG1 and FG2, and improve the efficiency of the program operation and / or erase operation in the program element section 20.

[0021] In the present embodiment, the first and second assist element impurity regions of the assist elements TAS1 and TAS2 are connected to the bit line BL as nodes, but these nodes can also be controlled by independent nodes.

[0022] 2 illustrates a layout corresponding to the circuit diagram of FIG. 1. It shows an active region 61 (indicated by widely spaced diagonal lines from the upper left to the lower right) provided on a semiconductor substrate, various gate sections 62 (indicated by closely spaced diagonal lines from the upper right to the lower left), and a metal wiring layer 63 (indicated by dots). The memory cells 50, memory cell select gate section 10, program element section 20, erase element section 30, and assist element section 40 all correspond to those in FIG. 1. For example, the layout of FIG. 2 can be used to realize the circuit of FIG. 1.

[0023] Next, the program operation, erase operation, and read operation in the semiconductor memory device of this embodiment will be described.

[0024] During a program operation (write), the select transistor TSG1 is turned on and a high voltage is applied to both the bit line BL, generating hot carriers in the transistors TFG1 and TFG2 that make up the program element section 20. The charge of the hot carriers passes through the insulating film and enters the floating gates FG1 and FG2. As a result, the threshold values ​​of the transistors TFG1 and TFG2 become high, and no current flows. This puts them into the program state.

[0025] At this time, since a high voltage is applied to the bit line BL, the assist element section 40 acts to increase the potential of the floating gates FG1 and FG2, thereby improving the efficiency of programming.

[0026] Furthermore, a voltage that does not cause an erase operation (that is, a voltage lower than that during an erase operation) is applied to the nodes ER of the erase elements TER1 and TER2 of the erase element section 30. This also makes it possible to improve the efficiency of programming.

[0027] During the erase operation, the select transistor TSG1 is turned off, the bit line BL is set to ground voltage or in a floating state, and a high voltage is applied to the erase node ER. This removes the charge stored in the floating gates FG1 and FG2. As a result, the threshold voltages of the transistors TFG1 and TFG2 are lowered, allowing current to flow. This completes the erase operation.

[0028] During a read operation, the select transistor TSG1 is turned on and a voltage is applied that does not cause a program operation (i.e., lower than that during a program operation). In this state, the current value flowing through the bit line BL determines whether it is in the on or off state. In other words, a determination current value that serves as the basis for on / off is set, and if the current value flowing through the bit line BL is greater than the determination current value, it is determined to be on, and if it is less than the determination current value, it is determined to be off. Note that during a read operation, the erase node ER is set to ground voltage.

[0029] The programmed state and erased state may be verified by a read operation, and an additional program operation and an additional erase operation may be performed so that the cell current becomes an appropriate current.

[0030] --Reducing memory cell defects-- Next, it will be explained how the semiconductor memory device of this embodiment can reduce defects in the memory cells 50 as a whole even when defects such as SILC mode defects occur.

[0031] In devices that store data based on the presence or absence of charge in the floating gate (FG), if the charge stored in the floating gate is lost, the correct memory state cannot be maintained and a defective bit occurs. In particular, when the charge is lost due to a thin gate insulating film or defects, this is called SILC mode. Defects due to SILC mode (hereinafter also referred to as SILC defects) can occur in each floating gate.

[0032] In the semiconductor memory device of this embodiment, the program element section 20 in one memory cell 50 includes two transistors TFG1 and TFG2 connected in parallel. These two transistors correspond to one select transistor TSG1 in the memory cell select gate section 10. Transistors TFG1 and TFG2 use floating gates FG1 and FG2, respectively, as gate nodes.

[0033] With this configuration, even if a defect occurs in one of the two floating gates FG1 and FG2, the memory cell 50 can still retain correct data. Therefore, the occurrence of defective bits can be significantly reduced. In other words, if the chip failure rate when a defect occurs in one floating gate with a certain probability is about 1000 ppm, the probability that an SILC defect will occur with the same probability in the floating gates FG1 and FG2 provided in the memory cell 50, causing the chip to fail, will be about 1 ppm.

[0034] In order for memory cell 50 to retain correct data even if an SILC defect occurs in one floating gate, the current values ​​for transistors TFG1 and TFG2 and the current value for determining whether memory cell 50 is on or off are set, as will be further explained below.

[0035] Table 1 shows the current values ​​in each state for each of transistors TFG1 and TFG2 and for the entire program element unit 20. The states are the initial state, the programmed state, the SILC defect state during programming, the erased state, and the SILC defect state during erasing. The SILC defect state is a state in which an SILC defect occurs in one of the transistors (transistor TFG1). The same is essentially true if an SILC defect occurs in transistor TFG2 instead of transistor TFG1.

[0036] [Table 1]

[0037] In the example of Table 1, when transistors TFG1 and TFG2 are in the initial state, the current flowing through each transistor during a read operation is 3 μA. The initial state refers to the state in which each element is formed in the manufacturing process of a semiconductor memory device and floating gates FG1 and FG2 are stable (a state in which no charge is injected, etc.).

[0038] In a program (write) state where no SILC fault occurs, the current value in transistors TFG1 and TFG2 is set to 0 μA. Since the two transistors TFG1 and TFG2 are connected in parallel, in the program state, the current value of the entire program element unit 20 (hereinafter also referred to as the overall current) is 0 μA.

[0039] In addition, in an erased state where no SILC defects occur, the current values ​​in the transistors TFG1 and TFG2 are set to 15 μA, and the total current is 30 μA.

[0040] Generally, when an SILC defect occurs in a transistor and charge is removed from the floating gate, the floating gate transistor approaches its initial state. Therefore, in the SILC defect state during programming and erasing, the current value in the defective transistor TFG1 is 3 μA, the same as in the initial state.

[0041] From the above, in the SILC defective state during programming, the total current is 3 μA, which is the sum of 0 μA and 3 μA. Also, in the SILC defective state during erasure, the total current is 18 μA, which is the sum of 15 μA and 3 μA.

[0042] In this case, the threshold current value that serves as the reference for turning on / off the memory cell 50 is set to, for example, 5 μA, which is a value between the total currents (3 μA and 18 μA) in the SILC defective state during programming and the SILC defective state during erasure.

[0043] In this way, the total current in a non-faulty programmed state is 0 μA, which is smaller than the threshold current value (5 μA), and is therefore determined to be in a programmed state. Also, in a SILC fault state during programming, the total current is 3 μA, which is smaller than the threshold current value, and is therefore correctly determined to be in a programmed state.

[0044] Next, the total current in the erased state is 30 μA, which is larger than the judgment current value, so it is judged to be in the erased state. Also, even in the SILC defective state during erasure, the total current is 18 μA, which is larger than the judgment current value, so it can be correctly judged to be in the erased state.

[0045] As described above, the semiconductor memory device of this embodiment can correctly determine the programmed state and erased state even when a SILC-mode failure occurs in transistor TFG1. Note that even when a SILC-mode failure occurs in transistor TFG2 instead of transistor TFG1, the total current in each state is the same as the value shown in Table 1, and correct determination can be made in the same way.

[0046] The current value to be determined is set to a value greater than half the total current (6 μA) when the transistors TFG1 and TFG2 are in the initial state. In the example of Table 1, the value is set to a value greater than 3 μA.

[0047] For this reason, the configuration of this embodiment is suitable when the current value in the initial state is small. This is because the lower limit of the judgment current value becomes smaller as the current value in the initial state becomes smaller, and the range in which the judgment current value can be set becomes wider. The current value in the initial state is determined by various factors, but can be adjusted by the assist element unit 40. In this embodiment, it may be appropriate to set the effect of the assist element unit 40 to a relatively small value. Also, a configuration without the assist element unit 40 may be used.

[0048] The determination current value is preferably smaller than half the total current value when the transistors TFG1 and TFG2 are in the erased state, and in the example of Table 1, it is set to a value smaller than 15 μA.

[0049] The judgment current value may be the total current in the initial state (6 μA in the example of Table 1). Furthermore, considering that the current of the memory cell 50 when turned on (erased) decreases at high temperatures and that the current may vary among the memory cells 50, it is preferable to set the judgment current value to a value slightly lower than the total current in the initial state, which is set to 5 μA in the example of this embodiment.

[0050] 3 shows the bit error rate over time under various temperature conditions for the semiconductor memory device of this embodiment. The graph shows time on the horizontal axis and bit error rate on the vertical axis, and the occurrence of defective bits is suppressed even over time.

[0051] As a comparative example, Figure 4 shows a similar bit error rate for a semiconductor memory device including a conventional memory cell using a single transistor (with the floating gate serving as the gate node). This semiconductor memory device does not include the transistor TFG2, floating gate FG2, assist element TAS2, or erase element TER2 shown in Figure 1. In this case, the bit error rate increases over time.

[0052] In the case of Figure 4, temperature dependence is evident, with a tendency for defects to increase as the temperature increases. However, SILC-mode defects have little temperature dependence. Therefore, accelerated evaluation and screening at high temperatures are difficult.

[0053] The semiconductor memory device of the present disclosure can reduce defects without including an ECC (Error Correction Code) circuit to deal with SILC mode defects, although it is of course possible to include an ECC circuit for safety in various cases.

[0054] (Modification of the first embodiment) A modification of the first embodiment will be described with reference to Fig. 5. Fig. 5 is a plan view showing the layout of a semiconductor memory device in this modification, and corresponds to Fig. 2 in the first embodiment. Fig. 5 also shows a different layout from Fig. 2, which realizes the circuit diagram of Fig. 1.

[0055] 5 is different from the layout of Fig. 2 with respect to the assist elements TAS1 and TAS2 of the assist element section 40. That is, the assist effect is improved by forming the gate into a ring shape and arranging the active region 61 below the assist gate.

[0056] 2, two bit lines in the same cell are not connected by an active region 61, but are connected by a metal wiring layer 63. In contrast, in the layout of FIG. 5, two bit lines are directly connected by an active region 61, and an added active region 61 is also electrically connected to the bit lines by metal.

[0057] This layout allows for a larger capacitance between the floating gate and the bit line. As a result, the floating gate potential can be increased during a program operation, improving program efficiency and ultimately shortening the program time. Furthermore, during an erase operation, the capacitance of the assist element in the assist element section 40 is increased, making it less likely for the floating gate potential to float. This increases the potential difference actually applied to the erase elements TER1 and TER2 during erase, ultimately shortening the erase time.

[0058] In this way, the layout of this modification can improve performance without increasing the cell size compared to the layout of FIG.

[0059] (Second embodiment) A second embodiment of the present disclosure will be described with reference to the drawings. Fig. 6 is a diagram showing a circuit configuration of an exemplary semiconductor memory device according to the second embodiment. Fig. 7 is a plan view showing an example layout of the semiconductor memory device of this embodiment.

[0060] 6 is compared with the circuit diagram of the first embodiment shown in FIG. 1, the program element section 20 is different, but the memory cell select gate section 10, erase element section 30, and assist element section 40 are the same. The differences will be mainly described below.

[0061] 2, transistors TFG1 and TFG2 are connected in parallel, whereas in this embodiment, these transistors are connected in series. Specifically, the source of transistor TFG1 is connected to the drain of transistor TFG2. The drain of transistor TFG1 is connected to bit line BL. The source side of transistor TFG2 is connected to the drain of select transistor TSG1 of memory cell select gate unit 10.

[0062] The transistors TFG1 and TFG2 have floating gates FG1 and FG2, respectively, as gate nodes. An erase element TER1 and an assist element TAS1 are connected to the floating gate FG1, and an erase element TER2 and an assist element TAS2 are connected to the floating gate FG2, as in the first embodiment. In this embodiment, the impurity regions of the assist elements TAS1 and TAS2 are connected to the bit line BL as nodes. However, these nodes can also be controlled by independent nodes.

[0063] Figure 7 illustrates a layout corresponding to the circuit diagram of Figure 6. Figure 7 also shows an active region 61 and a gate section 62. The memory cell 50, the memory cell select gate section 10, the program element section 20, the erase element section 30, and the assist element section 40 all correspond to Figure 6. For example, the layout of Figure 6 can realize the circuit of Figure 5.

[0064] Next, the program operation, erase operation, and read operation in the semiconductor memory device of this embodiment will be described.

[0065] During the programming operation, the selection transistor TSG1 is turned on and a high voltage is applied to both the bit line BL, generating hot carriers in the transistors TSG1 and TFG2 that make up the programming element section 20. When the hot carriers enter the floating gates FG1 and FG2, the threshold values ​​of the transistors TFG1 and TFG2 become high, and no current flows, thereby entering the programming state.

[0066] At this time, since a high voltage is applied to the bit line BL, the assist element section 40 acts to increase the potential of the floating gates FG1 and FG2, thereby improving the efficiency of programming.

[0067] Furthermore, a voltage that does not cause an erase operation (that is, a voltage lower than that during an erase operation) is applied to the nodes ER of the erase elements TER1 and TER2 of the erase element section 30. This also makes it possible to improve the efficiency of programming.

[0068] During the erase operation, the select transistor TSG1 is turned off, the bit line BL is set to ground voltage or in a floating state, and a high voltage is applied to the erase node ER. This removes the charge stored in the floating gates FG1 and FG2. As a result, the threshold voltages of the transistors TFG1 and TFG2 are lowered, allowing current to flow. This completes the erase operation.

[0069] During a read operation, the select transistor TSG1 is turned on, and a voltage is applied to the bit line BL that does not cause a program operation (i.e., a voltage lower than that used during a program operation). In this state, the current value flowing through the bit line BL determines whether it is in the on or off state. In other words, a determination current value is set as the reference for on / off, and if the current value flowing through the bit line BL is greater than the determination current value, it is determined to be on, and if it is less than the determination current value, it is determined to be off. Note that during a read operation, the erase node ER is set to ground voltage.

[0070] The programmed state and erased state may be verified by a read operation, and an additional program operation and an additional erase operation may be performed so that the cell current becomes an appropriate current.

[0071] --Reducing memory cell defects-- Next, it will be explained how the semiconductor memory device of this embodiment can reduce defects in the memory cells 50 as a whole even when defects such as SILC mode defects occur.

[0072] In the semiconductor memory device of this embodiment, the program element section 20 in one memory cell 50 includes two transistors TFG1 and TFG2 connected in series. These two transistors correspond to one select transistor TSG1 in the memory cell select gate section 10. Transistors TFG1 and TFG2 use floating gates FG1 and FG2, respectively, as gate nodes.

[0073] This configuration also significantly reduces the occurrence of defective bits, as in the first embodiment. To achieve this, the current values ​​in the transistors TFG1 and TFG2 and the current value for determining whether the memory cell 50 is on or off are set. This will be explained further below.

[0074] Table 2 shows the current values ​​in each state for each of transistors TFG1 and TFG2 and for the entire program element unit 20. The states are the initial state, the program state, the SILC failure state during programming, the erase state, and the SILC failure state during erasing. The SILC failure state is a state in which an SILC failure occurs in one of the transistors (transistor TFG1).

[0075] [Table 2]

[0076] In the example of Table 2, when the transistors TFG1 and TFG2 are in the initial state, the current value flowing through each of them during a read operation is 15 μA.

[0077] In a program (write) state where no SILC fault occurs, the current value in transistors TFG1 and TFG2 is set to 0 μA. Since the two transistors TFG1 and TFG2 are connected in series, in the program state, the current value (total current) of the entire program element unit 20 is 0 μA.

[0078] In addition, in an erased state where no SILC failure occurs, the current value in the serially connected transistors TFG1 and TFG2 is set to 30 μA, and the total current is 30 μA.

[0079] In addition, in the SILC defective state during programming and in the SILC defective state during erasing, the current value in the defective transistor TFG1 is 15 μA, the same as in the initial state.

[0080] From the above, in the SILC failure state during programming, the current values ​​of the serially connected transistors TFG1 and TFG2 are 15 μA and 0 μA, respectively, so the total current is 0 μA. Also, in the SILC failure state during erasure, the current values ​​of the serially connected transistors TFG1 and TFG2 are 15 μA and 30 μA, respectively, so the total current is 15 μA.

[0081] In this case, the determination current value is set to, for example, 12 μA, which is a value between the total currents (15 μA and 0 μA) in the SILC defective state during programming and the SILC defective state during erasing.

[0082] In this way, in the programmed state and in the SILC defective state during programming, the total current is 0 μA, which is smaller than the determination current value of 12 μA, so that the programmed state can be correctly determined.

[0083] In addition, the total current in the erased state without defects is 30 μA, which is larger than the judgment current value, so it is judged as the erased state.Furthermore, even in the SILC defective state during erasure, the total current is 15 μA, which is larger than the judgment current value, so it is correctly judged as the erased state.

[0084] As described above, the semiconductor memory device of this embodiment can correctly determine the programmed state and erased state even when a SILC-mode failure occurs in transistor TFG1. Note that even when a SILC-mode failure occurs in transistor TFG2 instead of transistor TFG1, the total current in each state is the same as the value shown in Table 2, and a correct determination can be made in the same way.

[0085] The current value for determination is set to a value smaller than the total current value that flows through the transistors TFG1 and TFG2 in the initial state.

[0086] The configuration of this embodiment is suitable for cases where the current value in the initial state is large and SILC mode defects on the on side are unlikely to occur. The current value in the initial state is determined by various factors, but can be adjusted by the assist element unit 40. In this embodiment, it may be appropriate to set the effect of the assist element unit 40 to be relatively large. Furthermore, it may be appropriate to configure the assist element unit 40 to be controlled using a signal other than the signal from the bit line BL, thereby increasing the assist effect. However, the effect of the assist element unit 40 is limited to a range that does not result in a programmed state during a read operation.

[0087] (Third embodiment) A third embodiment of the present disclosure will be described with reference to the drawings. Fig. 8 is a diagram showing a circuit configuration of an exemplary semiconductor memory device according to the third embodiment. Fig. 9 is a plan view showing an example layout of the semiconductor memory device of this embodiment.

[0088] 8 is similar to the circuit diagram of the first embodiment shown in FIG. 1 in that it includes a memory cell selection gate section 10, a program element section 20, an erase element section 30, and an assist element section 40. The memory cell selection gate section 10 also has the same configuration.

[0089] The program element unit 20 includes six transistors TFG1 to TFG6. The source of transistor TFG1 is connected to the drain of transistor TFG5. The source of transistor TFG2 is connected to the drain of transistor TFG6. The source of transistor TFG3 is connected to the drain of transistor TFG4.

[0090] Pairs of two transistors connected in series as described above are connected in parallel to each other to form the program element section 20. That is, the sources of transistors TFG4, TFG6, and TFG5 are connected to each other and to the drain of select transistor TSG1. In addition, the drains of transistors TFG3, TFG2, and TFG1 are connected to each other and to bit line BL.

[0091] Three assist elements TAS1, TAS2, and TAS3 are provided in the assist element section 40. The assist element TAS3 has the same configuration as the assist elements TAS1 and TAS2, and includes a third assist gate and a third assist element impurity region.

[0092] In this embodiment, the impurity regions of the assist elements TAS1, TAS2, and TAS3 are connected as nodes to the bit line BL, but these nodes can also be controlled by independent nodes.

[0093] Three erase elements TER1, TER2, and TER3 are provided in the erase element section 30. The erase element TER3 has the same configuration as the erase elements TER1 and TER2, and includes a third erase gate and a third erase section impurity region.

[0094] The impurity regions of the erase elements TER1, TER2, and TER3 are connected as nodes to an erase node ER.

[0095] Also provided are three floating gates FG1, FG2 and FG3.

[0096] The floating gate FG1 is connected to the gates of the transistors TFG1 and TFG4, the erase element TER3, and the assist element TAS3.

[0097] The floating gate FG2 is connected to the gates of the transistors TFG2 and TFG5, the erase element TER2, and the assist element TAS2.

[0098] The floating gate FG3 is connected to the gates of the transistors TFG3 and TFG6, the erase element TER3, and the assist element TAS3.

[0099] 9 illustrates a layout corresponding to the circuit diagram of FIG. 9. Also in FIG. 9, an active region 61, a gate section 62, and a metal wiring layer 63 are shown. The memory cell 50, the memory cell select gate section 10, the program element section 20, the erase element section 30, and the assist element section 40 all correspond to those in FIG. 8. For example, the layout of FIG. 9 can realize the circuit of FIG. 8.

[0100] Next, the program operation, erase operation, and read operation in the semiconductor memory device of this embodiment will be described.

[0101] During the programming operation, the selection transistor TSG1 is turned on and a high voltage is applied to both the bit line BL, generating hot carriers in each of the transistors TFG1 to TFG6 that make up the programming element section 20. When the hot carriers enter the floating gates FG1 and FG2, the threshold values ​​of the transistors TFG to TFG6 become high, and no current flows, thereby entering the programming state.

[0102] At this time, since a high voltage is applied to the bit line BL, the assist element section 40 acts to increase the potential of the floating gates FG1 to FG3, thereby improving the efficiency of programming.

[0103] During the erase operation, the select transistor TSG1 is turned off, the bit line BL is set to the ground voltage level or in a floating state, and a high voltage is applied to the erase node ER. This removes the charge accumulated in the floating gates FG1 to FG3. As a result, the threshold voltages of the transistors TFG1 to TFG6 are lowered, allowing current to flow. This completes the erase operation.

[0104] During a read operation, the select transistor TSG1 is turned on, and a voltage that does not cause a program operation (i.e., a voltage lower than that during a program operation) is applied to the bit line BL. In this state, the current value flowing through the bit line BL determines whether it is in the on state or the off state. During a read operation, the erase node ER is set to ground voltage.

[0105] The programmed state and erased state may be verified by a read operation, and an additional program operation and an additional erase operation may be performed so that the cell current becomes an appropriate current.

[0106] --Reducing memory cell defects-- Next, it will be explained how the semiconductor memory device of this embodiment can reduce defects in the memory cells 50 as a whole even when defects such as SILC mode defects occur.

[0107] In the semiconductor memory device of this embodiment, the program element section 20 in one memory cell 50 has six transistors TFG1 to TFG6 connected as described above, and one select transistor TSG1 in the memory cell select gate section 10 corresponds to these transistors TFG1 to TFG6.

[0108] This configuration significantly reduces the occurrence of defective bits even if a defect occurs in any of the floating gates FG1-FG3. To achieve this, the current values ​​in the transistors TFG1-TFG6 and the current values ​​for determining whether the memory cell 50 is on or off are set. This will be explained further below.

[0109] Table 3 shows the current values ​​in each state for three pairs of serially connected transistors, namely, transistors TFG1 / TFG4, transistors TFG2 / TFG5, and transistors TFG3 / TFG6, and for the entire program element unit 20. The states are the initial state, the programmed state, the SILC failure state during programming, the erased state, and the SILC failure state during erasing. The SILC failure state is defined as a state in which the SILC failure state occurs in the floating gate FG1 (in other words, in either transistor TFG1 or TFG4).

[0110] The current values ​​in the two series-connected transistors are simplified values ​​and are not necessarily accurate. This is because the following explanation can be made clearer and simpler than if accurate values ​​were used, and the use of simplified values ​​has little effect on the explanation of the configuration and effects of the invention.

[0111] [Table 3]

[0112] In the example of Table 3, the current value of each of transistors TFG1 to TFG6 in the initial state is 3 μA. Therefore, the total current (the current value of the entire program element unit 20) is the sum of the currents in the three sets of transistors connected in parallel, which is 9 μA.

[0113] In this embodiment as well, when an SILC defect occurs in the transistor and charge is released from the floating gate, the floating gate transistor approaches its initial state (current value of 3 μA).

[0114] In a programmed state where no SILC defects occur, the current value in each of the transistors TFG1 to TFG6 is set to 0 μA, and therefore the total current is also 0 μA.

[0115] In a SILC failure state during programming, the threshold voltages of transistors TFG1 and TFG4 connected to floating gate FG1 fluctuate, allowing a current of 3 μA to flow through each. However, because transistor TFG1 is connected in series with transistor TFG5 and transistor TFG4 is connected in series with transistor TFG3, the current flowing through these pairs is 0 μA. Therefore, in a SILC failure state during programming, the total current is 0 μA. Therefore, memory cell 50 is not considered defective.

[0116] In addition, in an erased state where no SILC defects occur, the current value in each of the transistors TFG1 to TFG6 is set to 10 μA, so the total current is 30 μA.

[0117] In the SILC failure state during erasure, the threshold voltages of the transistors TFG1 and TFG4 connected to the floating gate FG1 change, and the current that flows changes from 10 μA (current value during erasure) to 3 μA.

[0118] In this case, of the three pairs of series-connected transistors, two pairs containing transistors TFG1 or TFG4 have a current value of 3 μA. The remaining pair, transistors TFG2 and TFG3, maintains a current of 10 μA. Because the three pairs are connected in parallel, the total current is 16 μA.

[0119] Here, if the determination current value is set to a value between 0 μA and 16 μA, for example, 5 μA, even if SILC defects occur in some floating gates, the memory cell 50 can be determined to be in the erased state and will not be considered defective.

[0120] The determination current value is set in a range that is smaller than the total current in the SILC defective state during erasure and larger than the total current in the programmed state.

[0121] According to the configuration of this embodiment, regardless of the current value in the initial state, it is possible to reduce defects as a memory cell and accurately determine whether it is on or off. The above description has been given using an example in which a SILC mode defect occurs in floating gate FG1. However, even if a SILC mode defect occurs in another floating gate (FG2 or FG3), the total current in each state is the same as the value shown in Table 3, and a correct determination can be made in the same way.

[0122] The first embodiment mainly addresses the effects of defects on the ON side, and the second embodiment mainly addresses the effects of defects on the OFF side, whereas this embodiment can equally address the effects of defects on both the ON side and the OFF side.

[0123] On the other hand, in the configurations of the first and second embodiments, the number of transistors, erase elements, and assist elements provided in the program element section 20, erase element section 30, and assist element section 40 is smaller than that in the configuration of the third embodiment. Therefore, the first or second embodiment can reduce the size of the memory cell 50 or increase the cell current in a memory cell 50 of the same size.

[0124] In the above description, various elements are configured in the same well using N-channel transistors, but this is not limiting and P-channel transistors may also be used.

[0125] Furthermore, as the third embodiment, a configuration in which three pairs of two series-connected transistors are connected in parallel (2x3 configuration) has been described, but this is not limited to this and configurations such as 3x2, 3x4, etc. may also be used.

[0126] The above-described embodiments may be modified in form and detail without departing from the spirit of the claims. Furthermore, the contents of the embodiments may be combined and substituted as appropriate as long as the functions of the subject matter of the present disclosure are not impaired. [Industrial Applicability]

[0127] The semiconductor memory device of the present disclosure can significantly reduce the occurrence of defects such as SILC mode, and is also useful as a semiconductor memory device equipped with a nonvolatile memory. [Explanation of symbols]

[0128] 10 Select gate section 20 Program element section 30 Erasing element section 40 Assist element section 50 memory cells 61 Active region 62 Gate 63 Metal Wiring Layer SG Select gate signal SL Source signal (ground voltage VSS) BL Bit signal line ER erase signal line FG1~FG3 Floating Gates TSG1 Memory cell select transistor TFG1~TFG6 transistors (floating gate transistors) TER1~TER3 erasing elements TAS1~TAS3 assist elements

Claims

1. A plurality of memory cells are formed on a semiconductor substrate; each said memory cell comprises a first floating gate transistor, a second floating gate transistor, a first erase element, a second erase element and a memory cell select transistor; a gate of the first floating gate transistor electrically connected to a gate of the first erase element; a gate of the second floating gate transistor electrically connected to a gate of the second erase element; the source of the first floating gate transistor is electrically connected to the drain of the memory cell select transistor; the source of the second floating gate transistor is electrically connected to the drain of the memory cell select transistor; the source of the first floating gate transistor and the source of the second floating gate transistor are electrically connected; the drain of the first floating gate transistor and the drain of the second floating gate transistor are electrically connected; the drains of the first floating gate transistor and the second floating gate transistor are connected to a bit line; During a program operation and a read operation for the memory cell, a voltage is applied to the bit line; a voltage applied in the program operation is greater than a voltage applied in the read operation; current values ​​of the first floating gate transistor and the second floating gate transistor in an initial state are smaller than current values ​​of the first floating gate transistor and the second floating gate transistor in an erased state, respectively; a current value for determining whether the memory cell is in an on state or an off state, the current value being smaller than the sum of the current value in the initial state and the current value in the erased state;

2. In claim 1, a first assist element that controls a gate potential of the first floating gate transistor; a second assist element for controlling the gate potential of the second floating gate transistor.

3. In claim 1, the first erase element includes a first erase gate and a first impurity region formed on the semiconductor substrate; the second erase element includes a second erase gate and a second impurity region formed on the semiconductor substrate; a first impurity region and a second impurity region electrically connected to each other;

4. A plurality of memory cells are formed on a semiconductor substrate, each said memory cell comprises a first floating gate transistor, a second floating gate transistor, a first erase element, a second erase element and a memory cell select transistor; a gate of the first floating gate transistor electrically connected to a gate of the first erase element; a gate of the second floating gate transistor electrically connected to a gate of the second erase element; the source of the second floating gate transistor is electrically connected to the drain of the memory cell select transistor; the source of the first floating gate transistor and the drain of the second floating gate transistor are electrically connected; the drain of the first floating gate transistor is connected to a bit line; During a program operation and a read operation for the memory cell, a voltage is applied to the bit line; a voltage applied in the program operation is greater than a voltage applied in the read operation; current values ​​of the first floating gate transistor and the second floating gate transistor in an initial state are smaller than current values ​​of the first floating gate transistor and the second floating gate transistor in an erased state, respectively; a current value for determining whether the memory cell is in an on state or an off state, the current value being smaller than the current value in the initial state;

5. In claim 4, the first erase element includes a first erase gate and a first impurity region formed on the semiconductor substrate; the second erase element includes a second erase gate and a second impurity region formed on the semiconductor substrate; a first impurity region and a second impurity region electrically connected to each other;

6. A plurality of memory cells are formed on a semiconductor substrate, each said memory cell comprises a first floating gate transistor, a second floating gate transistor, a first erase element, a second erase element and a memory cell select transistor; a third floating gate transistor, a fourth floating gate transistor, a fifth floating gate transistor, and a sixth floating gate transistor, and a third erase element; a gate of the first floating gate transistor electrically connected to a gate of the first erase element; a gate of the second floating gate transistor electrically connected to a gate of the second erase element; a gate of the third floating gate transistor electrically connected to a gate of the third erase element; a gate of the fourth floating gate transistor electrically connected to a gate of the first erase element; a gate of the fifth floating gate transistor electrically connected to a gate of the second erase element; a gate of the sixth floating gate transistor electrically connected to a gate of the third erase element; the source of the first floating gate transistor is electrically connected to the drain of the fifth floating gate transistor; the source of the second floating gate transistor is electrically connected to the drain of the sixth floating gate transistor; the source of the third floating gate transistor is electrically connected to the drain of the fourth floating gate transistor; the drain of the first floating gate transistor, the drain of the second floating gate transistor, and the drain of the third floating gate transistor are electrically connected to each other; a source of the fourth floating gate transistor, a source of the fifth floating gate transistor, and a source of the sixth floating gate transistor are electrically connected to the drain of the memory cell select transistor.

7. In claim 6, the first erase element includes a first erase gate and a first impurity region formed on the semiconductor substrate; the second erase element includes a second erase gate and a second impurity region formed on the semiconductor substrate; the third erase element includes a third erase gate and a third impurity region formed on the semiconductor substrate; a first impurity region, a second impurity region, and a third impurity region, the first impurity region, and the third impurity region being electrically connected to each other;

8. In claim 1, a determining current value for determining whether the memory cell is in an on state or an off state, the determining current value exceeding half of the total current value when the first floating gate transistor and the second floating gate transistor are both in an initial state;

9. In claim 1, A semiconductor memory device characterized in that a determination current value for determining whether the memory cell is in an on state or an off state is less than half of the total current value when the first floating gate transistor and the second floating gate transistor are both in an erased state.

10. In claim 5, a determining current value for determining whether the memory cell is in an on state or an off state, the determining current value being smaller than the total current value when the first floating gate transistor and the second floating gate transistor are both in an initial state;

11. In claim 5, a determination current value for determining whether the memory cell is in an on state or an off state, the determination current value being greater than the total current value when the first floating gate transistor and the second floating gate transistor are both in a programmed state.

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