Semiconductor drive device and power conversion device

Abstract

The semiconductor drive device (10) includes a gate drive unit (11) that drives a semiconductor switching element (50) and an overcurrent protection unit (12), and the overcurrent protection unit (12) includes an overcurrent determination unit (13) that receives a detection signal and determines an overcurrent, a gate voltage reduction unit (14) that reduces the voltage applied to the gate when the overcurrent is determined, and an off-gate current adjustment unit (18) that reduces the off-gate current when the overcurrent is determined. When an overcurrent is detected in the semiconductor switching element (50), the gate voltage is reduced and the off-gate current during the off operation of the semiconductor switching element is reduced, resulting in soft shutdown.

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor driving device and a power conversion device. [Background technology]

[0002] Semiconductor switching elements are used in a variety of power conversion devices. The semiconductor driver that controls the on / off of these semiconductor switching elements is equipped with an overcurrent protection circuit that instantly detects and protects the semiconductor switching element from overcurrent caused by an arm short circuit due to a malfunction or failure.

[0003] In an example of a semiconductor driver equipped with an overcurrent protection circuit, when an overcurrent detection unit detects an overcurrent, the gate voltage is clamped to a predetermined value to suppress short-circuit current, and the off-gate resistance is switched to a large value during short-circuit shutdown to softly shut off, reducing surge voltage and preventing damage to semiconductor switching elements due to overvoltage (see, for example, Patent Document 1). However, in a configuration in which the driver, which requires a power supply, and the switching elements are mounted separately, the presence of gate wiring with large parasitic inductance can cause noise superimposed on the wiring, potentially preventing high-speed, high-precision overcurrent detection and protection operations. The overcurrent detection unit and the gate voltage clamping unit in Patent Document 1 also require power supplies.

[0004] In response to this, the applicant has proposed a semiconductor driving device that has an overcurrent detection unit and gate voltage reduction unit that do not require a power supply located in close proximity to the semiconductor switching element, thereby suppressing malfunctions caused by noise resulting from long wiring, and achieving high-speed, high-precision overcurrent detection and prevention of overvoltage breakdown by suppressing short-circuit current (see Patent Document 2). [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2014-82904 [Patent Document 2] International Publication No. 2023 / 032024 Summary of the Invention [Problem to be solved by the invention]

[0006] According to Patent Document 2, by providing an overcurrent detection unit and a gate voltage reduction unit that do not require a power supply in close proximity to a semiconductor switching element, it is possible to perform high-speed and highly accurate overcurrent detection and prevent overvoltage breakdown of the semiconductor switching element.

[0007] On the other hand, when a smoothing capacitor and a snubber capacitor are applied to the main circuit of a power conversion device equipped with a semiconductor drive device having a circuit that reduces the gate voltage when an overcurrent is detected, voltage resonance occurs between the smoothing capacitor and the snubber capacitor when the gate voltage is reduced when an overcurrent is detected, and the problem of overvoltage breakdown of the semiconductor switching element becomes apparent when the current is interrupted. This voltage resonance tends to be particularly large when the parasitic inductance of the gate wiring is large.

[0008] Therefore, even in a power conversion device including the semiconductor driving device according to Patent Document 2, when a smoothing capacitor and a snubber capacitor are applied to a long gate wiring, this problem needs to be solved.

[0009] The present disclosure discloses a technology for solving the above-mentioned problems, and aims to provide a semiconductor driving device that can protect a semiconductor switching element from overcurrent even when the semiconductor switching element and the gate driving unit of the semiconductor driving device are arranged at a distance from each other, and a highly reliable semiconductor driving device that can protect the semiconductor switching element from overvoltage even when a power conversion device equipped with a semiconductor switching element driven by this semiconductor driving device has a smoothing capacitor and a snubber capacitor. [Means for solving the problem]

[0010] The semiconductor driving device according to the present disclosure comprises: a gate driver that applies a voltage to a control terminal of a semiconductor switching element to turn the semiconductor switching element on and off; an overcurrent protection unit for protecting the semiconductor switching element, the overcurrent protection unit having a first overcurrent determination unit that receives a detection signal based on a voltage current between main terminals of the semiconductor switching element and determines an overcurrent flowing through the semiconductor switching element, a gate voltage reduction unit that reduces the voltage applied to the control terminal when the overcurrent is determined, and an off-gate current adjustment unit that adjusts an off-gate current flowing between the gate driver unit and the control terminal when the semiconductor switching element is turned off by the gate driver unit, the first overcurrent determination unit includes a clamp diode that clamps the potential of a signal input unit that is an input unit for the detection signal to the potential of the control terminal, a first transistor to which the signal input unit is connected, and a low-pass filter that is provided in the signal input unit, and when the potential of the signal input unit reaches a set value, the first transistor is turned on to determine an overcurrent in the semiconductor switching element; the off-gate current adjusting unit is the above The voltage applied to the control terminal by the gate voltage reducing unit is From a preset value Reduced rear To, The semiconductor switching element The off-gate current is reduced. [Effects of the Invention]

[0011] According to the present disclosure, it is possible to provide a semiconductor driving device that can drive a semiconductor switching element with high reliability, by protecting the semiconductor switching element from overcurrent and also from overvoltage when the element is turned off. [Brief explanation of the drawings]

[0012] [Figure 1] 1 is a diagram showing a schematic configuration of a semiconductor driving device according to a first embodiment. [Figure 2] 3 is a diagram showing a circuit configuration of an overcurrent protection unit according to the first embodiment. FIG. [Figure 3]3 is a waveform diagram of each part showing the operation of the semiconductor driving device according to the first embodiment. FIG. [Figure 4] 5 is a diagram showing another circuit configuration of the overcurrent protection unit according to the first embodiment. FIG. [Figure 5] 3 is a waveform diagram of each part showing the operation of the semiconductor driving device according to the first embodiment. FIG. [Figure 6] FIG. 10 is a diagram showing a circuit configuration of an overcurrent protection unit according to a second embodiment. [Figure 7] FIG. 10 is a diagram showing a circuit configuration of an overcurrent protection unit according to a third embodiment. [Figure 8] FIG. 10 is a diagram showing a schematic configuration of a semiconductor driving device according to a fourth embodiment. [Figure 9] 10A and 10B are waveform diagrams of various parts illustrating the operation of the semiconductor driving device according to the fourth embodiment. [Figure 10] FIG. 10 is a diagram showing a schematic configuration of a semiconductor driving device according to a fifth embodiment. [Figure 11] 10 is a waveform diagram of each part showing the operation of the semiconductor driving device according to the fifth embodiment. FIG. [Figure 12] FIG. 13 is a diagram showing a schematic configuration of a semiconductor driving device according to a sixth embodiment. [Figure 13] 13 is a waveform diagram of each part showing the operation of the semiconductor driving device according to the sixth embodiment. FIG. [Figure 14] FIG. 13 is a diagram showing a schematic configuration of a semiconductor driving device according to a seventh embodiment. [Figure 15] FIG. 13 is a diagram showing a circuit configuration of an overcurrent protection unit according to a seventh embodiment. [Figure 16] 13 is a waveform diagram of each part showing the operation of the semiconductor driving device according to the seventh embodiment. FIG. [Figure 17] FIG. 13 is a diagram showing a schematic configuration of a semiconductor driving device according to an eighth embodiment. [Figure 18] FIG. 13 is a diagram showing a circuit configuration of an overcurrent protection unit according to an eighth embodiment. [Figure 19] 13 is a waveform diagram of each part showing the operation of the semiconductor driving device according to the eighth embodiment. FIG. [Figure 20] FIG. 13 is a block diagram showing a schematic configuration of a power conversion device according to a ninth embodiment. [Figure 21] FIG. 13 is a diagram showing a schematic configuration of a power conversion device according to a ninth embodiment. [Figure 22] FIG. 20 is a diagram showing a circuit configuration of an overcurrent protection unit according to a ninth embodiment. [Figure 23] 13 is a waveform diagram of each part showing the operation of the power conversion device according to the ninth embodiment. FIG. [Figure 24] FIG. 22 is a diagram showing a schematic configuration of a power conversion device according to a tenth embodiment. [Figure 25] 13 is a waveform diagram of each part showing the operation of the power conversion device according to the tenth embodiment. FIG. [Figure 26] FIG. 22 is a diagram showing a schematic configuration of a power conversion device according to an eleventh embodiment. [Figure 27] 13 is a waveform diagram of each part showing the operation of the power conversion device according to the eleventh embodiment. FIG. [Figure 28] FIG. 23 is a diagram showing a schematic configuration of a power conversion device according to a twelfth embodiment. [Figure 29] 23 is a waveform diagram of each part showing the operation of the power conversion device according to the twelfth embodiment. FIG. [Figure 30] FIG. 23 is a diagram showing a schematic configuration of a power conversion device according to a thirteenth embodiment. [Figure 31] 23 is a waveform diagram of each part showing the operation of the power conversion device according to the thirteenth embodiment. FIG. [Figure 32] FIG. 23 is a diagram showing a schematic configuration of a power conversion device according to a fourteenth embodiment. [Figure 33] 23 is a waveform diagram of each part showing the operation of the power conversion device according to the fourteenth embodiment. FIG. [Figure 34] FIG. 23 is a block diagram showing a schematic configuration of a power conversion device according to a fifteenth embodiment. [Figure 35] FIG. 23 is a diagram showing a schematic configuration of a power conversion device according to a fifteenth embodiment. [Figure 36] 23 is a waveform diagram of each part showing the operation of the power conversion device according to the fifteenth embodiment. FIG. [Figure 37] FIG. 23 is a diagram illustrating a configuration of a power conversion device according to a sixteenth embodiment. [Figure 38] FIG. 23 is a diagram illustrating another configuration of a power conversion device according to the sixteenth embodiment. [Figure 39] FIG. 23 is a diagram illustrating still another configuration of the power conversion device according to the sixteenth embodiment. [Figure 40] FIG. 10 is a diagram showing a schematic configuration of a power conversion device using another semiconductor switching element. [Figure 41] FIG. 10 is a diagram showing a schematic configuration of a power conversion device using another semiconductor switching element. [Figure 42] FIG. 2 is a diagram showing the hardware configuration of a control unit according to the first to sixteenth embodiments. DETAILED DESCRIPTION OF THE INVENTION

[0013] The present embodiment will be described below with reference to the drawings, in which the same reference numerals indicate the same or corresponding parts.

[0014] Embodiment 1 FIG. 1 is a diagram showing a schematic configuration of a semiconductor driving device according to the first embodiment. The semiconductor driving device 10 controls the conductive / non-conductive state between the collector C and emitter E, which are the main terminals of the semiconductor switching element 50, by a gate voltage Vge applied between a control terminal (hereinafter, gate terminal) G and a reference terminal (hereinafter, emitter control terminal) ES. In this case, an IGBT (Insulated Gate Bipolar Transistor) is shown as an example of the semiconductor switching element 50, but the present invention can also be applied to other semiconductor switching elements such as a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) having a control terminal.

[0015] 1, the semiconductor driver 10 includes a gate driver 11 and an overcurrent protection unit 12. The overcurrent protection unit 12 is disposed immediately adjacent to or immediately above the semiconductor switching element 50, and the gate driver 11 and the overcurrent protection unit 12 are connected by a two-wire connection wiring 15. The gate driver 11 includes an output stage circuit configured with a positive power supply PG1, a negative power supply PG2, a P-type MOSFET MG1, an N-type MOSFET MG2, and gate resistors RG1 and RG2, a control unit 16 that controls this output stage circuit, and a protection operation detection unit 19. The emitter control terminal ES of the semiconductor switching element 50 is connected to a reference potential VG0 at the connection point between the positive power supply PG1 and the negative power supply PG2.

[0016] The control unit 16 receives a command signal SIN transmitted from a higher-level control device (not shown), and controls the output stage circuit based on a signal GSD from a protection operation detection unit 19. The control unit 16 may control the output stage circuit by logically combining the signal GSD with various abnormality detection signals such as over-temperature or power supply drop. The operation of the protection operation detection unit 19 will be described later.

[0017] Also, in this case, an example is shown in which the output stage circuit outputs a positive power supply potential VG1 or a negative power supply potential VG2, but a configuration without using a negative power supply PG2, i.e., a configuration in which the negative power supply potential VG2 is equal to the reference potential VG0, is also possible. Also, in this case, constant voltage drive is shown in which a P-type MOSFET MG1 and an N-type MOSFET MG2 are used as the output stage buffer of the gate driver 11, and the switching speed is adjusted by gate resistors RG1 and RG2, but the present invention is not limited to this.

[0018] The overcurrent protection unit 12 includes a first overcurrent determination unit 13 that determines an overcurrent flowing through the semiconductor switching element 50, a gate voltage reduction unit 14 that reduces the voltage applied to the gate terminal G of the semiconductor switching element 50 when an overcurrent is determined, and an off-gate current adjustment unit 18 that reduces the off-gate current of the semiconductor switching element 50. The first overcurrent determination unit 13 includes a first transistor Q1, a clamp diode D1, and a low-pass filter (R, C1) made up of a resistor R and a capacitor C1. A detection signal SOC based on a collector voltage Vce, which is the voltage between the main terminals of the semiconductor switching element 50, is input to the first transistor Q1 via the low-pass filter (R, C1), and an overcurrent determination signal OCD is output.

[0019] In this case, when the first transistor Q1 is turned on, the determination signal OCD changes, and an overcurrent in the semiconductor switching element 50 is determined. The gate voltage reducing unit 14 receives the overcurrent determination signal OCD and operates to reduce the gate voltage Vge applied to the gate terminal G to a level lower than the voltage (VG1) of the positive power supply PG1. At this time, the gate driving unit 11 uses the protection operation detecting unit 19 to detect that the gate voltage reducing unit 14 has reduced the gate voltage Vge, and generates a signal GSD serving as a protection operation detection signal and transmits it to the control unit 16.

[0020] When the first overcurrent determination unit 13 determines that the semiconductor switching element 50 has an overcurrent, the off-gate current adjustment unit 18 turns off the transistor Qg1, and when the gate drive unit 11 turns off the semiconductor switching element 50, the off-gate current flows through the resistor RG3, thereby reducing the off-gate current and performing a soft shutdown of the semiconductor switching element 50.

[0021] When the control unit 16 receives the signal GSD, it keeps the semiconductor switching element 50 in the off state for a predetermined period regardless of the state of the command signal SIN. The method by which the protection operation detection unit 19 detects the protection operation of the gate voltage reduction unit 14 can be realized by a known technique, such as by detecting that the output potential or output current of the gate drive unit 11 (output stage circuit) has fallen below a set value for a predetermined period, and therefore a detailed explanation will be omitted.

[0022] In this case, the detection signal SOC input to the first overcurrent determining unit 13 is the voltage at the collector sense terminal CS (collector voltage Vce). The parasitic inductance Lc between the collector C and the collector sense terminal CS, and the parasitic inductance Le between the emitter E and the emitter control terminal ES are shown.

[0023] The emitter control terminal ES and collector sense terminal CS are usually formed close to the main element so that the parasitic inductance L present on the main element side is minimized. This eliminates the effects of the electromotive force (L·dI / dt) caused by the parasitic inductance L. Semiconductor switching elements 50 used in large-capacity power modules and the like are usually provided with an emitter control terminal ES to prevent a drop in gate voltage Vge due to the electromotive force (L·dI / dt). When detecting the collector voltage Vce, a collector sense terminal CS is provided to detect the collector voltage Vce while preventing the addition of extra voltage due to the electromotive force (L·dI / dt).

[0024] In this embodiment, the case where the emitter control terminal ES and the collector sense terminal CS are provided is shown, but it is also possible to use the emitter E and collector C, which are the main terminals used by the semiconductor switching element 50 to connect to external elements, without providing the emitter control terminal ES and the collector sense terminal CS. The collector voltage Vce in this embodiment is slightly different from the actual voltage between the main terminals (collector C, emitter E), but is the voltage between the main terminals (Vce) used for control.

[0025] FIG. 2 is a circuit configuration diagram showing details of the overcurrent protection unit 12 of the semiconductor driving device according to the first embodiment. 2, the overcurrent protection unit 12 includes a first overcurrent determination unit 13 that receives the detection signal SOC and outputs an overcurrent determination signal OCD, a gate voltage reduction unit 14 that reduces the gate voltage Vge based on the determination signal OCD, and an off-gate current adjustment unit 18 that reduces the off-gate current when an overcurrent is detected in the semiconductor switching element 50. The gate voltage reduction unit 14 also includes a drive circuit 141 that reduces the gate voltage Vge, and an amplifier circuit 142 that amplifies the output signal from the first overcurrent determination unit 13 to drive the drive circuit 141.

[0026] The first overcurrent determination unit 13 includes resistors R1, R2, R3, and R4 connected in series, a clamp diode D1, and a capacitor C1. It also includes a series circuit in which a first transistor Q1, which is an NPN bipolar transistor, resistors R5 and R6, and a reverse current prevention diode D3 are connected in series. A capacitor C2 is connected in parallel with the resistor R6, and a protection diode D2 is provided between the base and emitter of the first transistor Q1. In this case, the resistor R (R1, R2, R3) and capacitor C1 form a low-pass filter (R, C1). The connection point P1 between the resistor R (R1, R2, R3) and resistor R4 serves as the input for the detection signal SOC and is connected to the base of the first transistor Q1. The potential of the connection point P1, which is the base potential of the first transistor Q1 relative to the emitter control terminal ES, is defined as the input potential VA1.

[0027] The clamp diode D1 has an anode connected to the capacitor C1 of the low-pass filter (R, C1), and a junction thereof connected to the junction P1 and the base of the first transistor Q1. The detection signal SOC is divided by resistors R1 to R4 and input to the base of the first transistor Q1 via a low-pass filter (R, C1) consisting of the voltage-dividing resistors R (R1, R2, R3) and a capacitor C1. The base of the first transistor Q1 is clamped to the negative power supply potential VG2 by a clamp diode D1 when the semiconductor switching element 50 is in the off state. Although the clamp diode D1 is shown as being connected to the output side of the low-pass filter (R, C1) by way of example, it may be connected to the input side of the low-pass filter (R, C1).

[0028] In this case, when the semiconductor switching element 50 is turned off, the gate driver 11 negatively biases the gate voltage Vge, so that the base potential and collector potential of the first transistor Q1 are also negatively biased. For this reason, a protection diode D2 and a backflow prevention diode D3 are provided to protect the first transistor Q1. The protective diode D2 is an anti-parallel diode that is normally used in bipolar transistors, and prevents a large negative voltage from being applied between the base and emitter of the first transistor Q1, which would otherwise deteriorate the characteristics of the first transistor Q1.

[0029] The blocking diode D3 protects the first transistor Q1 by preventing current from flowing backward in the current-carrying direction of the first transistor Q1. In this case, when the first transistor Q1 is in the off state, a negative voltage is applied to the gate terminal G, preventing reverse bias between the collector and emitter of the first transistor Q1 and protecting it. Furthermore, the backflow prevention diode D3 is provided on the emitter side of the first transistor Q1, and the base potential (input potential VA1) of the first transistor Q1 relative to the emitter control terminal ES can raise the voltage level required to turn on the first transistor Q1, thereby improving resistance to voltage-related noise. The backflow prevention diode D3 may be provided on the collector side of the first transistor Q1.

[0030] The base and emitter of a bipolar transistor are PN junctions, just like a diode. For simplicity's sake, the base threshold voltage, which is the voltage between the base and emitter required to turn on a bipolar transistor, and the forward voltage of the diode are both defined as Vf. In this case, the first transistor Q1 turns on to detect an overcurrent. When the first transistor Q1 turns on, the base potential (input potential VA1) is expressed by the following equation (1). VA1=Vce×R4 / (R1+R2+R3+R4)=2Vf ···(1)

[0031] When the semiconductor switching element 50 is turned off, the base potential (input potential VA1) of the first transistor Q1 is instantly negatively biased by the action of the clamp diode D1. This makes it possible to prevent erroneous detection of an overcurrent due to an increase in the collector voltage Vce when the semiconductor switching element 50 is turned off. Furthermore, by negatively biasing the initial state of the capacitor C1 in the low-pass filter (R, C1), it is possible to prevent erroneous detection of an overcurrent during the period until the collector voltage Vce drops when the semiconductor switching element 50 is turned on.

[0032] Next, the amplifier circuit 142 in the gate voltage reduction unit 14 amplifies the determination signal OCD from the first overcurrent determination unit 13, and includes a series circuit in which a second transistor Q2, which is a PNP bipolar transistor, is connected in series with resistors R7 and R8. A capacitor C3 is connected in parallel with the resistor R8, and a protective diode D4 is provided between the base and emitter of the second transistor Q2. The voltage of the determination signal OCD is applied to the base of the second transistor Q2. The drive circuit 141 in the gate voltage reduction unit 14 is a circuit that amplifies the output signal from the first overcurrent determination unit 13, and includes a series circuit in which a third transistor Q3 made of an NPN bipolar transistor, a resistor R10, and a diode D6 are connected in series. In addition, a resistor R9 is provided between this series circuit and the base of the second transistor Q2, and a protective diode D5 is provided between the base and emitter of the third transistor Q3.

[0033] When the first transistor Q1 turns on and determines that the semiconductor switching element 50 is in an overcurrent state, the second transistor Q2 turns on, and then the third transistor Q3 turns on. Specifically, the operation is as follows. When the semiconductor switching element 50 is in a normal on-state, the first transistor Q1 is off, and therefore the potential of the determination signal OCD, i.e., the base potential of the second transistor Q2, is the same as the gate potential (positive power supply potential VG1) of the semiconductor switching element 50. When an overcurrent occurs and the first transistor Q1 is turned on, the potential of the determination signal OCD drops, and when it drops to a potential (VG1-Vf) that is lower than the positive power supply potential VG1 by the threshold voltage Vf of the second transistor Q2, the second transistor Q2 is turned on.

[0034] The resistors R5 and R6 connected in series to the first transistor Q1 are set in advance to satisfy the following formula. (VG1-Vf)×R6 / (R5+R6)>Vf

[0035] When the second transistor Q2 turns on, the collector potential of the second transistor Q2 rises to the positive power supply potential VG1, which causes the base potential of the third transistor Q3 to rise, applying a voltage equal to or greater than the threshold voltage Vf to the base of the third transistor Q3 and turning on the third transistor Q3.

[0036] The resistors R7 and R8 connected in series to the second transistor Q2 are set in advance to satisfy the following formula. VG1×R8 / (R7+R8)>Vf

[0037] In this way, the first transistor Q1, the second transistor Q2, and the third transistor Q3 are sequentially turned on. The gate charge accumulated in the capacitance between the gate and emitter of the semiconductor switching element 50 is discharged, causing a gate discharge current IA to flow through the third transistor Q3, reducing the gate voltage Vge. This makes it possible to suppress overcurrent in the semiconductor switching element 50.

[0038] In the semiconductor switching element 50, the gate input capacitance increases as the current capacity increases. Therefore, in order to reduce the gate voltage Vge of the semiconductor switching element 50 with a large current capacity and protect it from overcurrent, it is necessary to discharge a large amount of gate charge. For example, for a semiconductor switching element 50 with a current capacity of several hundred amperes, it is necessary to flow a gate discharge current IA of several amperes.

[0039] The base current of the first transistor Q1 is determined by the constraint of minimizing the parasitic leakage current, i.e., heat generation, while the semiconductor switching element 50 is off, and therefore the magnitude of the collector current of the first transistor Q1 is also limited. The base current of the first transistor Q1, which becomes the parasitic leakage current, is approximately 1 mA. Furthermore, taking into account the temperature and frequency characteristics, the current amplification factor of the first transistor Q1 and the third transistor Q3 is, for example, approximately 30. If two-stage current amplification were performed without the amplifier circuit 142, only a gate discharge current IA of approximately 1 A or less would be able to flow. In this case, the first transistor Q1, the second transistor Q2, and the third transistor Q3 are turned on in sequence to increase the base current, and a three-stage current amplification is used to achieve a large gate charge discharge in a short time. The three-stage current amplification can handle a gate discharge current IA of up to several tens of amperes, for example.

[0040] It should be noted that the drive circuit 141 in the gate voltage reducing unit 14 can operate even without the amplifier circuit 142, and therefore can be omitted as necessary.

[0041] Generally, when the third transistor Q3 turns on and the gate voltage Vge decreases, this operation causes the overcurrent detection signal SOC to approach a state where there is no overcurrent, the operation of reducing the gate voltage Vge is canceled, and the state becomes an overcurrent again, and an oscillation operation in which this is repeated may occur. In this embodiment, resistor R9 is provided to provide deep hysteresis to the overcurrent determination operation, thereby preventing the above-mentioned oscillation. That is, when the third transistor Q3 is turned on, the base potential of the second transistor Q2 is lowered by the action of resistor R9, and the overcurrent determination operation is maintained for a predetermined time. As a result, the gate voltage reducer 14 continues to reduce the gate voltage Vge for the predetermined time.

[0042] The value of resistor R10, which determines the gate discharge current IA that flows during overcurrent protection operation, must be designed to prevent a surge voltage that occurs when the gate voltage Vge of the semiconductor switching element 50 suddenly drops to a value equal to or lower than the gate threshold voltage Vth, and is set to satisfy, for example, the following equation (2): (VG1-VG0)×R10 / (RG1+R10)>Vth...(2)

[0043] In addition, since the semiconductor switching element 50 generally has an internal gate resistor, in practice, even if the above formula (2) is not satisfied, the gate voltage inside the semiconductor switching element 50 will remain higher than the gate threshold voltage Vth as long as the period during which the gate voltage Vge is reduced is short. Therefore, the surge voltage may not be a problem.

[0044] On the other hand, when the protection operation detection unit 19 detects the protection operation and the control unit 16 turns off the semiconductor switching element 50, if the gate voltage Vge after being reduced by the protection operation is too large, a sudden current interruption may occur, causing a concern that the semiconductor switching element 50 may be degraded by a surge voltage. For this reason, it is desirable to adjust the value of the resistor R10 so that the surge voltage Vsa generated in the collector voltage Vce during the protection operation and the surge voltage Vsb generated in the collector voltage Vce when the semiconductor switching element 50 is subsequently turned off are approximately the same.

[0045] Next, in the off-gate current adjusting unit 18, a parallel circuit in which a diode Dg4 and a resistor RG3 are connected in parallel is connected within the connecting wiring 15 connected to the gate terminal G of the semiconductor switching element 50, and a series circuit in which a transistor Qg1 consisting of a PNP bipolar transistor and a backflow prevention diode Dg2 are connected in series is connected in parallel to this parallel circuit. A series circuit formed by connecting transistor Qg1 and blocking diode Dg2 in series is connected in parallel to a series circuit formed by connecting resistors R11 and R12 in series, and the base of transistor Qg1 is connected to the midpoint of resistors R11 and R12, blocking diode Dg1, and the collector of second transistor Q2. Furthermore, a protection diode Dg3 is connected between the base and emitter of transistor Qg1.

[0046] When the semiconductor switching element 50 is in a normal on state (the P-type MOSFET MG1 of the gate driver 11 is on and the N-type MOSFET MG2 is off), an on-gate current flows to the gate terminal G mainly via the diode Dg4. When the semiconductor switching element 50 is in a normal on state, as described above, the base potential of the second transistor Q2 is the same as the gate potential of the semiconductor switching element 50, so the second transistor Q2 is off. Therefore, the base potential of the transistor Qg1 is at the emitter level, and the backflow prevention diode Dg1 prevents a signal from entering the base of the transistor Qg1.

[0047] Furthermore, when the semiconductor switching element 50 is turned off (the P-type MOSFET MG1 of the gate driver 11 is turned off and the N-type MOSFET MG2 is turned on), the gate driver 11 negatively biases the gate voltage Vge, causing the wiring of the gate terminal G to drop from a positive potential to a negative potential. Therefore, the negative voltage is divided by resistors R11 and R12, and the divided voltage is applied to the base of the transistor Qg1. This voltage is designed in advance to exceed the threshold voltage Vf of the transistor Qg1, turning the transistor Qg1 on. This causes an off-gate current to flow from the gate terminal G of the semiconductor switching element 50 through the diode Dg2 and the transistor Qg1. In normal operation, the transistor Qg1 should be in an on state when the off-gate voltage is high and switching is turned off.

[0048] When an overcurrent in the semiconductor switching element 50 is detected, the first transistor Q1 and the second transistor Q2 turn on. When the second transistor Q2 turns on, the collector potential of the second transistor Q2 rises to the positive power supply potential VG1, and the base potential of the transistor Qg1 drops to a potential (VG1-Vf) that is the power supply potential VG1 minus the forward voltage of the diode Dg1. Meanwhile, the emitter of the transistor Qg1 reaches a potential that is the forward voltage of the diode Dg2, and a reverse bias of Vf is applied to the base of the transistor Qg1, turning the transistor Qg1 off.

[0049] That is, when an overcurrent of the semiconductor switching element 50 is detected in the parallel circuit of the resistor RG3 and the transistor Qg1 in the off-gate current adjusting unit 18, the transistor Qg1 turns off and the off-gate current flows through the resistor RG3. As a result, even if a power conversion device including the semiconductor switching element 50 driven by this semiconductor driving device 10 has a smoothing capacitor and a snubber capacitor, an overcurrent of the semiconductor switching element 50 is detected and the off-gate current is reduced when the semiconductor switching element 50 is turned off, thereby suppressing voltage resonance between the smoothing capacitor and the snubber capacitor.

[0050] This switching to resistor RG3 by off-gate current adjuster 18 corresponds to a function of increasing the gate resistance when semiconductor switching element 50 is turned off by control unit 16 compared to normal off-state after protection operation detector 19 detects protection operation, a so-called soft shutdown function. However, in this embodiment, off-gate current adjuster 18 can increase the gate resistance more quickly than conventional methods when an overcurrent in semiconductor switching element 50 is detected.

[0051] Furthermore, when an overcurrent in the semiconductor switching element 50 is detected, the gate voltage reducing unit 14 turns on the third transistor Q3 to protect the semiconductor switching element 50. At this time, the charge accumulated in the capacitance between the gate and emitter is discharged, and a gate discharge current IA flows from the gate terminal G to the gate voltage reducing unit 14. However, in the path from the gate terminal G to the gate voltage reducing unit 14, the transistor Qg1 of the off gate current adjusting unit 18 is turned off, so the current flows via resistor RG3. The resistance value of resistor RG3 will be described later.

[0052] The backflow prevention diode Dg1 connected to the base of the transistor Qg1 is provided to prevent the transistor Qg1 from malfunctioning. The protective diode Dg3 connected between the base and emitter of transistor Qg1 is an anti-parallel diode typically used in bipolar transistors, and prevents a large positive voltage from being applied between the base and emitter of transistor Qg1, which would cause the characteristics to deteriorate.

[0053] The blocking diode Dg2 connected to the emitter of transistor Qg1 protects transistor Qg1 by preventing current from flowing backward in the direction of current flow through transistor Qg1. The blocking diode Dg2 is also connected to the emitter of transistor Qg1, and this increases the base potential of transistor Qg1 relative to the emitter, thereby raising the voltage level required to turn on transistor Qg1. In particular, the blocking diode Dg1 is connected to the base of transistor Qg1, preventing the forward voltage of this blocking diode Dg1 from causing transistor Qg1 to lose on / off control.

[0054] FIG. 3 is a waveform diagram of each part showing the operation of the semiconductor driving device according to the first embodiment. The overcurrent protection operation of the semiconductor driving device 10 will be described in detail below with reference to FIGS. During normal operation before time t1, the gate voltage Vge is output in response to a command signal SIN sent from the higher-level control device, and the collector current Ic of the semiconductor switching element 50 and the collector voltage Vce, which serves as the detection signal SOC, also have waveforms that correspond to the command signal SIN. When the semiconductor switching element 50 is in the off state, the base potential (input potential) VA1 of the first transistor Q1, relative to the emitter control terminal ES, is clamped to a potential (VG2+Vf) obtained by adding the forward voltage Vf of the clamp diode D1 to the negative power supply potential VG2. When the semiconductor switching element 50 is in the on state, the collector voltage Vce drops to several volts, and the voltage VA1 divided by the resistors R (R1, R2, R3) and R4 becomes close to the reference potential VG0.

[0055] The potential of the determination signal OCD, that is, the base potential of the second transistor Q2, is the same as the gate potential (positive power supply potential VG1) when the semiconductor switching element 50 is in the ON state, and is pulled down to the negative power supply potential VG2 when the semiconductor switching element 50 is in the OFF state.

[0056] Under normal circumstances, when semiconductor switching element 50 is on, the resistance of resistor RG3 is sufficiently large, so that the on-gate current flows mainly via diode Dg4, and when semiconductor switching element 50 is off, the off-gate current flows via transistor Qg1, so that the resistance value R_OFFGI of off-gate current adjustment unit 18 is small. Note that transistor Qg1 of normal-state off-gate current adjustment unit 18 is on when semiconductor switching element 50 is off, and is on or off depending on the base potential of transistor Qg1 when semiconductor switching element 50 is on. Therefore, in Figure 3, during normal circumstances before time t1, when semiconductor switching element 50 is on, transistor Qg1 is shown by a dotted line as being on.

[0057] At time t1, after the semiconductor switching element 50 is turned on, if an overcurrent occurs due to an arm short circuit with another connected arm, the peak value Icp of the collector current Ic saturates, and the collector voltage Vce, which normally decreases, becomes high, causing the base potential (input potential) VA1 of the first transistor Q1 to rise above the reference potential VG0.

[0058] At time t2, the base potential (input potential) VA1 of the first transistor Q1 rises to 2Vf, i.e., when the above formula (1) is satisfied, the first transistor Q1 turns on. This detects an overcurrent in the semiconductor switching element 50. When the first transistor Q1 turns on, the potential of the determination signal OCD drops. When it drops from the positive power supply potential VG1 to a potential (VG1-Vf) that is lower by the threshold voltage Vf of the second transistor Q2, the second transistor Q2 turns on. This also increases the base potential of the third transistor Q3, applying a voltage equal to or greater than the threshold voltage Vf to the base and turning on the third transistor Q3. This causes a gate discharge current IA to flow, reducing the gate voltage Vge. At this time, the collector current Ic decreases to a value Ica corresponding to the reduced gate voltage Vge, and a surge voltage Vsa occurs in the collector voltage Vce.

[0059] Furthermore, when the second transistor Q2 turns on, the collector potential of the second transistor Q2 rises to the positive power supply potential VG1, and the base potential of the transistor Qg1 drops from the positive power supply potential VG1 to a potential (VG1 - Vf) that is a drop of the forward voltage of the diode Dg1. Meanwhile, the emitter of the transistor Qg1 drops to a potential that is a drop of the forward voltage of the diode Dg2, and the base of the transistor Qg1 is reverse-biased by Vf, turning the transistor Qg1 off. Therefore, the resistance value R_OFFGI of the off-gate current adjustment unit 18 increases (RG3).

[0060] At time t3, the protection operation detector 19 detects a drop in the gate voltage Vge and generates a signal GSD. Between time t3 and time t4, the control unit 16 performs a current interruption operation on the semiconductor switching element 50, turning it off. At this time, a surge voltage Vsb occurs in the collector voltage Vce. As described above, it is desirable to set the resistor R10 to satisfy the above formula (2) so that the surge voltage Vsb is approximately the same as the preceding surge voltage Vsa. Furthermore, when the control unit 16 turns off the semiconductor switching element 50, the off-gate current flows through the resistor RG3 of the off-gate current adjusting unit 18, so that the off-gate current is reduced compared to normal times, and soft cutoff is performed.

[0061] At time t5, after the delay time Tf has elapsed since the generation of the signal GSD, the command signal SIN from the higher-level control device is maintained in the OFF state, and the abnormality signal FAIL is generated.

[0062] Next, the magnitude of the resistance value of the resistor RG3 provided in the off-gate current adjusting section 18 will be described. When an overcurrent in the semiconductor switching element 50 is detected, the first transistor Q1, the second transistor Q2, and the third transistor Q3 are turned on, causing the gate discharge current IA drawn from the gate terminal G to flow to the gate voltage reducing unit 14, thereby reducing the gate voltage. This reduces the short-circuit current and protects the semiconductor switching element 50. Furthermore, the transistor Qg1 of the off-gate current adjusting unit 18 is turned off, thereby reducing the off-gate current when the semiconductor switching element 50 is off, thereby performing soft shutdown and suppressing surge voltage.

[0063] To reliably perform these operations, the resistance of resistor RG3 used to perform soft shutdown must be greater than that of resistor R10, which is used to pass gate discharge current IA through gate voltage reduction unit 14. In other words, the relationship RG3 > R10 must be satisfied. By making the resistance of resistor R10 smaller than that of resistor RG3, the gate voltage is sufficiently reduced to suppress short-circuit current, and when semiconductor switching element 50 is turned off, the off-gate current is suppressed by resistor RG3, which has a large resistance, thereby suppressing surge voltage and ensuring soft shutdown. When an overcurrent is detected, the route for flowing the gate discharge current IA drawn from the gate terminal G to the gate voltage reduction unit 14 also passes through the resistor RG3. However, since the resistance value of the resistor R10 is smaller than that of the resistor RG3, the gate voltage can be reduced by sufficiently flowing the gate discharge current IA.

[0064] Also, the resistance value of the resistor R10 needs to be larger than the resistance value of the gate resistor RG1 of the gate drive unit 11. The gate resistor RG1 is an on-gate resistor that limits the on-gate current. When an overcurrent of the semiconductor switching element 50 is detected, the P-type MOSFET MG1 of the gate drive unit 11 is on and the N-type MOSFET MG2 is off, so an on-gate current is flowing. However, the gate discharge current IA flows and the gate voltage Vge is reduced. At that time, the collector current Ic decreases to a value Ica corresponding to the reduced gate voltage Vge, and a surge voltage Vsa is generated in the collector voltage Vce accordingly. At this time, if the resistance value of the resistor R10 is too small, the surge voltage Vsa will become large. Therefore, by satisfying the above formula (2) and RG1 < R10, the surge voltage Vsa can be suppressed.

[0065] As described above, in this embodiment, the semiconductor drive device 10 includes an overcurrent protection unit 12 having a first overcurrent determination unit 13 that determines an overcurrent flowing through the semiconductor switching element 50, and a gate voltage reduction unit 14 that reduces the gate voltage Vge when an overcurrent is determined. The first overcurrent determination unit 13 includes a clamp diode D1 that clamps the potential (input potential) VA1 of the signal input unit (connection point P1) of the detection signal SOC to the gate potential, a first transistor Q1 to which the signal input unit is connected, and a low-pass filter (R, C1) provided in the signal input unit. When the input potential VA1 reaches the set value 2Vf, the first transistor Q1 turns on to determine the overcurrent of the semiconductor switching element 50.

[0066] As a result, the overcurrent protection unit 12 does not require a power supply for itself, but can use the threshold voltage of the first transistor Q1 to detect and protect the semiconductor switching element 50 from an overcurrent. In addition, the clamp diode D1 and the low-pass filter (R, C1) function to suppress malfunctions caused by noise and perform overcurrent protection. As a result, even when the semiconductor switching element 50 and the gate drive unit 11 of the semiconductor drive device 10 are placed apart, the overcurrent protection unit 12, which does not require a power supply, can be placed close to the semiconductor switching element 50, thereby providing highly reliable overcurrent protection.

[0067] Furthermore, the off-gate current adjusting unit 18 adjusts the resistance to suppress the off-gate current when the semiconductor switching element 50 is turned off when an overcurrent is detected, thereby suppressing surge voltage and enabling soft shutdown. In particular, even when the semiconductor switching element 50 and the gate driving unit 11 of the semiconductor driving device 10 are disposed apart, a highly reliable semiconductor driving device can be provided that can protect the semiconductor switching element 50 from overcurrent. Furthermore, even when a power conversion device including the semiconductor switching element 50 driven by the semiconductor driving device 10 has a smoothing capacitor and a snubber capacitor, the off-gate current when the semiconductor switching element 50 is turned off is suppressed when an overcurrent is detected, thereby enabling soft shutdown to suppress voltage resonance, thereby enabling a highly reliable power conversion device to be provided.

[0068] The functions of the clamp diode D1 and the low-pass filter (R, C1) will be explained below. When the collector voltage Vce is used as the detection signal SOC as in this embodiment, if the timing at which the collector voltage Vce changes due to switching exceeds the design range, or if the voltage amplitude of the collector voltage Vce exceeds the design range, an erroneous detection of an overcurrent may occur.

[0069] For example, the former occurs when the drop in collector voltage Vce is delayed due to the influence of noise or the like during the turn-on operation of semiconductor switching element 50. In this case, the gate voltage Vge rises, causing the clamp diode D1 to not clamp the input potential VA1, resulting in a phenomenon in which the delayed drop in collector voltage Vce, i.e., a normal turn-on operation, is erroneously determined to be an overcurrent. On the other hand, an example of the latter is when electric field coupling or magnetic coupling noise is superimposed during the turn-off or recovery of the semiconductor switching element 50. When the clamp diode D1 clamps the input potential VA1, voltage or current changes at the main terminal of the semiconductor switching element 50 can cause noise equal to or greater than the threshold voltage to be superimposed on the input potential VA1, i.e., on the base of the first transistor Q1. In this case, a normal turn-off or recovery of the semiconductor switching element 50 is erroneously determined to be an overcurrent.

[0070] In this embodiment, a clamp diode D1 that clamps the input potential VA1 to the gate potential is provided, thereby preventing erroneous detection of an overcurrent due to noise when the semiconductor switching element 50 is in the off state. Furthermore, by providing the clamp diode D1 and a low-pass filter (R, C1), the above-mentioned erroneous detection of an overcurrent can also be suppressed.

[0071] For example, the problem of false detection during the ON operation of the semiconductor switching element 50 can be improved as follows: During the delay period from when the clamp diode D1 no longer clamps the input potential VA1 until the collector voltage Vce actually drops, false detection of an overcurrent can be prevented by using a low-pass filter (R, C1). Furthermore, when the gate potential is negatively biased while the semiconductor switching element 50 is in the off state, the capacitor C1 for the low-pass filter (R, C1) is also negatively biased via the clamp diode D1. This increases both the voltage margin and charge margin that could lead to erroneous detection of an overcurrent, and improves electric field coupling or magnetic coupling noise resistance during the off operation or recovery of the semiconductor switching element 50.

[0072] In addition, this embodiment is configured to include a backflow prevention diode D3 that blocks current flowing backward in the conduction direction of the first transistor Q1, protecting the first transistor Q1 and applying a large negative bias (VG2+Vf) to the capacitor C1 without being affected by the protection diode D2, thereby improving the noise resistance of the first transistor Q1 and suppressing erroneous detection of overcurrent. Furthermore, an NPN bipolar transistor is used for the first transistor Q1, and a signal based on the input potential VA1 used for determination is input to the base, which provides current amplification, so that the first transistor Q1 can be operated effectively with a small signal input.

[0073] Although the transistor Qg1 of the off-gate current adjusting section 18 is a PNP bipolar transistor in the above example, it may be an NPN bipolar transistor. Fig. 4 is a circuit configuration diagram different from Fig. 2, showing details of the overcurrent protection unit 12 of the semiconductor driving device according to embodiment 1. The configuration of the off-gate current adjustment unit 18A is different from that of Fig. 2, but other configurations are similar, so the following description will focus on the differences from Fig. 2.

[0074] Next, in the off-gate current adjustment unit 18A, a parallel circuit in which a diode Dg4 and a resistor RG3 are connected in parallel is connected within the connection wiring 15 that is connected to the gate terminal G of the semiconductor switching element 50, and a series circuit in which a transistor Qg1 consisting of an NPN bipolar transistor, a backflow prevention diode Dg2, and a backflow prevention diode Dg5 are connected in series is connected in parallel to this parallel circuit. A series circuit of resistors R11 and R12 is connected in parallel to the series circuit of transistor Qg1 and blocking diode Dg2, and the base of transistor Qg1 is connected to the midpoint of resistors R11 and R12, blocking diode Dg1, and resistor R9. Furthermore, a protection diode Dg3 is connected between the base and emitter of transistor Qg1.

[0075] When the semiconductor switching element 50 is in a normal on state, gate current flows to the gate terminal G mainly via the diode Dg4. When the semiconductor switching element 50 is in a normal on state, as described above, the base potential of the second transistor Q2 is the same as the gate potential of the semiconductor switching element 50, so the second transistor Q2 is off and the third transistor Q3 is also off. Therefore, the base potential of the transistor Qg1 is at the emitter level.

[0076] Furthermore, when the semiconductor switching element 50 is turned off, the gate driver 11 negatively biases the gate voltage Vge, causing the wiring of the gate terminal G to drop from a positive potential to a negative potential. Therefore, the negative voltage is divided by resistors R11 and R12, and the divided voltage is applied to the base of the transistor Qg1. At this time, the emitter of the transistor Qg1 has a potential increased by the forward voltage of the diodes Dg2 and Dg5. The transistor Qg1 is designed in advance so that a relatively positive voltage of Vf is applied to its base, turning the transistor Qg1 on. This causes gate current to flow from the gate terminal G of the semiconductor switching element 50 through the transistor Qg1 and the diode Dg2.

[0077] When an overcurrent in the semiconductor switching element 50 is detected, the first transistor Q1 and the second transistor Q2 turn on. When the second transistor Q2 turns on, the base potential of the second transistor Q2 drops from the positive power supply potential VG1 to VG1 - Vf, the third transistor Q3 turns on, and current flows from the connection wiring 15 to the gate voltage reduction unit 14. As a result, the voltage is divided by the resistors R11 and R12, and a potential increased by the forward voltage of the diode Dg1 is applied to the base of the transistor Qg1. Meanwhile, the emitter potential is increased by the forward voltage of the diodes Dg2 and Dg5, so a relatively negative voltage of Vf is applied to the base of the transistor Qg1, turning it off.

[0078] The backflow prevention diode Dg1 connected to the base of the transistor Qg1 is provided to prevent the transistor Qg1 from malfunctioning. The protective diode Dg3 connected between the base and emitter of transistor Qg1 is an anti-parallel diode typically used in bipolar transistors, and prevents a large negative voltage from being applied between the base and emitter of transistor Qg1, which would cause deterioration of its characteristics.

[0079] The blocking diode Dg2 connected to the emitter of transistor Qg1 protects transistor Qg1 by preventing current from flowing backward in the direction of current flow through transistor Qg1. The blocking diode Dg2 is also connected to the emitter of transistor Qg1, and this increases the base potential of transistor Qg1 relative to the emitter, thereby raising the voltage level required to turn on transistor Qg1. In particular, the blocking diode Dg1 is connected to the base of transistor Qg1, preventing the forward voltage of this blocking diode Dg1 from causing transistor Qg1 to lose on / off control.

[0080] FIG. 5 is a waveform diagram of each part showing the operation of the semiconductor driving device including the overcurrent protection unit 12 shown in FIG. 3, at time t1, after the semiconductor switching element 50 is turned on, if an overcurrent occurs due to an arm short circuit with another connected arm, the peak value Icp of the collector current Ic saturates, and the collector voltage Vce, which normally decreases, becomes high. As a result, the base potential (input potential) VA1 of the first transistor Q1 rises above the reference potential VG0.

[0081] At time t2, the base potential (input potential) VA1 of the first transistor Q1 rises to 2Vf, i.e., when the above formula (1) is satisfied, the first transistor Q1 turns on. This detects an overcurrent in the semiconductor switching element 50. When the first transistor Q1 turns on, the potential of the determination signal OCD drops. When it drops from the positive power supply potential VG1 to a potential (VG1-Vf) that is lower by the threshold voltage Vf of the second transistor Q2, the second transistor Q2 turns on. This also increases the base potential of the third transistor Q3, applying a voltage equal to or greater than the threshold voltage Vf to the base and turning on the third transistor Q3. This causes a gate discharge current IA to flow, reducing the gate voltage Vge. At this time, the collector current Ic decreases to a value Ica corresponding to the reduced gate voltage Vge, and a surge voltage Vsa occurs in the collector voltage Vce.

[0082] Furthermore, when the third transistor Q3 is turned on, a current flows from the connection wiring 15 to the gate voltage reducing unit 14. As a result, the voltage is divided by resistors R11 and R12, and a potential increased by the forward voltage of diode Dg1 is applied to the base of transistor Qg1. Meanwhile, the emitter potential is increased by the forward voltage of diodes Dg2 and Dg5, so a relatively negative voltage of Vf is applied to the base of transistor Qg1, turning transistor Qg1 off. The resistance value R_OFFGI of the off-gate current adjusting unit 18 increases (RG3). As a result, the off-gate current when the gate driver 11 turns off the semiconductor switching element 50 flows through resistor RG3 of the off-gate current adjusting unit 18.

[0083] As described above, when the transistor Qg1 included in the off-gate current adjusting unit 18 is a PNP bipolar transistor, it can be turned off using the collector voltage of the second transistor Q2, that is, using the determination result of the first overcurrent determining unit 13. When the transistor Qg1 included in the off-gate current adjusting unit 18 is an NPN bipolar transistor, it can be turned off by a signal from the gate voltage reducing unit 14.

[0084] Embodiment 2 In the first embodiment, the first transistor Q1 is an NPN bipolar transistor, but in this second embodiment, the first transistor Q1 is a PNP bipolar transistor, the second transistor Q2 is an NPN bipolar transistor, and the third transistor Q3 is a PNP bipolar transistor. 6 is a diagram showing an overcurrent protection unit 12A in the circuit configuration of a semiconductor driving device according to embodiment 2. A semiconductor driving device 10 includes a gate driving unit 11 and an overcurrent protection unit 12A, but the detailed circuit configuration of the overcurrent protection unit 12A differs from that of embodiment 1, and other parts are the same as those of embodiment 1.

[0085] The overcurrent protection unit 12A uses the same detection signal SOC as in the first embodiment, and includes a first overcurrent determination unit 13A that receives the detection signal SOC and outputs an overcurrent determination signal OCD, a gate voltage reduction unit 14A that reduces the gate voltage Vge based on the determination signal OCD, and an off-gate current adjustment unit 18 that reduces the off-gate current of the semiconductor switching element 50 when an overcurrent is detected by the first overcurrent determination unit 13A. The gate voltage reduction unit 14A also includes a drive circuit 141A that reduces the gate voltage Vge, and an amplifier circuit 142A that amplifies the output signal from the overcurrent determination unit 13A to drive the drive circuit 141A.

[0086] The first overcurrent determination unit 13A includes series-connected resistors R1, R2, R3, and R4, a clamp diode D1, and a capacitor C1. It also includes a series circuit in which a first transistor Q1, a PNP bipolar transistor, resistors R5 and R6, and a backflow prevention diode D3 are connected in series. A capacitor C2 is connected in parallel with the resistor R6, and a protection diode D2 is provided between the base and emitter of the first transistor Q1. It also includes series-connected resistors R14 and R15, and a capacitor C4 connected in parallel with the resistor R15.

[0087] In this case as well, a resistor R consisting of three resistors R1, R2, and R3 and a capacitor C1 form a low-pass filter (R, C1). Furthermore, a connection point P2 between the resistors R (R1, R2, R3) and R4 serves as an input for the detection signal SOC and is connected to the emitter of the first transistor Q1. The potential of the connection point P2, which is the emitter potential of the first transistor Q1 with respect to the emitter control terminal ES, is defined as an input potential VA2.

[0088] The emitter potential (input potential VA2) of the first transistor Q1 is given by the following equation. VA2=Vce×R4 / (R1+R2+R3+R4) The base potential VB of the first transistor Q1 is the potential at the connection point between the resistors R14 and R15, and is given by the following equation: VB=Vge×R15 / (R14+R15)

[0089] In this embodiment as well, an overcurrent is detected by turning on the first transistor Q1. When the first transistor Q1 is turned on, the emitter potential (input potential VA2) is expressed by the following equation (3). VA2=VB+Vf (3)

[0090] When the semiconductor switching element 50 is turned off, the emitter potential (input potential VA2) of the first transistor Q1 is immediately negatively biased by the action of the clamp diode D1. This makes it possible to prevent erroneous detection of an overcurrent when the semiconductor switching element 50 is turned off. Furthermore, by negatively biasing the initial state of the capacitor C1 in the low-pass filter (R, C1), it is possible to prevent erroneous detection of an overcurrent when the semiconductor switching element 50 is turned on.

[0091] Next, the amplifier circuit 142A in the gate voltage reduction unit 14A amplifies the determination signal OCD from the first overcurrent determination unit 13A and includes a series circuit consisting of a second transistor Q2 made of an NPN bipolar transistor, resistors R7 and R8, and a reverse current prevention diode D7. A capacitor C3 is connected in parallel with the resistor R8, and a protection diode D4 is provided between the base and emitter of the second transistor Q2. The base of the second transistor Q2 has the same potential as the determination signal OCD. The drive circuit 141A in the gate voltage reduction unit 14A amplifies the output signal from the overcurrent determination unit 13A and includes a series circuit in which a third transistor Q3 made of a PNP bipolar transistor, a resistor R10, and a diode D6 are connected in series. A resistor R9 is provided between this series circuit and the base of the second transistor Q2, and a protective diode D5 is provided between the base and emitter of the third transistor Q3.

[0092] In this embodiment, similarly to the first embodiment, when the first transistor Q1 turns on and determines that the semiconductor switching element 50 is in an overcurrent state, the second transistor Q2 turns on, and then the third transistor Q3 turns on. In this case, by appropriately setting the resistors R5 and R6 connected in series to the first transistor Q1, the second transistor Q2 turns on after the first transistor Q1 turns on. Also, by appropriately setting the resistors R7 and R8 connected in series to the second transistor Q2, the third transistor Q3 turns on after the second transistor Q2 turns on.

[0093] Then, by discharging the gate charge accumulated in the capacitance between the gate and emitter of the semiconductor switching element 50, a gate discharge current IA flows through the third transistor Q3, reducing the gate voltage Vge, thereby suppressing overcurrent in the semiconductor switching element 50.

[0094] In the off-gate current adjusting unit 18, a parallel circuit in which a diode Dg4 and a resistor RG3 are connected in parallel is connected within the connecting wiring 15 that is connected to the gate terminal G of the semiconductor switching element 50, and a series circuit in which a transistor Qg1 made of a PNP bipolar transistor and a backflow prevention diode Dg2 are connected in series is connected in parallel to this parallel circuit. A series circuit formed by connecting transistor Qg1 and blocking diode Dg2 in series is connected in parallel to a series circuit formed by connecting resistors R11 and R12 in series, and the base of transistor Qg1 is connected to the midpoint of resistors R11 and R12, blocking diode Dg1, and the output of determination signal OCD. Furthermore, protection diode Dg3 is connected between the base and emitter of transistor Qg1. The base of transistor Qg1 has the same potential as determination signal OCD.

[0095] Under normal conditions, the emitter potential (input potential) VA2 of the first transistor Q1, with respect to the emitter control terminal ES, is clamped to a potential (VG2+Vf) obtained by adding the forward voltage Vf of the clamp diode D1 to the negative power supply potential VG2 when the semiconductor switching element 50 is in the off state. When the semiconductor switching element 50 is in the on state, the collector voltage Vce drops to several volts, and the voltage VA2 divided by the resistors R (R1, R2, R3) and R4 becomes close to the reference potential VG0. The potential of the determination signal OCD, that is, the base potential of the second transistor Q2, is maintained at the reference potential VG0 regardless of the on / off state of the semiconductor switching element 50.

[0096] Furthermore, when the semiconductor switching element 50 is turned off, the gate driver 11 negatively biases the gate voltage Vge, causing the wiring of the gate terminal G to drop from a positive potential to a negative potential. Therefore, the negative voltage is divided by resistors R11 and R12, and the divided voltage is applied to the base of the transistor Qg1. This voltage is designed to exceed the threshold voltage Vf of the transistor Qg1, turning the transistor Qg1 on. This causes a gate current to flow from the gate terminal G of the semiconductor switching element 50 through the diode Dg2 and the transistor Qg1. It is only necessary that the transistor Qg1 is in an on state when the off-gate voltage is high and switching is turned off.

[0097] When the emitter potential (input potential) VA2 of the first transistor Q1 rises to (VB + Vf), i.e., when the above formula (3) is satisfied, the first transistor Q1 turns on. This detects an overcurrent in the semiconductor switching element 50. When the first transistor Q1 turns on, the potential of the determination signal OCD rises, and when it reaches a potential (VG0 + Vf) that is higher than the reference potential VG0 by the threshold voltage Vf of the second transistor Q2, the second transistor Q2 turns on. This also reduces the base potential of the third transistor Q3, and a voltage equal to or higher than the threshold voltage Vf is applied to the base, turning on the third transistor Q3. Then, the gate discharge current IA flows, and the gate voltage Vge is reduced. At this time, the collector current Ic decreases to a value Ica corresponding to the reduced gate voltage Vge, and a surge voltage Vsa is generated in the collector voltage Vce.

[0098] When the first transistor Q1 turns on and an overcurrent is detected in the semiconductor switching element 50, the potential of the determination signal OCD rises. The base of the transistor Qg1 rises from this potential to a potential dropped by the forward voltage of the diode Dg1. Meanwhile, the emitter of the transistor Qg1 reaches a potential dropped by the forward voltage of the diode Dg2, and a reverse bias of Vf is applied to the base of the transistor Qg1, turning the transistor Qg1 off.

[0099] In this embodiment, as in the first embodiment, the overcurrent protection unit 12A does not require its own power supply and can detect and protect the semiconductor switching element 50 from overcurrent by using the threshold voltage of the first transistor Q1. In addition, the clamp diode D1 and the low-pass filter (R, C1) function to suppress malfunctions due to noise and perform overcurrent protection. As a result, even when the semiconductor switching element 50 and the gate drive unit 11 of the semiconductor drive device 10 are placed apart, the overcurrent protection unit 12, which does not require a power supply, can be placed close to the semiconductor switching element 50, thereby providing highly reliable overcurrent protection. Furthermore, an overcurrent in the semiconductor switching element 50 is detected and the off-gate current is reduced by the off-gate current adjusting section 18 when the semiconductor switching element is turned off, thereby realizing soft cutoff.

[0100] Furthermore, the provision of a backflow prevention diode D3 protects the first transistor Q1 and also improves the noise resistance of the first transistor Q1, thereby making it possible to suppress erroneous detection of an overcurrent.

[0101] In addition, in this embodiment, a PNP bipolar transistor is used for the first transistor Q1 in the first overcurrent judgment unit 13A, so the input potential VA2 used for judgment can be set to a higher level, thereby improving voltage noise resistance.

[0102] Embodiment 3 In the above first and second embodiments, an overcurrent is determined based on the input potentials VA1 and VA2 obtained by attenuating the collector voltage Vce (detection signal SOC) of the semiconductor switching element 50 using a voltage dividing resistor, but this embodiment uses a different method. 7 is a diagram showing an overcurrent protection unit 12B in the circuit configuration of a semiconductor driving device according to embodiment 3. The semiconductor driving device 10 includes a gate driving unit 11 and an overcurrent protection unit 12B. As shown in FIG. 7, the overcurrent protection unit 12B includes a first overcurrent determination unit 13B that outputs an overcurrent determination signal OCD based on the detection signal SOC similar to those in embodiments 1 and 2, a gate voltage reducing unit 14A that reduces the gate voltage Vge based on the determination signal OCD, and an off-gate current adjusting unit 18 that reduces the off-gate current of the semiconductor switching element 50 when an overcurrent is detected by the first overcurrent determination unit 13B.

[0103] This embodiment is the same as the second embodiment except that the detection signal SOC is connected to the first overcurrent determination unit 13B. In this case, a DESAT method is used to determine the collector voltage Vce (detection signal SOC) by passing a constant current through a high-voltage diode D8 to the collector sense terminal CS of the semiconductor switching element 50. The following describes the differences from the second embodiment. In the first overcurrent determination unit 13B, a constant current diode CRD, a resistor R1, and a high-voltage diode D8 are connected in series to a collector sense terminal CS. The constant current diode CRD is connected to a power supply line connected to a gate terminal G, and the connection point between the constant current diode CRD and the resistor R1 is connected to the emitter of a first transistor Q1.

[0104] In this case, the resistor R of the low-pass filter (R, C1) is formed by only the resistor R1. A connection point P2 connecting the constant current diode CRD to the emitter of the first transistor Q1 is used as an input part for the detection signal SOC, and the potential of the connection point P2, which is the emitter potential of the first transistor Q1, is used as an input potential VA2.

[0105] When the semiconductor switching element 50 is in the on state, the constant current diode CRD acts to pass a constant current of about several mA from the positive power supply potential VG1. In a normal state where the semiconductor switching element 50 is not in current saturation, the collector voltage Vce drops to several volts, causing the current of the constant current diode CRD to flow to the collector sense terminal CS. At this time, the emitter potential (input potential VA2) of the first transistor Q1 drops to several volts, so the first transistor Q1 does not turn on.

[0106] When the semiconductor switching element 50 reaches current saturation and the collector voltage Vce rises, the current from the constant current diode CRD cannot flow to the collector sense terminal CS, but flows to the resistor R4. As a result, the emitter potential (input potential) VA2 of the first transistor Q1 rises to (VB + Vf), which satisfies the above equation (3), turning on the first transistor Q1. This detects an overcurrent in the semiconductor switching element 50. The product of the constant current value of the constant current diode CRD and the resistance value of the resistor R4 is designed in advance to be larger than VB+Vf.

[0107] When the first transistor Q1 turns on, the second transistor Q2 turns on, and then the third transistor Q3 turns on, causing the gate discharge current IA to flow and reducing the gate voltage Vge. In addition, when the first transistor Q1 turns on and detects an overcurrent, the transistor Qg1 of the off-gate current adjusting unit 18 turns off, and the off-gate current generated when the semiconductor switching element 50 is turned off by the gate driving unit 11 flows through RG3, adjusting the off-gate current to be reduced.

[0108] The third embodiment provides the same effects as the second embodiment. Furthermore, in this embodiment, the collector voltage Vce can be detected to a lower level than in the first and second embodiments in which the collector voltage Vce is attenuated by a voltage dividing resistor before detection.

[0109] Embodiment 4 In each of the first to third embodiments, the collector voltage Vce of the semiconductor switching element 50 is detected from the collector sense terminal CS to be used as the detection signal SOC, but in this embodiment, a different detection signal SOC is used. FIG. 8 is a diagram showing a schematic configuration of a semiconductor driving device according to the fourth embodiment. In the fourth embodiment, the semiconductor switching element 50A is provided with a current detection element on the emitter side through which a current reduced to, for example, several thousandths flows, and the reduced emitter current flowing from the current detection terminal EE of the current detection element is Iee is the detection signal SOC.

[0110] 8, the semiconductor driving device 10C includes a gate driving unit 11 and an overcurrent protection unit 12C. The overcurrent protection unit 12C includes a first overcurrent determination unit 13C that outputs an overcurrent determination signal OCD based on the emitter current Iee (detection signal SOC), a gate voltage reducing unit 14 that reduces the gate voltage Vge based on the determination signal OCD, and an off-gate current adjusting unit 18 that reduces the off-gate current of the semiconductor switching element 50 when an overcurrent is detected by the first overcurrent determination unit 13C. The gate driving unit 11, the gate voltage reducing unit 14, and the off-gate current adjusting unit 18 are the same as those in the first embodiment. The first overcurrent determining unit 13C also has a circuit configuration similar to that of the overcurrent determining unit 13 of the first embodiment, although it handles a different detection signal SOC.

[0111] FIG. 9 is a waveform diagram of each part showing the operation of the semiconductor driving device according to the fourth embodiment. In this case, the emitter current Iee that becomes the detection signal SOC is connected to the base of the first transistor Q1 and becomes the base current that is input to the base. When an overcurrent occurs while the semiconductor switching element 50A is in the on state, the emitter current Iee (detection signal SOC) rises, and when it exceeds a set threshold value IX, the first transistor Q1 turns on. This detects an overcurrent in the semiconductor switching element 50. Except for the use of the emitter current Iee as the detection signal SOC, the operating waveforms of each part are the same as those shown in FIG. 3 of the first embodiment.

[0112] This embodiment also provides the same effects as those of the above-described embodiment 1. Furthermore, although it is applicable only to the semiconductor switching element 50A equipped with a current detection element, it is possible to detect overcurrent with higher accuracy because it detects the current value itself and determines overcurrent without needing to contact a high-voltage section.

[0113] Embodiment 5. In this embodiment, a further different detection signal SOC is used. FIG. 10 is a diagram showing a schematic configuration of a semiconductor driving device according to the fifth embodiment. In this fifth embodiment, the emitter voltage VEe between the emitter E, which is the low-voltage side main terminal of the semiconductor switching element 50B, and the emitter control terminal ES is used as the detection signal SOC. This utilizes the electromotive force (Le·dIc / dt) generated across the parasitic inductance Le on the emitter side.

[0114] 10, the semiconductor driver 10D includes a gate driver 11 and an overcurrent protection unit 12D. The overcurrent protection unit 12D includes a first overcurrent determination unit 13D that outputs an overcurrent determination signal OCD based on the emitter voltage VEe (detection signal SOC), a gate voltage reducing unit 14 that reduces the gate voltage Vge based on the determination signal OCD, and an off-gate current adjusting unit 18 that reduces the off-gate current of the semiconductor switching element 50 when an overcurrent is detected by the first overcurrent determination unit 13D. The gate driver 11, the gate voltage reducing unit 14, and the off-gate current adjusting unit 18 are the same as those in the first embodiment.

[0115] The first overcurrent determining unit 13D also has a circuit configuration similar to that of the first overcurrent determining unit 13 of the first embodiment, although the detection signal SOC that it handles is different. However, while in the first embodiment the entire overcurrent protection unit 12 is configured with the potential of the emitter control terminal ES as the reference, in this embodiment only the first overcurrent determination unit 13D in the overcurrent protection unit 12D is configured with the potential of the emitter E as the reference, and the rest are configured with the potential of the emitter control terminal ES as the reference. That is, the emitter control terminal ES is connected to the high-voltage side of the resistor R1, and the emitter voltage VEe (detection signal SOC) from the emitter E is connected to the low-voltage side of the resistor R4.

[0116] FIG. 11 is a waveform diagram of each part showing the operation of the semiconductor driving device according to the fifth embodiment. In this case, the emitter voltage VEe, which becomes the detection signal SOC, has a waveform similar to the differential value (dIc / dt) of the collector current Ic. When an overcurrent occurs while the semiconductor switching element 50B is in the on state, the emitter voltage VEe (detection signal SOC) drops, and when it drops below a set threshold VX, the first transistor Q1 turns on. This detects an overcurrent in the semiconductor switching element 50B. Except for the use of the emitter voltage VEe as the detection signal SOC, the operating waveforms of each part are the same as those shown in FIG. 3 of the first embodiment.

[0117] This embodiment also provides the same effects as those of the above-described embodiment 1. Moreover, by utilizing the electromotive force generated in the parasitic inductance Le on the emitter side, it is possible to obtain current information quickly and accurately and detect overcurrent without using a current detection element.

[0118] In the above embodiment, the emitter voltage VEe is compared with the threshold value VX, which serves as the determination voltage. However, the voltage amplitude (Le·dIc / dt) of the emitter voltage VEe may be integrated using an integrating circuit to obtain information similar to the collector current Ic, and an overcurrent may be determined.

[0119] Embodiment 6 In this embodiment, the rate of change of the current between the main terminals is detected and converted into a voltage signal, which is used as the detection signal SOC. FIG. 12 is a diagram showing a schematic configuration of a semiconductor driving device according to the sixth embodiment. 12, a current-voltage conversion element CT is provided on the outside of an emitter E, which is one of the main terminals of a semiconductor switching element 50C. The current-voltage conversion element CT detects the rate of change of a collector current Ic, which is a current between the main terminals, and outputs voltage information Vct (detection signal SOC). The current-voltage conversion element CT is, for example, a Rogowski coil formed on a printed circuit board that constitutes the overcurrent protection unit 12E.

[0120] 12, semiconductor driving device 10E includes gate driving unit 11 and overcurrent protection unit 12E. Overcurrent protection unit 12E includes first overcurrent determination unit 13E that outputs an overcurrent determination signal OCD based on voltage information Vct (detection signal SOC), a gate voltage reducing unit 14 that reduces gate voltage Vge based on the determination signal OCD, and an off-gate current adjusting unit 18 that reduces the off-gate current of semiconductor switching element 50 when an overcurrent is detected by first overcurrent determination unit 13E. Gate driving unit 11, gate voltage reducing unit 14, and off-gate current adjusting unit 18 are the same as those in the first embodiment.

[0121] The first overcurrent determining unit 13E also has a circuit configuration similar to that of the first overcurrent determining unit 13 of the first embodiment, although it handles a different detection signal SOC. FIG. 13 is a waveform diagram of each part showing the operation of the semiconductor driving device according to the sixth embodiment. In this case, the voltage information Vct that becomes the detection signal SOC has a waveform similar to the differential value (dIc / dt) of the collector current Ic. When an overcurrent occurs while the semiconductor switching element 50C is in the on state, the voltage information Vct (detection signal SOC) rises, and when it exceeds a set threshold VXa, the first transistor Q1 turns on. This detects an overcurrent in the semiconductor switching element 50C. Except for using the voltage information Vct as the detection signal SOC, the operating waveforms of each part are the same as those shown in FIG. 3 of the first embodiment.

[0122] In this embodiment, the same effects as those in the first embodiment can be obtained. Moreover, by mounting the overcurrent protection unit 12E on a printed circuit board and using a Rogowski coil (current-voltage conversion element CT) formed on the printed circuit board, it is possible to achieve non-contact, highly accurate overcurrent detection.

[0123] Embodiment 7 In the first embodiment, a low-pass filter (R, C1) is provided at the input section of the detection signal SOC. In this embodiment, a semiconductor driving device is shown that includes a first low-pass filter and a second low-pass filter as the low-pass filters. FIG. 14 is a diagram showing a schematic configuration of a semiconductor driving device according to the seventh embodiment. 14, a semiconductor driver 10F includes a gate driver 11 and an overcurrent protection unit 12F. The overcurrent protection unit 12F includes a first overcurrent determination unit 13F that determines an overcurrent flowing through a semiconductor switching element 50, a gate voltage reduction unit 14 that reduces the voltage applied to the gate terminal G of the semiconductor switching element 50 when an overcurrent is determined, and an off-gate current adjustment unit 18 that reduces the off-gate current of the semiconductor switching element 50 when an overcurrent is detected by the first overcurrent determination unit 13F. The gate driver 11, the gate voltage reduction unit 14, and the off-gate current adjustment unit 18 are the same as those in the first embodiment.

[0124] The first overcurrent determining unit 13F includes a first transistor Q1, a clamp diode D1, a backflow prevention diode D3, a resistor R, capacitors C1a and C1b, and a diode DL. In this case, a first low-pass filter (R, C1a) is formed by the resistor R and the capacitor C1a, and a second low-pass filter (R, C1b) is formed by the resistor R and the capacitor C1b. Then, a detection signal SOC based on the collector voltage Vce, which is the voltage between the main terminals of the semiconductor switching element 50, is input to the first transistor Q1 via a first low-pass filter (R, C1a) and a second low-pass filter (R, C1b), and an overcurrent determination signal OCD is output.

[0125] FIG. 15 is a diagram showing an overcurrent protection unit 12F in the circuit configuration of the semiconductor driving device according to the seventh embodiment. 15, in the first overcurrent determination unit 13F, a resistor R consisting of three resistors R1, R2, and R3 and capacitors C1a and C1b form a first low-pass filter (R, C1a) and a second low-pass filter (R, C1b). A connection point P1 between the resistors R (R1, R2, and R3) and R4 serves as an input for the detection signal SOC and is connected to the base of the first transistor Q1. The potential of the connection point P1, which is the base potential of the first transistor Q1 with respect to the emitter control terminal ES, is defined as an input potential VA1.

[0126] The anode of the clamp diode D1, which clamps the gate potential (Vge), is connected to the capacitor C1 of the first low-pass filter (R, C1a). The connection point is connected to the connection point P1 and the base of the first transistor Q1, and is also connected to the capacitor C1b of the second low-pass filter (R, C1b) via the diode DL. The detection signal SOC is divided by resistors R1 to R4 and input to the base of the first transistor Q1 via a first low-pass filter (R, C1a) and a second low-pass filter (R, C1b) consisting of the voltage-dividing resistors R (R1, R2, R3) and two capacitors C1a and C1b.

[0127] The base of the first transistor Q1 is clamped to the negative power supply potential VG2 by the clamp diode D1 when the semiconductor switching element 50 is in the off state. The first low-pass filter (R, C1a) is clamped to the gate potential (Vge) via the clamp diode D1, while the second low-pass filter (R, C1b) is not clamped to the gate potential (Vge) due to the action of the diode DL.

[0128] The diode DL is provided to prevent the second low-pass filter (R, C1b) from being clamped to the negative power supply potential VG2, but its forward voltage acts as an offset voltage for the second low-pass filter (R, C1b), which reduces the noise immunity of the first transistor Q1. For this reason, the offset voltage is suppressed by using a diode with a small forward voltage, such as a Schottky barrier diode. Also, as shown in Figure 15, the offset voltage can be eliminated by providing a backflow prevention diode D3 on the emitter side of the first transistor Q1.

[0129] Furthermore, the capacitor C1a of the first low-pass filter (R, C1a) is configured to have a small capacitance, and the capacitor C1b of the second low-pass filter (R, C1b) is configured to have a large capacitance. When the semiconductor switching element 50 is in the off state, the capacitor C1a of the first low-pass filter (R, C1a) is negatively biased. When the semiconductor switching element 50 is turned on and the capacitor C1a recovers from the negative bias state, it takes time to recover if the capacitance of the capacitor C1a is large. Here, the capacitance of the capacitor C1a is set small, so the capacitor C1a recovers from the negative bias quickly, and overcurrent detection can be achieved within a specified delay time. The first low-pass filter (R, C1a) functions in the same manner as the low-pass filter (R, C1) described in the first embodiment, and suppresses erroneous detection of an overcurrent.

[0130] If the second low-pass filter (R, C1b) is not provided, i.e., in the same case as in the first embodiment, when the semiconductor switching element 50 is in the on state, the first low-pass filter (R, C1a) having a small capacitance capacitor C1a alone will have low resistance to current noise. In this case, the provision of the second low-pass filter (R, C1b) having a large capacitance capacitor C1b makes it possible to suppress erroneous detection of overcurrent due to current noise, even when the semiconductor switching element 50 is in the on state.

[0131] FIG. 16 is a waveform diagram of each part showing the operation of the semiconductor driving device according to the seventh embodiment. The operating waveforms other than the base potential (input potential) VA1 of the first transistor Q1 with respect to the emitter control terminal ES are the same as those shown in Fig. 3 of the above-mentioned embodiment 1. Note that the VA1 waveform in the case of the above-mentioned embodiment 1 is shown by a dotted line.

[0132] During normal operation before time t1, the base potential (input potential) VA1 of the first transistor Q1 is clamped to a potential (VG2+Vf) obtained by adding the forward voltage Vf of the clamp diode D1 to the negative power supply potential VG2 when the semiconductor switching element 50 is in the off state. Furthermore, when the semiconductor switching element 50 is in the on state, the collector voltage Vce drops to several volts, and the voltage VA1 divided by the resistors R (R1, R2, R3) and R4 becomes close to the reference potential VG0. In this case, since a small-capacity capacitor C1a is used in the first low-pass filter (R, C1a) clamped by the clamp diode D1, the period in which the base potential (input potential) VA1 returns from the negative bias when the semiconductor switching element 50 transitions from the off state to the on state is shortened.

[0133] At time t1, after the semiconductor switching element 50 is turned on, if an overcurrent occurs due to an arm short circuit with another connected arm, the peak value Icp of the collector current Ic saturates and the collector voltage Vce, which normally decreases, becomes high. Here too, after the semiconductor switching element 50 is turned on, the base potential (input potential) VA1 quickly recovers from the negative bias and further rises beyond the reference potential VG0.

[0134] In this embodiment, as in the first embodiment, the overcurrent protection unit 12F does not require a power supply for itself, but can detect and protect the semiconductor switching element 50 by using the threshold voltage of the first transistor Q1. Furthermore, the clamp diode D1, the first low-pass filter (R, C1a), and the second low-pass filter (R, C1b) work together to suppress malfunctions due to noise and provide overcurrent protection. As a result, even when the semiconductor switching element 50 and the gate drive unit 11 of the semiconductor drive device 10 are placed apart, the overcurrent protection unit 12, which does not require a power supply, can be placed close to the semiconductor switching element 50, thereby providing highly reliable overcurrent protection. Furthermore, an overcurrent in the semiconductor switching element 50 is detected and the off-gate current is reduced by the off-gate current adjusting section 18 when the semiconductor switching element is turned off, thereby realizing soft cutoff.

[0135] Furthermore, the first low-pass filter (R, C1a) is configured to be clamped to the gate potential (Vge), and the second low-pass filter (R, C1b) is configured not to be clamped to the gate potential (Vge). This allows the first low-pass filter (R, C1a) and the second low-pass filter (R, C1b) to be used individually depending on whether the semiconductor switching element 50 is in the off state or the on state, thereby effectively eliminating the effects of noise. In addition, the capacitor C1a of the first low-pass filter (R, C1a) is configured to have a small capacitance, and the capacitor C1b of the second low-pass filter (R, C1b) is configured to have a large capacitance. This shortens the time it takes for the base potential (input potential) VA1 of the first transistor Q1 to recover from a negative bias, enabling quick overcurrent detection and improving noise immunity.

[0136] In the above-described first to seventh embodiments, an example in which the overcurrent protection unit includes an off-gate current adjustment unit has been described. When the overcurrent protection unit is mounted on a single substrate, the overcurrent protection unit does not have a power supply and can adjust the off-gate resistance based on a signal from the first overcurrent determination unit to perform soft shutdown. The substrate on which this overcurrent protection unit is mounted corresponds to the semiconductor switching element. When multiple semiconductor switching elements and overcurrent protection units are mounted in parallel on a single substrate, i.e., when configuring a power conversion device with multiple semiconductor switching elements, the substrate can be used as a common substrate on which the overcurrent protection unit is mounted. Furthermore, a single gate driver can control multiple semiconductor switching elements and overcurrent protection units. Therefore, the use of a common substrate reduces costs, eliminates the need to adjust the substrate constants for each substrate, and improves the performance of the semiconductor switching elements and, ultimately, the power conversion device.

[0137] Embodiment 8 In the above first to seventh embodiments, an example in which the overcurrent protection unit includes an off-gate current adjustment unit has been shown, but in this embodiment, an example in which the gate driver unit includes an off-gate current adjustment unit will be described. FIG. 17 is a diagram showing a schematic configuration of a semiconductor driving device according to the eighth embodiment. 17, the semiconductor driver 10G includes a gate driver 11G and an overcurrent protection unit 12G. The overcurrent protection unit 12G includes a first overcurrent determination unit 13 that determines whether an overcurrent flows through the semiconductor switching element 50, and a gate voltage reduction unit 14 that reduces the voltage applied to the gate terminal G of the semiconductor switching element 50 when an overcurrent is determined. As in the first to seventh embodiments described above, the gate driver 11G includes an output stage circuit, a control unit 16 that controls the output stage circuit, and a protection operation detection unit 19 that detects a drop in the gate voltage Vge after an overcurrent is detected and generates a signal GSD to turn off the semiconductor switching element 50. An off-gate current adjustment unit 18G is provided in the output stage circuit of the gate driver 11G.

[0138] The off-gate current adjusting unit 18G includes an N-type MOSFET MG3 connected between the N-type MOSFET MG2 and the gate resistor RG2, and a resistor RG4 connected in parallel to the series circuit of the gate resistor RG2 and the N-type MOSFET MG3. The resistance value of the resistor RG4 is set to a value greater than the resistance value of the gate resistor RG2 (RG4>RG2).

[0139] Normally, when the semiconductor switching element 50 is turned on, the control unit 16 turns on the P-type MOSFET MG1 based on the command signal SIN, and an on-gate current flows from the gate resistor RG1 to the gate terminal G. Normally, when the semiconductor switching element 50 is turned off, the control unit 16 turns on the N-type MOSFET MG2 based on the command signal SIN, and the off-gate current flows from the gate terminal G to the gate resistor RG2 direction Flows to. In addition, under normal circumstances, the N-type MOSFET MG3 is always on.

[0140] When the first transistor Q1 turns on, the determination signal OCD changes, and an overcurrent in the semiconductor switching element 50 is determined. That is, the first overcurrent determination unit 13 detects the overcurrent. The gate voltage reduction unit 14 receives the overcurrent determination signal OCD and operates to reduce the gate voltage Vge applied to the gate terminal G to a level lower than the voltage (VG1) of the positive power supply PG1. At this time, the gate drive unit 11G uses the protection operation detection unit 19 to detect that the gate voltage reduction unit 14 has reduced the gate voltage Vge, and generates a signal GSD, which serves as a protection operation detection signal, and transmits it to the control unit 16. Here, the N-type MOSFET MG3 is preset so that the gate changes from high to low upon input of the signal GSD. Therefore, the N-type MOSFET MG3 is turned off upon input of the signal GSD.

[0141] When control unit 16 receives signal GSD, it holds semiconductor switching element 50 in the off state for a predetermined period, regardless of the state of command signal SIN. At this time, N-type MOSFET MG3 is off, so when N-type MOSFET MG2 is turned on, an off-gate current flows from gate terminal G toward resistor RG4. As described above, the resistance of resistor RG4 is greater than the resistance of gate resistor RG2, through which the off-gate current flows under normal conditions, so the off-gate current is reduced and soft shutdown is performed.

[0142] Next, the circuit configuration of the overcurrent protection unit 12G will be described. 18 is a diagram showing the circuit configuration of overcurrent protection unit 12G. It differs from overcurrent protection unit 12 shown in FIGS. 2 and 4 of embodiment 1 only in that it does not include off-gate current adjustment unit 18. Other configurations and operations are similar, so description thereof will be omitted.

[0143] FIG. 19 is a waveform diagram of each part showing the operation of the semiconductor driving device according to the first embodiment. Hereinafter, the overcurrent protection operation by the semiconductor driver 10G will be described in detail with reference to FIGS. During normal operation before time t1, the gate voltage Vge is output in response to a command signal SIN sent from the higher-level control device, and the collector current Ic of the semiconductor switching element 50 and the collector voltage Vce, which serves as the detection signal SOC, also have waveforms that correspond to the command signal SIN. When the semiconductor switching element 50 is in the off state, the base potential (input potential) VA1 of the first transistor Q1, relative to the emitter control terminal ES, is clamped to a potential (VG2+Vf) obtained by adding the forward voltage Vf of the clamp diode D1 to the negative power supply potential VG2. When the semiconductor switching element 50 is in the on state, the collector voltage Vce drops to several volts, and the voltage VA1 divided by the resistors R (R1, R2, R3) and R4 becomes close to the reference potential VG0.

[0144] The potential of the determination signal OCD, that is, the base potential of the second transistor Q2, is the same as the gate potential (positive power supply potential VG1) when the semiconductor switching element 50 is in the ON state, and is pulled down to the negative power supply potential VG2 when the semiconductor switching element 50 is in the OFF state.

[0145] At time t1, after the semiconductor switching element 50 is turned on, if an overcurrent occurs due to an arm short circuit with another connected arm, the peak value Icp of the collector current Ic saturates, and the collector voltage Vce, which normally decreases, becomes high, causing the base potential (input potential) VA1 of the first transistor Q1 to rise above the reference potential VG0.

[0146] At time t2, the base potential (input potential) VA1 of the first transistor Q1 rises to 2Vf, i.e., when the above formula (1) is satisfied, the first transistor Q1 turns on. This detects an overcurrent in the semiconductor switching element 50. When the first transistor Q1 turns on, the potential of the determination signal OCD drops, and when it drops from the positive power supply potential VG1 to a potential (VG1-Vf) that is lower by the threshold voltage Vf of the second transistor Q2, the second transistor Q2 turns on. This also causes the base potential of the third transistor Q3 to rise, and a voltage equal to or greater than the threshold voltage Vf is applied to the base, turning the third transistor Q3 on. Then, the gate discharge current IA flows, and the gate voltage Vge is reduced. At this time, the collector current Ic decreases to a value Ica corresponding to the reduced gate voltage Vge, and a surge voltage Vsa is generated in the collector voltage Vce.

[0147] At time t3, the protection operation detector 19 detects a drop in the gate voltage Vge and generates a signal GSD. Between time t3 and time t4, control unit 16 performs a current cut-off operation on semiconductor switching element 50, turning it off. Signal GSD from protection operation detection unit 19 is input to control unit 16 and also input to the gate of N-type MOSFET MG3, turning N-type MOSFET MG3 off. An off-gate current flows from gate terminal G toward resistor RG4. When control unit 16 performs a cut-off operation on semiconductor switching element 50, the off-gate current flows through resistor RG4, which has a large resistance, so the off-gate current is reduced compared to normal, and soft cut-off is performed.

[0148] During this current interruption operation, a surge voltage Vsb occurs in the collector voltage Vce. As mentioned above, it is desirable to set the resistor R10 to satisfy the above formula (2) so that the surge voltage Vsb is approximately the same as the preceding surge voltage Vsa. Furthermore, when the gate voltage is reduced, the off-gate current is also reduced, resulting in soft shutdown. Therefore, even if a power conversion device equipped with a semiconductor switching element 50 driven by this semiconductor driving device 10G has a smoothing capacitor and a snubber capacitor, resonance between the capacitors is suppressed when the semiconductor switching element is shut off, and a highly reliable semiconductor driving device capable of implementing overcurrent protection can be provided.

[0149] At time t5, after the delay time Tf has elapsed since the generation of the signal GSD, the command signal SIN from the higher-level control device is maintained in the OFF state, and the abnormality signal FAIL is generated.

[0150] In this embodiment, as in the first embodiment, the overcurrent protection unit 12G does not require its own power supply and can use the threshold voltage of the first transistor Q1 to detect and protect the semiconductor switching element 50 from overcurrent. Furthermore, the clamp diode D1, the first low-pass filter (R, C1a), and the second low-pass filter (R, C1b) work together to suppress malfunctions caused by noise and provide overcurrent protection. As a result, even when the semiconductor switching element 50 and the gate drive unit 11 of the semiconductor drive device 10 are placed apart, the overcurrent protection unit 12, which does not require a power supply, can be placed close to the semiconductor switching element 50, thereby providing highly reliable overcurrent protection.

[0151] Furthermore, since the gate driver 11G includes an off-gate current adjuster 18G and the protection operation detector 19 detects a drop in the gate voltage Vge and generates a signal GSD to reduce the off-gate current, the off-gate current is also reduced when the gate voltage is reduced, enabling soft shutdown. Therefore, even if a power conversion device including a semiconductor switching element 50 driven by this semiconductor driver 10G has a smoothing capacitor and a snubber capacitor, resonance between the capacitors is suppressed when the semiconductor switching element is shut off, and a highly reliable semiconductor driver 10G capable of implementing overcurrent protection can be provided. Furthermore, when a common substrate is used in which the semiconductor switching element and the overcurrent protection unit are mounted on one substrate, the substrate size is limited, and if the substrate area is small, the constraints on the substrate size can be met by providing the off-gate current adjustment unit 18G in the gate drive unit 11G, as in this embodiment.

[0152] 18 shows the circuit configuration of overcurrent protection unit 12G, which differs from overcurrent protection unit 12 shown in FIGS. 2 and 4 of embodiment 1 only in that it does not include off-gate current adjustment unit 18. However, the present invention is not limited to this. Overcurrent protection unit 12G according to this embodiment may be overcurrent protection unit 12A shown in FIG. 6 of embodiment 2 minus off-gate current adjustment unit 18, overcurrent protection unit 12B shown in FIG. 7 of embodiment 3 minus off-gate current adjustment unit 18, or overcurrent protection unit 12F shown in FIGS. 14 and 15 of embodiment 7 minus first overcurrent determination unit 13F but minus off-gate current adjustment unit 18.

[0153] Furthermore, the circuit configuration of overcurrent protection unit 12G in this embodiment may be such that semiconductor switching element 50 has the circuit configuration of semiconductor switching element 50A shown in FIG. 8 of embodiment 4, with off-gate current adjustment unit 18 removed from overcurrent protection unit 12C in FIG. 8; or semiconductor switching element 50 has the circuit configuration of semiconductor switching element 50B shown in FIG. 10 of embodiment 5, with off-gate current adjustment unit 18 removed from overcurrent protection unit 12D in FIG. 10; or semiconductor switching element 50 has the circuit configuration of semiconductor switching element 50C shown in FIG. 12 of embodiment 6, with off-gate current adjustment unit 18 removed from overcurrent protection unit 12E in FIG. 12.

[0154] Embodiment 9 A power conversion device according to a ninth embodiment will be described below with reference to the drawings. FIG. 20 is a block diagram showing a schematic configuration of a power conversion device 1 according to the ninth embodiment. In FIG. 20, the power conversion device 1 includes a power converter 20 having semiconductor switching elements and converting power from a DC power supply (not shown) to supply the power to a load 70, and a semiconductor driving device 10H that drives the semiconductor switching elements of the power converter 20. The semiconductor driving device 10H includes a second overcurrent determination unit 17, a control unit 16 that receives a command signal SIN transmitted from a higher-level control device (not shown) and generates an ON / OFF command signal for the semiconductor switching elements based on the signal from the second overcurrent determination unit 17, a gate driving unit 11H that includes an output stage circuit 110 that applies a voltage to the semiconductor switching elements to drive them based on the ON / OFF command signal input via an insulated communication unit ICV, and an overcurrent protection unit 12 that detects and protects the semiconductor switching elements from overcurrent. Next, a detailed circuit configuration will be described with reference to FIGS. 21 and 22.

[0155] FIG. 21 is a diagram showing the circuit configuration of the main part of the power conversion device according to the ninth embodiment, and FIG. 22 is a diagram showing the circuit configuration of the overcurrent protection unit 12. As shown in FIG. The power converter 20 includes an arm section in which a semiconductor switching element 50a and a semiconductor switching element 50b are connected in series. An on / off command signal GDOa output from the control unit 16 is input to an output stage circuit 110a via an insulated communication unit ICVa to a control terminal (hereinafter referred to as a gate terminal) Ga of the semiconductor switching element 50a in the upper arm, and a voltage based on this on / off command signal GDOa is applied to the control terminal Ga. The power converter 20 also includes an overcurrent protection unit 12a that detects an overcurrent flowing through the semiconductor switching element 50a and reduces the gate voltage if it is determined that an overcurrent is flowing.

[0156] Similarly, an on / off command signal GDOb output from the control unit 16 is input to the output stage circuit 110b via the insulated communication unit ICVb, and a voltage based on this on / off command signal GDOb is applied to the gate terminal Gb of the semiconductor switching element 50b of the lower arm. Also, an overcurrent protection unit 12b is provided which detects an overcurrent flowing through the semiconductor switching element 50b and reduces the gate voltage if it is determined that an overcurrent is flowing.

[0157] As described above, the functional units and semiconductor switching elements 50a, 50b related to the control of the upper and lower arms are equivalent, and in the following description, the reference numerals may be appended with "a" or "b," or the description of one may be omitted.Furthermore, the functional units may be collectively referred to without the "a" or "b." 21 shows an example of a single-phase power converter 20 having one leg circuit configured by upper and lower arms, but the power converter 20 may also be a three-phase power converter 20 having three leg circuits connected in parallel. The power converter 20 includes at least one leg circuit.

[0158] The semiconductor driver 10H controls the conductive / non-conductive state between the collector C and emitter E, which are the main terminals of the semiconductor switching element 50, by a gate voltage Vge applied between the gate terminal G and a reference terminal (hereinafter referred to as the emitter control terminal) ES. In this case, as described in the first embodiment, an IGBT is shown as an example of the semiconductor switching element 50, but the present invention can also be applied to other semiconductor switching elements such as a MOSFET having a control terminal.

[0159] The overcurrent protection unit 12 is disposed immediately adjacent to or immediately above the semiconductor switching element 50, and the gate drive unit 11H and the overcurrent protection unit 12 are connected by two connection wires 15. The overcurrent protection unit 12 includes a first overcurrent determination unit 13, a gate voltage reduction unit 14, and an off-gate current adjustment unit 18, the details of which will be described later. The output stage circuit 110 includes an output stage circuit configured with a positive power supply PG1, a negative power supply PG2, a P-type MOSFET MG1, an N-type MOSFET MG2, and gate resistors RG1 and RG2, and is connected to a control unit 16 that controls this output stage circuit via an insulated communication unit ICV. The emitter control terminal ES of the semiconductor switching element 50 is connected to a reference potential VG0 at the connection point between the positive power supply PG1 and the negative power supply PG2.

[0160] As described above, the control unit 16 receives the command signal SIN transmitted from the higher-level control device (not shown), and controls the output stage circuit 110 via the insulated communication unit ICV based on the determination signal OCD1 from the second overcurrent determination unit 17. The control unit 16 may control the output stage circuit by logically combining the determination signal OCD1 with various abnormality detection signals such as overtemperature or power supply drop. The operation of the second overcurrent determination unit 17 will be described later.

[0161] The isolated communication unit ICV is configured to electrically insulate the input from the output and transmit an instruction signal from the input to the output, and receives an on / off command signal GDO generated by the control unit 16 and outputs it to the gates of the P-type MOSFET MG1 and the N-type MOSFET MG2 of the output stage circuit 110. The isolated communication unit ICV is configured by, for example, a photocoupler, but may be configured by means other than a photocoupler as long as it is configured to electrically insulate the input from the output and to transmit an instruction signal from the input to the output.

[0162] Although the example in which the output stage circuit 110 outputs a positive power supply potential VG1 or a negative power supply potential VG2 has been shown, a configuration without a negative power supply PG2, i.e., a configuration in which the negative power supply potential VG2 is equal to the reference potential VG0, is also possible. In this case, the output stage buffer of the output stage circuit 110 is shown to be a constant voltage drive using a P-type MOSFET MG1 and an N-type MOSFET MG2, with the switching speed adjusted by gate resistors RG1 and RG2, but this is not limiting. The output stage circuit 110 also has the same configuration as that described in the first embodiment.

[0163] The overcurrent protection unit 12 includes a first overcurrent determination unit 13 that determines an overcurrent flowing through the semiconductor switching element 50, a gate voltage reduction unit 14 that reduces the voltage applied to the gate terminal G of the semiconductor switching element 50 when an overcurrent is determined, and an off-gate current adjustment unit 18 that reduces the off-gate current of the semiconductor switching element 50. Note that while FIG. 21 simply shows the structure of the overcurrent protection unit 12b connected to the lower arm, as described above, the structure of the overcurrent protection unit 12a connected to the upper arm is similar to that of the overcurrent protection unit 12b. The first overcurrent determination unit 13b of the overcurrent protection unit 12b connected to the lower arm uses a determination signal OCD2b, and the first overcurrent determination unit 13a (not shown) of the overcurrent protection unit 12a connected to the upper arm uses a determination signal OCD2a.

[0164] Fig. 22 is a circuit configuration diagram showing details of overcurrent protection unit 12 according to embodiment 9. As described above, when overcurrent protection unit 12 is for the upper arm, the reference numerals of the parts in Fig. 22 are marked with "a", and when overcurrent protection unit 12 is for the lower arm, the reference numerals of the parts are marked with "b". 22, the overcurrent protection unit 12 includes a first overcurrent determination unit 13 that receives the detection signal SOC and outputs an overcurrent determination signal OCD2, and a gate voltage reduction unit 14 that reduces the gate voltage Vge based on the determination signal OCD2. The gate voltage reduction unit 14 also includes a drive circuit 141 that reduces the gate voltage Vge, and an amplifier circuit 142 that amplifies the output signal from the first overcurrent determination unit 13 to drive the drive circuit 141. The details of the circuit configuration and the basic operation of the overcurrent protection unit 12 are the same as those in the first embodiment. Same as Figure 2 Therefore, the description will be omitted here.

[0165] Next, the second overcurrent determining unit 17 will be described with reference to FIG. The second overcurrent determination unit 17 includes a first comparator VHD that determines whether the potential of the output terminal Ea of the power converter 20, which is made up of upper and lower arms, is near a positive electrode potential, and a second comparator VLD that determines whether the potential of the output terminal Ea is near a negative electrode potential. The second overcurrent determination unit 17 further includes a logic synthesis unit 171 that detects overcurrent in the semiconductor switching elements 50a and 50b based on the outputs of the first comparator VHD and the second comparator VLD and on / off command signals GDOa and GDOb that control the on / off of the semiconductor switching elements 50a and 50b, and outputs a determination signal OCD1 to the control unit 16. This will be described in detail below.

[0166] The potential at the connection point P0 is divided by resistors R173, R174, R175 and resistors R177, R178 and input as a reference voltage to the negative input terminal of the first comparator VHD, and the potential at the emitter control terminal ESa of the semiconductor switching element 50a is divided by resistors R170, R171, R172 and resistor R176 and input to the positive input terminal. The potential at the connection point P0 is divided by resistors R173, R174, R175, R178 and resistor R177 and input as a reference voltage to the positive input terminal of the second comparator VLD, and the potential at the emitter control terminal ESa of the semiconductor switching element 50a is divided by resistors R170, R171, R172 and resistor R176 and input to the negative input terminal.

[0167] Strictly speaking, the potential of the emitter control terminal ESa of the semiconductor switching element 50a is different from the potential of the output terminal Ea of the power converter 20. However, since they are equivalent in a steady state after the switching of the semiconductor switching element 50a is complete, the two will be treated as equivalent here, assuming that state. While the semiconductor switching element 50a of the upper arm is on, the potential of the output terminal Ea is the positive potential of a DC power supply (not shown), and while the semiconductor switching element 50b of the lower arm is on, the potential of the output terminal Ea is the negative potential of the DC power supply (not shown). Therefore, the potential of the emitter control terminal ESa or the potential of the output terminal Ea of the power converter 20 corresponds to the output potential of the leg circuit.

[0168] Furthermore, one end of the wiring to which the connection point P0 is connected is connected to the positive side of a DC power supply (not shown) and the other end is connected to the positive side of the upper arm, and the potential of the connection point P0 is the power supply potential, which corresponds to the positive-negative voltage of the leg circuit consisting of the upper and lower arms. Therefore, by generating the reference voltages of the first comparator VHD and the second comparator VLD from the main circuit power supply voltage, the robustness of the voltage determination accuracy against fluctuations in the main circuit power supply voltage is improved.

[0169] Here, resistors R170, R171, R172 and a capacitor C170 form a low-pass filter LF1. Also, bypass capacitors for stabilizing the reference voltages input to the negative input terminal of the first comparator VHD and the positive input terminal of the second comparator VLD are omitted.

[0170] The first comparator VHD and the second comparator VLD are configured as window comparators, and the first comparator VHD compares the reference voltage with the divided potential of the emitter control terminal ESa, and outputs a high (H) signal if the voltage is within the range of the set value. In other words, it determines that the potential of the emitter control terminal ESa is close to the positive potential. Similarly, the second comparator VLD compares the reference voltage with the divided potential of the emitter control terminal ESa, and if it is within the range of the set value, it outputs a high (H) signal, i.e., it determines that the potential of the emitter control terminal ESa is near the negative potential. The potential of the emitter control terminal ESa does not have to be the same as the power supply potential, and can be considered to be the power supply potential as long as it is within a certain range. Here, the term "nearby" is used because a potential within a predetermined range of the power supply potential can be considered to be that potential or near that potential. The setting value of the window comparator is set to a value that can be considered to be near that potential.

[0171] The outputs of the first comparator VHD and the second comparator VLD are input to the logic synthesis unit 171 and subjected to a logical operation with the input on / off command signals GDOa and GDOb. The on / off command signal GDOa for the upper arm is output in a state that is substantially inverted from the on / off command signal GDOb. Under normal circumstances, when the on / off command signal GDOa is output (high: H), the upper arm semiconductor switching element 50a is on and the potential of the emitter control terminal ESa is close to the positive potential of the DC power supply (not shown), so the output from the first comparator VHD is high. In this case, the logic synthesis unit 171 outputs the determination signal OCD1 as low (L).

[0172] Similarly, during normal operation, when the on / off command signal GDOb is output (high: H), the semiconductor switching element 50b of the lower arm is on and the potential of the emitter control terminal ESa is close to the negative potential of the DC power supply (not shown), so the output from the second comparator VLD is high. In this case, the logic synthesis unit 171 outputs the determination signal OCD1 as low (L).

[0173] If any other case continues for a predetermined time or longer, it is determined that an overcurrent has flowed in one of the arms, and the logic synthesis unit 171 outputs a high (H) determination signal OCD1 to the control unit 16. During the dead time and voltage transition period when the semiconductor switching elements 50a and 50b are switching, the on / off command signals GDOa and GDOb and the outputs of the first and second comparators VHD and VLD are in states different from those in the normal state described above. To avoid erroneously detecting this state as an overcurrent state, the flow of an overcurrent is determined based on whether or not the state continues for a predetermined time or longer.

[0174] When the control unit 16 receives the high (H) determination signal OCD1, it stops the operation of the power converter 20 without outputting the on / off command signals GDOa and GDOb. At this time, that is, when it is determined that an overcurrent has flowed through the arm, the determination signal OCD2 turns on the first transistor Q1 and the second transistor Q2, causing the collector potential of the second transistor Q2 to rise to the positive power supply potential VG1 and turning off the transistor Qg1, thereby increasing the resistance value R_OFFGI (RG3) of the off-gate current regulator 18. This is because the off-gate current generated when the control unit 16 turns off the semiconductor switching element 50b mainly flows through the resistor RG3 of the off-gate current regulator 18. Therefore, the power converter 20 performs soft shutdown.

[0175] FIG. 23 is a waveform diagram of each part showing the operation of the power conversion device 1 according to the ninth embodiment. The overcurrent protection operation of the power conversion device 1 will be described in detail below with reference to Figures 21, 22, and 23. Here, an example in which a fault occurs in the upper arm will be described, but an example in which a fault occurs in the lower arm can also be described in the same way, so a description thereof will be omitted. During normal operation before time t0, the lower arm outputs a gate voltage Vgeb in response to an ON / OFF command signal GDOb generated by a command signal SIN transmitted from a higher-level control device. The collector current Icb of the semiconductor switching element 50b and the collector voltage Vceb, which serves as the detection signal SOCb, also have waveforms corresponding to the ON / OFF command signal GDOb. When the semiconductor switching element 50b is in the OFF state, the base potential (input potential) VA1b of the first transistor Q1b, relative to the emitter control terminal ESb, is clamped to a potential (VG2b+Vf) obtained by adding the forward voltage Vf of the clamp diode D1b to the negative power supply potential VG2b. When the semiconductor switching element 50b is in the ON state, the collector voltage Vceb drops to several volts, and the voltage VA1b divided by resistors Rb (R1b, R2b, R3b) and R4b approaches the reference potential VG0b.

[0176] The potential of the determination signal OCD2b, ie, the base potential of the second transistor Q2b, is the same as the gate potential (positive power supply potential VG1b) when the semiconductor switching element 50b is in the ON state, and is pulled down to the negative power supply potential VG2b when the semiconductor switching element 50b is in the OFF state. Since the on / off command signal GDOa for the upper arm is substantially the inverse of the on / off command signal GDOb, the collector voltage Vcea serving as the detection signal SOCa of the semiconductor switching element 50a of the upper arm also has a waveform substantially the inverse of the collector voltage Vceb of the lower arm.

[0177] Under normal circumstances, when semiconductor switching element 50b is on, the resistance of resistor RG3 is sufficiently large, so that current flows mainly through diode Dg4, and when semiconductor switching element 50b is off, current flows through transistor Qg1, so that the resistance value R_OFFGI of off-gate current adjuster 18 is small. Note that under normal circumstances, transistor Qg1 of off-gate current adjuster 18 is on when semiconductor switching element 50b is off, and is in an on or off state depending on the base potential of transistor Qg1 when semiconductor switching element 50b is on. Therefore, in Figure 23, during normal circumstances before time t0, when semiconductor switching element 50b is on, transistor Qg1 is shown by a dotted line as being in an on state.

[0178] The output waveform of the second comparator VLD is a waveform that corresponds to the on / off command signal GDOb for the lower arm, and the output waveform of the first comparator VHD is a waveform that is inverted from the on / off command signal GDOb for the lower arm. That is, when the on / off command signal GDOb for the lower arm is high, the output waveform of the second comparator VLD is high and the output waveform of the first comparator VHD is low. When the on / off command signal GDOb for the lower arm is low, the output waveform of the second comparator VLD is low and the output waveform of the first comparator VHD is high. In FIG. 23, since the on / off duty of the semiconductor switching element is not 50%, the output waveform of the first comparator VHD and the output waveform of the second comparator VLD are not completely inverted in phase.

[0179] Assume that a fault occurs in the upper arm at time t0. At this time, the on / off command signal GDOa (not shown) for the upper arm transitions from high to low, turning off the semiconductor switching element 50a, and the collector voltage Vcea should be maintained at a high voltage. However, due to a fault (abnormal breakdown voltage) in the upper arm, the collector voltage Vcea begins to drop while it was rising. As a result, the output waveform of the first comparator VHD also drops in a pulse-like manner in response to the collector voltage Vcea.

[0180] After that, at time t11, the upper arm remains conductive due to the fault, so the lower arm on / off command signal GDOb goes high, turning on the semiconductor switching element 50b, and an overcurrent occurs due to an arm short circuit. As a result, the peak value Icbp of the collector current Icb saturates, and the collector voltage Vceb, which normally decreases, becomes high. This causes the base potential (input potential) VA1b of the first transistor Q1b to rise above the reference potential VG0b. Normally, the output of the first comparator VHD would switch low at this time, but the overcurrent keeps it high.

[0181] At time t12, the base potential (input potential) VA1b of the first transistor Q1b rises to 2Vf, i.e., when the above formula (1) is satisfied, the first transistor Q1b turns on. This detects an overcurrent in the semiconductor switching element 50b. When the first transistor Q1b turns on, the potential of the determination signal OCD2b drops, and when it drops from the positive power supply potential VG1b to a potential (VG1b-Vf) that is lower by the threshold voltage Vf of the second transistor Q2b, the second transistor Q2b turns on. This also raises the base potential of the third transistor Q3b, and a voltage equal to or greater than the threshold voltage Vf is applied to the base, turning the third transistor Q3b on. Then, the gate discharge current IAb flows and the gate voltage Vgeb decreases. At this time, the collector current Icb decreases from the peak value Icbp to a value Icba corresponding to the decreased gate voltage Vgeb, and a surge voltage Vsa occurs in the collector voltage Vceb.

[0182] Furthermore, when the second transistor Q2 turns on, the collector potential of the second transistor Q2 rises to the positive power supply potential VG1, and the base potential of the transistor Qg1 drops from the positive power supply potential VG1 to a potential (VG1 - Vf) that is a drop of the forward voltage of the diode Dg1. Meanwhile, the emitter of the transistor Qg1 drops to a potential that is a drop of the forward voltage of the diode Dg2, and the base of the transistor Qg1 is reverse-biased by Vf, turning the transistor Qg1 off. Therefore, the resistance value R_OFFGI of the off-gate current adjustment unit 18 increases (RG3).

[0183] At time t13, the second overcurrent determination unit 17 detects an overcurrent in the power converter 20, and the determination signal OCD1 becomes high. Between time t13 and time t14, the control unit 16 stops the operation of the power converter 20. Specifically, the ON / OFF command signals GDOa and GDOb are stopped, and the semiconductor switching elements 50a and 50b are turned off by performing a current interruption operation. At this time, a surge voltage Vsb is generated in the collector voltage Vceb. In order to stop the operation of the power converter 20, the control unit 16 applies an off-gate voltage to the gate terminals Ga and Gb of the semiconductor switching elements 50a and 50b. However, at time t12, the transistor Qg1 of the off-gate current adjusting unit 18 is in the off state, so the off-gate current flows through the resistor RG3, which has a large resistance value, and a soft shutdown is performed.

[0184] When the control unit 16 turns off the semiconductor switching element 50, if the gate voltage Vgeb is too large even after it has been reduced, a sudden current interruption may occur, raising concerns that a surge voltage may degrade the semiconductor switching element 50. For this reason, it is desirable to adjust the value of resistor R10 so that the surge voltage Vsa generated in the collector voltage Vce during the protection operation and the surge voltage Vsb generated in the collector voltage Vceb when the semiconductor switching element 50 is subsequently turned off are approximately the same.

[0185] Furthermore, when the control unit 16 turns off the semiconductor switching element 50, the off-gate current adjusting unit 18 increases the gate resistance to a value greater than that during normal off-state operation. This reduces the off-gate current and executes soft shutdown, thereby suppressing surge voltage during protection operation. As described in the first embodiment, it is desirable that the resistance value of resistor RG3 for performing soft shutdown be greater than the resistance value of resistor R10 of gate voltage reduction unit 14, and that the resistance value of resistor R10 be greater than the resistance value of gate resistor RG1 of output stage circuit 110.

[0186] 23, even though the on / off command signal GDOa has switched to low, the logic synthesis unit 171 of the second overcurrent determination unit 17 should output the determination signal OCD1 as high because the output waveform of the first comparator VHD has become low. However, in this embodiment, the determination signal OCD1 is generated at time t13, which is later than time t0. At time t0, the second overcurrent determination unit 17 detects an overcurrent in the power converter 20, causing the determination signal OCD1 to go high. When this occurs, the control unit 16 controls the semiconductor switching element 50 to turn off in order to shut down the power converter 20. This causes the above-described problem to occur. Specifically, the turning-off operation of the semiconductor switching element 50 and the operation of the overcurrent protection unit 12 to reduce the gate voltage to mitigate the overcurrent in the semiconductor switching element 50 occur simultaneously, causing the turn-off operation of the semiconductor switching element 50 to be faster than normal. This generates an excessive surge voltage. This excessive surge voltage may then cause secondary damage to the semiconductor switching element 50.

[0187] In this embodiment, the determination signal OCD1 that can be generated at time t0 is controlled to be delayed until time t13. This suppresses the generation of an excessive surge voltage, preventing secondary breakdown of the semiconductor switching element 50. In addition, since the off-gate current is reduced by the off-gate current adjusting unit 18, the speed of the turn-off operation is also suppressed.

[0188] Next, the timing at which the determination signal OCD1 is output will be described. (1) Delaying the output of the judgment signal OCD1 Since the first overcurrent judgment unit 13 and the second overcurrent judgment unit 17 of the overcurrent protection unit 12 each have a low-pass filter, one method is to make the time constant of the low-pass filter LF1 provided in the second overcurrent judgment unit 17 larger than the time constant of the low-pass filter of the first overcurrent judgment unit 13. The time constant and the like of the low-pass filter (R, C1) of the first overcurrent determination unit 13, together with the clamp diode D1, are set so as to suppress malfunction due to noise and perform overcurrent protection. Therefore, by making the time constant of the low-pass filter LF1 provided in the second overcurrent determination unit 17 larger than that, the generation of the determination signal OCD1 can be delayed from time t0. The method of delaying the generation of the determination signal OCD1 is not limited to adjusting the time constant. For example, the output of the determination signal OCD1 may be delayed by providing a signal mask circuit that inhibits output for a certain period of time in the logic synthesis unit 171 of the second overcurrent determination unit 17. The signal mask circuit may be, for example, a timer.

[0189] (2) Timing for outputting judgment signal OCD1 The determination signal OCD1 is output, the semiconductor switching element 50 is turned off, and the power converter 20 is stopped for a time period (short-circuit tolerance time) after the operation of lowering the gate voltage Vge of the semiconductor switching element 50 until the short-circuit tolerance of the semiconductor switching element 50 reaches the tolerance range. 23, this is the time after the collector current Icb has decreased from its peak value Icbp to the value Icba due to the gate voltage Vgeb being reduced by the gate voltage reduction operation. In other words, this is the time after the gate discharge current IAb starts to flow. For example, if the time from when an overcurrent occurs due to a fault (time t0) until the short-circuit resistance of the semiconductor switching element 50 is reached is 10 μs, the time (t13) at which the determination signal OCD1 is output is preferably about 7 or 8 μs. In this case, the secondary breakdown described above can be prevented by adjusting the timing at which the overcurrent protection unit 12 reduces the gate voltage of the semiconductor switching element 50 to about half that time, for example, about 3 or 4 μs.

[0190] As described above, after the first overcurrent determination unit 13 detects an overcurrent, the gate voltage reducing unit 14 maintains the operation of reducing the gate voltage Vge for a predetermined time, but it is desirable that the maintenance time exceed the time when the second overcurrent determination unit 17 determines an overcurrent. In other words, the state of reducing the gate voltage Vge is released before the time when the second overcurrent determination unit 17 determines an overcurrent, and an excessive short-circuit current is not generated again. Therefore, it is desirable that the predetermined time period for maintaining the state of reducing the gate voltage Vge be set to be longer than the time difference between the time when the first overcurrent determination unit 13 determines an overcurrent and the time when the second overcurrent determination unit 17 determines an overcurrent.

[0191] Furthermore, as described in the first embodiment, the clamp diode D1 and the low-pass filter (R, C1) function in the same manner. That is, in the ninth embodiment as well. By providing the clamp diode D1 that clamps the input potential VA1 to the gate potential, it is possible to prevent erroneous detection of an overcurrent due to noise when the semiconductor switching element 50 is in the off state. Furthermore, by providing the clamp diode D1 and the low-pass filter (R, C1), it is possible to suppress the above-mentioned erroneous detection of an overcurrent.

[0192] Also in this ninth embodiment, a backflow prevention diode D3 is provided to block current flowing in the reverse direction of the first transistor Q1, protecting the first transistor Q1 and applying a large negative bias (VG2+Vf) to the capacitor C1 without being affected by the protective diode D2. This improves the noise resistance of the first transistor Q1 and suppresses erroneous detection of overcurrent. Furthermore, an NPN bipolar transistor is used for the first transistor Q1, and a signal based on the input potential VA1 used for determination is input to the base, which provides current amplification, so that the first transistor Q1 can be operated effectively with a small signal input.

[0193] Furthermore, since the second overcurrent determination unit 17 uses the potential of the emitter control terminal ESa, which corresponds to the potential of the output terminal Ea of the power converter 20, the control unit 16 can confirm whether the output on-off command signal GDOa is being output with the correct pulse width. For example, it can compare the high period of the on-off command signal GDOa with the high period of the comparator VHD. Normally, the pulse width of the output voltage of the power converter 20 varies depending on the characteristics of the semiconductor switching elements and the circuit constants of the gate driver, but by comparing the high period of the on-off command signal GDOa generated by the control unit 16 with the high period of the output of the comparator VHD and feeding this back to the control unit 16, it is possible to generate an on-off command signal with the difference corrected. In other words, highly accurate control can be achieved.

[0194] In addition, the control unit 16 can divide and obtain the potential of the emitter control terminal ESa, which corresponds to the potential of the output terminal Ea of the power converter 20, via the second overcurrent judgment unit 17, so that it can detect abnormalities in the main withstand voltage of the semiconductor switching element.

[0195] For example, the logic synthesis unit 171 may be configured to detect a main withstand voltage anomaly based on the outputs of the comparators VHD and VLD during a period when both the upper-arm semiconductor switching element 50a and the lower-arm semiconductor switching element 50b, which are connected in series, are off, and transmit the detected anomaly to the control unit 16. That is, during a power converter stop period when neither on-off command signal GDOa nor GDOb is output, and when there is no need to detect an overcurrent state, the logic synthesis unit 171 is configured to set the determination signal OCD1 low when the outputs of the comparators VHD and VLD are low, and set OCD1 high otherwise. As a result, when there is no main withstand voltage anomaly, the potential of the output terminal Ea is set near the midpoint according to the ratio of the resistors provided in the semiconductor drive device 10. However, when a main withstand voltage anomaly occurs, the potential of the output terminal Ea becomes near the positive or negative side, so that the output of the comparator VHD or VLD becomes high, causing the determination signal OCD1 to become high, and this state can be identified as a state in which a main withstand voltage anomaly has occurred. As a specific determination method, a known method proposed by the applicant can be used (for example, International Publication No. 2024 / 004208).

[0196] As described above, the power conversion device of the ninth embodiment achieves the same effects as those of the first to seventh embodiments. Furthermore, the overcurrent determination by the first overcurrent determination unit precedes the overcurrent determination by the second overcurrent determination unit. When the second overcurrent determination unit determines an overcurrent, the control unit controls at least the semiconductor switching elements of the leg circuit determined to be experiencing an overcurrent to the off state. Therefore, the turning-off operation of the semiconductor switching elements to stop the power conversion device and the reducing operation of the gate voltage to mitigate the overcurrent of the semiconductor switching elements do not function simultaneously. Therefore, if both operations function simultaneously, the semiconductor switching elements' turn-off operation becomes faster than usual, generating an excessive surge voltage. This excessive surge voltage could potentially cause secondary damage to the semiconductor switching elements. However, this problem is eliminated. Therefore, this configuration protects the semiconductor switching elements and the power conversion device from overcurrent, providing a highly reliable power conversion device.

[0197] Furthermore, the first overcurrent judgment unit and the second overcurrent judgment unit each have a filter element that sets the time from when the signal input to each unit is in an overcurrent state until the first overcurrent judgment unit and the second overcurrent judgment unit judge that there is an overcurrent, so that the overcurrent judgment by the first overcurrent judgment unit can easily be made to precede the overcurrent judgment by the second overcurrent judgment unit through circuit design.

[0198] Furthermore, even if this power conversion device has a smoothing capacitor and a snubber capacitor, if an overcurrent is detected, the off-gate current when the semiconductor switching element is turned off is reduced and soft shutdown is performed, thereby making it possible to suppress voltage resonance and provide a highly reliable power conversion device.

[0199] In this case, the time constant of the first filter element provided in the second overcurrent judgment unit is larger than the time constant of the second filter element provided in the first overcurrent judgment unit, and the time from when an overcurrent state signal is input to when the first overcurrent judgment unit judges whether an overcurrent has occurred is set to be shorter than the short-circuit allowable time determined by the short-circuit withstand capability of the semiconductor switching element. This not only prevents the off operation of the semiconductor switching element to stop the power conversion device and the gate voltage reduction operation to alleviate the overcurrent of the semiconductor switching element from functioning simultaneously, but also makes it possible to stop (turn off) the semiconductor switching element within the short-circuit withstand capability of the semiconductor switching element, thereby providing a more reliable power conversion device.

[0200] Furthermore, when the first overcurrent judgment unit judges that an overcurrent has occurred, the gate voltage reduction unit continues to reduce the voltage applied to the control terminal of the semiconductor switching element for a predetermined period of time, and by setting this period to be longer than the time difference between when the first overcurrent judgment unit judges that an overcurrent has occurred and when the second overcurrent judgment unit judges that an overcurrent has occurred, it is possible to suppress the occurrence of surge voltage that also accompanies sudden fluctuations in the gate voltage.

[0201] In the power conversion device of the ninth embodiment, the second overcurrent determination unit uses the potential of the output terminal of the leg circuit to determine whether an overcurrent has occurred in the semiconductor switching element. Therefore, the control unit can generate an ON / OFF command signal with an adjusted pulse width based on the potential of the output terminal of the leg circuit. Furthermore, the first overcurrent determination unit can determine whether there is an abnormality in the main withstand voltage of the semiconductor switching element based on the potential of the output terminal of the leg circuit during a period when no ON / OFF command signal is being output. This makes it possible to provide a power conversion device that allows for highly accurate control.

[0202] Although the circuit configuration of overcurrent protection unit 12 is shown in FIG. 22 as being similar to that of FIG. 2 in embodiment 1, it may also be similar to that of overcurrent protection unit 12 shown in FIG. 4 in embodiment 1, overcurrent protection unit 12A shown in FIG. 6 in embodiment 2, or overcurrent protection unit 12B shown in FIG. 7 in embodiment 3. Since the operation is similar to each other, a description thereof will be omitted. Even with such a configuration, the same effect as that of embodiment 9 can be achieved.

[0203] Embodiment 10 The power conversion device according to the tenth embodiment will be described below with reference to the drawings. 24 is a diagram showing the configuration of a power conversion device 1 according to a tenth embodiment. In the tenth embodiment, a second overcurrent determination unit 17A having a circuit configuration different from that of the second overcurrent determination unit 17 of the ninth embodiment is used. Note that the overcurrent protection unit 12 is the same as that of the ninth embodiment, and therefore a description thereof will be omitted.

[0204] In the second overcurrent judgment unit 17 of the above-mentioned embodiment 9, the power supply voltage of the DC power supply, which is the potential at the connection point P0, is used as the reference voltage. However, in this embodiment, the second overcurrent judgment unit 17A is provided with a reference voltage generation unit 172, and one comparator VHLD is configured to judge whether the potential at the output terminal Ea is near the positive electrode potential or near the negative electrode potential.

[0205] 24, the reference voltage generator 172 receives the on / off command signals GDOa and GDOb from the controller 16, and switches between outputting a reference voltage for determining whether the potential is near the positive electrode potential and a reference voltage for determining whether the potential is near the negative electrode potential, depending on the state of the input on / off command signals GDOa and GDOb. That is, when the on / off command signal GDOa is high, the reference voltage for determining whether the potential is near the positive electrode potential is output to the negative input terminal of the comparator VHLD. When the on / off command signal GDOb is high, the reference voltage for determining whether the potential is near the negative electrode potential is output to the negative input terminal of the comparator VHLD. The potential of the emitter control terminal ESa of the semiconductor switching element 50a is divided by resistors R170, R171, and R172 and resistor R176 and input to the positive input terminal of the comparator VHLD. As described above, the potential of the emitter control terminal ESa corresponds to the potential of the output terminal Ea of the power converter 20.

[0206] The comparator VHLD is configured to switch the reference voltage using the reference voltage generation unit 172 instead of a window comparator, and compares the reference voltage with the divided potential of the emitter control terminal ESa. A reference voltage for determining proximity to a positive electrode potential is input, and if the potential of the emitter control terminal ESa is within a set value range, the comparator determines that the potential of the emitter control terminal ESa is near a positive electrode potential and outputs a high (H) signal. Also, a reference voltage for determining proximity to a negative electrode potential is input, and if the reference voltage is within a set value range, the comparator determines that the potential of the emitter control terminal ESa is near a negative electrode potential and outputs a low (L) signal.

[0207] Specifically, the timing for detecting a short circuit in the upper arm is limited to when the upper arm is on, i.e., when the on / off command signal GDOa is high, and during this period there is no need to detect a short circuit in the lower arm. Therefore, while the upper arm is on, the setting value of the comparator VHLD is set to a high-level value Vrefa close to the positive electrode potential. If the potential is between the positive electrode potential and Vrefa, it is determined that the potential of the emitter control terminal ESa is near the positive electrode potential. If it does not reach Vrefa, the logic synthesis unit 171 determines that a short circuit has occurred. Conversely, while the lower arm is on, the setting value of the comparator VHLD is set to a low-level value Vrefb close to the negative electrode potential. If the potential is between the negative electrode potential and Vrefb, it is determined that the potential of the emitter control terminal ESa is near the negative electrode voltage. If it is not within that range, the logic synthesis unit 171 determines that a short circuit has occurred.

[0208] The output of the comparator VHLD is input to a logic synthesis unit 171, and is subjected to a logical operation with the input on / off command signals GDOa and GDOb. Under normal circumstances, when the on / off command signal GDOa is output (high: H), the output voltage of the power converter 20 is the output voltage from the upper arm, i.e., the potential of the emitter control terminal ESa is close to the positive voltage, so the output from the comparator VHLD is high. In this case, the logic synthesis unit 171 outputs the determination signal OCD1 as low (L). Similarly, when the on / off command signal GDOb is output (high: H), the output voltage of the power converter 20 is the output voltage from the lower arm, i.e., the potential of the emitter control terminal ESa is near the negative voltage, so the output from the comparator VHLD is low. In this case, the logic synthesis unit 171 outputs the determination signal OCD1 at low (L). In other cases, it is determined that an overcurrent has flowed in one of the arms, and the logic synthesis unit 171 outputs a high (H) determination signal OCD1 to the control unit 16.

[0209] When the control unit 16 receives the determination signal OCD1 at high (H), it does not output the on / off command signals GDOa and GDOb, and stops the operation of the power converter 20.

[0210] In this second overcurrent determining unit 17A, a resistor R179 and a capacitor C170 form a low-pass filter LF2. Here, as in the ninth embodiment, the output of the determination signal OCD1 is delayed. That is, the time constant of the low-pass filter LF2 included in the second overcurrent determination unit 17A is made larger than the time constant of the low-pass filter included in the first overcurrent determination unit 13. Alternatively, a signal mask circuit such as a timer is provided in the logic synthesis unit 171. As a result, after the first overcurrent judgment unit 13 makes a judgment, the gate voltage of the semiconductor switching element 50 is reduced, and then the second overcurrent judgment unit 17A can stop the semiconductor switching element 50, thereby preventing the semiconductor switching element 50 from being destroyed by an excessive surge voltage.

[0211] FIG. 25 is a waveform diagram of each part showing the operation of the power conversion device 1 according to the tenth embodiment. The following description will focus on the differences from FIG. 23 of the ninth embodiment, and overlapping points will be omitted. Under normal conditions before time t0, the signal of the comparator VHLD is inverted to the on / off command signal GDOb. In other words, when the on / off command signal GDOb is high, the comparator VHLD is low, and it is determined that the potential of the emitter control terminal ESa is near the negative voltage.

[0212] Assume that a fault occurs in the upper arm at time t0. At this time, the on / off command signal GDOa (not shown) for the upper arm transitions from high to low, turning off the semiconductor switching element 50a, and the collector voltage Vcea should be maintained at a high voltage. However, due to a fault (abnormal breakdown voltage) in the upper arm, the collector voltage Vcea begins to drop while it was rising. As a result, the output waveform of the comparator VHLD also drops in a pulse-like manner in response to the collector voltage Vcea.

[0213] After that, at time t11, because the upper arm remains conductive due to the fault, the lower arm on / off command signal GDOb goes high, turning on the semiconductor switching element 50b, and an overcurrent occurs due to an arm short circuit. As a result, the peak value Icbp of the collector current Icb saturates, and the collector voltage Vceb, which normally decreases, becomes high. This causes the emitter potential (input potential) VA2b of the first transistor Q1b to rise to 2Vf, exceeding the reference potential VG0b. Normally, the output of the comparator VHLD would switch low at this time, but the overcurrent keeps it high.

[0214] After that, at time t12, the first overcurrent determination unit 13 detects an overcurrent in the semiconductor switching element 50b, and the gate voltage Vgeb is reduced by the gate voltage reduction unit 14. At that time, the collector current Ic decreases from the peak value Icbp to a value Icba corresponding to the reduced gate voltage Vgeb, and a surge voltage Vsa is generated in the collector voltage Vceb.

[0215] Furthermore, when the second transistor Q2 turns on, the collector potential of the second transistor Q2 rises to the positive power supply potential VG1, and the base potential of the transistor Qg1 drops from the positive power supply potential VG1 to a potential (VG1 - Vf) that is a drop from the positive power supply potential VG1 by the forward voltage of the diode Dg1. Meanwhile, the base emitter of the transistor Qg1 drops to a potential that is a drop by the forward voltage of the diode Dg2, and the base of the transistor Qg1 is reverse-biased by Vf, turning the transistor Qg1 off. Therefore, the resistance value R_OFFGI of the off-gate current adjustment unit 18 increases (RG3).

[0216] At time t13, the second overcurrent determination unit 17A detects an overcurrent in the power converter 20, and the determination signal OCD1 becomes high. Between time t13 and time t14, the control unit 16 stops the operation of the power converter 20. Specifically, the ON / OFF command signals GDOa and GDOb are stopped, and the semiconductor switching elements 50a and 50b are turned off by performing a current interruption operation. At this time, a surge voltage Vsb is generated in the collector voltage Vceb.

[0217] In order to stop the operation of the power converter 20, the control unit 16 applies an off-gate voltage to the gate terminals Ga and Gb of the semiconductor switching elements 50a and 50b. However, at time t12, the transistor Qg1 of the off-gate current adjusting unit 18 is in the off state, so the off-gate current flows through the resistor RG3, which has a large resistance value, and a soft shutdown is performed.

[0218] Furthermore, when the control unit 16 turns off the semiconductor switching element 50, the off-gate current adjusting unit 18 increases the gate resistance to a value greater than that during normal off-state operation, thereby reducing the off-gate current and implementing soft shutdown, thereby suppressing surge voltage during protection operation. As described in the first embodiment, it is desirable that the resistance value of resistor RG3 for performing soft shutdown be greater than the resistance value of resistor R10 of gate voltage reduction unit 14, and that the resistance value of resistor R10 be greater than the resistance value of gate resistor RG1 of output stage circuit 110.

[0219] As in the ninth embodiment, the second overcurrent determination unit 17A uses the potential of the emitter control terminal ESa, which corresponds to the potential of the output terminal Ea of the power converter 20. This allows the control unit 16 to confirm whether the output on-off command signal GDOa is being output with the correct pulse width. For example, the high period of the on-off command signal GDOa can be compared with the high period of the comparator VHLD. The pulse width of the output voltage of the power converter 20 typically varies depending on the characteristics of the semiconductor switching elements and the circuit constants of the gate driver, but the control unit 16 can compare the high period of the on-off command signal GDOa it generates with the high period of the output of the comparator VHLD and feed this back to the control unit 16 to correct the difference.

[0220] Furthermore, similar to the ninth embodiment, the control unit 16 can divide and acquire the potential of the emitter control terminal ESa, which corresponds to the potential of the output terminal Ea of the power converter 20, via the second overcurrent judgment unit 17A, and therefore can detect an abnormality in the main withstand voltage of the semiconductor switching element.

[0221] For example, the logic synthesis unit 171 may be configured to detect a main withstand voltage anomaly based on the output of the comparator VHLD during a period when both the upper-arm semiconductor switching element 50a and the lower-arm semiconductor switching element 50b, which are connected in series, are off, and transmit the detected anomaly to the control unit 16. That is, during a power converter stop period when neither on-off command signal GDOa nor GDOb is output, and when there is no need to detect an overcurrent state, the logic synthesis unit 171 is configured to set the determination signal OCD1 low when the output of the comparator VHLD is low, and set OCD1 high when the output of the comparator VHLD is high. As a result, when there is no main withstand voltage anomaly, the potential of the output terminal Ea is set near the midpoint according to the ratio of the resistors provided in the semiconductor drive device 10. However, when a main withstand voltage anomaly occurs, the potential of the output terminal Ea becomes near the positive or negative side, so that the output of the comparator VHLD becomes high, causing the determination signal OCD1 to become high, and this state can be identified as a state in which a main withstand voltage anomaly has occurred. As a specific determination method, a known method proposed by the applicant can be used (for example, International Publication No. 2024 / 004208).

[0222] As described above, the tenth embodiment can also achieve the same effects as the ninth embodiment. That is, the determination signal OCD1 that can be generated at time t0 is controlled to be delayed until time t13, and the off-gate current adjusting unit 18 increases the gate resistance when the control unit 16 turns off the semiconductor switching element 50 compared to when the element is normally off. This reduces the off-gate current and executes soft shutdown, thereby suppressing the occurrence of excessive surge voltage and preventing secondary breakdown of the semiconductor switching element 50. Furthermore, even if this power conversion device includes a smoothing capacitor and a snubber capacitor, if an overcurrent is detected, voltage resonance can be suppressed by reducing the off-gate current when the semiconductor switching element is off and executing soft shutdown. This makes it possible to provide a highly reliable power conversion device.

[0223] In addition, in embodiment 10, the overcurrent protection unit 12 is not limited to that of embodiment 9, i.e., the same configuration as that of FIG. 2 of embodiment 1 shown in FIG. 22, but may be the same configuration as that of overcurrent protection unit 12 shown in FIG. 4 of embodiment 1, overcurrent protection unit 12A shown in FIG. 6 of embodiment 2, or overcurrent protection unit 12B shown in FIG. 7 of embodiment 3, and the same effect can be achieved by applying these.

[0224] Embodiment 11 The power conversion device according to the eleventh embodiment will be described below with reference to the drawings. In the above ninth and tenth embodiments, the collector voltage Vce of the semiconductor switching element 50 is detected from the collector sense terminal CS to be used as the detection signal SOC, but in this embodiment, a different detection signal SOC is used. FIG. 26 is a diagram showing a schematic configuration of a power conversion device 1 according to the eleventh embodiment. In this embodiment 11, the semiconductor switching element 50Ab has a current detection element on the emitter side through which a current reduced to, for example, several thousandths flows, and the reduced emitter current Ieeb flowing from the current detection terminal EEb is used as the detection signal SOCb. The upper arm semiconductor switching element 50Aa also includes a current detection element and a current detection terminal EEa, and a duplicated description will be omitted below.

[0225] As shown in FIG. 26, the power conversion device 1 includes a power converter 20A and a semiconductor driver 10J that drives semiconductor switching elements of the power converter 20A. The semiconductor driver 10J includes a control unit 16, insulated communication units ICVa and ICVb, output stage circuits 110a and 110b, overcurrent protection units 12Ca and 12Cb, and a second overcurrent determination unit 17. The overcurrent protection units 12Ca and 12Cb include a first overcurrent determination unit 13C that outputs an overcurrent determination signal OCD2 based on the emitter current Iee (detection signal SOC), and a gate voltage reduction unit 14 that reduces the gate voltage Vge based on the determination signal OCD2. The output stage circuits 110a and 110b and the gate voltage reduction unit 14 are the same as those in the ninth embodiment. The overcurrent protection units 12Ca and 12Cb are the same circuit as the overcurrent protection unit 12C shown in FIG. 8 of the fourth embodiment. The first overcurrent determination unit 13C also has a circuit configuration similar to that of the first overcurrent determination unit 13 of the ninth embodiment, although it handles a different detection signal SOC. It also has a circuit configuration similar to that of the first overcurrent determination unit 13C of the fourth embodiment shown in FIG. 8, which handles the same detection signal SOC, and operates in the same manner.

[0226] FIG. 27 is a waveform diagram of each part showing the operation of the power conversion device 1 according to the eleventh embodiment. In FIG. 27, it is assumed that the device operates normally before time t0, and that a fault such as a voltage resistance abnormality occurs in the upper arm at time t0. In FIG. 27, the emitter current Ieeb that becomes the detection signal SOCb is connected to the base of the first transistor Q1b and becomes the base current that is input to the base. When an overcurrent occurs while the semiconductor switching element 50Ab is on (time t11), the emitter current Ieeb (detection signal SOCb) rises and exceeds a preset threshold value IX, turning on the first transistor Q1b. This detects an overcurrent in the semiconductor switching element 50Ab. Except for the use of the emitter current Ieeb as the detection signal SOCb, the operating waveforms of each part are the same as those shown in FIG. 23 of the ninth embodiment.

[0227] In the eleventh embodiment, the same effects as those of the ninth embodiment can be obtained. In addition, although the present invention is applicable only to semiconductor switching elements 50 equipped with current detection elements, it is possible to detect overcurrent with higher accuracy because it detects the current value itself and determines overcurrent without needing to come into contact with a high-voltage section.

[0228] In addition, in Figure 26, an example is described in which the power conversion device 1 of embodiment 11 is equipped with the second overcurrent judgment unit 17, but it goes without saying that the second overcurrent judgment unit 17A described in embodiment 10 can also be applied.

[0229] Embodiment 12 The power conversion device according to the twelfth embodiment will be described below with reference to the drawings. In the twelfth embodiment, a detection signal SOC that is different from the detection signal SOC used in the ninth and tenth embodiments and the detection signal SOC used in the eleventh embodiment is used.

[0230] FIG. 28 is a diagram showing a schematic configuration of a power conversion device 1 according to the twelfth embodiment. In this embodiment 12, the emitter voltage VEe between the emitter E, which is the low-voltage side main terminal of the semiconductor switching element 50B, and the emitter control terminal ES is used as the detection signal SOC. This utilizes the electromotive force (Le·dIc / dt) generated across the parasitic inductance Le on the emitter side.

[0231] As shown in FIG. 28, the power conversion device 1 includes a power converter 20B and a semiconductor driving device 10K that drives the semiconductor switching elements of the power converter 20B. The semiconductor driving device 10K includes a control unit 16, insulated communication units ICVa and ICVb, output stage circuits 110a and 110b, overcurrent protection units 12a and 12b, and a second overcurrent determination unit 17. The overcurrent protection units 12a and 12b include a first overcurrent determination unit 13D that outputs an overcurrent determination signal OCD2 based on an emitter voltage VEe (detection signal SOC), and a gate voltage reduction unit 14 that reduces a gate voltage Vge based on the determination signal OCD2. The other configurations are the same as those in the ninth embodiment. The overcurrent protection units 12Da and 12Db are the same circuit as the overcurrent protection unit 12D shown in FIG. 10 of the fifth embodiment.

[0232] The first overcurrent determining unit 13D also has a circuit configuration similar to that of the first overcurrent determining unit 13 of the ninth embodiment, although it handles a different detection signal SOC. However, while in the above-described ninth embodiment the entire overcurrent protection unit 12 was configured with the potential of the emitter control terminal ES as the reference, in this embodiment only the first overcurrent determination unit 13 in the overcurrent protection unit 12D is configured with the potential of the emitter E as the reference, and the rest are configured with the potential of the emitter control terminal ES as the reference. That is, the emitter control terminal ES is connected to the high-voltage side of resistor R1, and the emitter voltage VEe (detection signal SOC) from emitter E is connected to the low-voltage side of resistor R4. This is similar to the operation of the first overcurrent determination unit 13D shown in FIG. 10 of the fifth embodiment, which handles the same detection signal.

[0233] FIG. 29 is a waveform diagram of each part showing the operation of the power conversion device 1 according to the twelfth embodiment. Also in FIG. 29, it is assumed that the device operates normally before time t0, and that a fault such as a voltage resistance abnormality occurs in the upper arm at time t0. In FIG. 29, the emitter voltage VEeb, which becomes the detection signal SOCb, has a waveform similar to the differential value (dIcb / dt) of the collector current Ic. When an overcurrent occurs while the semiconductor switching element 50Bb is on, the emitter voltage VEeb (detection signal SOCb) drops, and when it drops below a set threshold VX, the first transistor Q1b turns on. This detects an overcurrent in the semiconductor switching element 50Bb. Except for the use of the emitter voltage VEeb as the detection signal SOCb, the operating waveforms of the various components are the same as those shown in FIG. 23 of the ninth embodiment.

[0234] In the present embodiment 12, the same effects as those in the above-described embodiment 9 can be obtained. Moreover, by utilizing the electromotive force generated in the parasitic inductance Le on the emitter side, it is possible to acquire current information quickly and accurately and detect an overcurrent without providing a current detection element.

[0235] In the above embodiment, the emitter voltage VEe is compared with the threshold value VX, which serves as the determination voltage. However, the voltage amplitude (Le·dIc / dt) of the emitter voltage VEe may be integrated using an integrating circuit to obtain information similar to the collector current Ic and to determine whether an overcurrent exists.

[0236] In Figure 28, an example is described in which the power conversion device 1 of embodiment 12 is equipped with the second overcurrent judgment unit 17, but it goes without saying that the second overcurrent judgment unit 17A described in embodiment 10 can also be applied.

[0237] Embodiment 13 The power conversion device according to the thirteenth embodiment will be described below with reference to the drawings. In the thirteenth embodiment, a signal obtained by detecting the rate of change of current between the main terminals and converting it into a voltage is used as the detection signal SOC. FIG. 30 is a diagram showing a schematic configuration of a power conversion device 1 according to the thirteenth embodiment. 30, a current-voltage conversion element CT is provided on the outside of an emitter E, which is one of the main terminals of a semiconductor switching element 50C. The current-voltage conversion element CT detects the rate of change of a collector current Ic, which is a current between the main terminals, and outputs voltage information Vct (detection signal SOC). The current-voltage conversion element CT is, for example, a Rogowski coil formed on a printed circuit board that constitutes the overcurrent protection unit 12E.

[0238] As shown in FIG. 30, the power conversion device 1 includes a power converter 20C and a semiconductor driving device 10L that drives a semiconductor switching element of the power converter 20C. The semiconductor driving device 10 includes a control unit 16, insulated communication units ICVa and ICVb, output stage circuits 110a and 110b, overcurrent protection units 12Ea and 12Eb, and a second overcurrent determination unit 17. The overcurrent protection units 12Ea and 12Eb include a first overcurrent determination unit 13E that outputs an overcurrent determination signal OCD2 based on voltage information Vct (detection signal SOC), and a gate voltage reduction unit 14 that reduces the gate voltage Vge based on the determination signal OCD2. The other configurations are the same as those in the ninth embodiment. The overcurrent protection units 12Ea and 12Eb are the same circuit as the overcurrent protection unit 12E shown in FIG. 12 of the sixth embodiment.

[0239] The first overcurrent determination unit 13E also has a circuit configuration similar to that of the first overcurrent determination unit 13 of the above-mentioned embodiment 9, although it handles a different detection signal SOC. It also has a circuit configuration similar to that of the first overcurrent determination unit 13E of embodiment 6 shown in FIG. 12 that handles the same detection signal SOC, and operates in the same manner.

[0240] FIG. 31 is a waveform diagram of each part showing the operation of the power conversion device 1 according to the thirteenth embodiment. In FIG. 31, it is assumed that the device operates normally before time t0, and that a fault such as a voltage resistance abnormality occurs in the upper arm at time t0. In FIG. 31, the voltage information Vctb that becomes the detection signal SOCb has a waveform similar to the differential value (dIcb / dt) of the collector current Icb. When an overcurrent occurs while the semiconductor switching element 50Cb is on (time t11), the voltage information Vctb (detection signal SOCb) rises, and when it exceeds the set threshold VXa (time t2), the first transistor Q1b turns on. This detects an overcurrent in the semiconductor switching element 50Cb. Except for using the voltage information Vctb as the detection signal SOCb, the operating waveforms of each part are the same as those shown in FIG. 23 of the ninth embodiment.

[0241] In the thirteenth embodiment, the same effects as those in the ninth embodiment can be obtained. Moreover, by mounting the overcurrent protection unit 12E on a printed circuit board and using a Rogowski coil (current-voltage conversion element CT) formed on the printed circuit board, it is possible to achieve non-contact, highly accurate overcurrent detection.

[0242] In addition, in Figure 30, an example is described in which the power conversion device 1 of embodiment 13 is equipped with the second overcurrent judgment unit 17, but it goes without saying that the second overcurrent judgment unit 17A described in embodiment 10 can also be applied.

[0243] Embodiment 14 The power conversion device according to the fourteenth embodiment will be described below with reference to the drawings. In the above-described ninth embodiment, as shown in Fig. 22, a low-pass filter (R, C1) is provided at the input part of the detection signal SOC of the first overcurrent determination unit 13. In the fourteenth embodiment, a first low-pass filter and a second low-pass filter are provided as low-pass filters of the first overcurrent determination unit 13F.

[0244] FIG. 32 is a diagram showing a schematic configuration of a power conversion device 1 according to a fourteenth embodiment. 32, the power conversion device 1 includes a power converter 20 and a semiconductor driving device 10M that drives a semiconductor switching element of the power converter 20. The semiconductor driving device 10M includes a control unit 16, insulated communication units ICVa and ICVb, output stage circuits 110a and 110b, overcurrent protection units 12Fa and 12Fb, and a second overcurrent determination unit 17. The overcurrent protection units 12Fa and 12Fb include a first overcurrent determination unit 13F that determines an overcurrent flowing through the semiconductor switching element 50, and a gate voltage reduction unit 14 that reduces the voltage applied to the gate terminal G of the semiconductor switching element 50 when an overcurrent is determined. The control unit 16, the insulated communication units ICVa and ICVb, the output stage circuits 110a and 110b, and the gate voltage reduction unit 14 are the same as those in the ninth embodiment.

[0245] The first overcurrent determining unit 13F according to the fourteenth embodiment includes a first transistor Q1, a clamp diode D1, a blocking diode D3, a resistor R, capacitors C1a and C1b, and a diode DL. In this case, a first low-pass filter (R, C1a) is formed by the resistor R and the capacitor C1a, and a second low-pass filter (R, C1b) is formed by the resistor R and the capacitor C1b. Then, a detection signal SOC based on the collector voltage Vce, which is the voltage between the main terminals of the semiconductor switching element 50, is input to the first transistor Q1 via the first low-pass filter (R, C1a) and the second low-pass filter (R, C1b), and an overcurrent determination signal OCD2 is output. The circuit configuration of the overcurrent protection unit 12F according to the fourteenth embodiment is the same as that shown in FIG. 15 of the seventh embodiment, and the operation is similar, so detailed description thereof will be omitted.

[0246] The capacitor C1a of the first low-pass filter (R, C1a) is configured to have a small capacitance, and the capacitor C1b of the second low-pass filter (R, C1b) is configured to have a large capacitance. When the semiconductor switching element 50 is in the off state, the capacitor C1a of the first low-pass filter (R, C1a) is negatively biased. When the semiconductor switching element 50 is turned on and the capacitor C1a recovers from the negative bias state, it takes time to recover if the capacitance of the capacitor C1a is large. Here, the capacitance of the capacitor C1a is set small, so the capacitor C1a recovers from the negative bias quickly, and overcurrent detection can be achieved within a specified delay time. The first low-pass filter (R, C1a) functions in the same manner as the low-pass filter (R, C1) described in the first and ninth embodiments, and suppresses erroneous detection of an overcurrent.

[0247] If the second low-pass filter (R, C1b) is not provided, i.e., in the same case as in the first embodiment, when the semiconductor switching element 50 is in the on state, the first low-pass filter (R, C1a) having a small capacitance capacitor C1a alone will have low resistance to current noise. In this case, the provision of the second low-pass filter (R, C1b) having a large capacitance capacitor C1b makes it possible to suppress erroneous detection of overcurrent due to current noise, even when the semiconductor switching element 50 is in the on state.

[0248] FIG. 33 is a waveform diagram of each part showing the operation of the power conversion device 1 according to the fourteenth embodiment. In FIG. 33 as well, it is assumed that operation is normal before time t0, and that a fault such as a voltage resistance abnormality occurs in the upper arm at time t0. 33, the operating waveforms other than the base potential (input potential) VA1b of the first transistor Q1b with respect to the emitter control terminal ESb are the same as those shown in Fig. 23 of the above-mentioned embodiment 9. Note that the VA1b waveform in the case of the above-mentioned embodiment 9 is indicated by a dotted line.

[0249] During normal operation before time t0, the base potential (input potential) VA1b of the first transistor Q1b is clamped to a potential (VG2+Vf) obtained by adding the forward voltage Vf of the clamp diode D1 to the negative power supply potential VG2b when the semiconductor switching element 50b is in the off state. Also, when the semiconductor switching element 50b is in the on state, the collector voltage Vceb drops to several volts, and the voltage VA1b divided by the resistors Rb (R1b, R2b, R3b) and R4b becomes close to the reference potential VG0b. In this case, since a small-capacity capacitor C1ab is used in the first low-pass filter (Rb, C1ab) clamped by the clamp diode D1b, the period in which the base potential (input potential) VA1b returns from the negative bias when the semiconductor switching element 50b transitions from the off state to the on state is shortened.

[0250] At time t0, a fault such as a voltage resistance abnormality occurred in the upper arm. At time t11, the upper arm remains conductive due to a fault, so if an overcurrent occurs due to an arm short circuit at the time the semiconductor switching element 50b is turned on, the peak value Icbp of the collector current Icb will saturate, and the collector voltage Vceb, which normally decreases, will become high. Here too, after the semiconductor switching element 50b is turned on, the base potential (input potential) VA1b quickly recovers from the negative bias and further rises beyond the reference potential VG0b.

[0251] At time t12, the base potential (input potential) VA1b of the first transistor Q1b rises to 2Vf, i.e., when the above formula (1) is satisfied, the first transistor Q1b turns on. As a result, an overcurrent in the semiconductor switching element 50b is detected. When the first transistor Q1b turns on, the second transistor Q2b and the third transistor Q3b turn on. Then, the gate discharge current IAb flows and the gate voltage Vgeb decreases. At this time, the collector current Icb decreases from the peak value Icbp to a value Icba corresponding to the decreased gate voltage Vgeb, and a surge voltage Vsa occurs in the collector voltage Vceb.

[0252] Furthermore, when the second transistor Q2 turns on, the collector potential of the second transistor Q2 rises to the positive power supply potential VG1, and the base potential of the transistor Qg1 drops from the positive power supply potential VG1 to a potential (VG1 - Vf) that is a drop of the forward voltage of the diode Dg1. Meanwhile, the emitter of the transistor Qg1 drops to a potential that is a drop of the forward voltage of the diode Dg2, and the base of the transistor Qg1 is reverse-biased by Vf, turning the transistor Qg1 off. Therefore, the resistance value R_OFFGI of the off-gate current adjustment unit 18 increases (RG3).

[0253] In this embodiment, as in the above-described ninth embodiment, at time t13, the second overcurrent determination unit 17 detects an overcurrent in the power converter 20, and the determination signal OCD1 goes high. Between time t13 and time t14, the control unit 16 stops the operation of the power converter 20. Specifically, the ON / OFF command signals GDOa and GDOb are stopped, and the semiconductor switching elements 50a and 50b are turned off by performing a current interruption operation. At this time, a surge voltage Vsb is generated in the collector voltage Vceb.

[0254] In this embodiment, the time constant of the low-pass filter LF1 included in the second overcurrent determination unit 17 is set to be larger than both the first low-pass filter (R, C1a) and the second low-pass filter (R, C1b) of the overcurrent protection unit 12F. As a result, after the gate voltage is reduced by the overcurrent protection unit 12F, a current cut-off operation is performed on the semiconductor switching element 50 in response to a determination signal OCD1 from the second overcurrent determination unit 17. In order to stop the operation of the power converter 20, the control unit 16 applies an off-gate voltage to the gate terminals Ga and Gb of the semiconductor switching elements 50a and 50b. However, at time t12, the transistor Qg1 of the off-gate current adjusting unit 18 is in the off state, so the off-gate current flows through the resistor RG3, which has a large resistance value, and a soft shutdown is performed.

[0255] In this embodiment, as in the above-described ninth embodiment, the overcurrent protection unit 12F does not require a power supply for itself, but can detect and protect the semiconductor switching element 50 from an overcurrent by utilizing the threshold voltage of the first transistor Q1. Furthermore, the clamp diode D1, the first low-pass filter (R, C1a), and the second low-pass filter (R, C1b) work together to suppress malfunctions due to noise and provide overcurrent protection. As a result, even when the semiconductor switching element 50 and the output stage circuits 110a, 110b or gate drive unit 11 of the semiconductor drive device 10M are arranged at a distance from each other, the overcurrent protection unit 12F, which does not require a power supply, can be arranged close to the semiconductor switching element 50, thereby enabling overcurrent protection to be performed with high reliability.

[0256] 32 has been described as an example in which the second overcurrent determination unit 17 of the power conversion device 1 of the fourteenth embodiment is provided, but it goes without saying that the second overcurrent determination unit 17A described in the tenth embodiment can also be applied. In this case, too, the time constant of the low-pass filter LF2 provided in the second overcurrent determination unit 17A is set to be larger than both the first low-pass filter (R, C1a) and the second low-pass filter (R, C1b) of the overcurrent protection unit 12F.

[0257] In the above-described ninth to fourteenth embodiments, an example was shown in which the overcurrent protection unit includes an off-gate current adjustment unit. When the overcurrent protection unit is mounted on a single board, the overcurrent protection unit does not have a power supply and can adjust the off-gate resistance and perform soft shutdown based on a signal from the first overcurrent determination unit. The board on which this overcurrent protection unit is mounted corresponds to each arm of the power converter and can be used as a common board on which the overcurrent protection unit is mounted. Furthermore, a single gate driver can control multiple semiconductor switching elements and the overcurrent protection unit. Therefore, the board can be shared, which reduces costs and eliminates the need to adjust the board constants for each board, thereby improving the performance of the power conversion device.

[0258] Embodiment 15 In the above-mentioned ninth to fourteenth embodiments, an example was shown in which the overcurrent protection unit includes an off-gate current adjustment unit, but in this embodiment, an example in which the gate driver includes an off-gate current adjustment unit will be described. FIG. 34 is a block diagram showing a schematic configuration of a power conversion device 1 according to a fifteenth embodiment. As shown in FIG. 34, the power conversion device 1 includes a power converter 20 that supplies power to a load 70 and a semiconductor driving device 10N that drives a semiconductor switching element of the power converter 20. The semiconductor driving device 10N includes a second overcurrent determination unit 17, a control unit 16 that receives a command signal SIN transmitted from a higher-level control device (not shown) and generates an ON / OFF command signal for the semiconductor switching element based on the signal from the second overcurrent determination unit 17, a gate driving unit 11N that includes an output stage circuit 110A that applies a voltage to the semiconductor switching element to drive it based on the ON / OFF command signal input via an insulated communication unit ICV, and an overcurrent protection unit 12G that detects and protects the semiconductor switching element from an overcurrent. Next, a detailed circuit configuration will be described with reference to FIG. 35.

[0259] FIG. 35 is a diagram showing a circuit configuration of a main part of a power conversion device according to the fifteenth embodiment. 35, output stage circuit 110A includes an off-gate current adjusting section 18G and a protection operation detecting section 19. Note that although both output stage circuits 110Aa and 110Ab include an off-gate current adjusting section 18G and a protection operation detecting section 19, the circuit configurations and operations of output stage circuits 110Aa and 110Ab are similar, and therefore only the circuit configuration of output stage circuit 110Ab will be shown and described in detail here. The off-gate current adjusting unit 18G includes an N-type MOSFET MG3b connected between the N-type MOSFET MG2b and the gate resistor RG2b, and a resistor RG4b connected in parallel to the series circuit of the gate resistor RG2b and the N-type MOSFET MG3b. The resistance value of the resistor RG4b is set to be larger than the resistance value of the gate resistor RG2b (RG4b>RG2b).

[0260] Normally, when turning on the semiconductor switching element 50b, the control unit 16 turns on the P-type MOSFET MG1b based on the on / off command signal GDOb, and an on-gate current flows from the gate resistor RG1b toward the gate terminal Gb. Normally, when turning off the semiconductor switching element 50b, the control unit 16 turns on the N-type MOSFET MG2b based on the on / off command signal GDOb, and the off-gate current flows from the gate terminal Gb mainly toward the gate resistor RG2b. In addition, under normal circumstances, the N-type MOSFET MG3b is always on.

[0261] When an overcurrent is detected in either arm of power converter 20, overcurrent protection unit 12G reduces gate voltage Vgeb, and when this is detected, protection operation detection unit 19b inputs signal GSDb to the gate of N-type MOSFET MG3b. Here, N-type MOSFET MG3b is preset so that the input of signal GSDb changes its gate from high to low. Therefore, input of signal GSDb turns off N-type MOSFET MG3b.

[0262] Furthermore, it is determined that an overcurrent has flowed in either arm, and the logic synthesis unit 171 outputs a high (H) determination signal OCD1 to the control unit 16. When the high (H) determination signal OCD1 is input, the control unit 16 does not output the on / off command signals GDOa and GDOb, and stops the operation of the power converter 20.

[0263] At this time, that is, when it is determined that an overcurrent has flowed through the arm, the N-type MOSFET MG3b is turned off in response to the input of signal GSDb. Therefore, when the N-type MOSFET MG2b is turned on, the off-gate current flows from the gate terminal Gb toward resistor RG4b. As described above, the resistance value of resistor RG4b is greater than the resistance of gate resistor RG2b, through which the off-gate current flows under normal conditions, so the off-gate current is reduced and soft shutdown is performed. In other words, when it is determined that an overcurrent has flowed through the arm, the resistance value R_OFFGI of off-gate current adjuster 18G becomes greater (RG4b) than it is under normal conditions (RG2b).

[0264] The operation of the off-gate current adjusting section 18G of the output stage circuit 110A is similar to the operation of the off-gate current adjusting section 18G in the gate driving section 11G of the eighth embodiment shown in FIG. Moreover, the circuit configuration of the overcurrent protection unit 12G is the same as that shown in FIG. 18 of the eighth embodiment, and the operation is the same, so a description thereof will be omitted.

[0265] FIG. 36 is a waveform diagram of each part showing the operation of the power conversion device 1 according to the fifteenth embodiment. Hereinafter, details of the overcurrent protection operation by the power conversion device 1 will be described with reference to Figures 35 and 36. Here, an example in which a fault occurs in the upper arm will be described, but an example in which a fault occurs in the lower arm can also be described in the same way, so a description thereof will be omitted. During normal operation before time t0, the lower arm outputs a gate voltage Vgeb in response to an ON / OFF command signal GDOb generated by a command signal SIN transmitted from a higher-level control device. The collector current Icb of the semiconductor switching element 50b and the collector voltage Vceb, which serves as the detection signal SOCb, also have waveforms corresponding to the ON / OFF command signal GDOb. When the semiconductor switching element 50b is in the OFF state, the base potential (input potential) VA1b of the first transistor Q1b, relative to the emitter control terminal ESb, is clamped to a potential (VG2b+Vf) obtained by adding the forward voltage Vf of the clamp diode D1b to the negative power supply potential VG2b. When the semiconductor switching element 50b is in the ON state, the collector voltage Vceb drops to several volts, and the voltage VA1b divided by resistors Rb (R1b, R2b, R3b) and R4b approaches the reference potential VG0b.

[0266] The potential of the determination signal OCD2b, ie, the base potential of the second transistor Q2b, is the same as the gate potential (positive power supply potential VG1b) when the semiconductor switching element 50b is in the ON state, and is pulled down to the negative power supply potential VG2b when the semiconductor switching element 50b is in the OFF state. Since the on / off command signal GDOa for the upper arm is substantially the inverse of the on / off command signal GDOb, the collector voltage Vcea serving as the detection signal SOCa of the semiconductor switching element 50a of the upper arm also has a waveform substantially the inverse of the collector voltage Vceb of the lower arm.

[0267] The output waveform of the second comparator VLD is a waveform that corresponds to the on / off command signal GDOb for the lower arm, and the output waveform of the first comparator VHD is a waveform that is inverted from the on / off command signal GDOb for the lower arm. That is, when the on / off command signal GDOb for the lower arm is high, the output waveform of the second comparator VLD is high and the output waveform of the first comparator VHD is low. When the on / off command signal GDOb for the lower arm is low, the output waveform of the second comparator VLD is low and the output waveform of the first comparator VHD is high.

[0268] Assume that a fault occurs in the upper arm at time t0. At this time, the on / off command signal GDOa (not shown) for the upper arm transitions from high to low, turning off the semiconductor switching element 50a, and the collector voltage Vcea should be maintained at a high voltage. However, due to a fault (abnormal breakdown voltage) in the upper arm, the collector voltage Vcea begins to drop while it was rising. As a result, the output waveform of the first comparator VHD also drops in a pulse-like manner in response to the collector voltage Vcea.

[0269] After that, at time t11, the upper arm remains conductive due to the fault, so the lower arm on / off command signal GDOb goes high, turning on the semiconductor switching element 50b, and an overcurrent occurs due to an arm short circuit. As a result, the peak value Icbp of the collector current Icb saturates, and the collector voltage Vceb, which normally decreases, becomes high. This causes the base potential (input potential) VA1b of the first transistor Q1b to rise above the reference potential VG0b. Normally, the output of the first comparator VHD would switch low at this time, but the overcurrent keeps it high.

[0270] At time t12, the base potential (input potential) VA1b of the first transistor Q1b rises to 2Vf, i.e., when the above formula (1) is satisfied, the first transistor Q1b turns on. This detects an overcurrent in the semiconductor switching element 50b. When the first transistor Q1b turns on, the potential of the determination signal OCD2b drops, and when it drops from the positive power supply potential VG1b to a potential (VG1b-Vf) that is lower by the threshold voltage Vf of the second transistor Q2b, the second transistor Q2b turns on. This also raises the base potential of the third transistor Q3b, and a voltage equal to or greater than the threshold voltage Vf is applied to the base, turning the third transistor Q3b on. Then, the gate discharge current IAb flows and the gate voltage Vgeb decreases. At this time, the collector current Icb decreases from the peak value Icbp to a value Icba corresponding to the decreased gate voltage Vgeb, and a surge voltage Vsa occurs in the collector voltage Vceb.

[0271] At time t13, the protection operation detector 19b detects a drop in the gate voltage Vgeb and generates a signal GSDb. Also, the second overcurrent detector 17 detects an overcurrent in the power converter 20 and the determination signal OCD1 goes high. Between time t13 and time t14, the control unit 16 stops the operation of the power converter 20. Specifically, the ON / OFF command signals GDOa and GDOb are stopped, and the semiconductor switching elements 50a and 50b are turned off by performing a current interruption operation.

[0272] To stop the operation of the power converter 20, the control unit 16 applies an off-gate voltage to the gate terminals Ga and Gb of the semiconductor switching elements 50a and 50b. At this time, a signal GSDb from the protection operation detection unit 19b is input to the gate of the N-type MOSFET MG3b, turning off the N-type MOSFET MG3b. An off-gate current flows from the gate terminal Gb toward the resistor RG4b. When the control unit 16 performs the cutoff operation on the semiconductor switching element 50, the off-gate current flows through the resistor RG4b, which has a large resistance, so the off-gate current is reduced compared to normal, and a soft cutoff is performed.

[0273] During this current interruption operation, a surge voltage Vsb occurs in the collector voltage Vceb. As described above, it is desirable to set the resistor R10 to satisfy the above formula (2) so that the surge voltage Vsb is approximately the same as the preceding surge voltage Vsa. Furthermore, when the gate voltage is reduced, the off-gate current is also reduced, resulting in soft shutdown. Therefore, even if the power conversion device 1 has a smoothing capacitor and a snubber capacitor, resonance between the capacitors is suppressed when the semiconductor switching element is shut off, and a semiconductor drive device with highly reliable overcurrent protection can be provided. Furthermore, when a common substrate on which the arm and the overcurrent protection unit are mounted is used, the substrate size is limited, and if the substrate area is small, the constraints on the substrate size can be met by providing the off-gate current adjustment unit 18G in the gate drive unit 11N, as in this embodiment.

[0274] Moreover, the circuit configuration of overcurrent protection unit 12G of the present embodiment is similar to that shown in Fig. 18 of embodiment 8, and operates in the same manner, but is not limited to this. It may be overcurrent protection unit 12 shown in Fig. 4 of embodiment 1 minus the configuration of off-gate current adjustment unit 18A, it may be overcurrent protection unit 12A shown in Fig. 6 of embodiment 2 minus off-gate current adjustment unit 18, it may be overcurrent protection unit 12B shown in Fig. 7 of embodiment 3 minus off-gate current adjustment unit 18, or it may be overcurrent protection unit 12F shown in Fig. 15 of embodiment 7 equipped with first overcurrent determination unit 13F and minus off-gate current adjustment unit 18.

[0275] Furthermore, the circuit configuration of overcurrent protection unit 12G in this embodiment may be such that power converter 20 has the circuit configuration of power converter 20A shown in Figure 26 of embodiment 11, and the overcurrent protection unit is overcurrent protection unit 12C of Figure 26 without the configuration of off-gate current adjustment unit 18, or power converter 20 has the circuit configuration of power converter 20B shown in Figure 28 of embodiment 12, and the overcurrent protection unit is overcurrent protection unit 12D of Figure 28 without the configuration of off-gate current adjustment unit 18, or power converter 20 has the circuit configuration of power converter 20C shown in Figure 30 of embodiment 13, and the overcurrent protection unit is overcurrent protection unit 12E of Figure 30 without the configuration of off-gate current adjustment unit 18.

[0276] In this embodiment, the second overcurrent determining unit 17 included in the semiconductor driving device 10N may be the second overcurrent determining unit 17A shown in FIG. 24 of the tenth embodiment.

[0277] Embodiment 16 FIG. 37 is a diagram illustrating a configuration of a power conversion device according to the sixteenth embodiment. 37, the power conversion device 1 includes a power converter 20X configured with a plurality of semiconductor switching elements 50, and a semiconductor driving device 10X that drives each of the semiconductor switching elements 50 in the power converter 20X. In this case, the power conversion device 1 is an inverter that converts DC power from a DC power source 60 into AC power and supplies it to a load 70 (AC motor). The semiconductor driving devices 10, 10C, 10D, 10E, 10F, and 10G according to the first to eighth embodiments are provided for each semiconductor switching element 50, and a group of the individual semiconductor driving devices 10 is referred to as a semiconductor driving device 10X of this embodiment. Furthermore, the semiconductor driving devices 10H, 10I, 10J, 10K, 10L, 10M, and 10N according to the above-mentioned embodiments 9 to 15 are provided for each upper and lower arm, i.e., each leg circuit, and a collection of these semiconductor driving devices 10 is referred to as the semiconductor driving device 10X of this embodiment.

[0278] The power converter 20X is an inverter circuit having a three-phase (U, V, W) configuration and including a smoothing capacitor 40, a snubber capacitor 45, and leg circuits 23 for each phase between DC buses. The leg circuits 23 for each phase are configured by connecting upper arms 21A and lower arms 22A in series, each of which has a semiconductor switching element 50.

[0279] In this sixteenth embodiment, each semiconductor switching element 50 in the power converter 20X is driven by a semiconductor driving device 10X that employs the semiconductor driving device according to any one of the first to fifteenth embodiments, so that the semiconductor switching elements 50 can be highly reliably protected from overcurrent without requiring an additional power supply. Therefore, even when the semiconductor switching elements 50 and the gate driving unit of the semiconductor driving device 10X are disposed apart, the semiconductor switching elements 50 can be highly reliably protected from overcurrent, thereby providing an inexpensive and highly reliable power conversion device 1.

[0280] Although the power converter 20X has been described as outputting two-level AC voltages, positive and negative, it may instead be an inverter capable of outputting multilevel voltages in which any number of semiconductor switching elements 50 are connected in series and parallel. In this case, the power converter 20X also has a configuration including a leg circuit 23 in which an upper arm 21A and a lower arm 22A each having a semiconductor switching element 50 are connected in series.

[0281] FIG. 38 is a diagram illustrating a configuration of a power conversion device according to another example of the sixteenth embodiment. In FIG. 38, the power conversion device 1 includes a power converter 20Y configured with a plurality of semiconductor switching elements 50, and a semiconductor driving device 10Y that drives each of the semiconductor switching elements 50 in the power converter 20Y. In this case, the power conversion device 1 operates as a boost converter that boosts the DC voltage of a DC power supply 60 and supplies it to a DC load 70A. As described above, the semiconductor driving device 10Y may be a collection of individual semiconductor driving devices 10 that drive each of the semiconductor switching elements 50, or may be a semiconductor driving device 10 that drives a leg circuit 23A.

[0282] The power converter 20Y includes an input-side smoothing capacitor 41, a snubber capacitor 46, an output-side smoothing capacitor 42, a leg circuit 23A, and a boost reactor 43. The leg circuit 23A is configured by connecting in series an upper arm 21B and a lower arm 22B, each of which has a semiconductor switching element 50.

[0283] In this case, too, the semiconductor switching element 50 can be reliably protected from overcurrent without the need for an additional power supply. Therefore, even when the semiconductor switching element 50 and the gate drive unit of the semiconductor drive device 10 are disposed apart, the semiconductor switching element 50 can be reliably protected from overcurrent, thereby providing an inexpensive and highly reliable power conversion device 1.

[0284] Although the above example shows a boost converter, the present invention can also be applied to a step-down converter or a step-up / step-down converter that combines a step-up converter and a step-down converter. Furthermore, a wide bandgap semiconductor material may be used for the semiconductor switching element 50, which can speed up the switching operation of the semiconductor switching element 50 and reduce the size of the boost reactor 43. As the wide bandgap semiconductor material, any of silicon carbide (SiC), gallium nitride, gallium oxide-based materials, and diamond can be used.

[0285] FIG. 39 is a diagram illustrating a configuration of a power conversion device according to still another example of the sixteenth embodiment. In FIG. As shown in Fig. 39, power conversion device 1 includes a main circuit (power converter) in which power converter 20Y shown in Fig. 38 is connected to the DC side of power converter 20X shown in Fig. 37, and semiconductor driving device 10Z that drives each semiconductor switching element 50. In this case, power conversion device 1 boosts the DC voltage of DC power supply 60 using power converter 20Y, and the boosted DC power is converted into AC power by power converter 20X and supplied to load 70 (AC motor).

[0286] This power conversion device 1 operates as a boost inverter system and is applied to, for example, an electric vehicle. In this case, too, the semiconductor switching element 50 can be highly reliably protected from overcurrent without requiring an additional power supply. Therefore, even when the semiconductor switching element 50 and the gate drive unit of the semiconductor drive device 10X are disposed apart, the semiconductor switching element 50 can be protected from overcurrent, thereby providing an inexpensive and highly reliable power conversion device 1.

[0287] Even in the configuration of the power conversion device having a smoothing capacitor and a snubber capacitor as shown in FIGS. 37 to 39, it is possible to protect the semiconductor switching elements from an overvoltage when an overcurrent occurs. Furthermore, it goes without saying that even in a power conversion device that does not have a snubber capacitor, the semiconductor driving device according to this embodiment can provide overcurrent protection for semiconductor switching elements.

[0288] The power converter 20X in the power conversion device 1 may be an inverter capable of outputting multilevel voltages. Furthermore, the power converter 20Y in the power conversion device 1 is not limited to a boost converter, but may also be a buck converter or a buck-boost converter that combines a boost converter and a buck converter.

[0289] Although the semiconductor switching element 50 is an IGBT in the drawing, it may be another semiconductor switching element having a control terminal, such as a MOSFET.

[0290] Furthermore, a multi-gate type semiconductor switching element having a plurality of gate terminals may be used as the semiconductor switching element. An example of a power conversion device 1 using a double-gate semiconductor switching element 50wG is shown in Fig. 40. The power conversion device 1 in Fig. 40 uses, for example, the semiconductor driving device 10 according to the first embodiment as the semiconductor driving device 10, and as described in the first embodiment, the semiconductor driving device 10 includes a gate driving unit 11 and an overcurrent protection unit 12 arranged between the double-gate semiconductor switching element 50wG and the gate driving unit 11. As shown in FIG. 40, the double-gate semiconductor switching element 50wG has two gate terminals G1 and G2, and by controlling the on / off timing of the two gate terminals G1 and G2, it has advantages such as improved turn-off speed.

[0291] In the above-described single-gate semiconductor switching element, when an overcurrent is detected by the first overcurrent determination unit 13, the gate voltage Vge is reduced by the gate voltage reduction unit 14, thereby reducing the collector current Ic. Since the double-gate semiconductor switching element 50wG can independently control the gate terminals G1 and G2, it is sufficient to control the voltage applied to each gate terminal and reduce the voltage applied to the double-gate semiconductor switching element 50wG. For example, when an overcurrent is detected, one of the gate terminals can be reduced to a value equal to or lower than the gate threshold voltage Vth, or one of the gate terminals can be turned off, thereby reducing the gate voltage Vge applied to the double-gate semiconductor switching element 50wG and reducing the collector current Ic.

[0292] Similarly, when a multi-gate semiconductor switching element is used, at least one gate terminal can be reduced to a value equal to or lower than the gate threshold voltage Vth or at least one gate terminal can be turned off when an overcurrent is detected, thereby reducing the gate voltage Vge applied to the multi-gate semiconductor switching element and reducing the collector current Ic. In this way, by using a semiconductor switching element with multiple gates, it becomes possible to precisely control the gate voltage when an overcurrent occurs.

[0293] Furthermore, the off-gate current adjusting unit 18 can reduce the off-gate current flowing through each gate terminal, allowing for more precise soft shutdown. Also, if the degree of reduction in the gate voltage Vge of each gate differs, it is possible to perform soft shutdown in accordance with the degree of reduction.

[0294] The power conversion device 1 of FIG. 40 is not limited to the semiconductor driving device 10 according to the first embodiment, and any of the semiconductor driving devices 10, 10C, 10D, 10E, 10F, and 10G according to the second to seventh embodiments may be applied. 40 shows an example in which the overcurrent protection unit 12 includes the off-gate current adjusting unit 18, but the off-gate current adjusting unit 18 may be included in the gate driving unit 11. In this case, the semiconductor driving device 10G according to the eighth embodiment may be applied to the power conversion device 1 in FIG.

[0295] Another example of a power conversion device 1 using a double-gate semiconductor switching element 50wG is shown in Fig. 41. The power conversion device 1 in Fig. 41 uses, for example, the semiconductor driving device 10H according to the ninth embodiment as the semiconductor driving device 10. As described in the ninth embodiment, the semiconductor driving device 10 includes a gate driving unit 11 and an overcurrent protection unit 12 arranged between the switching element 50wG and the gate driving unit 11.

[0296] 41 shows the semiconductor switching element of one arm as the configuration of power converter 20 of power conversion device 1, and shows a simplified view of power conversion device 1 as a whole, but it goes without saying that, as in embodiment 9, double-gate type semiconductor switching element 50wG or multi-gate type semiconductor switching element may be used as the switching element used in power converter 20. When an overcurrent flowing through double-gate type semiconductor switching element 50wG is detected, overcurrent protection unit 12 reduces the gate voltage applied to two gate terminals G1, G2, and power converter 20 is stopped by the output of second overcurrent determination unit 17. The operation and effect of the semiconductor driver 10 in FIG. 41 are the same as those in FIG. 40, so a description thereof will be omitted.

[0297] The power conversion device 1 of FIG. 41 is not limited to the semiconductor driving device 10H according to the ninth embodiment, and any of the semiconductor driving devices 10I, 10J, 10K, 10L, and 10M according to the tenth to fourteenth embodiments may be applied. 41 shows an example in which the overcurrent protection unit 12 includes the off-gate current adjustment unit 18, but the off-gate current adjustment unit 18 may be included in the gate drive unit 11. In this case, the power conversion device 1 in FIG. 41 applies the semiconductor drive device 10N according to the fifteenth embodiment, and includes a protection operation detection unit 19 in the gate drive unit 11. Furthermore, in the power conversion device 1 of FIG. 41, the second overcurrent determining unit 17 may be the second overcurrent determining unit 17A shown in the tenth embodiment.

[0298] Furthermore, the power converter 1 shown in FIGS. 38 to 40 can also be configured using double-gate type semiconductor switching elements or multi-gate type semiconductor switching elements as the semiconductor switching elements 50. Although the double-gate semiconductor switching element 50wG is illustrated as an IGBT, it may be another semiconductor switching element having a gate terminal, such as a MOSFET.

[0299] An example of the hardware configuration of the control unit 16 of the power conversion device 1 according to the above-described first to sixteenth embodiments is shown in Fig. 42. As shown in Fig. 42, the control unit 16 includes, for example, a processor 1000 and a storage device 1100 as processing circuits.

[0300] The processor 1000 may include a CPU (Central Processing Unit), an ASIC (Application Specific Integrated Circuit), an IC (Integrated Circuit), an FPGA (Field Programmable Gate Array), various logic circuits, various signal processing circuits, etc. Furthermore, a plurality of processors 1000 of the same type or different types may be provided, and each process may be shared and executed.

[0301] The storage device 1100 includes a RAM (Random Access Memory) configured to allow data to be read from and written to the processor 1000, and a ROM (Read Only Memory) configured to allow data to be read from the processor 1000. The processor 1000 executes a program input from the storage device 1100 such as a ROM.

[0302] While the present disclosure describes various exemplary embodiments and examples, the various features, aspects, and functions described in one or more embodiments are not limited to application to a particular embodiment, but may be applied to the embodiments alone or in various combinations. Therefore, countless variations not exemplified are conceivable within the scope of the technology disclosed in this specification, including, for example, cases where at least one component is modified, added, or omitted, and cases where at least one component is extracted and combined with components of another embodiment. [Explanation of symbols]

[0303] 1: power conversion device; 10, 10C, 10D, 10E, 10F, 10G, 10H, 10I, 10J, 10K, 10L, 10M, 10N, 10X, 10Y, 10Z: semiconductor drive device; 11, 11G, 11H, 11N: gate drive unit; 110, 110a, 110A, 110Aa, 110Ab, 110b: output stage circuit; 12, 12a, 12b, 12A, 12B, 12C, 12Ca, 12D, 12Da, 12E, 12Ea, 12F, 12Fa, 12G: overcurrent protection unit; 13, 13a, 13b, 13A, 13B, 13C, 13D, 13E, 13F: first overcurrent determination unit; 14, 14A: Gate voltage reduction unit, 15: Connection wiring, 16: Control unit, 17, 17A: Second overcurrent determination unit, 18, 18A, 18G: Off-gate current adjustment unit, 141, 141A: Drive circuit, 142, 142A: Amplification circuit, 19, 19b: Protection operation detection unit, 20, 20A, 20B, 20C, 20X, 20Y: Power converter, 21A, 21B: Upper arm, 22A, 22B: Lower arm, 23, 23A: Leg circuit, 40, 41, 42: Smoothing capacitor, 45, 46: Snubber capacitor, 50, 50A, 50B, 50a, 50b, 50Aa, 50Ab, 50Bb, 50C, 50Cb, 50wG: Semiconductor switching element, 60: DC power supply, 70, 70A: load, 171: logic synthesis unit, ICV, ICVa, ICVb: insulated communication unit, CS: collector sense terminal, CT: current-voltage conversion element, D1, D1b: clamp diode, D3, Dg1, Dg2, Dg5: reverse current prevention diode, EEa, EEb: current detection terminal, ES: emitter control terminal, G, Ga, Gb, G1, G2: gate terminal, OCD1, OCD2a, OCD2b: judgment signal, Q1, Q1b: first transistor, Q2, Q2b: second transistor, Q3, Q3b: third transistor, VA1, VA2: input potential, (R, C1): low-pass filter, (R, C1a): first low-pass filter, (R, C1b): second low-pass filter, CRD: constant current diode, (CRD, C1): low-pass filter, LF1, LF2: low-pass filter, Qg1: transistor, RG1, RG1b, RG2, RG2b: gate resistors, R10, RG3, RG4,RG4b: resistor, Dg3: protection diode, Dg4: diode, VHD: first comparator, VLD: second comparator, VHLD: comparator, GDO, GDOa, GDOb: on / off command signal.

Claims

1. a gate driver that applies a voltage to a control terminal of a semiconductor switching element to turn the semiconductor switching element on and off; an overcurrent protection unit for protecting the semiconductor switching element, the overcurrent protection unit having a first overcurrent determination unit that receives a detection signal based on a voltage current between main terminals of the semiconductor switching element and determines an overcurrent flowing through the semiconductor switching element, a gate voltage reduction unit that reduces the voltage applied to the control terminal when the overcurrent is determined, and an off-gate current adjustment unit that adjusts an off-gate current flowing between the gate driver unit and the control terminal when the semiconductor switching element is turned off by the gate driver unit, the first overcurrent determination unit includes a clamp diode that clamps the potential of a signal input unit that is an input unit for the detection signal to the potential of the control terminal, a first transistor to which the signal input unit is connected, and a low-pass filter that is provided in the signal input unit, and when the potential of the signal input unit reaches a set value, the first transistor is turned on to determine an overcurrent in the semiconductor switching element; The off-gate current adjusting unit reduces the off-gate current of the semiconductor switching element to a value lower than normal after the voltage applied to the control terminal is reduced by the gate voltage reducing unit to a value lower than a predetermined value.

2. a gate driver that applies a voltage to a control terminal of a semiconductor switching element to turn the semiconductor switching element on and off; an overcurrent protection unit that protects the semiconductor switching element, the overcurrent protection unit having a first overcurrent determination unit that receives a detection signal based on a voltage current between main terminals of the semiconductor switching element and determines an overcurrent flowing through the semiconductor switching element, and a gate voltage reduction unit that reduces the voltage applied to the control terminal when an overcurrent is determined, the first overcurrent determination unit includes a clamp diode that clamps the potential of a signal input unit that is an input unit for the detection signal to the potential of the control terminal, a first transistor to which the signal input unit is connected, and a low-pass filter that is provided in the signal input unit, and when the potential of the signal input unit reaches a set value, the first transistor is turned on to determine an overcurrent in the semiconductor switching element; the gate driver includes a protection operation detector that detects when the voltage applied to the control terminal is reduced below a preset value, and an off-gate current adjuster that adjusts an off-gate current flowing between the gate driver and the control terminal when turning off the semiconductor switching element, The semiconductor driving device, wherein, based on a signal from the protection operation detection unit, the off-gate current adjustment unit reduces the off-gate current compared to when the semiconductor switching element is normal, and maintains the semiconductor switching element in an off state.

3. 2. The semiconductor driving device according to claim 1, wherein the off-gate current adjusting unit has a parallel body in which a second transistor and a first resistor are connected in parallel, the parallel body being arranged between the gate driving unit and the control terminal of the semiconductor switching element, and a first backflow prevention diode is connected to the control terminal of the second transistor, and when an overcurrent determination signal is input by the first overcurrent determination unit via the first backflow prevention diode, or when a signal in which the voltage applied to the control terminal of the semiconductor switching element is reduced by the gate voltage reducing unit is input via the first backflow prevention diode, the second transistor is turned off and the off-gate current flows through the first resistor.

4. 4. The semiconductor driving device according to claim 3, further comprising a second backflow prevention diode on the emitter side of said second transistor.

5. the gate voltage reducing unit has a series body in which a second resistor and a third transistor are connected in series, and in response to an overcurrent determination signal from the first overcurrent determination unit, the third transistor is turned on to discharge accumulated charges from the control terminal of the semiconductor switching element via the second resistor, thereby reducing the voltage applied to the control terminal of the semiconductor switching element; 4. The semiconductor driving device according to claim 3, wherein the resistance value of the second resistor is smaller than the resistance value of the first resistor of the off-gate current adjusting section.

6. 6. The semiconductor driving device according to claim 5, wherein a value of the second resistance of the gate voltage reducing unit is greater than a resistance value of an on-gate resistor that limits the on-gate current of the gate driving unit.

7. the off-gate current adjusting unit includes a second transistor connected in series to an off-gate resistor that limits the off-gate current of the gate driver, and a parallel circuit in which a first resistor is connected in parallel to the series circuit of the off-gate resistor and the second transistor, and a resistance value of the first resistor is greater than a resistance value of the off-gate resistor; 3. The semiconductor driving device according to claim 2, wherein the second transistor is turned off based on a signal from the protection operation detection unit, and the off-gate current flows through the first resistor.

8. 8. A semiconductor driving device according to claim 1, wherein the low-pass filter of the signal input section comprises a first low-pass filter that is clamped to the potential of the control terminal of the semiconductor switching element by the clamp diode, and a second low-pass filter that has a capacitance larger than that of the first low-pass filter and is not clamped to the potential of the control terminal of the semiconductor switching element.

9. 8. The semiconductor driving device according to claim 1, wherein the clamp diode clamps the potential of the input section of the detection signal to the potential of the control terminal when the semiconductor switching element is in an OFF state.

10. 8. The semiconductor driving device according to claim 1, wherein the gate voltage reducing unit comprises a driving circuit that reduces the voltage applied to the control terminal of the semiconductor switching element, and an amplifier circuit that amplifies the output signal from the first overcurrent determining unit to drive the driving circuit.

11. the amplifier circuit of the gate voltage reduction unit has a fourth transistor, and the drive circuit of the gate voltage reduction unit has a third transistor; the first transistor, the third transistor, and the fourth transistor are each a bipolar transistor, and when the first transistor is turned on, the fourth transistor is turned on, and then the third transistor is turned on, so that the base currents of the first transistor, the fourth transistor, and the third transistor increase in this order; a main terminal current of the third transistor reduces a voltage applied to a control terminal of the semiconductor switching element; The semiconductor driving device according to claim 10.

12. The first overcurrent determination unit a voltage between the main terminals of the semiconductor switching element; a current detected by a current detection element for detecting a main terminal current of the semiconductor switching element or a small current similar thereto; a voltage generated between the low-voltage side main terminal and the control reference terminal of the semiconductor switching element; and a detection signal based on a signal obtained by converting a rate of change of a main terminal current of the semiconductor switching element into a voltage, thereby determining whether an overcurrent has occurred in the semiconductor switching element.

8. The semiconductor driving device according to claim 1.

13. The semiconductor switching element is a multi-gate type semiconductor switching element having at least two control terminals, 8. The semiconductor driving device according to claim 1, wherein the gate voltage reducing unit reduces the voltage of at least one control terminal of the multi-gate type semiconductor switching element to a gate threshold voltage or less when an overcurrent is determined by the first overcurrent determining unit.

14. a power converter including at least one leg circuit in which an upper arm and a lower arm each having the semiconductor switching element are connected in series; A power conversion device comprising the semiconductor driving device according to any one of claims 1 to 7 for driving each of the semiconductor switching elements.

15. a power converter having at least one leg circuit in which the semiconductor switching elements are connected in series; and the semiconductor driving device according to any one of claims 1 to 7, which applies a voltage to a control terminal of the semiconductor switching element to turn on and off the semiconductor switching element, The semiconductor driving device is a control unit that generates an on / off command signal that determines an on / off state of the semiconductor switching element and outputs the signal to the gate driver; a second overcurrent determination unit that determines an overcurrent in the semiconductor switching element based on a potential of the output terminal of the leg circuit, using a power supply voltage of a DC power supply as a reference voltage, an overcurrent determination by the first overcurrent determination unit precedes an overcurrent determination by the second overcurrent determination unit; When the second overcurrent determination unit determines that an overcurrent is occurring, the control unit controls at least a semiconductor switching element of the leg circuit determined to be experiencing an overcurrent to an off state.

16. the first overcurrent determination unit and the second overcurrent determination unit each include a filter element that sets a time from when a signal input thereto indicates an overcurrent state until when the first overcurrent determination unit and the second overcurrent determination unit determine that an overcurrent has occurred; 16. The power conversion device according to claim 15, wherein a time constant of a second filter element included in the second overcurrent determination unit is larger than a time constant of a first filter element included in the first overcurrent determination unit, and a time period from when an overcurrent state signal is input to when the second overcurrent determination unit determines that an overcurrent exists is shorter than a short-circuit allowable time determined by a short-circuit withstand capability of the semiconductor switching element.

17. 16. The power conversion device according to claim 15, wherein, when the first overcurrent determination unit determines that an overcurrent exists, the gate voltage reduction unit continues to reduce the voltage applied to the control terminal of the semiconductor switching element for a period of time longer than a time difference between when the first overcurrent determination unit determines that an overcurrent exists and when the second overcurrent determination unit determines that an overcurrent exists.

18. The second overcurrent determination unit a first comparator that determines whether the potential of the output terminal of the leg circuit is near a positive electrode potential of the DC power supply, and a second comparator that determines whether the potential of the output terminal of the leg circuit is near a negative electrode potential of the DC power supply, 16. The power conversion device according to claim 15, wherein an overcurrent in the semiconductor switching element is determined based on the output signal of the first comparator, the output signal of the second comparator, and the on / off command signal generated by the control unit.

19. The control unit The power conversion device according to claim 18 , wherein the on / off command signal is generated using at least one of the output signal of the first comparator and the output signal of the second comparator.

20. the second overcurrent determination unit includes a third comparator that determines whether the potential of the output terminal of the leg circuit is near a positive electrode potential or a negative electrode potential of the DC power supply, 16. The power conversion device according to claim 15, wherein the reference voltage input to the third comparator is switched between a voltage that detects a potential close to a positive electrode potential and a voltage that detects a potential close to a negative electrode potential, based on the on / off command signal generated by the control unit.

21. The second overcurrent determination unit 16. The power conversion device according to claim 15, wherein, during a period in which the semiconductor switching elements connected in series in the leg circuit are both turned off, it is determined whether or not an abnormality exists in the main withstand voltage of the semiconductor switching elements, based on the potential of the output terminal of the leg circuit input to the second overcurrent determination unit.

22. an inverter that converts a DC voltage between the positive and negative terminals of the leg circuit into an AC voltage; or a step-up or step-down converter provided with a reactor between the DC power supply and the leg circuit; Alternatively, the power conversion device according to claim 15 is a step-up or step-down inverter system in which the inverter and the step-up or step-down converter are combined.

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