Processing device and processing method

Abstract

To reduce power consumption of an arithmetic processing device by preventing a zero-value from being written to a high-order bit of a register in which an arithmetic result of a command with a small data width is stored.SOLUTION: An arithmetic processing device includes: an arithmetic unit capable of operating as a plurality of sub arithmetic units according to a bit width of data to be calculated; a plurality of registers each including a plurality of subregions corresponding to the plurality of sub arithmetic units, respectively; a mask circuit for masking, when an operation that uses a part of the plurality of sub arithmetic units is executed, storage of invalid operation result data output from the sub arithmetic unit that does not receive data of an arithmetic target in the subregion; and a data replacement circuit for replacing data output from the subregion in which the storage is masked, with a zero-value for outputting thereof to the arithmetic unit when arithmetic that uses data held in the register including the subregion in which the storage is masked, is executed.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a processing device and a processing method. [Background technology]

[0002] A processing unit is known that can execute vector-friendly instructions of different data types, supports merging write masking and zeroing write masking, and has a register renaming function (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2017-79078 Summary of the Invention [Problem to be solved by the invention]

[0004] The instruction set architecture of a processing unit such as a CPU (Central Processing Unit) may include instructions with various data widths, such as 32 bits or 64 bits. When a second instruction with a wider data width is executed using the result of a first instruction with a narrower data width, for example, a value of 0 is stored in the upper bits of a register that stores the result of the instruction with the narrower data width in order to correctly execute the second instruction.

[0005] It may not be known at the time of executing the first instruction whether the register that stores the calculation result of the first instruction will be used in the second instruction. For this reason, the processing unit writes a value of 0 to the upper bits of the register that stores the calculation result each time the first instruction is executed. When a value of 0 is written to the upper bits of the register, power consumption increases compared to when a value of 0 is not written.

[0006] In one aspect, the present invention aims to reduce the power consumption of a processing unit by preventing the writing of a value of 0 to the upper bits of a register that stores the operation results of an instruction with a small data width. [Means for solving the problem]

[0007] According to one aspect, an arithmetic processing device includes an arithmetic unit operable as a plurality of sub-arithmetic units according to the bit width of data to be operated on, a plurality of registers each including a plurality of sub-areas respectively corresponding to the plurality of sub-arithmetic units, a mask circuit which, when an operation using some of the plurality of sub-arithmetic units is performed, masks invalid operation result data output from a sub-arithmetic unit that does not receive data to be operated on from being stored in the sub-areas, and a data substitution circuit which, when an operation using data held in a register including a sub-area whose storage is masked, replaces data output from a sub-area whose storage is masked with a value of 0 and outputs the data to the arithmetic unit. The memory controller has a decoding unit that decodes an instruction and outputs the instruction code of the decoded instruction, the logical register number included in the decoded instruction, the physical register number indicating the register used corresponding to the logical register number, and the bit width of the data used to execute the instruction, and a renaming table that holds the physical register number and the bit width in correspondence with the logical register number, wherein the mask circuit determines whether or not to mask the storage of the operation result data in the sub-area based on the bit width output from the decoding unit together with the physical register number, and the data replacement circuit determines whether or not to replace the data output from the sub-area with a value of 0 based on the bit width read from the renaming table together with the physical register number. [Effects of the Invention]

[0008] By preventing the writing of 0 values ​​to the upper bits of a register that stores the results of an instruction with a small data width, it is possible to reduce the power consumption of the processing unit. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 2 is a block diagram illustrating an example of a processing unit according to an embodiment. [Figure 2] FIG. 2 is an explanatory diagram showing an example of the operation of the arithmetic processing device of FIG. [Figure 3] FIG. 10 is a block diagram illustrating an example of a processing unit according to another embodiment. [Figure 4] FIG. 4 is a block diagram showing an example of an FPR renaming table in FIG. 3. [Figure 5] 4 is a block diagram showing an example of a method for setting physical register numbers to be stored in the FPR renaming table of FIG. 3. FIG. [Figure 6]4 is a block diagram showing an example of a circuit that executes a load instruction or a store instruction in the execution unit of FIG. 3. FIG. [Figure 7] 4 is a block diagram showing an example of a circuit that executes an operation instruction in the operation execution unit of FIG. 3. FIG. [Figure 8] FIG. 4 is a block diagram illustrating an example of a circuit that writes data to the FPR of FIG. 3. [Figure 9] FIG. 4 is an explanatory diagram showing an outline of writing data to the FPR in FIG. 3. [Figure 10] FIG. 4 is a block diagram illustrating an example of a circuit for reading data from the FPR of FIG. 3. [Figure 11] 11 is a timing diagram showing an example of an operation of reading data from an FPR by the circuit shown in FIG. 10. [Figure 12] FIG. 10 is a block diagram illustrating an example of a processing unit according to another embodiment. [Figure 13] 13 is an explanatory diagram showing an example of a load instruction executed by the arithmetic processing unit of FIG. 12; [Figure 14] FIG. 10 is a block diagram illustrating an example of another arithmetic processing device. [Figure 15] FIG. 15 is a block diagram showing an example of an FPR renaming table in FIG. 14. [Figure 16] FIG. 15 is a block diagram showing an example of a circuit that writes data to the FPR of FIG. 14. [Figure 17] FIG. 15 is a block diagram showing an example of a circuit for reading data from the FPR of FIG. 14. DETAILED DESCRIPTION OF THE INVENTION

[0010] Hereinafter, embodiments will be described with reference to the drawings.

[0011] Fig. 1 shows an example of a processing device according to an embodiment. The processing device 1 shown in Fig. 1 is a processor such as a CPU having a function of executing multiple multiply-add operations in parallel using, for example, SIMD (Single Instruction Multiple Data) instructions. The processing device 1 may also include an instruction cache 10, an instruction buffer 20, a decode unit 30, an FPR renaming table 40, and a GPR renaming table 42, all of which are described in Fig. 3. The processing device 1 may also include reservation stations 50 and 52, an address generation calculator 67, a load / store unit 70, and a data cache 80, all of which are described in Fig. 3.

[0012] The arithmetic processing device 1 has a computing unit 2, a register file 3, a plurality of AND circuits AND, and a plurality of selectors SEL. The AND circuits AND are an example of a mask circuit, and the selectors SEL are an example of a data substitution circuit. The computing unit 2 has a plurality of sub-computing units SOP (SOP0-SOP3) that can operate according to the bit width of the data to be computed. The register file 3 has a plurality of registers REG (registers REG0-REGn; n is an integer equal to or greater than 2), each of which includes a plurality of sub-areas SR (SR0-SR3) corresponding to the sub-computing units SOP.

[0013] Each thick signal line between the arithmetic unit 2 and the register file 3 indicates that multiple bits of data are transferred. The arithmetic unit 2 then executes an operation using at least one piece of data SDT transferred from the register file 3.

[0014] Although not particularly limited, in the following description, it is assumed that the arithmetic unit 2 can execute operations on up to 128-bit data, and each sub-arithmetic unit SOP can execute operations on 32-bit data. In this case, the arithmetic unit 2 can execute, for example, a 128-bit arithmetic instruction, a 64-bit arithmetic instruction, a 32-bit arithmetic instruction, two 64-bit SIMD arithmetic instructions, or four 32-bit SIMD arithmetic instructions.

[0015] The data DDT (operation result data) output from each sub-operation unit SOP is 32 bits, and the data SDT (operand data used in the operation) input to each sub-operation unit SOP is 32 bits.

[0016] The data DDT1-DDT3 output from the sub-operation units SOP1-SOP3 are supplied to the sub-regions SR1-SR3 of the register REG via AND circuits AND, respectively. Each AND circuit AND masks the output of the corresponding data DDT to the register REG when the corresponding mask signal MSK (MSK1-MSK3) indicates a masked state (low level). Each AND circuit AND outputs the corresponding data DDT to the register REG when the corresponding mask signal MSK indicates a non-masked state (high level).

[0017] Data SDT1-SDT3 read from the sub-areas SR1-SR3 of the register REG are supplied to the sub-operational units SOP1-SOP3 via the selectors SEL. When the corresponding selection signal SLCT (SLCT1-SLCT3) is at an active level, each selector SEL outputs the corresponding data SDT to the operation unit 2. When the corresponding selection signal SLCT is at an inactive level, each selector SEL outputs a value of 0 to the operation unit 2 instead of outputting the corresponding data SDT to the operation unit 2.

[0018] In addition, between the sub-operation unit SOP0 and the register file 3, there may be provided an AND circuit AND that masks the transfer of data DDT0 from the sub-operation unit SOP0 to the sub-area SR0, and a selector SEL that replaces data SDT0 from the sub-area SR0 with a value of 0.

[0019] Fig. 2 shows an example of the operation of the arithmetic processing device 1 of Fig. 1. In the example shown in Fig. 2, the arithmetic unit 2 executes a 64-bit arithmetic instruction and stores the 64-bit arithmetic result in register REG1, and then executes a 128-bit arithmetic instruction using the data held in register REG1.

[0020] When the arithmetic unit 2 executes a 64-bit arithmetic instruction, the mask signal MSK1 is set to the non-mask level, and the mask signals MSK2 and MSK3 are set to the mask level. When the arithmetic unit 2 executes a 128-bit arithmetic instruction using the register REG that holds the arithmetic result of the 64-bit arithmetic instruction, the selection signal SLCT1 is set to the valid level, and the selection signals SLCT2 and SLCT3 are set to the invalid level.

[0021] In a 64-bit operation instruction, the sub-operation units SOP0 and SOP1 perform operations using valid data to be operated on and output the operation results as data DDT0 and DDT1. The sub-operation units SOP2 and SOP3 operate on invalid data that is not the operation target and output the operation results as invalid data DDT2 and DDT3.

[0022] The AND circuit AND (Figure 1) corresponding to the sub-operation unit SOP1 receives the mask signal MSK1 at the non-mask level and outputs the data DDT1 to the register REG. Then, the data DDT0 and DDT1 are stored in the sub-areas SR0 and SR1 of the register REG, respectively. The AND circuits AND (Figure 1) corresponding to the sub-operation units SOP2 and SOP3 receive the mask signals MSK2 and MSK3 at the mask level and mask the output of the invalid data DDT2 and DDT3 to the register REG. As a result, the data OLD, which is unrelated to the current operation result, is held in the sub-areas SR2 and SR3 of the register REG1 without being updated.

[0023] For example, in order to correctly execute the subsequent arithmetic instruction stored in register REG1, it is preferable that the data OLD stored in sub-areas SR2 and SR3 be updated to a value of 0 according to the 64-bit arithmetic result. However, in this embodiment, writing of a value of 0 to sub-areas SR2 and SR3 is suppressed, so that the power consumed in sub-areas SR2 and SR3 for writing a value of 0 can be reduced.

[0024] In a 128-bit operation instruction that uses data held in register REG1 in which writing of a zero value is inhibited, operation unit 2 executes the operation using all sub-operation units SOP0-SOP3. The selector SEL corresponding to sub-operation unit SOP1 receives a select signal SLCT1 at an active level and outputs data DT1 read from sub-area SR1 of register REG1 to sub-operation unit SOP1. The selectors SEL corresponding to sub-operation units SOP2 and SOP3 receive select signals SLCT2 and SLCT3 at an inactive level, respectively. The selectors SEL corresponding to sub-operation units SOP2 and SOP3 then output a value of zero to sub-operation units SOP2 and SOP3 instead of data OLD read from sub-areas SR2 and SR3 of register REG1.

[0025] This allows the calculator 2 to correctly execute a 128-bit operation instruction using the data read from the register REG1 even if a 0 value is not written to the sub-areas SR2 and SR3 of the register REG during a 64-bit operation instruction.

[0026] When the arithmetic unit 2 executes a 32-bit arithmetic instruction, the selection signals SLCT1-SLCT3 are set to an invalid level, and the mask signals MSK1-MSK3 are set to a mask level. Therefore, invalid execution result data by the sub-arithmetic units SOP1-SOP3 is not stored in the sub-areas SR1-SR3 of the register REG. The data OLD held in the sub-areas SR1-SR3 is maintained without being updated.

[0027] After this, assume that a 64-bit arithmetic instruction or a 128-bit arithmetic instruction is executed using the register REG in which the arithmetic result data of the 32-bit arithmetic instruction is stored. Since the selection signals SLCT0-SLCT3 are set to an invalid level, a value of 0 is output to the sub-arithmetic units SOP1-SOP3 instead of the data OLD read from the sub-areas SR1-SR3. This reduces the power consumed in the sub-areas SR1-SR3 due to writing a value of 0, while allowing the subsequent arithmetic unit 2 to correctly execute the arithmetic operation.

[0028] When a 128-bit arithmetic instruction using valid data held in the register REG is executed, the select signals SLCT1-SLCT3 are set to the valid level, and data is transferred from the register REG to each of the sub-operation units SOP0-SOP3 of the operation unit 2. Then, the operation result data DDT0-DDT3 is stored in the register REG without being masked.

[0029] As described above, in this embodiment, the arithmetic processing device 1 suppresses writing of 0 values ​​to the sub-area SR of the register REG corresponding to the higher-order bits larger than the data width of the arithmetic instruction. This reduces the power consumed in the sub-area SR for writing 0 values, thereby reducing the power consumption of the arithmetic processing device 1. Furthermore, when an arithmetic instruction with a large data width is executed using a register that stores the arithmetic result of an arithmetic instruction with a small data width, 0 values ​​are supplied to the arithmetic unit 2 instead of the data OLD read from the register REG. This allows the arithmetic unit 2 to correctly execute the arithmetic instruction with a large data width even when 0 values ​​are not written to the higher-order bits of the register REG that stores the arithmetic result of the arithmetic instruction. As a result, the arithmetic processing device 1 can correctly execute an arithmetic instruction with a large data width even when power consumption is reduced by suppressing writing of some data to the register REG.

[0030] The sub-area SR that suppresses writing of 0 values ​​is not limited to the sub-area SR on the higher-order bit side that is larger than the data width of the arithmetic instruction, but may be any sub-area SR that corresponds to the sub-operation unit SOP that does not receive the data to be operated on.Furthermore, the sub-area SR that outputs data to be replaced with 0 values ​​is not limited to the sub-area SR on the higher-order bit side, but may be any sub-area SR in which writing of 0 values ​​is suppressed.

[0031] FIG. 3 shows an example of a processing unit according to another embodiment. Detailed descriptions of elements similar to those described in FIGS. 1 and 2 will be omitted. The processing unit 100 shown in FIG. 3 includes an instruction cache 10, an instruction buffer 20, a decode unit 30, an FPR renaming table 40, and a GPR renaming table 42. The processing unit 100 also includes a reservation station 50 (RSE; Reservation Station for Execution), a reservation station 52 (RSA; Reservation Station for Address), an execution unit 60, a load / store unit 70, and a data cache 80. The execution unit 60 includes, for example, a floating-point unit 62, a physical register 64 (FPR; Floating Point Register), an address generation unit 67, and a physical register 68 (GPR; General Purpose Register). Hereinafter, the physical register 64 will also be referred to as an FPR 64, and the physical register 68 will also be referred to as a GPR 68.

[0032] The instruction cache 10 holds instructions transferred from a memory such as the main memory, and outputs the held instructions to the instruction buffer 20. For example, the instruction cache 10 may be a primary instruction cache. The instruction buffer 20 accumulates a plurality of instructions transferred from the instruction cache 10, and sequentially outputs the accumulated instructions to the decode unit 30 in order.

[0033] The decode unit 30 decodes instructions received from the instruction buffer 20. When the decode unit 30 decodes a floating-point operation instruction, it outputs the instruction code INSC, bit length W-LEN, physical register number WP-FPRN used in the operation, etc. to the FPR renaming table 40 and the reservation station 50. When the decode unit 30 decodes a memory access instruction, it outputs the instruction code INSC, bit length W-LEN, physical register number WP-GPRN used in the operation, etc. to the GPR renaming table 42 and the reservation station 52.

[0034] The physical register number WP-FPRN indicates the number of the entry (physical register) in FPR64 where the operation result data is updated, and is represented by 6 bits [5:0]. The physical register number RP-FPRN indicates the number of the entry (physical register) in FPR64 that holds the data used in the operation, and is represented by 6 bits [5:0]. The physical register number RP-FPRN is output from the FPR renaming table 40 together with the bit length R-LEN that indicates the bit width of the data used in the operation.

[0035] The logical register number W-FPRN indicates the logical register number of the destination operand included in the arithmetic instruction and the entry number of the FPR renaming table 40, and is represented by 5 bits [4:0]. The logical register number R-FPRN indicates the logical register number of the source operand included in the arithmetic instruction and the entry number of the FPR renaming table 40 from which the physical register number RP-FPRN and bit length R-LEN are read, and is represented by 5 bits [4:0].

[0036] The physical register number WP-GPRN indicates the number of the entry (physical register) in GPR 68 where data is updated by a load instruction, is represented by 6 bits [5:0], and is also written to the GPR renaming table 42. The physical register number RP-GPRN indicates the number of the entry (physical register) in GPR 68 where data is read by a store instruction, and is represented by 6 bits [5:0]. The physical register number RP-GPRN is output from the GPR renaming table 42.

[0037] The logical register number W-GPRN indicates the logical register number of the destination operand included in a load instruction and the entry number of the GPR renaming table 42, is represented by 5 bits [4:0], and is read from the GPR renaming table 42. The logical register number R-GPRN indicates the logical register number of the source operand included in a store instruction and the entry number of the GPR renaming table 42 from which the physical register number RP-GPRN and bit length R-LEN are read. The logical register number R-GPRN is represented by 5 bits [4:0].

[0038] The bit length W-LEN output from the decode unit 30 is information identifying the bit width of data used in the instruction decoded by the decode unit 30, and is represented by, for example, 1 bit. In this embodiment, the decode unit 30 sets the bit length W-LEN to "0" when it decodes a 64-bit operation instruction, and sets the bit length W-LEN to "1" when it decodes a 128-bit operation instruction.

[0039] The bit length R-LEN indicates the bit width of the data used in the operation and is read from the FPR renaming table 40. When the decode unit 30 decodes a memory access instruction, it may output the bit lengths W-LEN and R-LEN to the GPR renaming table 42, the reservation station 50, and the GPR 68.

[0040] The decode unit 30 obtains the physical register numbers WP-FPRN and WP-GPRN using, for example, a technique called a free list method. This prevents the physical register numbers WP-FPRN and WP-GPRN from being used by multiple instructions at the same time. The free list method is described in FIG. 5.

[0041] When decoding a floating-point operation instruction, decoding unit 30 outputs the logical register number R-FPRN of the source operand included in the floating-point operation instruction to FPR renaming table 40. When decoding a floating-point operation instruction, decoding unit 30 outputs the logical register number W-FPRN of the destination operand included in the floating-point operation instruction to FPR renaming table 40.

[0042] When decoding unit 30 decodes a floating-point arithmetic instruction, it outputs a physical register number WP-FPRN indicating an entry in FPR64 used by floating-point arithmetic unit 62 to FPR renaming table 40 and reservation station 50. When decoding unit 30 decodes a floating-point arithmetic instruction, it outputs a bit length W-LEN of the floating-point arithmetic instruction to FPR renaming table 40 and reservation station 50.

[0043] When the decoding unit 30 decodes a memory access instruction, it outputs the logical register number R-GPRN of the source operand included in the memory access instruction to the GPR renaming table 42. When the decoding unit 30 decodes a memory access instruction, it outputs the logical register number W-GPRN of the destination operand included in the memory access instruction to the GPR renaming table 42.

[0044] When the decode unit 30 decodes a load instruction, it outputs the logical register number W-GPRN of the destination operand (the storage destination of the load data) included in the load instruction to the GPR renaming table 42. When the decode unit 30 decodes a load instruction, it outputs the physical register number WP-GPRN indicating the entry of the GPR 68 that stores the load data to the GPR renaming table 42 and the reservation station 52. When the decode unit 30 decodes a store instruction, it outputs the logical register number R-GPRN of the source operand (the source from which the store data is read) included in the store instruction to the GPR renaming table 42.

[0045] The FPR renaming table 40 has entries whose number corresponds to the number of logical registers (operands) that can be specified by an arithmetic instruction written in a program executed by the arithmetic processing unit 100. The FPR renaming table 40 associates the number of a logical register specified by an arithmetic instruction with the number of an entry (physical register) of the FPR 64 used by the floating-point arithmetic unit 62. For example, the FPR renaming table 40 outputs the physical register number RP-FPRN and bit length R-LEN held in the entry indicated by the logical register number R-FPRN received from the decode unit 30 to the reservation station 50. An example of the FPR renaming table 40 is described in FIG. 4.

[0046] The GPR renaming table 42 has entries whose number corresponds to the number of logical registers (operands) that can be specified by a memory access instruction written in a program executed by the arithmetic processing unit 100. The GPR renaming table 42 associates the number of the logical register specified by the memory access instruction with the number of the entry (physical register) of the GPR 68 used by the address generation calculator 67. The GPR renaming table 42 outputs to the reservation station 52 the physical register number RP-GPRN and bit length R-LEN held in the entry indicated by the logical register number R-GPRN received from the decode unit 30.

[0047] The reservation station 50 has a queue containing multiple entries that hold arithmetic instructions (including instruction code INSC, register number, etc.) and bit lengths W-LEN and R-LEN. The reservation station 50 outputs the arithmetic instructions, including instruction code INSC, etc., held in the entries, to the floating-point arithmetic unit 62 or a fixed-point arithmetic unit (not shown) in an out-of-order manner in the order in which they can be executed. The reservation station 50 also outputs physical register numbers WP-FPRN, RP-FPRN and bit lengths W-LEN and R-LEN to the FPR 64 to access the FPR 64. Although not shown, the reservation station 50 may be connected to the fixed-point arithmetic unit and the GPR 68. Hereinafter, the reservation station 50 will also be referred to as the RSE 50.

[0048] The reservation station 52 has a queue including multiple entries that hold memory access instructions (including instruction code INSC, register number, etc.) and bit lengths W-LEN, R-LEN. The reservation station 52 outputs the memory access instructions, including the instruction code INSC, etc., held in the entries to the address generation calculator 67 out of order in the order in which they can be executed. The memory access instructions are store instructions or load instructions. The reservation station 52 also outputs physical register numbers WP-GPRN, RP-GPRN and bit lengths W-LEN, R-LEN to the GPR 68 to access the GPR 68. Hereinafter, the reservation station 52 is also referred to as the RSA 52. The processor 100 may have a reservation station that combines the reservation stations 50 and 52.

[0049] The floating-point unit 62 reads data to be operated on from the FPR 64 based on an operation instruction issued by the RSE 50, performs the operation, and stores the operation result data RSLTD in the FPR 64. The FPR 64 has multiple entries for holding data DT. The number of entries in the FPR 64 is greater than the number of entries in the renaming table 40. The data DT held in the FPR 64 is read from the data cache 80 based on a load instruction, and written to the data cache 80 based on a store instruction. An example of the FPR 64 is shown in FIG. 8.

[0050] The address generation calculator 67 calculates a memory access address by reading data from the GPR 68 and performing addition processing, etc., based on a memory access instruction issued by the RSA 52. The address generation calculator 67 outputs the memory access address obtained by the calculation to the load / store unit 70.

[0051] The load store unit 70 has a load store queue 72 including a plurality of entries holding memory access instructions (memory access addresses and access types indicating load or store) received from the address generation calculator 67. The load store unit 70 sequentially outputs the memory access instructions held in the load store queue 72 to the data cache 80, and executes data load processing or data store processing.

[0052] The data cache 80 reads the data to be accessed based on a load instruction from the load store unit 70, and transfers the read data to the FPR64 or GPR68. The data cache 80 stores the data to be accessed transferred from the FPR64 or GPR68 in a memory area indicated by an access address based on a store instruction from the load store unit 70. If the data cache 80 does not hold the data to be accessed (a cache miss), it reads the data from a memory such as a secondary cache or main memory.

[0053] Fig. 4 shows an example of the FPR renaming table 40 of Fig. 3. In Fig. 4, the symbol D in parentheses at the end of a signal indicates that the signal is generated in the D cycle of Figs.

[0054] For example, the FPR renaming table 40 has 32 entries, which corresponds to the number of logical registers that can be specified by operands included in an arithmetic instruction. Each entry has an area for storing a physical register number WP-FPRN and a bit length W-REN.

[0055] The decode unit 30 stores the 6-bit physical register number WP-FPRN and the bit length W-REN in the entry of the FPR renaming table 40 corresponding to the 5-bit register number W-FPRN indicating the logical register specified by the instruction. At this time, the decode unit 30 determines the physical register number WP-FPRN using a free list method.

[0056] Furthermore, the decoding unit 30 outputs the register number R-FPRN to a selector 41 of the FPR renaming table 40. The FPR renaming table 40 reads the physical register number WP-FPRN and bit length W-LEN from the entry indicated by the register number R-FPRN. The FPR renaming table 40 outputs the read physical register number WP-FPRN and bit length W-LEN to the reservation station 50 as the physical register number RP-FPRN and bit length R-LEN.

[0057] The reservation station 50 sequentially stores in entries the instructions (instruction code INSC, physical register numbers WP-FPRN, RP-FPRN, and bit lengths W-LEN, R-LEN) received from the decode unit 30 and the FPR renaming table 40. The reservation station 50 then outputs the instructions stored in the entries to the floating-point arithmetic unit 62 in the order in which they can be executed.

[0058] For example, the floating-point arithmetic unit 62 sequentially executes instructions 1 and 2 received from the reservation station 50. For example, instruction 1 is a 64-bit addition instruction. The floating-point arithmetic unit 62 adds the 64-bit data held in registers f2 and f3, and stores the 64-bit addition result data in register f1. For example, instruction 2 is a 128-bit addition instruction. The floating-point arithmetic unit 62 adds the 128-bit data held in registers f1 and f4, and stores the 128-bit addition result data in register f5.

[0059] The numbers at the end of registers f1, f2, f3, f4, and f5 indicate the logical register numbers, respectively. For example, the addition result data of instruction 1 is stored in the physical register corresponding to logical register number W-FPRN (WP-FPRN="8" in FIG. 4). The decode unit 30 sets the bit lengths W-LEN and R-LEN of an instruction whose bit length (bit width) is 64 bits to "0," and sets the bit lengths W-LEN and R-LEN of an instruction whose bit length (bit width) is 128 bits to "1." Note that the bit length LEN may be extended to 2 bits or more when the bit length LEN is greater than 128 bits or when the bit length is divided into 32-bit units.

[0060] When decoding instruction 1, decode unit 30 stores physical register number WP-FPRN (=8) and bit length W-LEN (=0) indicating a 64-bit bit length in the entry of FPR renaming table 40 corresponding to logical register number W-FPRN (=1). When decoding instruction 2, decode unit 30 outputs logical register number R-FPRN (=1) to FPR renaming table 40. FPR renaming table 40 outputs physical register number RP-FPRN (=8) and bit length R-LEN (=0) read from the entry corresponding to logical register number R-FPRN (=1) to reservation station 50. Then, instruction 2 is executed by floating-point unit 62.

[0061] Note that each instruction may have multiple source operands, such as registers f1 and f2 in instruction 1 and registers f1 and f4 in instruction 2. Therefore, decode unit 30 actually outputs multiple logical register numbers R-FPRN corresponding to the multiple source operands for each instruction. FPR renaming table 40 outputs multiple physical register numbers RP-FPRN and bit lengths R-LEN to reservation station 50 based on the multiple logical register numbers R-FPRN received in parallel. Note that the configuration and function of GPR renaming table 42 are similar to those of FPR renaming table 40, except that the register numbers correspond to GPR 68.

[0062] Fig. 5 shows an example of a method for setting physical register numbers WP-FPRN to be stored in FPR renaming table 40 of Fig. 3. In Fig. 5, the symbols D and W shown in parentheses at the end of signals indicate that the signals are generated in the D cycle and W cycle, respectively, of Fig. 7.

[0063] 3, the processing unit 100 has a reorder buffer 32, and an FPR commit renaming table 34 and an FPR free list 36 corresponding to the FPR renaming table 40. The processing unit 100 also has a GPR commit renaming table and a GPR free list corresponding to the GPR renaming table 42, but these are not shown in the figure. The method of setting the physical register numbers WP-GPRN to be stored in the GPR renaming table 42 is the same as the method of setting the physical register numbers WP-FPRN to be stored in the FPR renaming table 40.

[0064] The reorder buffer 32 has a queue that holds instructions issued out of order from the reservation station 50 so that the instructions are completed in the order in which they are written in the program. The decode unit 30 also stores in the reorder buffer 32 the logical register number W-FPRN1, physical register number WP-FPRN, and bit length W-LEN that are output to the FPR renaming table 40.

[0065] The reorder buffer 32 monitors whether the instructions registered in the queue have been executed. When the instruction whose execution has been confirmed is at the head of the queue (i.e., when all preceding instructions have been completed), the reorder buffer 32 commits (completes) the instruction. The committed instruction is deleted from the reorder buffer 32, and the logical register number W-FPRN1, physical register number WP-FPRN, and bit length W-LEN registered in the reorder buffer 32 are transferred to the FPR commit renaming table 34.

[0066] The FPR commit renaming table 34 has multiple entries, similar to the FPR renaming table 40 in Fig. 4. The FPR commit renaming table 34 records the correspondence between the logical register number W-FPRN and the physical register number WP-FPRN of the committed instruction. For example, when a branch prediction misses, the uncommitted instruction is an instruction in the wrong branch direction, so the pipeline is cleared and discarded.

[0067] At this time, the state of the FPR renaming table 40 is also restored to the state of the branch instruction that was mispredicted. At that time, the execution state of the instruction can be restored by copying the contents of the FPR commit renaming table 34 to the FPR renaming table 40. The FPR commit renaming table 34 stores the physical register number WP-FPRN and the bit length W-LEN using the logical register number W-FPRN as an index.

[0068] At this time, the physical register number WP-FPRN held in the FPR commit renaming table 34 becomes unnecessary, so it is read out using the logical register number W-FPRN and transferred as the free physical register number FWP-FPRN to the FPR free list 36. For example, the FPR free list 36 has 32 entries.

[0069] 8, FPR64 has 64 entries in the queue structure, so there are 64 possible physical register numbers WP-FPRN. Of the physical register numbers WP-FPRN, 32, which is the same as the number of logical registers, are registered in the FPR renaming table 40, so the remaining 32 physical register numbers WP-FPRN are held in the FPR free list 36.

[0070] The free physical register number FWP-FPRN output from the FPR commit renaming table 34 is stored in the entry of the FPR free list 36 indicated by the in-pointer INP. The in-pointer INP is, for example, incremented when the free physical register number WP-FPRN is registered in the FPR free list 36. On the other hand, the physical register number WP-FPRN held in the FPR free list 36 is read from the entry indicated by the out-pointer OUTP and output from the decode unit 30 to the FPR renaming table 40 in FIG. 4. The out-pointer OUTP is, for example, incremented when the physical register number WP-FPRN is read from the FPR free list 36.

[0071] The number of physical register numbers WP-FPRN registered in the FPR free list 36 may be determined by the difference between the in-pointer INP and the out-pointer OUTP, or by the count value of a separately provided counter. If there is no free space in the FPR free list 36, the decode unit 30 suppresses instruction decoding. This makes it possible to manage the 64 unique physical register numbers WP-FPRN without any excess or deficiency.

[0072] Fig. 6 shows an example of a circuit that executes a load instruction or a store instruction in the execution unit 60 of Fig. 3. In Fig. 6, the D cycle, P cycle, B cycle, and A cycle, as well as the "P", "B", and "A" shown in parentheses at the end of register numbers, etc., indicate cycles of the instruction pipeline. Flip-flops FF1 and FF2 are provided to mark the cycles.

[0073] In the P cycle, the RSA 52 selects one of the stored load instructions and store instructions, and transfers the physical register number RP-GPRN(P), valid signal VLD(P), instruction code INSC(P), and physical register number WP-GPRN(P) of the selected instruction to the flip-flop FF1 of the execution unit 60.

[0074] The valid signal VLD indicates that the instruction code INSC and physical register numbers RP-GPRN and WP-GPRN in the same cycle are valid. The valid signal VLD is also used to start the address generation calculator 67 in cycle A and to trigger a memory access request to the load store unit 70.

[0075] The physical register number RP-GPRN is used to read the 64-bit data RDT(B) from the GPR 68 in cycle B. The data RDT(B) read from the GPR 68 is output to the operand register 66. Although not shown, for example, if there are two source operands in an arithmetic instruction, there will be two physical register numbers RP-GPRN and two data RDTs.

[0076] The address generation calculator 67 executes an operation to generate a memory access address in cycle A using data RDT(A) output from the operand register 66. The generated memory access address is output to the load store unit 70 as 64-bit operation result data RSLTD(A).

[0077] The instruction code INSC is used to instruct address calculation and to instruct the load / store unit 70. The instruction to the load / store unit 70 is, for example, a load or store instruction, but may also include a more complex multi-bit instruction. The load / store unit 70 executes memory access using the calculation result data RSLTD(A) and the instruction code INSC, triggered by the valid signal VLD(A). For example, in the case of a load instruction, data loaded from memory is stored in one of the 64 entries of GPR68 or 64 entries of FPR64 using the 6-bit physical register number WP-GPRN.

[0078] Figure 7 shows an example of a circuit that executes an arithmetic instruction in the execution unit 60 of Figure 3. Detailed descriptions of elements similar to those in Figure 6 will be omitted. In Figure 7, the D cycle, P cycle, B cycle, X cycle, and U cycle, as well as the "P", "B", "X", and "U" shown in parentheses at the end of register numbers, etc., indicate cycles of the instruction pipeline. Flip-flops FF3, FF4, and FF5 are provided to mark the cycles.

[0079] In the P cycle, the RSE 50 selects one of the accumulated floating-point operation instructions. The RSE 50 transfers the physical register numbers RP-FPRN(P), WP-FPRN(P), valid signal VLD(P), instruction code INSC(P), and bit lengths R-LEN(P), W-LEN(A) of the selected floating-point operation instruction to the flip-flop FF3 of the operation execution unit 60.

[0080] The valid signal VLD indicates that the instruction code INSC and physical register numbers RP-FPRN and WP-FPRN in the same cycle are valid. The valid signal VLD is also used to start the floating-point arithmetic unit 62 in the X cycle.

[0081] The physical register number RP-FPRN and bit length R-LEN are used to read 128-bit data RDT(B) from FPR in cycle B, as will be described later in FIG. 10. The data RDT(B) read from FPR 64 is output to operand register 66. Although not shown, for example, if there are three source operands in an arithmetic instruction, there will be three physical register numbers RP-GPRN and three data RDTs.

[0082] The floating-point arithmetic unit 62 executes a floating-point operation in X cycle using data RDT(X) output from the operand register 66. The operation result generated by the floating-point arithmetic unit 62 is transferred to the result register 63 as operation result data RSLTD(X).

[0083] The instruction code INSC is used to instruct a floating-point operation. Although not shown, the instruction code INSC may include multiple bits depending on the number of types of operations supported. As described in FIG. 8, in the U cycle, the valid signal VLD(U) is used as a write enable signal, and the operation result data RSLTD(U) is stored in the entry of FPR64 indicated by the physical register number WP-FPRN(U) and bit length W-LEN(U). The reading of data RDT(B) from FPR64 in the B cycle is described in FIG. 10. The RSE 50 can select a fixed-point operation instruction and perform a fixed-point operation using data RDT(B) from GPR68.

[0084] 8 shows an example of a circuit that writes data to the FPR64 of FIG. 3. In FIG. 8, the symbols X and U in parentheses at the end of signals indicate that the signals are generated in the X cycle and U cycle of FIG. 7, respectively. The FPR64 has 64 entries that hold 128-bit data DT. Therefore, physical register numbers WP-FPRN that identify entries in the FPR64 are represented by 6 bits [5:0]. Although not shown in the figure, the GPR64, like the FPR64, also has 64 entries that hold 128-bit data DT.

[0085] 8, for ease of explanation, FPR64 is divided into lower bits [63:0] and upper bits [127:64], but entries with the same physical register number WP-FPRN are accessed simultaneously. In the following, for example, an entry corresponding to physical register number WP-FPRN="1" is also referred to as entry FPR1.

[0086] 8 shows an example in which floating-point arithmetic unit 62 writes operation result data RSLTD to FPR64. For example, floating-point arithmetic unit 62 can simultaneously execute two 64-bit operations (two SIMD operations). When executing a SIMD operation using FPR64 with a data width of 128 bits, floating-point arithmetic unit 62 operates as two 64-bit arithmetic units, arithmetic unit 0 and arithmetic unit 1. arithmetic unit 0 and arithmetic unit 1 are examples of sub-arithmetic units.

[0087] The arithmetic unit 0 performs an operation on the lower bits of the data, and the arithmetic unit 1 performs an operation on the higher bits of the data. When the floating-point arithmetic unit 62 executes a 128-bit operation instruction, for example, a carry from the arithmetic unit 0 is transmitted to the arithmetic unit 1, and the arithmetic units 0 and 1 operate in cooperation with each other.

[0088] When the valid signal VLD is valid, the operation result data RSLTD[63:0] by the operator 0 is stored in the lower bits of the entry of FPR64 indicated by the physical register number WP-FPRN[5:0] in synchronization with the clock CLK. For example, the valid level of the valid signal VLD is a logical value of 1.

[0089] When the valid signal VLD is valid and the bit length W-LEN is "1", the operation result data RSLTD[127:64] by the operator 1 is stored in the upper bit side of the entry of FPR64 indicated by the physical register number WP-FPRN[5:0] in synchronization with the clock CLK. The entry of FPR64 is an example of a register, and the lower bit side and upper bit side of the entry are examples of sub-areas.

[0090] When the bit length W-LEN is "0", the storage of the operation result data RSLTD[127:64] in FPR64 is masked by the AND circuits AND1 and AND2. The AND circuits AND1 and AND2 are an example of a mask circuit that determines whether or not to mask the storage of the operation result data RSLTD[127:64] in FPR64.

[0091] As described above, a bit length W-LEN of "0" indicates a 64-bit operation, and a bit length W-LEN of "1" indicates a 128-bit operation. Therefore, when the bit length W-LEN is "0", the operation result data RSLTD[127:64] output from the arithmetic unit 1 is an invalid value. In this case, the specification of the instruction set architecture expects, for example, that the value of FPR64 to be updated be 0.

[0092] In this embodiment, the upper 64 bits are guaranteed to be 0 during 64-bit operations when the source operand data is read from the FPR, as will be described in Fig. 10. Therefore, when data RSLTD is stored in FPR64 shown in Fig. 8, a value of 0 is not written to FPR64. The signal line for the operation result data RSLTD output from the arithmetic unit 1 is connected directly to FPR64 via the result register 63, unlike Fig. 16, which will be described later.

[0093] When the bit length W-LEN is "0," the operation result data RSLTD[127:64] from the arithmetic unit 1 is an invalid value and does not affect the operation of subsequent instructions, regardless of whether FPR64[127:64] is updated. However, when the bit length W-LEN is "0," the AND circuits AND1 and AND2 can stop the supply of the clock CLK to FPR64[127:64], thereby reducing the power consumption of FPR64. On the other hand, when the bit length W-LEN is "1," the valid operation result data RSLTD[127:64] output from the arithmetic unit 1 is stored in FPR64[127:64] in synchronization with the clock CLK.

[0094] Figure 9 shows an overview of writing data to FPR64 in Figure 3. When the bit length W-LEN is "1" (when executing a 128-bit operation), execution of a floating-point operation instruction updates all bits [127:0] of the entry to be operated on in FPR64 from old data OLD to new data NEW.

[0095] On the other hand, when the bit length W-LEN is "0" (when executing 64-bit operations), the execution of a floating-point operation instruction updates the lower 64 bits [63:0] of the entry to be operated on in FPR64 from the old data OLD to the new data NEW. The upper 64 bits [127:64] of the entry to be operated on in FPR64 are not updated (zero values ​​are not written either) and remain as the old data OLD.

[0096] Figure 10 shows an example of a circuit that reads data from FPR64 in Figure 3. In Figure 10, the symbols P, B, and X in parentheses at the end of the signals indicate that the signals are generated in the P cycle, B cycle, and W cycle, respectively, in Figure 7. Flip-flops FF30, FF31, and FF32 correspond to flip-flop FF3 in Figure 7.

[0097] The flip-flop FF30 inputs the physical register number RP-FPRN to the selector 65 on the lower bits [63:0] side of the FPR64 in synchronization with the clock CLK. Then, the data RDT[63:0] is output from the entry of the FPR64 indicated by the physical register number RP-FPRN and stored in the lower bits [63:0] side of the operand register 66.

[0098] The flip-flop FF31 receives the clock CLK via an AND circuit AND4 that receives the bit length R-LEN. If the bit length R-LEN is "1", the AND circuit AND4 outputs the clock CLK to the flip-flop FF31, and if the bit length R-LEN is "0", it stops outputting the clock CLK to the flip-flop FF31. The AND circuit AND4 is an example of a clock stop circuit.

[0099] When the bit length R-LEN is "1", indicating 128-bit data, flip-flop FF31 inputs the physical register number RP-FPRN to the selector 65 on the upper bit [127:64] side of FPR64 in synchronization with the clock CLK. Then, data RDT[127:64] is output from the entry of FPR64 indicated by the physical register number RP-FPRN. When the bit length R-LEN output from flip-flop FF32 is "1", selector 69 selects the data RDT[127:64]. Then, the data RDT[127:64] is stored in the upper bit [127:64] side of the operand register 66 via the selector 69. Therefore, when the bit length R-LEN is "1", the 128-bit data RDT[127:0] output from FPR64 is stored in the operand register 66.

[0100] On the other hand, when the bit length R-LEN is "0", which indicates 64-bit data, flip-flop FF31 does not receive the clock CLK and therefore does not output the physical register number RP-FPRN to FPR. When the bit length R-LEN is "0", the upper [127:64] side of FPR64 holds invalid data. By preventing the reading of invalid data, power consumption can be reduced.

[0101] As described above, after the execution of a 64-bit operation, the upper bits [127:64] of the operation result data RSLTD are expected to be updated to a value of 0 according to the specifications of the instruction set architecture. That is, a value of 0 is expected to be written to the upper bits [127:64] of the operand register 66. When the bit length R-LEN output from the flip-flop FF32 is "0", the selector 69 selects a value of 0 and stores the selected value of 0 in the upper bits [127:64] of the operand register 66. The selector 69 is an example of a data substitution circuit that replaces the data output from the upper bits [127:64] of the FPR64 with a value of 0.

[0102] Therefore, when the bit length R-LEN is "0," the lower 64 bits of data RDT[63:0] output from the FPR64 are written to the lower bits [63:0] of the operand register 66. Also, a value of 0 is written to the upper bits [127:64] of the operand register 66. That is, data not used in the operation defined by the instruction set architecture can be set to a value of 0 when the data RDT[127:0] is stored in the operand register 66. If an increase in power consumption during the read operation of the data RDT[127:64] from the FPR64 is acceptable when the bit length R-LEN is "0," the AND circuit AND may not be provided, and the clock CLK may be supplied directly to the flip-flop FF31. In this case, too, a value of 0 is written to the upper bits [127:64] of the operand register 66 by the operation of the selector 69.

[0103] Fig. 11 shows an example of an operation for reading data from FPR64 using the circuit shown in Fig. 10. In the operation shown in Fig. 11, it is assumed that data DT1 is held in the lower bits [63:0] of entry FPR2 of FPR64, and data DT2 is held in the upper bits [127:64] of entry FPR2. It is also assumed that data DT3 is held in the lower bits [63:0] of entry FPR3 of FPR64, and data DT4 is held in the upper bits [127:64] of entry FPR3.

[0104] First, the operation when the bit length R-LEN is 1 will be explained. In cycle CYC1, the valid signals VLD(P) and VLD(B) are 0, so the old values ​​remain in the physical register numbers RP-FPRN(P), RP-FPRN0(B), and RP-FPRN1(B) and the bit lengths R-LEN(P) and R-LEN(B).

[0105] In cycle CYC2, the valid signal VLD(P) becomes "1", the physical register number RP-FPRN(P) is updated to "3", and the bit length R-LEN(P) is updated to "1". Since the P cycle signal becomes the B cycle in cycle CYC3, the valid signal VLD(B) becomes "1" in cycle CYC3.

[0106] In cycle CYC3, physical register numbers RP-FPRN0(B) and RP-FPRN1(B) are set to "3" by the physical register number RP-FPRN(P) in cycle CYC2. The value of physical register number RP-FPRN1(B) depends on the value of bit length R-LEN(P). Since the AND circuit AND4 in FIG. 10 receives bit length R-LEN(P)="1" and outputs clock CLK, physical register number RP-FPRN1(B) is set to "3", the same as RP-FPRN(P) in cycle CYC2. Physical register number RP-FPRN0(B) does not depend on the value of bit length R-LEN(P), and is set to "3", the same as RP-FPRN(P) in cycle CYC2.

[0107] Since the physical register numbers RP-FPRN0(B) and RP-FPRN1(B) are both "3", the data RDT(B)[63:0] (="DT3") and RDT(B)[127:64] (="DT4") are read from entry FPR3 of FPR64. Since R-LEN(B) is "1", the selector 65 in FIG. 10 selects the data RDT(B)[127:64] from FPR. Therefore, the operand register 66 in FIG. 10 outputs the data RDT(X)[127:64]="DT4" in cycle CYC4.

[0108] Next, the operation when the bit length R-LEN is "0" will be explained. Detailed explanations of the same operations as when the bit length R-LEN is "1" will be omitted. Operations that differ from when the bit length R-LEN is "1" are indicated by shading. The bit lengths R-LEN(P) and R-LEN(B) are set to "0" regardless of the cycle.

[0109] The operation of cycle CYC1 is the same as the operation when the bit length R-LEN is "1". The operation of cycle CYC2 is the same as the operation when the bit length R-LEN is "1", except that the bit length R-LEN(P) is set to "0".

[0110] In cycle CYC3, the bit length R-LEN(P) is "0", so the AND circuit AND4 in FIG. 10 does not output the clock CLK. Therefore, the physical register number RP-FPRN1(B) is maintained at "2", the same as RP-FPRN1(B) in cycle CYC2. The data RDT(B)[127:64] output from FPR64 is maintained at "DT2" output from entry FPR2 of FPR. Since R-LEN(B) is "0", the selector 65 selects "0". On the other hand, the physical register number RP-FPRN0(B) is updated to "3" regardless of the bit length R-LEN(P), so the data RDT(B)[63:0](="DT3") is read from entry FPR3 of FPR64.

[0111] In cycle CYC4, the operand register 66 outputs "0" selected by the selector 69 as the data RDT(X)[127:64], rather than "DT2" held in entry FPR2 of FPR64.

[0112] As described above, this embodiment can also achieve the same effects as the above-described embodiments. For example, by suppressing the writing of zeros to the upper bits of FPR64 that are not used in an arithmetic instruction, it is possible to reduce power consumption when writing zeros to FPR64, thereby reducing the power consumption of the arithmetic processing device 100. Furthermore, by replacing the upper bits of data read for a 128-bit arithmetic instruction from an FPR64 entry that stores 64-bit arithmetic result data RSLTD with zeros, it is possible to correctly execute an arithmetic operation. As a result, the arithmetic processing device 100 can correctly execute an arithmetic operation even when power consumption is reduced by suppressing the writing of some data to FPR64.

[0113] Furthermore, in this embodiment, it is possible to prevent the writing of a value of 0 to RPR 64 by stopping the supply of the clock CLK to the upper bits of FPR 64 using simple circuits such as AND circuits AND1 and AND2. As a result, it is possible to prevent the writing of a value of 0 to RPR 64 while suppressing an increase in the circuit size of the arithmetic processing device 100, thereby reducing the power consumption of the arithmetic processing device 100.

[0114] By suppressing the supply of the clock CLK to the read circuit on the upper bit side of the FPR64 that holds the data to be replaced with a value of 0, reading of invalid data can be suppressed, and the power consumption of the arithmetic processing device 100 can be reduced.

[0115] The decode unit 30 outputs the bit length W-LEN together with the physical register number WP-FPRN for each instruction to the renaming table 40. This makes it possible to transfer the bit lengths W-LEN and R-LEN along with instruction information such as the register number to the target circuit in each cycle of the pipeline, and to correctly prevent writing of 0 and replace data with 0 for each instruction.

[0116] Furthermore, the reservation station 50 receives the instruction code INSC, the physical register number WP-FPRN, and the bit length W-LEN from the decode unit 30, and receives the physical register number RP-FRPN and the bit length R-LEN from the renaming table 40. This allows the arithmetic processing device 100, which executes instructions out of order in the order in which they can be executed, to correctly suppress the writing of 0 values ​​and replace data with 0 values ​​for each instruction.

[0117] Figure 12 shows an example of a processing device according to another embodiment. Elements similar to those in Figures 3 to 10 are given the same reference numerals, and detailed descriptions thereof will be omitted. The processing device 100A shown in Figure 12 has a decoding unit 30A instead of the decoding unit 30 in Figure 3, and also has new OR circuits OR1 and OR2. The other configuration of the processing device 100A is similar to that of the processing device 100 in Figure 3.

[0118] The arithmetic processing device 100A has a function of updating multiple entries in the FPR64 or GPR68 in Fig. 3 with a single instruction, similar to the ldp instruction of ARM (registered trademark). For example, the arithmetic processing device 100A can execute an ldp instruction that divides data loaded from one address in a memory area into two and stores the data in two entries of either the FPR64 or the GPR68. The ldp instruction is an example of a split load instruction.

[0119] The decode unit 30A decodes the ldp instruction as a 64-bit instruction. Therefore, when the decode unit 30A decodes the ldp instruction, it outputs a bit length W-LEN of "0" along with the physical register number RP-FRPN, etc. in cycle D. In addition, the decode unit 30A sets the control signals LDP-F1(D) and LDP-F2(D) to "1" in cycle D to sequentially execute two flows ldp-f1 and ldp-f2 described in FIG. 13. The flow ldp-f1 is an example of a first instruction, and the flow ldp-f2 is an example of a second instruction.

[0120] When the OR circuit OR1 receives the control signal LDP-F1(D) of "1", it outputs the bit length W-LEN(D) of "1" to the RSE 50, regardless of the bit length W-LEN(D) output by the decode unit 30A. As a result, in the flow ldp-f1 shown in FIG. 13, when data is loaded from memory as a 64-bit instruction to entry FPR1 of FPR64, the mask of the upper bits [127:64] of the data from being stored in entry FPR1 is released.

[0121] When the OR circuit OR2 receives the control signal LDP-F2(D) of "1", it outputs the bit length R-LEN(D) of "1" to the RSE 50 regardless of the bit length R-LEN(D) output from the FPR renaming table 40. This prevents the upper bits [127:64] of the entry FPR1 from being replaced with 0 when 64-bit data is transferred from FPR64 as a 64-bit instruction to the entry FPR2 in the flow ldp-f2 shown in FIG.

[0122] 13 shows an example of a load instruction executed by the arithmetic processing device 100A of FIG. 12. The ldp instruction shown in the upper part of FIG. 13 is described as "ldp d1,d2,[x10]". In this description, first, 128-bit data in a memory area indicated by data (address) held in an entry of GPR68 specified by logical register number="10" is read from memory (or data cache 80). Then, the read data is stored for each of 64-bit data DT1 and DT2 in, for example, two entries FPR1 and FPR2 of FPR64 specified by logical register numbers "d1" and "d2", respectively. To achieve this operation, the arithmetic processing device 100A divides the ldp instruction into two flows ldp-f2 and ldp-f2 and executes them, as shown in the lower part of FIG. 13.

[0123] In the upper part of FIG. 13, the upper bits [127:64] of entries FPR1 and FPR2 are set to "0". However, in this embodiment, as described in FIG. 10, when the bit length R-LEN is "0", the upper bits [127:64] are set to "0" at the time of reading. Therefore, the upper bits [127:64] of entries FPR1 and FPR2 may retain old data, as in FIG. 9. Entry FPR1 is an example of a first register, and entry FPR2 is an example of a second register.

[0124] In the lower part of Figure 13, flow ldp-f1 loads 128-bit data DT1 and DT2 from memory and stores the loaded data DT1 and DT2 in entry FPR1 of FPR64 specified by register d1. Although only the lower bits [63:0] need to be stored in register d1, storing 128 bits allows the upper bits [127:64] to be used as data to be stored in register d2 by flow ldp-2. Furthermore, because the upper bits [127:64] are read as 0 when read, subsequent operations can be performed correctly even if invalid data is stored.

[0125] As described in FIG. 12, the decode unit 30A decodes the ldp instruction as a 64-bit instruction and sets the bit lengths W-LEN and R-LEN to "0". However, in flow ldp-f1, the bit length W-LEN of "0" output from the decode unit 30A is converted to "1" by the OR circuit OR1 that receives the control signal LDP-F1(D) of "1" and is output to the RSE 50. Therefore, even when the decode unit 30A outputs a bit length W-LEN of "0", the 128-bit data read from memory by the load store unit 70 can be stored in the FPR64 (FIG. 8) without being masked.

[0126] Since the ldp instruction is a 64-bit instruction, a bit length W-LEN of "0" is stored in the renaming table 40. Therefore, even when 128-bit data is stored in entry FPR1 of FPR64, in the subsequent instruction, the selector 65 in FIG. 10 sets the upper bits [127:64] to "0" and the data can be supplied to the arithmetic unit 1 via the operand register 66.

[0127] Flow ldp_f2 reads the data stored in register d1 in flow ldp_f1 and shifts the upper bits [127:64] (=DT2) 64 bits to the right using the floating-point unit 62. Then, the right-shifted 64-bit data DT2 is stored in the lower bits [63:0] of register d2. For example, register d2 corresponds to entry FPR2 of FPR64.

[0128] In flow ldp-f2, the bit length R-LEN of "0" output from the renaming table 40 is converted to "1" by the OR circuit OR2 that receives the control signal LDP-F2(D) of "1" and is output to the RSE 50. Therefore, even when the decode unit 30A decodes the ldp instruction as a 64-bit instruction, it is possible to read 128-bit data from entry FPR1 of FPR64.

[0129] For example, if an increase in circuit area is acceptable, two entry FPRs can be updated with one load instruction by increasing the write port of FPR64. On the other hand, in this embodiment, by adding OR circuits OR1 and OR2, one load instruction is divided into two instruction processing flows, and two entry FPRs are updated with one load instruction, thereby suppressing an increase in circuit area.

[0130] 12, the arithmetic processing device 100A can execute instruction processing every cycle by having, for example, one pipeline for load instructions and one floating-point arithmetic unit 62. This allows instruction processing to be executed efficiently, and high throughput can be achieved.

[0131] In contrast, in a processing unit to which this embodiment is not applied, in addition to flows ldp-f1 and ldp-f2, for example, flow ldp-f3 for embedding "0" in register d1 is added. In this case, the operating time of the floating-point arithmetic unit 62 becomes a bottleneck, and there is a risk that instructions can only be processed once every two cycles, which could halve the throughput of instruction processing.

[0132] Increasing the number of floating-point arithmetic units 62 and instruction pipelines solves the problem of reduced instruction processing throughput, but it also increases the number of times the floating-point arithmetic unit 62 reads and writes from and to the FPR 64, which in turn increases the circuit area.

[0133] Another possible control is to split the LDP instruction into two loads. However, if there is only one load pipeline, instructions are processed once every two cycles, halving the instruction processing throughput. In this case, the problem can be solved by increasing the number of load pipelines, but this would increase the number of reads from the data cache 80 and increase the circuit area, for example.

[0134] As described above, this embodiment can also achieve the same effects as the above-described embodiments. Furthermore, in this embodiment, the decode unit 30A treats an ldp instruction that combines multiple 64-bit load instructions as a 64-bit arithmetic instruction and outputs bit lengths W-LEN and R-LEN of "0." In response to flow ldp-f1, the OR circuit OR1 converts the "0" of the bit length W-LEN output from the decode unit 30A to "1" and outputs it to the reservation station 50. In response to flow ldp-f2, the OR circuit OR2 converts the "0" of the bit length R-LEN output from the FPR renaming table 40 to "1" and outputs it to the reservation station 50.

[0135] As a result, when the arithmetic processing device 100A executes flow ldp-f1, it can store 128-bit data from memory in an entry of FPR64. Then, when the arithmetic processing device 100A executes flow ldp-f2, it can read the upper bits of the 128-bit data stored in the entry of FPR64 and store it as 64-bit data in another entry of FPR64.

[0136] Furthermore, the throughput of the ldp instruction can be improved while minimizing an increase in circuit area without significantly changing the structure of the arithmetic processing device 100A compared to the arithmetic processing device 100 shown in Fig. 3. Furthermore, if it is possible to increase both the load pipelines and the floating-point arithmetic pipelines, the throughput of instruction processing can be improved in proportion to the increased number.

[0137] In the above-described embodiment, an example has been described in which the present invention is applied to the arithmetic processing devices 100 and 100A having an FPR64 with a data bit width of 128 bits and a floating-point arithmetic unit 62 capable of executing 64-bit 2SIMD operations. However, the data bit width of the FPR64 and the floating-point arithmetic unit 62 may be greater or smaller than 128 bits.

[0138] Furthermore, the above-described embodiments are not limited to SIMD operations, but can also be applied to processing of operations with small data widths, such as single-precision floating-point operations. In such cases, by increasing the number of bits of the bit lengths W-LEN and R-LEN to two or more, it is possible to accommodate, for example, four-bit lengths W-LEN and R-LEN. Furthermore, although the above-described embodiments have been described using FPR64 as an example, they can also be applied to other arithmetic registers such as GPR68. Furthermore, the above-described embodiments can be applied not only to cases focusing on writing of operation results, but also to cases focusing on writing of load instructions.

[0139] FIG. 14 is a block diagram showing an example of another arithmetic processing device. Elements similar to those in the above-described embodiment are assigned the same reference numerals, and detailed description thereof will be omitted. The arithmetic processing device 100B shown in FIG. 14 has a decoding unit 30B, an FPR renaming table 40B, and a GPR renaming table 42B instead of the decoding unit 30, the FPR renaming table 40, and the GPR renaming table 42 of FIG. 1. Furthermore, the arithmetic processing device 100B has reservation stations 50B and 52B and an arithmetic execution unit 60B instead of the reservation stations 50 and 52 and the arithmetic execution unit 60 of FIG. 1. The arithmetic execution unit 60B has an FPR64B and a GPR68B instead of the FPR64 and GPR68 of FIG. 3. The other configurations and functions of the arithmetic processing device 100B are similar to those of the arithmetic processing device 100 of FIG. 3.

[0140] Fig. 15 is a block diagram showing an example of the FPR renaming table 40B of Fig. 14. The FPR renaming table 40B has the same configuration and function as the FPR renaming table 40 of Fig. 4, except that it does not have an area for holding the bit length W-LEN and does not have the function for outputting the bit length R-LEN.

[0141] The decoding unit 30B has the same functions as the decoding unit 30 in Fig. 3 except that it does not have the function of outputting the bit length W-LEN. The reservation station 50B has the same configuration and functions as the reservation station 50 in Fig. 3 except that it does not have the function of inputting and outputting the bit lengths W-LEN and R-LEN.

[0142] Although not shown, the GPR renaming table 42B has the same configuration and function as the FPR renaming table 40 in Fig. 4, except that it does not have an area to hold the bit length W-LEN and does not have the function to output the bit length R-LEN. Although not shown, the reservation station 52B has the same configuration and function as the reservation station 52 in Fig. 3, except that it does not have the function to input and output the bit lengths W-LEN and R-LEN.

[0143] Fig. 16 shows an example of a circuit for writing data to FPR64B in Fig. 14. The circuit for writing data to FPR64B is similar to the circuit for writing data to FPR64 in Fig. 8, except that it does not have the AND circuit AND1 in Fig. 8 and has a selector SEL62 between the arithmetic unit 1 and the result register 63.

[0144] When executing a 64-bit operation, the arithmetic processing device 100B uses the selector SEL62 to replace invalid operation result data RSLTD(X)[127:64] with a value of 0 and transfers it to the result register 63. Then, the arithmetic processing device 100B stores a value of 0 in the upper bits [127:64] of the target entry of FPR64 via the result register 63. When a value of 0 is stored in the upper bits [127:64] of FPR64 every time a 64-bit operation is executed, power consumption increases compared to when data storage in the upper bits [127:64] of FPR64 is masked.

[0145] The circuit that controls FPR64B has the same configuration and function as the circuit that controls FPR64 in Figure 8, except that it does not have the function of masking data from being stored in the upper bits [127:64] according to the logical value of the bit length W-LEN. Although not shown, the circuit that controls GPR68B has the same configuration and function as the circuit that controls FPR64 in Figure 8, except that it does not have the function of masking data from being stored in the upper bits [127:64] according to the logical value of the bit length W-LEN. Furthermore, the circuit that controls GPR64B has the same configuration and function as the circuit that controls FPR64 in Figure 10, except that it does not have the function of setting the upper bits [127:64] of data to "0" according to the logical value of the bit length R-LEN and outputting it.

[0146] Fig. 17 shows an example of a circuit for reading data from FPR64B in Fig. 14. The circuit for reading data from FPR64B is similar to the circuit for reading data from FPR64 in Fig. 10, except that it does not have the AND circuit AND4, flip-flop FF32, and selector 69 in Fig. 10.

[0147] When executing a 64-bit operation, the arithmetic processing device 100B reads out the data RDT(B)[127:64] of 0 held in the upper bits [127:64] of FPR64B and stores it in the operand register 66. When a 128-bit operation is performed using the result of the 64-bit operation, the value 0 stored in the upper bits [127:64] of FPR64B is read out, and the floating-point unit 62 can correctly execute the operation.

[0148] 17, the arithmetic processing device 100A does not have the AND circuit AND4 (FIG. 10) that prevents the reading of data RDT(B)[127:64] from the upper bits [127:64] of FPR64B. Therefore, the arithmetic processing device 100A reads data not only from the lower bits [63:0] of FPR64B but also from the upper bits [127:64] in synchronization with the clock CLK. Therefore, the circuit in FIG. 17 has the problem of consuming more power than the circuit in FIG. 10.

[0149] The features and advantages of the embodiments will be apparent from the above detailed description. It is intended that the claims encompass the features and advantages of the above-described embodiments without departing from the spirit and scope of the claims. Furthermore, any improvements and modifications will be readily apparent to those skilled in the art. Therefore, it is not intended that the scope of the inventive embodiments be limited to the above-described embodiments, and appropriate improvements and equivalents within the scope of the disclosed embodiments may be utilized. [Explanation of symbols]

[0150] 1. Processing unit 2 Arithmetic unit 3 Register File 10 Instruction Cache 20 Instruction Buffer 30, 30A, 30B Decoder 32 Reorder Buffer 34 FPR Commit Renaming Table 35 Selector 36 FPR Free List 37 Selector 40, 40B FPR Renaming Table 41, 41B selector 42, 42B GPR Renaming Table 50, 50B(RSE) Reservation Station 51 Selector 52, 52B (RSA) Reservation Station 53 Selector 60, 60B Calculation execution unit 62 Floating-point arithmetic unit 63 Result Register 64, 64B Physical Registers (FPR) 65, 65B selector 66 Operand Registers 67 Address generation calculator 68, 68B Physical Register (GPR) 69 Selector 70 Load Store Unit 72 Load Store Queue 80 Data Cache 100, 100A, 100B Processing unit DDT Data INSC instruction code LDP-F1, LDP-F2 control signal MSK (MSK1-MSK3) mask signal RDT Data REG register R-FPRN Logical Register Number R-LEN bit length RP-FPRN Physical Register Number RP-GPRN Physical Register Number RSLTD Calculation result data SDT Data SEL, SEL62 selector SLCT (SLCT1-SLCT3) selection signal SOP (SOP0-SOP3) sub-operator SR (SR0-SR3) sub-area VLD Valid signal W-FPRN, W-FPRN0, W-FPRN1 Logical register number W-GPRN Logical Register Number W-GPRN Logical Register Number W-LEN bit length WP-FPRN Physical Register Number WP-GPRN Physical Register Number

Claims

1. a computing unit capable of operating as a plurality of sub-computing units according to the bit width of data to be computed; a plurality of registers each including a plurality of sub-areas corresponding to the plurality of sub-operational units; a mask circuit that masks storage of invalid operation result data output from a sub-operational unit that does not receive data to be operated on in the sub-area when an operation using some of the plurality of sub-operational units is executed; a data replacement circuit that replaces data output from a sub-area whose storage is masked with a value of 0 when an operation using data held in a register including the sub-area whose storage is masked is executed, and outputs the data to the operation unit; a decoding unit that decodes an instruction and outputs an instruction code of the decoded instruction, a logical register number included in the decoded instruction, a physical register number indicating the register used corresponding to the logical register number, and a bit width of data used to execute the instruction; a renaming table that stores the physical register number and the bit width in association with the logical register number, the mask circuit determines whether or not to mask the storage of the operation result data in the sub-area based on a bit width output from the decoding unit together with the physical register number; The data replacement circuit determines whether or not to replace the data output from the sub-area with a value of 0 based on the bit width read from the renaming table together with the physical register number. Processing unit.

2. each of the plurality of sub-areas of the register operates in synchronization with a clock; The mask circuit stops supplying a clock to a sub-area in which storage of the operation result data is masked. The processor according to claim 1 .

3. a clock stop circuit that stops the supply of a clock to a sub-area that holds data that is replaced with a zero value by the data replacement circuit; The processing unit according to claim 1 or 2.

4. a reservation station that holds an instruction code, a physical register number, and a bit width output from the decoding unit, and the physical register number and bit width read from the renaming table based on the logical register number output from the decoding unit, and outputs information corresponding to an executable instruction to the arithmetic unit; The mask circuit and the data replacement circuit operate based on the bit width output from the reservation station. The processor according to any one of claims 1 to 3.

5. when the decoding unit decodes a split load instruction for splitting and storing data read from memory into two or more of the registers, the decoding unit stores bit widths of the split data in areas of the renaming table corresponding to each of the two or more registers, and outputs a first instruction for loading the data read from memory into a first register of the two or more registers, and a second instruction for transferring the upper bits of the data loaded into the first register to the lower bits of a second register of the two or more registers; when loading data from the memory into the first register in accordance with the first instruction, the masking of the data to be stored in the sub-region by the mask circuit is cancelled; When data is transferred from the upper bit side of the first register to the lower bit side of the second register in accordance with the second instruction, the data substitution circuit is prevented from substituting a value of 0. The processor according to any one of claims 1 to 3.

6. 1. A processing method for a processing device having: a processing unit operable as a plurality of sub-processors according to a bit width of data to be processed; a plurality of registers each including a plurality of sub-areas corresponding to the plurality of sub-processors; a decoding unit that decodes an instruction and outputs an instruction code of the decoded instruction, a logical register number included in the decoded instruction, a physical register number indicating the register used corresponding to the logical register number, and a bit width of data used to execute the instruction; and a renaming table that holds the physical register number and the bit width in correspondence with the logical register number, When an operation using some of the plurality of sub-operational units is executed, invalid operation result data output from a sub-operational unit that does not receive data to be operated on is masked from being stored in the sub-area; When an operation using data held in a register including a sub-area whose storage is masked is executed, data output from the sub-area whose storage is masked is replaced with a value of 0 and output to the arithmetic unit; determining whether or not to mask the storage of the operation result data in the sub-area based on a bit width output from the decoding unit together with the physical register number; Whether or not to replace the data output from the sub-area with a value of 0 is determined based on the bit width read from the renaming table together with the physical register number. Arithmetic processing method.

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