Electro-optical device, electronic equipment, and method for driving an electro-optical device

Abstract

To reduce an influence on adjacent pixels to prevent so-called black floating.SOLUTION: A pixel circuit 110 provided in correspondence with a scan line 12 and a data line 14 has a transistor 121 and an OLED 130 that is one example of a light emitting device. In a compensation period, a gate node and a drain node of the transistor 121 are electrically connected to adjust a voltage of the gate node of the transistor 121 to a voltage corresponding to a threshold voltage. In a gate writing period, the voltage of the gate node of the transistor 121 is changed from the voltage corresponding to the threshold voltage to a voltage according to luminance of the OLED 130. In a drain writing period, the voltage according to the luminance of the OLED 130 is applied to the drain node of the transistor 121.SELECTED DRAWING: Figure 11

Description

[Technical Field]

[0001] The present invention relates to an electro-optical device, an electronic apparatus, and a method for driving an electro-optical device. [Background technology]

[0002] Electro-optical devices using light-emitting elements such as OLEDs are known. OLED stands for Organic Light Emitting Diode. Electro-optical devices include pixel circuits, each of which corresponds to a pixel of an image to be displayed. The pixel circuits include a light-emitting element and a transistor that supplies the light-emitting element with a current corresponding to the gradation level. However, if there is a parasitic capacitance on the drain node of a transistor that supplies current to a light-emitting element, the charge (leakage current) remaining in the parasitic capacitance flows into the light-emitting element, causing it to emit a small amount of light. This phenomenon is sometimes called "floating black," because the OLED emits light even when the gradation level is zero, making the black appear to be floating. For this reason, a technique has been proposed in which the charge remaining in the drain node of the transistor is reset before a current is supplied to the light emitting element (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2010-243560 Summary of the Invention [Problem to be solved by the invention]

[0004] However, as space saving and high definition advances, adjacent pixel circuits are placed closer to each other. When pixel circuits are placed closer to each other and the black level prevention technology described in Patent Document 1 is applied, the brightness of the adjacent pixel circuits is affected, resulting in a degradation of display quality. [Means for solving the problem]

[0005] An electro-optical device according to one embodiment of the present disclosure includes a pixel circuit provided corresponding to a scanning line and a data line, the pixel circuit having a first transistor and a light-emitting element, the first transistor being capable of supplying a current to the light-emitting element according to a voltage between a gate node of the first transistor and a source node of the first transistor, a horizontal scanning period during which the scanning line is selected includes, in order, a compensation period, a first period, and a second period, during the compensation period, the gate node of the first transistor and the drain node of the first transistor are electrically connected to set the gate node of the first transistor to a voltage corresponding to a threshold voltage of the first transistor, during the first period, the gate node of the first transistor is changed from the voltage corresponding to the threshold voltage to a voltage corresponding to the luminance of the light-emitting element, during the second period, a voltage corresponding to the luminance of the light-emitting element is applied to the drain node of the first transistor, and during a light-emitting period after the second period, the first transistor is caused to supply a current to the light-emitting element according to the voltage between the gate node of the first transistor and the source node of the first transistor. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a perspective view showing an electro-optical device according to a first embodiment. [Figure 2] FIG. 2 is a block diagram showing the electrical configuration of the electro-optical device. [Figure 3] FIG. 2 is a circuit diagram illustrating a part of an electro-optical device. [Figure 4] FIG. 2 is a diagram illustrating a pixel circuit in an electro-optical device. [Figure 5] 4 is a timing chart showing the operation of the electro-optical device. [Figure 6] 5A and 5B are diagrams illustrating the operation of the electro-optical device. [Figure 7] 5A and 5B are diagrams illustrating the operation of the electro-optical device. [Figure 8] 5A and 5B are diagrams illustrating the operation of the electro-optical device. [Figure 9] 5A and 5B are diagrams illustrating the operation of the electro-optical device. [Figure 10] 5A and 5B are diagrams illustrating the operation of the electro-optical device. [Figure 11] 5A and 5B are diagrams illustrating the operation of the electro-optical device. [Figure 12] 5A and 5B are diagrams illustrating the operation of the electro-optical device. [Figure 13] FIG. 2 is a diagram illustrating parasitic capacitance in a pixel circuit. [Figure 14] FIG. 10 is a diagram showing parasitic capacitances in adjacent pixel circuits. [Figure 15] FIG. 10 is a diagram for explaining the operation when the gradation level is zero. [Figure 16] FIG. 10 is a diagram for explaining the operation when the gradation level is other than zero. [Figure 17] FIG. 10 is a diagram for explaining the operation when the gradation level is zero. [Figure 18] FIG. 10 is a block diagram showing the electrical configuration of an electro-optical device according to a second embodiment. [Figure 19] FIG. 2 is a diagram illustrating a pixel circuit in an electro-optical device. [Figure 20] 4 is a timing chart showing the operation of the electro-optical device. [Figure 21] 5A and 5B are diagrams illustrating the operation of the electro-optical device. [Figure 22] 5A and 5B are diagrams illustrating the operation of the electro-optical device. [Figure 23] 5A and 5B are diagrams illustrating the operation of the electro-optical device. [Figure 24] 5A and 5B are diagrams illustrating the operation of the electro-optical device. [Figure 25] 5A and 5B are diagrams illustrating the operation of the electro-optical device. [Figure 26] 10 is a timing chart showing another example of the control signal / Gel(i). [Figure 27]FIG. 1 is a perspective view showing a head-mounted display using an electro-optical device. [Figure 28] FIG. 2 is a diagram illustrating an optical configuration of a head-mounted display. [Figure 29] 10A and 10B are diagrams illustrating the operation of an electro-optical device according to a reference example. DETAILED DESCRIPTION OF THE INVENTION

[0007] Electro-optical devices according to embodiments of the present invention will be described below with reference to the drawings. Note that the dimensions and scale of each part in each drawing are appropriately different from those of the actual ones. Furthermore, the embodiments described below are preferred examples, and therefore various technically preferable limitations are applied. However, the scope of the present invention is not limited to these embodiments unless otherwise specified in the following description to the effect that the present invention is limited thereto.

[0008] First Embodiment FIG. 1 is a perspective view showing an electro-optical device 10 according to a first embodiment. The electro-optical device 10 is a microdisplay panel that displays images in, for example, a head-mounted display. The electro-optical device 10 includes a plurality of pixel circuits and a drive circuit that drives the pixel circuits. The pixel circuits and the drive circuit are integrated on a semiconductor substrate. The semiconductor substrate is typically a silicon substrate, but may be another type of semiconductor substrate.

[0009] The electro-optical device 10 is housed in a frame-shaped case 192 that has an opening corresponding to the display area 100. One end of an FPC board 194 is connected to the electro-optical device 10. FPC is an abbreviation for Flexible Printed Circuits. The other end of the FPC board 194 is provided with a plurality of terminals 196 that are connected to a host device (not shown). When the plurality of terminals 196 are connected to the host device, video data, synchronization signals, and the like are supplied to the electro-optical device 10 from the host device via the FPC board 194.

[0010] In the figure, the X direction is the direction in which the scanning lines in the electro-optical device 10 extend, which corresponds to the horizontal direction on the display screen, and the Y direction is the direction in which the data lines extend, which corresponds to the vertical direction on the display screen. The two-dimensional plane defined by the X and Y directions is the substrate surface of the semiconductor substrate. The Z direction is perpendicular to the X and Y directions and corresponds to the emission direction of light emitted from the light-emitting element (OLED) included in the pixel circuit.

[0011] FIG. 2 is a block diagram showing the electrical configuration of the electro-optical device 10, and FIG. 3 is a diagram showing the configuration of the main parts of the electro-optical device 10. As shown in FIG. As shown in FIG. 2, the electro-optical device 10 includes a control circuit 20, a data signal output circuit 30, a switch group 40, a capacitive element group 50, an initialization circuit 60, an auxiliary circuit 70, a display area 100, and a scanning line driving circuit 120.

[0012] 3, in the electro-optical device 10, m rows of scanning lines 12 are arranged along the X direction in the figure, and (3q) columns of data lines 14b are arranged along the Y direction and are electrically insulated from each other of the scanning lines 12. m and q are integers of 2 or more.

[0013] To distinguish the rows in the scanning line 12, they are called rows 1, 2, 3, ..., (m-1), and m from top to bottom in the figure. Note that to generally describe the scanning line 12 without specifying the row, it may be referred to as the ith row, where i is an integer between 1 and m. To distinguish the columns of the data lines 14b, they are referred to as columns 1, 2, 3, ..., (3q-2), (3q-1), and (3q) from left to right in the figures. The data lines 14b are grouped into groups of three columns in Figures 2 and 3. To generalize the groups, an integer j between 1 and q is used. Counting from the left, the j-th group includes three columns of data lines 14b: the (3j-2), (3j-1), and (3j) columns.

[0014] The pixel circuits 110R, 110B, and 110G are provided corresponding to the scanning lines 12 arranged in m rows and the data lines 14b arranged in (3q) columns. Specifically, pixel circuit 110R is provided corresponding to the intersection of the i-th row scanning line 12 and the (3j-2)th column data line 14b. Pixel circuit 110B is provided corresponding to the intersection of the i-th row scanning line 12 and the (3j-1)th column data line 14b. Pixel circuit 110G is provided corresponding to the intersection of the i-th row scanning line 12 and the (3j)th column data line 14b.

[0015] Pixel circuit 110R includes a light-emitting element that emits light containing a red component, pixel circuit 110B includes a light-emitting element that emits light containing a blue component, and pixel circuit 110G includes a light-emitting element that emits light containing a green component. A single color is expressed by additive color mixing of light emitted from pixel circuits 110R, 110B, and 110G that are adjacent to each other and belong to the same row. Therefore, in this embodiment, an image is displayed in which one color pixel is arranged in a matrix of m rows and q columns.

[0016] The pixel circuits 110R, 110B, and 110G represent the red, blue, and green components of one color pixel, respectively, and therefore should strictly speaking be called sub-pixel circuits. However, for the sake of convenience, they will be called pixel circuits in this description. In this embodiment, the array of color pixels (i rows x q columns) represented by the pixel circuits 110R, 110B, and 110G matches the array of color pixels in the image to be displayed. Note that, as described above, the array of color pixels represented by the pixel circuits does not have to match the array of color pixels in the image to be displayed. Furthermore, when the pixel circuits 110R, 110B, and 110G are generally described without specifying a color, the pixel circuits will be denoted by the reference numeral 110. The region in which the pixel circuits 110R, 110B, and 110G are arranged is an example of a display region 100.

[0017] 2, a control circuit 20 controls each component based on video data Vid and a synchronization signal Sync output from a host device. The video data Vid, supplied in synchronization with the synchronization signal Sync, specifies the gradation level of pixels in an image to be displayed, for example, by 8 bits for each of red (R), blue (B), and green (G). The synchronization signal Sync also includes a vertical synchronization signal that instructs the start of vertical scanning of the video data Vid, a horizontal synchronization signal that instructs the start of horizontal scanning, and a dot clock signal that indicates the timing of one pixel of video data.

[0018] The control circuit 20 generates control signals Gcp, Gref, Y_Ctr, / Gini, / Gorst, / Drst, L_Ctr, Sel(1) to Sel(q) and a clock signal Clk to control each unit. Although omitted in Fig. 2, the control circuit 20 outputs a control signal / Gcp that is the logical inverse of the control signal Gcp, a control signal / Gref that is the logical inverse of the control signal Gref, and control signals / Sel(1) to / Sel(q) that are the logical inverse of Sel(1) to Sel(q).

[0019] These control signals are logic signals. A leading " / " in the symbol of these control signals indicates that the control signal is negative logic, active at L level and inactive at H level. Control signals without a leading " / " indicate that the control signal is positive logic, inactive at L level and active at H level. In addition, the L level of the control signal is 0V, which is the reference voltage of zero, and the H level is, for example, 6.0V. In this description, unless otherwise specified, the voltage at a certain point refers to the difference between the potential at that point and the ground potential, which is the L level of a logic signal. Examples of voltages that may be mentioned include the threshold voltage of a transistor and the holding voltage of a capacitance element, which will be described later.

[0020] The brightness characteristics of the OLED included in the pixel circuit 110 do not necessarily match the grayscale levels indicated by the video data Vid supplied from the host device. Therefore, in order to cause the OLED to emit light at a brightness corresponding to the grayscale levels indicated by the video data Vid, the control circuit 20 up-converts the 8 bits of the video data Vid to, for example, 10 bits and outputs the up-converted data as video data Vdat. Therefore, the 10-bit video data Vdat corresponds to the grayscale levels specified by the video data Vid. For up-conversion, a look-up table is used that stores in advance the correspondence between the 8 bits of input video data Vid and the 10 bits of output video data Vdat.

[0021] The scanning line driving circuit 120 is a circuit for driving the pixel circuits 110 arranged in m rows (3q columns) in units of one row in accordance with a control signal Y_Ctr. The data signal output circuit 30 outputs a data signal to the data line 14b. Specifically, the data signal output circuit 30 outputs a data signal of a voltage corresponding to the grayscale level of the pixel expressed by the pixel circuit 110. In this embodiment, the voltage amplitude of the data signal output from the data signal output circuit 30 is compressed before being supplied to the data line 14b. Therefore, the compressed data signal also has a voltage corresponding to the grayscale level of the pixel. The data signal output circuit 30 also has the function of converting the serially supplied video data Vdat into parallel data of multiple phases (in this example, three phases corresponding to the number of columns of the data lines 14b that make up the group) and outputting the data.

[0022] The data signal output circuit 30 includes a shift register 31, a latch circuit 32, a D / A conversion circuit group 33, and an amplifier group . The shift register 31 sequentially transfers the video data Vdat supplied serially in synchronization with the clock signal Clk, and stores one row's worth of data, that is, (3q) pixel circuits' worth.

[0023] The latch circuit 32 latches the (3q) pieces of video data Vdat stored in the shift register 31 in accordance with the control signal L_Ctr, converts the latched video data Vdat into three-phase parallel data in accordance with the control signal L_Ctr, and outputs the converted data.

[0024] The D / A conversion circuit group 33 includes three D / A (Digital to Analog) converters. The three D / A converters convert the three-phase video data Vdat output from the latch circuit 32 into analog signals. The amplifier group 34 includes three amplifiers. The three amplifiers amplify the three-phase analog signals output from the D / A conversion circuit group 33 and output them as data signals Vd(1), Vd(2), and Vd(3). As will be described later, the control circuit 20 outputs control signals Sel(1) to Sel(q) that sequentially and exclusively become H level during a compensation period preceding a gate write period. The D / A conversion circuit may be configured, for example, such that a switch and a capacitance element are provided corresponding to each bit, and the charging and discharging of the capacitance element are controlled by the switch in accordance with each bit. Also, depending on the configuration of the data signal output circuit 30, the amplifier group 34 is not necessarily required. For example, if the D / A conversion circuit is configured such that a switch and a capacitance element are provided corresponding to each bit, and the charging and discharging of the capacitance element are controlled by the switch in accordance with each bit, the amplifier group 34 may not be required.

[0025] The scanning line driving circuit 120 generates scanning signals for scanning the scanning lines 12 row by row in accordance with a control signal Y_Ctr. Here, the scanning signals supplied to the 1st, 2nd, 3rd, ..., (m-1), and mth scanning lines 12 are denoted as / Gwr(1), / Gwr(2), ..., / Gwr(m-1), and / Gwr(m), respectively. The scanning signal supplied to the i-th scanning line 12 is denoted as / Gwr(i). In addition to the scanning signals / Gwr(1) to / Gwr(m), the scanning line driving circuit 120 generates control signals synchronized with the scanning signals for each row and supplies them to the display area 100, but these are not shown in Figures 2 and 3.

[0026] In the electro-optical device 10, data transfer lines 14a are provided corresponding to the data lines 14b. The switch group 40 is a collection of transmission gates 45 provided for each data transfer line 14a. Among these, the input terminals of q transmission gates 45 corresponding to the data transfer lines 14a of columns 1, 4, 7, ..., (3q-2) are commonly connected. Note that a data signal Vd(1) is supplied to this input terminal in time series for each pixel. Furthermore, the input terminals of q transmission gates 45 corresponding to the data transfer lines 14a of columns 2, 5, 8, . . . , (3q-1) are commonly connected, and a data signal Vd(2) is supplied to the input terminal in time series for each pixel. Similarly, the input terminals of q transmission gates 45 corresponding to the 3rd, 6th, 9th, . . . (3q)th columns of data transfer lines 14a are commonly connected, and a data signal Vd(3) is supplied to the input terminals in time series for each pixel. The output terminal of the transmission gate 45 in a certain column is connected to one end of the data transfer line 14a of that column.

[0027] The three transmission gates 45 corresponding to columns (3j-2), (3j-1), and (3j) belonging to the jth group are turned on when the control signal Sel(j) is at H level (when the control signal / Sel(j) is at L level), and are turned off when the control signal Sel(j) is at L level (when the control signal / Sel(j) is at H level). Due to space limitations, only the first group and the qth group are shown in Fig. 3, and the other groups are omitted. Also, the transmission gate 45 in Fig. 3 is simplified and depicted as a simple switch in Fig. 2.

[0028] In this description, the "on state" of a switch, transistor, or transmission gate means that both ends of the switch, between the source and drain nodes of a transistor, or between the input and output ends of a transmission gate are electrically connected, resulting in a low impedance state. Additionally, the "off state" of a switch, transistor, or transmission gate means that both ends of the switch, between the source and drain nodes, or both ends of a transmission gate are electrically disconnected, resulting in a high impedance state. Also, in this description, "electrically connected" or simply "connected" means a direct or indirect connection or coupling between two or more elements.

[0029] The capacitive element group 50 is a collection of capacitive elements 51 provided for each data transfer line 14a. One end of the capacitive element 51 corresponding to a certain column of data transfer line 14a is connected to one end of the data transfer line 14a, and the other end of the capacitive element 51 is grounded to a constant potential, for example, a reference potential of zero voltage.

[0030] The initialization circuit 60 is a collection of P-channel MOS transistors 66, 67, and 68 provided for each data line 14b. Note that MOS is an abbreviation for Metal-Oxide-Semiconductor field-effect transistor. A control signal / Drst is supplied to the gate node of a transistor 66 corresponding to the data line 14b of a certain column, a voltage Vel is applied to the source node of the transistor 66, and the drain node of the transistor 66 is connected to the data line 14b of the column. In addition, a control signal / Gorst is supplied to the gate node of a transistor 67 corresponding to the data line 14b of a certain column, a reset voltage Vorst is applied to the source node of the transistor 67 via the power supply line 118, and the drain node of the transistor 67 is connected to the data line 14b of the column. A control signal / Gini is supplied to the gate node of the transistor 68 corresponding to the data line 14b of a certain column, a voltage Vini is applied to the source node of the transistor 68, and the drain node of the transistor 68 is connected to the data line 14b of the column.

[0031] The auxiliary circuit 70 is a collection of transmission gates 72 and 73 provided for each column and capacitance elements 74 and 75 provided for each column. Here, the transmission gate 72 corresponding to a certain column is turned on when the control signal Gcp is at H level (when the control signal / Gcp is at L level), and is turned off when the control signal Gcp is at L level (when the control signal / Gcp is at H level). The input terminal of the transmission gate 72 corresponding to a certain column is connected to the other end of the data transfer line 14a of that column, and the output terminal of the transmission gate 72 corresponding to that column is connected to the output terminal of the transmission gate 73 corresponding to that column, one terminal of the capacitance element 74 corresponding to that column, and one terminal of the capacitance element 75 corresponding to that column.

[0032] The transmission gate 73 corresponding to a certain column is turned on when the control signal Gref is at H level (when the control signal / Gref is at L level), and is turned off when the control signal Gref is at L level (when the control signal / Gref is at H level). A voltage Vref is commonly applied to the input terminals of the transmission gates 73 in each column. The other end of the capacitance element 75 corresponding to a certain column is grounded to a constant potential, for example, a reference potential of zero voltage. The other end of the capacitive element 74 corresponding to a certain column is connected to one end of the data line 14b corresponding to that column.

[0033] In the first embodiment, one end of the data transfer line 14a is connected to the output terminal of the transmission gate 45 and one end of the capacitive element 51, and the other end of the data transfer line 14a is connected to the input terminal of the transmission gate 72. Since the display area 100 is located between the switch group 40 and the auxiliary circuit 70, the data transfer line 14a passes through the display area 100. On the other hand, the data signal supplied to the data transfer line 14a via the transmission gate 45 is supplied to the pixel circuit 110 as a data signal via the transmission gate 72, the capacitive element 74, and the data line 14b. Therefore, the data signal output from the data signal output circuit 30 reaches the auxiliary circuit 70 located on the opposite side of the display area 100 via the data transfer line 14a, then returns and is supplied to the pixel circuit 110 via the capacitive element 74 and the data line 14b.

[0034] In this configuration, the area where the capacitive element 74 is provided and the data signal output circuit 30 are located on either side of the display area 100. Therefore, when the display area 100 is used as a reference, elements are not concentrated in the area where the data signal output circuit 30 is provided. The display area 100 needs to be spaced a certain distance from the four sides, and even areas where the data signal output circuit 30 is not provided need to be some distance from the sides. If elements are concentrated in the data signal output circuit 30 and its surrounding area, the area required for that area will increase, which may hinder miniaturization. In contrast, in the configuration of the first embodiment, the area required for that area is reduced, thereby enabling miniaturization.

[0035] 4 is a diagram showing the configuration of a pixel circuit 110. The pixel circuits 110 arranged in m rows (3q columns) are electrically identical to one another. For this reason, the pixel circuits 110 will be described by taking as a representative one pixel circuit 110 in the ith row and corresponding to an arbitrary column.

[0036] As shown in the figure, the pixel circuit 110 includes P-channel MOS transistors 121 to 124, an OLED 130, and a capacitance element 140. Furthermore, the pixel circuits 110 in the i-th row are supplied with the control signals / Gcmp(i) and / Gel(i) from the scanning line driving circuit 120 in addition to the scanning signal / Gwr(i).

[0037] The OLED 130 is a light-emitting element in which a light-emitting layer 132 is sandwiched between a pixel electrode 131 and a common electrode 133. The pixel electrode 131 functions as an anode, and the common electrode 133 functions as a cathode. The common electrode 133 is light-reflective and light-transmitting. In the OLED 130, when a current flows from the anode to the cathode, holes injected from the anode and electrons injected from the cathode recombine in the light-emitting layer 132 to generate excitons, thereby generating white light.

[0038] In this embodiment, the generated white light resonates in an optical resonator composed of, for example, a reflective layer and a semi-reflective semi-transmissive layer (not shown), and is emitted at a resonant wavelength set corresponding to one of the colors R (red), G (green), and B (blue). A color filter corresponding to the color is provided on the light exit side of the optical resonator. Therefore, the light emitted from the OLED 130 is colored by the optical resonator and color filter before being viewed by an observer. Note that the optical resonator is not shown. Furthermore, when the electro-optical device 10 simply displays a monochromatic image with only light and dark, the color filter is omitted.

[0039] In the transistor 121, the gate node g is connected to the drain node of the transistor 122, the source node s is connected to the power supply line 116 of the voltage Vel, and the drain node d is connected to the source node of the transistor 123 and the source node of the transistor 124. In addition, in the capacitance element 140, one end is connected to the gate node g of the transistor 121, and the other end is connected to the power supply line 116 of a constant voltage, for example, the voltage Vel. Therefore, the capacitance element 140 holds the voltage of the gate node g of the transistor 121. The capacitive element 140 may be, for example, a parasitic capacitance at the gate node g of the transistor 121, or a capacitance formed by sandwiching an insulating layer between different conductive layers on a silicon substrate.

[0040] In the transistor 122 of the pixel circuit 110 in the i-th row and any one column, the gate node is connected to the i-th row scanning line 12 and the source node is connected to the data line 14b of the column. In the transistor 123 of the pixel circuit 110 in the i-th row and any one column, the control signal / Gcmp(i) is supplied to the gate node, and the drain node is connected to the data line 14b of that column. In the transistor 124 of the pixel circuit 110 in the i-th row and any one column, a control signal / Gel(i) is supplied to the gate node, and the drain node is connected to the pixel electrode 131 which is the anode of the OLED 130. The common electrode 133, which functions as the cathode of the OLED 130, is connected to a power supply line of a voltage Vct. Since the electro-optical device 10 is formed on a silicon substrate, the substrate potential of the transistors 121 to 124 is set to a potential equivalent to, for example, the voltage Vel.

[0041] FIG. 5 is a timing chart for explaining the operation of the electro-optical device 10. As shown in FIG. In the electro-optical device 10, horizontal scanning is performed in the order of the 1st, 2nd, 3rd, . . . , mth rows during one frame (V) period. In this description, the period of one frame (V) refers to the period required to display one frame of the image specified by the video data Vid. If the length of one frame period is the same as the vertical synchronization period, for example, if the frequency of the vertical synchronization signal included in the synchronization signal Sync is 60 Hz, it is 16.7 milliseconds, which corresponds to one cycle of the vertical synchronization signal. The period required for horizontal scanning of one row is the horizontal scanning period (H). Note that in Figures 5 and 6, the vertical scale indicating voltage is not necessarily consistent across the signals.

[0042] The operation during the horizontal scanning period (H) in each row is almost the same for the pixel circuits 110. The operation of the pixel circuits 110 in the 1st to (3q)th columns of a row scanned in a certain horizontal scanning period (H) is also almost the same. Therefore, the following description will focus on the pixel circuit 110 in the i-th row and the (3j-2)th column.

[0043] In the electro-optical device 10, the horizontal scanning period (H) is divided into six periods in chronological order: an initialization period (A1), (B), (C), a compensation period (D), a gate writing period (E), and a drain writing period (F). The operation of the pixel circuit 110 further includes a light emitting period (G) in addition to the above six periods.

[0044] Of the initialization periods (A1), (B), and (C), the initialization period (A1) is a period for setting the transistor 121 to an off state. The initialization period (B) is a process for resetting the potential at the anode of the OLED 130, and the initialization period (C) is a period for applying a voltage to the gate node g to turn the transistor 121 to an on state at the start of the compensation period (D). The compensation period (D) is a period for causing the gate node g of the transistor 121 to converge to a voltage corresponding to the threshold voltage of the transistor 121. The gate write period (E) is a period during which a voltage corresponding to the gradation level is written to the gate node g of the transistor 121, and more specifically, is a period during which the gate node g of the transistor 121 is changed from a voltage corresponding to the threshold voltage by an amount corresponding to the current flowing through the OLED 130. The drain write period (F) is a period in which the voltage written to the gate node g of the transistor 121 during the gate write period is written to the drain node d of the transistor 121.

[0045] During the initialization period (A1) of each horizontal scanning period (H), the control signals / Gini and / Gorst are at H level, the control signal / Drst is at L level, the control signal Gref is at H level, and the control signal Gcp is at L level. As a result, the transistor 68 is turned off, the transistor 67 is turned off, the transistor 66 is turned on, the transmission gate 73 is turned on, and the transmission gate 72 is turned off.

[0046] Furthermore, during the initialization period (A1) of the horizontal scanning period (H) in which the i-th row is selected, the scanning signal / Gwr(i) is at L level, the control signal / Gcmp(i) is at H level, and the control signal / Gel(i) is at H level. As a result, in the pixel circuit 110, the transistor 122 is turned on and the transistors 123 and 124 are turned off.

[0047] 6, during the initialization period (A1), voltage Vref is applied to one end of capacitance element 74, one end of capacitance element 75, and the output end of transmission gate 72 via transmission gate 73. Also, in the pixel circuit 110, voltage Vel is applied to one end of capacitance element 140 and gate node g of transistor 121 via transistor 66, data line 14b, and transistor 122 in this order. When voltage Vel is applied to gate node g, the voltage between the gate node and source node becomes zero, forcing transistor 121 into an off state. Also, voltage Vel is applied to the other end of capacitance element 74 via data line 14b, so that capacitance element 74 is charged to voltage |Vel-Vref|. 6, the thick lines indicate the voltage application path and do not necessarily indicate the direction of current flow, as in FIGS. 7 to 11 and 21 to 24.

[0048] During the initialization period (B) of each horizontal scanning period (H), the control signal / Gini is at H level, the control signal / Gorst is at L level, the control signal / Drst is at H level, the control signal Gref is at H level, and the control signal Gcp is at L level. As a result, the transistor 68 remains off, the transistor 67 turns on, the transistor 66 turns off, the transmission gate 73 remains on, and the transmission gate 72 remains off.

[0049] Furthermore, during the initialization period (B) of the horizontal scanning period (H) in which the i-th row is selected, the scanning signal / Gwr(i) becomes H level, the control signal / Gcmp(i) becomes L level, and the control signal / Gel(i) becomes L. As a result, in the pixel circuit 110, the transistor 122 changes to the OFF state, and the transistors 123 and 124 change to the ON state.

[0050] Therefore, during the initialization period (B), as shown in FIG. 7, one end of the capacitor 74, one end of the capacitor 75, and the output end of the transmission gate 72 are maintained at voltage Vref. In the pixel circuit 110, a reset voltage Vorst is applied to the pixel electrode 131, which is the anode of the OLED 130, via the transistor 67, the data line 14b, and the transistors 123 and 124 in this order. The OLED 130 has a parasitic capacitance component because the light-emitting layer 132 is sandwiched between the pixel electrode 131 and the common electrode 133. During the initialization period (B), application of the reset voltage Vorst to the pixel electrode 131 resets the voltage held in the capacitance component, specifically, a voltage corresponding to the current flowing through the OLED 130 during the light-emitting period (G). The reset voltage Vorst is a voltage that causes the OLED 130 to not emit light, and is, specifically, zero volts corresponding to the L level or a voltage close to zero volts (0 to 1 volt). Furthermore, the reset voltage Vorst is applied to the other end of the capacitive element 74 via the data line 14b, so that the capacitive element 74 is charged to a voltage |Vorst-Vref|.

[0051] During the initialization period (C) of each horizontal scanning period (H), the control signal / Gini goes to L level, the control signal / Gorst goes to H level, the control signal / Drst is H level, the control signal Gref is H level, and the control signal Gcp is L level. As a result, the transistor 68 changes to the ON state, the transistor 67 changes to the OFF state, the transistor 66 remains OFF, the transmission gate 73 remains ON, and the transmission gate 72 remains OFF.

[0052] Furthermore, during the initialization period (C) of the horizontal scanning period (H) in which the i-th row is selected, the scanning signal / Gwr(i) goes to L level, the control signal / Gcmp(i) goes to H level, and the control signal / Gel(i) goes to H level. As a result, in the pixel circuit 110, the transistor 122 changes to the ON state, and the transistors 123 and 124 change to the OFF state.

[0053] 8, one end of the capacitance element 74, one end of the capacitance element 75, and the output end of the transmission gate 72 are maintained at voltage Vref. In addition, in the pixel circuit 110, voltage Vini is applied to one end of the capacitance element 140 and to the gate node g of the transistor 121, via transistor 68, data line 14b, and transistor 122 in this order. Since voltage Vini is applied to the other end of the capacitance element 74 via data line 14b, the capacitance element 74 is charged to voltage |Vini-Vref|.

[0054] In the compensation period (D) of each horizontal scanning period (H), the control signal / Gini becomes H level, the control signal / Gorst is H level, the control signal / Drst is H level, the control signal Gref is H level, and the control signal Gcp is L level. As a result, the transistor 68 changes to the OFF state, the transistor 67 maintains the OFF state, the transistor 66 maintains the OFF state, the transmission gate 73 maintains the ON state, and the transmission gate 72 maintains the OFF state.

[0055] Furthermore, during the compensation period (D) of the horizontal scanning period (H) in which the i-th row is selected, the scanning signal / Gwr(i) is at L level, the control signal / Gcmp(i) changes to L level, and the control signal / Gel(i) is at H level. As a result, in the pixel circuit 110, the transistor 122 maintains the ON state, the transistor 123 changes to the ON state, and the transistor 124 maintains the OFF state.

[0056] Therefore, during the compensation period (D), as shown in FIG. 9, one end of the capacitive element 74, one end of the capacitive element 75, and the output end of the transmission gate 72 are maintained at the voltage Vref. In the pixel circuit 110, the capacitive element 140 is in a state of holding the voltage (Vel-Vini) between the gate node and the source node of the transistor 121 during the immediately preceding initialization period (C). In this state, when transistors 122 and 123 are turned on, transistor 121 is turned on, and the gate node and drain node of transistor 121 are connected, i.e., the transistor is diode-connected. Therefore, the voltage Vgs between the gate node and source node of transistor 121 converges to approach the threshold voltage of transistor 121. Here, if the threshold voltage is denoted as Vth for convenience, the gate node g of transistor 121 converges to approach the voltage (Vel-Vth) corresponding to the threshold voltage Vth.

[0057] At the beginning of the compensation period (D), it is necessary for a current to flow from the source node to the drain node in the diode-connected transistor 121. Therefore, the voltage Vini applied to the gate node g in the initialization period (C) before the compensation period (D) is Vini <Vel-Vth This is the relationship.

[0058] Furthermore, during the compensation period (D), the gate node g of the transistor 121 is connected to the data line 14b via the transistor 122, and the drain node of the transistor 121 is connected to the data line 14b via the transistor 123. Therefore, the voltages of the data line 14b and the other end of the capacitance element 74 also converge to approach the voltage (Vel-Vth). Therefore, the capacitance element 74 is charged to the voltage |Vel-Vth-Vref|.

[0059] In the compensation period (D), the control signals Sel(1) to Sel(q) sequentially and exclusively go to H level. Although omitted in Fig. 9, in the compensation period (D), the control signals / Sel(1) to / Sel(q) sequentially and exclusively go to L level in synchronization with the control signals Sel(1) to Sel(q). Furthermore, when, for example, control signal Sel(j) among the control signals Sel(1) to Sel(q) goes high, the data signal output circuit 30 outputs data signals Vd(1) to Vd(3) for three pixels corresponding to the intersection of the scanning line 12 in the i-th row and the data line 14b belonging to the j-th group. More specifically, during the period when the control signal Sel(j) goes high, the data signal output circuit 30 outputs a data signal Vd(1) corresponding to the pixel in the i-th row (3j-2) column, a data signal Vd(2) corresponding to the pixel in the i-th row (3j-1) column, and a data signal Vd(3) corresponding to the pixel in the i-th row (3j) column. As a specific example, if j is "2", during the period when the control signal Sel(2) is at H level, the data signal output circuit 30 outputs a data signal Vd(1) corresponding to the pixel in the i-th row and fourth column, outputs a data signal Vd(2) corresponding to the pixel in the i-th row and fifth column, and outputs a data signal Vd(3) corresponding to the pixel in the i-th row and sixth column.

[0060] When the control signals Sel(1) to Sel(q) successively and exclusively go to H level, the voltage of the data signal corresponding to each pixel is held in the capacitive elements 51 corresponding to the 1st to (3q)th columns. Note that Figure 9 shows a state in which the control signal Sel(j) corresponding to the jth group to which the pixel circuit 110 belongs becomes H level during the compensation period (D), and the voltage Vdata of the data signal Vd(1) is held in the capacitive element 51.

[0061] During the gate writing period (E) of each horizontal scanning period (H), the control signal / Gini is at H level, the control signal / Gorst is at H level, the control signal / Drst is at H level, the control signal Gref becomes L level, and the control signal Gcp becomes H level. As a result, the transistors 68, 67, and 66 remain in the OFF state, the transmission gate 73 changes to the OFF state, and the transmission gate 72 changes to the ON state.

[0062] Furthermore, during the gate writing period (E) of the horizontal scanning period (H) in which the i-th row is selected, the scanning signal / Gwr(i) is at L level, the control signal / Gcmp(i) changes to H level, and the control signal / Gel(i) is at H level. As a result, in the pixel circuit 110, the transistor 122 maintains the ON state, the transistor 123 changes to the OFF state, and the transistor 124 maintains the OFF state.

[0063] 10 , during the gate writing period (E) of the horizontal scanning period (H) in which the i-th row is selected, one end of the capacitance element 74 changes from the voltage Vref in accordance with the voltage held at one end of the capacitance element 51 due to the OFF state of the transmission gate 73 and the ON state of the transmission gate 72. This voltage change is propagated to the gate node g via the capacitance element 74, the data line 14b, and the transistor 122 in this order. The voltage of the gate node g after this change is held in the capacitance element 140.

[0064] 10, the capacitance of the capacitive element 51 is denoted as Cref, the capacitance of the capacitive element 74 is denoted as Cblk, the capacitance of the capacitive element 75 is denoted as Cdt, and the capacitance of the capacitive element 140 is denoted as Cpix. Also, the voltage of the data signal Vd(1) held at one end of the capacitive element 51 during the compensation period (D) is denoted as Vdata. The voltage change ΔV of the gate node g from the compensation period (D) to the gate writing period (E) is expressed by the following equation (1).

[0065]

number

[0066] That is, as shown in equation (1), the gate node g changes to a value obtained by multiplying the voltage change (Vdata-Vref) at one end of the capacitance element 74 by the coefficient Ka. The coefficient Ka is a coefficient less than "1" and is determined by the capacitances Cref, Cblk, Cdt, and Cpix. In other words, the capacitances Cref, Cblk, Cdt, and Cpix are designed to have appropriate values, and the coefficient Ka is set to be less than "1." If the coefficient Ka is less than "1," the voltage amplitude from the minimum value to the maximum value of the data signal voltage Vdata is compressed according to the coefficient Ka and propagates to the gate node g. When the pixel circuit 110 is miniaturized, a very small change in the voltage Vgs between the gate node and the source node of the transistor 121 may cause a large change in the current flowing through the OLED 130 . Even in this case, in the first embodiment, the voltage amplitude of the voltage Vdata of the data signal is compressed according to the coefficient Ka and propagated to the gate node g, so that the current flowing through the OLED 130 can be controlled with high precision.

[0067] After the gate write period (E), the drain write period (F) begins. During the drain write period (F), the control signals / Gini, / Gorst, / Drst, Gref, and Gcp do not change from those during the gate write period (E). Therefore, the transistors 68, 67, and 66 remain off, the transmission gate 73 remains off, and the transmission gate 72 remains on.

[0068] Also, during the drain writing period (F) of the horizontal scanning period (H) in which the i-th row is selected, the scanning signal / Gwr(i) becomes H level, the control signal / Gcmp(i) becomes L level, and the control signal / Gel(i) is H level. As a result, in the pixel circuit 110, the transistor 122 changes to the OFF state, the transistor 123 changes to the ON state, and the transistor 124 maintains the OFF state.

[0069] 11, in the drain write period (F) of the horizontal scanning period (H) in which the i-th row is selected, the voltage at the other end of the capacitance element 74, i.e., the same voltage as the gate node g of the transistor 121 in the previous gate write period (E), is applied to the drain node d of the transistor 121 sequentially via the data line 14b and the on-state transistor 123. In other words, the same voltage as the voltage supplied to the data line 14b in the previous gate write period (E) is applied to the drain node d of the transistor 121 via the transistor 123. The effect of applying the same voltage as that applied to the gate node g of the transistor 121 to the drain node of the transistor 121 during the drain write period (F) will be described later.

[0070] After the drain writing period (F) ends, the scanning signal / Gwr(i) maintains the H level, and the control signal / Gcmp(i) changes from L to H. As a result, in the pixel circuit 110, the transistor 122 maintains the OFF state, and the transistor 123 changes to the OFF state. After this, a light emitting period (G) begins. In detail, in this embodiment, the light emitting period (G) continues from the horizontal scanning period (H) in which the i-th row is selected until the horizontal scanning period (H) in which the i-th row is selected again, after a period of one frame (V). In this period, the control signal / Gel(i) becomes L level. 12, in the light emission period (G) of the i-th row, the transistor 121 passes, to the OLED 130, a current Iel that corresponds to the voltage Vgs and is limited by the resistance between the source and drain of the transistor 124. Therefore, the OLED 130 emits light with a luminance that corresponds to the current Iel.

[0071] 6 to 12, the regions where the capacitive element group 50 and the initialization circuit 60 are provided are not particularly distinguished.

[0072] In the first embodiment, the amplitude of the voltage Vdata of the data signal output from the data signal output circuit 30 is compressed by passing it through the capacitive element 74, and is supplied to the gate node g of the pixel circuit 110 as a data signal. On the other hand, in the first embodiment, the threshold voltage Vth of the transistor 121 is compensated for during the compensation period (D). Next, we will explain the usefulness of the compensation period (D). To avoid complicating the equations, we will assume that the compression ratio of the data signal voltage Vdata is 1, i.e., that the data signal voltage Vdata is supplied to the data line 14b as is during the gate write period (E) after the compensation period (D). We will also assume that the resistance between the source and drain nodes of the transistor 124 is ideally zero during the light emission period (G). First, the current Iel flowing through the OLED 130 in the light emitting period (G) can be expressed as in the following equation (2).

[0073]

number

[0074]

number

[0075] In equation (3), W is the channel width of the transistor 121, L is the channel length of the transistor 121, μ is the carrier mobility, and Cox is the capacitance per unit area of ​​the (gate) oxide film in the transistor 121.

[0076] In a configuration in which the data signal voltage Vdata is not compressed and the threshold voltage of the transistor 121 is not compensated, when the data signal voltage Vdata is applied directly to the gate node g of the transistor 121, the voltage Vgs between the gate node and source node of the transistor 121 can be expressed as follows:

[0077]

number

[0078]

number

[0079] As expressed in equation (5), the current Iel is affected by the threshold voltage Vth. Here, due to semiconductor processes, the variation in the threshold voltage Vth of the transistor 121 is in the range of several mV to several tens of mV. If the threshold voltage Vth of the transistor 121 varies in the range of several mV to several tens of mV, there is a risk that the current Iel may differ by up to 40% between adjacent pixel circuits 110. The current-luminance characteristic of the OLED 130 is roughly linear. Therefore, in a configuration in which the threshold voltage Vth is not compensated, even if the same data signal voltage Vdata is supplied to the two pixel circuits 110 in order to make the two OLEDs 130 emit light at the same luminance, the currents that actually flow through the OLEDs 130 will differ. Therefore, in a configuration in which the threshold voltage Vth is not compensated, the luminance will vary, significantly impairing the display quality.

[0080] During the compensation period (D), if the gate node g of the transistor 121 is converged to approach the voltage (Vel-Vth) and then changed to the voltage Vdata, the voltage Vgs between the gate node and source node of the transistor 121 can be expressed as follows:

number

[0081] The coefficient k2 in equation (6) is a coefficient determined by the capacitances Cblk and Cpix in a configuration in which the voltage Vdata of the data signal is not compressed (a configuration without the capacitive element 74). When the voltage Vgs is expressed as in equation (6), the current Iel flowing through the OLED 130 can be expressed as in the following equation (7).

number

[0082] In equation (7), the term for the threshold voltage Vth is removed, and the current Iel is determined by the voltage Vdata of the data signal. This makes it possible to suppress degradation of display quality caused by the threshold voltage Vth of the transistor 121. In the embodiment, as shown in the formula (1), the voltage amplitude from the minimum value to the maximum value of the voltage Vdata of the data signal is actually compressed according to the coefficient Ka and propagated to the gate node g.

[0083] Furthermore, in the first embodiment, a drain writing period (F) is provided after the compensation period (D) and the gate writing period (E) and before the light emitting period (G). The drain node d of the transistor 121 converges to approach a voltage (Vel-Vth) corresponding to the threshold voltage Vth at the end of the compensation period (D), and the voltage (Vel-Vth) is held by the parasitic capacitance. That is, a charge remains at the drain node d of the transistor 121 at the end of the compensation period (D). If the drain writing period (F) is not provided and the light-emitting period (G) begins, a leakage current will flow to the OLED 130 due to the charge remaining at the drain node.

[0084] Specifically, during the gate writing period (E), even if a data signal corresponding to a gradation level of zero is held at the gate node g of the transistor 121, the residual charge causes a leakage current to flow through the OLED 130, resulting in a slight light emission (floating black).

[0085] Therefore, as a reference example, a configuration was considered in which a reset voltage Vorst is applied to the drain node d of the transistor 121 during the drain writing period (F) to reset the charge remaining from the end of the compensation period (D). Specifically, in this reference example, the control signals / Gcmp(i) and Gcp are set to the L level during the drain write period, as shown by the dashed line rst in Fig. 15 or 16. As a result, as shown in Fig. 29, the reset voltage Vorst is applied to the drain node d via the transistor 67 in the on state, the data line 14b, and the transistor 123 in the on state in this order.

[0086] However, in an actual pixel circuit 110, as shown in FIG. 13, a capacitance Cgd_1 exists parasitic between the gate node and the drain node of the transistor 121, and a capacitance Cgd_3 exists parasitic between the gate node and the drain node of the transistor 123.

[0087] Therefore, when the control signal / Gcmp(i) changes from L level to H level and the transistor 123 changes from an on state to an off state, the voltage at the drain node d of the transistor 123 changes in the direction of the change in the control signal / Gcmp(i), a phenomenon called push-up (also called punch-through or field-through) occurs. The drain node d of the transistor 123 is connected to the drain node of the transistor 121. Therefore, a voltage change at the drain node d of the transistor 123 results in a voltage change at the drain node d of the transistor 123.

[0088] Here, at the drain node d of the transistor 123 (121), the voltage change ΔVdr_d due to the push-up can be expressed as in the following equation (8).

[0089]

number

[0090] Furthermore, when a voltage change occurs at the drain node d of the transistor 123 (121), the voltage change propagates to the gate node g of the transistor 121 via the parasitic capacitance Cgd_1. A voltage change ΔVdr_g that is exerted on the gate node g of the transistor 121 by a voltage change at the drain node d of the transistor 123 (121) can be expressed as in the following equation (9).

[0091]

number

[0092] In this embodiment, since the transistors 121 and 123 are P-channel transistors, the potential change at the gate or drain node when they change from the on state to the off state is in the upward direction. If the transistors 121 and 123 were N-channel transistors, the potential change at the gate or drain node when they change from the on state to the off state would be in the downward direction, which is sometimes called push-down.

[0093] 13 is a diagram focusing on one pixel circuit 110, but parasitic capacitance may also be a problem between pixel circuits 110 adjacent to each other in the X direction. For example, as shown in Fig. 14, a parasitic capacitance Cpp exists between the gate node g of the transistor 121 in the pixel circuit 110R and the drain node d of the transistor 121 (123) in the pixel circuit 110G adjacent to the pixel circuit 110R on the left.

[0094] Figures 15 and 16 are diagrams comparing voltage changes at various parts of the pixel circuit 110 in the i-th row and an arbitrary column in the reference example and this embodiment, where the dashed line indicates the reference example and the solid line indicates this embodiment. In detail, Figures 15 and 16 show voltage changes for voltages Vdt, Vdr_d and Vdr_g during the compensation period (D), gate writing period (E), drain writing period (F) and light emission period (G) of the horizontal scanning period (H) in which the i-th row is selected. Note that voltage Vdt is the voltage at data line 14b in an arbitrary column, voltage Vdr_d is the voltage at drain node d of transistor 121 (123) in pixel circuit 110 in the i-th row and an arbitrary column, and voltage Vdr_g is the voltage at gate node g of transistor 121 in the pixel circuit 110. 15 shows a case where the gradation level is zero (black display) in the pixel circuit 110, and Fig. 16 shows a case where the gradation level is other than zero (white display) in the pixel circuit 110. In this embodiment, the gradation level at which a current is passed through the light emitting element 130 to emit light is taken as an example of a white display, and includes levels from the maximum gradation to a low gradation.

[0095] First, the operation of pixel circuit 110 when the grayscale level is set to zero will be described. 15, the voltage Vdt of the data line 14b converges from the voltage Vini in the initialization period (C) to approach a voltage (Vel-Vth) at the end of the compensation period (D). At the start of the gate writing period (E), the voltage Vdt changes to a voltage Vel corresponding to the black level. The voltage Vdr_d at the drain node d of the transistor 121 converges to approach the voltage (Vel-Vth) at the end of the compensation period (D). In this state, the voltage Vdr_g at the gate node g also converges to approach the voltage (Vel-Vth), and the source node-drain node of the transistor 121 is not in an off state. Therefore, when the transistor 123 enters an off state at the end of the compensation period (D), the voltage Vdr_d rises to the voltage Vel, as shown by U1 in FIG. 15. At the start of the gate write period (E), the voltage Vdr_g of the gate node g of the transistor 121 changes from a voltage that converges to approach the voltage (Vel-Vth) to a voltage Vel corresponding to the black level, as shown by U2 in Fig. 15. This voltage change propagates to the drain node d of the transistor 121 via the capacitance Cgd_1, and raises the voltage Vdr_d, as shown by U3 in Fig. 15. With regard to the period up to the gate writing period (E), there is no difference between the reference example and this embodiment.

[0096] Regarding the period after the drain write period (F), first, referring to a reference example, the voltage Vdt of the data line 14b becomes the reset voltage Vorst at the start of the drain write period (F), as shown by the dashed line in Fig. 15. Similarly, the voltage Vdr_d decreases to the reset voltage Vorst at the start of the drain write period (F), as shown by D1. The drop in the voltage Vdr_d to the reset voltage Vorst propagates through the capacitance Cgd_1 to the gate node g of the transistor 121. As a result, the voltage Vdr_g of the gate node g drops as shown by D2 during the drain write period (F).

[0097] When the drain write period (F) ends, the control signal / Gcmp(i) changes from L to H level, so that the voltage Vdr_d is pushed up as shown by U4 in FIG. It rises by the voltage change amount ΔVdr_d (see equation (8)).

[0098] The voltage change ΔVdr_d in the voltage Vdr_d propagates to the gate node g of the transistor 121 via the capacitance Cgd_1. As a result, the voltage Vdr_g at the gate node g changes as shown by U5 in Figure 15. The potential fluctuation of the voltage Vdr_g at U5 is as shown in equation (9). After the drain writing period (F) ends, the voltage Vdt of the data line 14b is set to the voltage Vel in the initialization period (A1) of the next horizontal scanning period (H). The voltage Vdr_d is fixed to a value corresponding to the current Iel supplied to the OLED 130 in accordance with the voltage Vdr_g at the gate node g of the transistor 121 in the light emission period (G).

[0099] In contrast to the reference example, in this embodiment, during the drain write period (F), the same voltage as during the data write period (E) is applied to the drain node d of the transistor 121 via the data line 14b. Therefore, in the present embodiment, during the drain writing period (F), the voltage Vdt of the data line 14b and the voltage Vdr_d at the drain node d both become the voltage Vel corresponding to the black level. In the present embodiment, during the drain writing period (F), the voltage Vdr_d at the drain node d becomes higher than that in the reference example, and therefore the leakage current to the OLED 130 acts in the direction of increasing (the direction of decreasing contrast).

[0100] In this embodiment, the change in voltage Vdr_d from the gate write period (E) to the drain write period (F) is smaller than that in the reference example, and therefore the voltage change D4 when the voltage change ΔVdr_d propagates to the gate node g via the capacitance Cgd_1 is also smaller than D2 in the reference example. Therefore, in this embodiment, the voltage Vdr_g of the gate node g becomes higher than that of the reference example after the drain writing period (F) ends, and therefore the leakage current to the OLED 130 acts in a decreasing direction. Therefore, in this embodiment, the increase in the voltage Vdr_d at the drain node d acts to increase the leakage current to the OLED 130, but this is offset by the increase in the voltage Vdr_g at the gate node g acting to decrease the leakage current to the OLED 130. Therefore, according to this embodiment, it is possible to prevent the black level from floating due to the leakage current of the OLED 130.

[0101] Next, an example of the operation of the pixel circuit 110 when the grayscale level is set to a value other than zero will be described. 16, the voltage Vdt of the data line 14b converges from the voltage Vini in the initialization period (C) to approach the voltage (Vel-Vth) at the end of the compensation period (D). At the start of the gate writing period (E), the voltage Vdt becomes close to the voltage (Vel-Vth) corresponding to the white level, and therefore does not change from the compensation period (D). The voltage Vdr_d at the drain node d of the transistor 121 converges to approach the voltage (Vel-Vth) at the end of the compensation period (D). In this state, the voltage Vdr_g at the gate node g also converges to approach the voltage (Vel-Vth), and the source node-drain node of the transistor 121 is not in an off state. Therefore, when the transistor 123 enters an off state at the end of the compensation period (D), the voltage Vdr_d rises to the voltage Vel, as shown by U11 in FIG. 16. When the gradation level shown in FIG. 16 is set, at the beginning of the gate writing period (E), the voltage Vdt of the data line 14b does not change, and therefore the voltage Vdr_g of the gate node g of the transistor 121 also does not change from a voltage close to (Vel-Vth). With regard to the period up to the gate writing period (E), there is no difference between the reference example and this embodiment.

[0102] Regarding the drain write period (F) and thereafter, first, a reference example will be described. In the drain write period (F), the voltage Vdt of the data line 14b becomes the reset voltage Vorst as shown by the dashed line in Fig. 16. Similarly, in the drain write period (F), the voltage Vdr_d drops to the reset voltage Vorst as shown by D11. The drop in the voltage Vdr_d to the reset voltage Vorst propagates through the capacitance Cgd_1 to the gate node g of the transistor 121. As a result, the voltage Vdr_g of the gate node g drops as shown by D12 during the drain write period (F).

[0103] When the drain write period (F) ends, the control signal / Gcmp(i) changes from L to H level, and the voltage Vdr_d changes due to push-up as shown by U14 in FIG.

[0104] The voltage change in the voltage Vdr_d propagates through the capacitance Cgd_1 to the gate node g of the transistor 121. As a result, the voltage Vdr_g at the gate node g changes as shown by U15 in FIG. After that, when the light emitting period (G) begins, the voltage Vdr_d of the drain node d is fixed at a value corresponding to the current Iel supplied to the OLED 130 in accordance with the voltage Vdr_g at the gate node g of the transistor 121 .

[0105] In contrast to the reference example, in this embodiment, during the drain writing period (F), a voltage close to the voltage (Vel-Vth) corresponding to the same white level as during the data writing period (E) is applied to the drain node d of the transistor 121 via the data line 14b, so that the voltage Vdr_d changes as shown by D13 in Fig. 16. The change in the voltage Vdr_d propagates to the gate node g via the capacitance Cgd_1, so that the voltage Vdr_g changes as shown by D14 in Fig. 16. When the drain write period (F) ends, the control signal / Gcmp(i) changes from L to H level, so that the voltage Vdr_d changes by push-up as shown by U16 in Fig. 16. The change in voltage Vdr_d propagates to the gate node g via the capacitance Cgd_1, so that the voltage Vdr_g changes as shown by U17 in Fig. 16.

[0106] After that, when the light emitting period (G) begins, the voltage Vdr_d of the drain node d is fixed at a value corresponding to the current Iel supplied to the OLED 130 in accordance with the voltage Vdr_g at the gate node g of the transistor 121 .

[0107] It should be noted here that in the reference example, after the voltage Vdr_d is set to the reset voltage Vorst during the drain write period (F), it rises as shown by U14 due to the change in the control signal / Gcmp(i) from L to H level, and then it further rises as shown by U18 due to the supply of current Iel during the light emission period (G). In particular, the rise in voltage Vdr_d at U18 propagates via capacitance Cpp (see FIG. 14) to the gate node g of transistor 121 in the adjacent pixel circuit 110, raising the voltage at that gate node g. This rise in voltage at the gate node g acts to reduce the current Iel during the light-emitting period (G), thereby reducing the light-emission brightness of the OLED 130 in that adjacent pixel circuit 110 and causing display unevenness. In the timing charts shown in FIGS. 15 and 16, the values ​​of the voltages Vdt, Vdr_d, and Vdr_g include deviations due to voltage drops and the like. For example, at the end of the compensation period (D), it is desirable that the value of the voltage Vdr_g be (Vel-Vth), but in reality, the value may be close to (Vel-Vth). This embodiment includes the above. Also, for example, in FIG. 16, the value of the voltage Vdr_g during the gate write period (E) is set to (Vel-Vth) as an example of a case where the voltage does not change from the voltage at the end of the compensation period (D). However, if the voltage at the end of the compensation period (D) is close to (Vel-Vth), the value of the voltage Vdr_g during the gate write period (E) will be close to (Vel-Vth). This embodiment includes the above.

[0108] In contrast, in this embodiment, the change in voltage Vdr_d is smaller than in the reference example, and therefore the voltage change is less likely to propagate to the gate node g of the transistor 121 in the adjacent pixel circuit 110. Since the current Iel is almost zero when the gradation level is set to zero, the voltage Vdr_d hardly changes even when the light-emitting period (G) begins. Therefore, display unevenness due to the propagation of voltage changes via the capacitance Cpp does not occur. In other words, display unevenness due to the propagation of voltage changes via the capacitance Cpp occurs when the current Iel in the light-emitting period (G) is large, that is, when the gradation level is medium or higher. As described above, according to this embodiment, when the grayscale level is medium or higher, it is possible to suppress the occurrence of display unevenness caused by the voltage change propagating via the capacitance Cpp.

[0109] 17 is a diagram showing a comparison of voltage changes at various parts of the pixel circuit 110 in a configuration according to another reference example in which no voltage is applied to the drain node d of the transistor 121 during the drain write period (F), where the dashed line indicates the other reference example and the solid line indicates this embodiment. Also, FIG. 17 shows the case where the gradation level in the pixel circuit 110 is zero (black display).

[0110] 17, when the gradation level is set to zero during the drain writing period (F), the voltage Vdr_d of the drain node d in this embodiment is lower than that in the configuration according to another reference example in which no voltage is applied to the drain node d of the transistor 121. Therefore, in this embodiment, the leakage current to the OLED 130 acts to be lower than that in the other reference example. On the other hand, the voltage Vdr_g of the gate node g is almost the same in this embodiment and the other reference examples. Therefore, in this embodiment, the occurrence of black floating can be suppressed and the contrast ratio can be increased compared to the other reference examples.

[0111] In the electro-optical device 10, the pixel circuits 110 are driven by the control circuit 20, the data signal output circuit 30, the switch group 40, the capacitive element group 50, the initialization circuit 60, the auxiliary circuit 70 and the scanning line driving circuit 120, and therefore can be conceptualized as a driving circuit for these pixel circuits 110.

[0112] Second Embodiment Next, an electro-optical device 10 according to a second embodiment will be described. The second embodiment differs from the first embodiment in the following respects. Specifically, the second embodiment differs from the first embodiment in the configuration of the pixel circuits 110, the configuration of the display area 100, and the waveforms of the scanning signals and control signals. Therefore, the second embodiment will be mainly described with respect to the differences from the first embodiment, and the same elements as those in the first embodiment will be given the same reference numerals and descriptions thereof will be omitted as appropriate.

[0113] FIG. 18 is a circuit diagram showing a part of an electro-optical device 10 according to the second embodiment, and FIG. 19 is a diagram showing the configuration of a pixel circuit 110 in the second embodiment. The circuit shown in Figure 18 differs from the first embodiment shown in Figure 3 in that the initialization circuit 60 does not have transistors 66, 67 provided for each data line 14b, and that the power supply line 118 extends to the display area 100 and supplies a reset voltage Vorst to each pixel circuit 110.

[0114] In the second embodiment, the transistors 66 and 67 are not provided, and therefore the supply of the control signals / Drst and / Gorst by the control circuit 20 is omitted. Note that the omitted control signal / Gorst was common to each row, but in the second embodiment, control signals / Gorst(1) to / Gorst(m) corresponding to the 1st to mth rows are instead supplied by the scanning line driving circuit 120.

[0115] The configuration of the pixel circuit 110 in the second embodiment will be described with reference to Fig. 19. The circuit shown in Fig. 19 differs from the circuit shown in Fig. 4 in that a transistor 125 is provided. In detail, the transistor 125 is a P-channel MOS type similar to the transistors 121 to 124. In the pixel circuit 110 in the i-th row and any one column, the source node of the transistor 125 is connected to the pixel electrode 131 and the drain node of the transistor 124, and the drain node of the transistor 125 is connected to the power supply line 118 that extends to the display area 100. A control signal / Gorst(i) corresponding to the i-th row is supplied to the gate node of the transistor.

[0116] FIG. 20 is a timing chart for explaining the operation of the electro-optical device 10 according to the second embodiment. In this electro-optical device 10, the horizontal scanning period (H) is divided into four periods in chronological order: an initialization period (A2), a compensation period (D), a gate writing period (E), and a drain writing period (F). That is, the second embodiment does not have the initialization periods (B) and (C) as in the first embodiment. Furthermore, the operation of the pixel circuit 110 further includes a light-emitting period (G) in addition to the above four periods.

[0117] During the initialization period (A2), a process for resetting the potential at the anode of the OLED 130 and a process for applying a voltage Vini to the gate node g to turn on the transistor 121 at the beginning of the compensation period (D) are carried out in parallel.

[0118] During the initialization period (A2) of each horizontal scanning period (H), the control signal / Gini is at L level, the control signal Gref is at H level, and the control signal Gcp is at L level, so that the transistor 68 is turned on, the transmission gate 73 is turned on, and the transmission gate 72 is turned off.

[0119] Furthermore, during the initialization period (A2) of the horizontal scanning period (H) in which the i-th row is selected, the scanning signal / Gwr(i) is at L level, the control signal / Gcmp(i) is at H level, the control signal / Gel(i) is at H level, the control signal / Gcmp(i) is at H level, the control signal / Gel(i) is at H level, and the control signal / Gorst(i) is at L level. As a result, in the pixel circuit 110, the transistor 122 is turned on, the transistors 123 and 124 are turned off, and the transistor 125 is turned on.

[0120] Therefore, in the initialization period (A2), the voltage Vref is applied to one end of the capacitive element 74, one end of the capacitive element 75, and the output end of the transmission gate 72, as shown in FIG. In the pixel circuit 110, the voltage Vini is applied to one end of the capacitance element 140 and to the gate node g of the transistor 121, via the transistor 68, the data line 14b, and the transistor 122 in this order. As a result, a voltage (Vel-Vini) is maintained between the gate node and source node of the transistor 121. Furthermore, the voltage Vini is applied to the other end of the capacitive element 74 via the data line 14b, so that the capacitive element 74 is charged to the voltage |Vini-Vref|. In the pixel circuit 110, the reset voltage Vorst is applied to the pixel electrode 131, which is the anode of the OLED 130, via the power supply line 118 and the transistor 125 in this order. This resets the voltage held in the capacitance component of the OLED 130, more specifically, the voltage corresponding to the current flowing through the OLED 130 during the light-emitting period (G).

[0121] During the compensation period (D) of each horizontal scanning period (H), the control signal / Gini becomes H level, the control signal Gref is H level, and the control signal Gcp is L level, so that the transistor 68 changes to the OFF state, the transmission gate 73 maintains the ON state, and the transmission gate 72 maintains the OFF state.

[0122] Furthermore, during the compensation period (D) of the horizontal scanning period (H) in which the i-th row is selected, the scanning signal / Gwr(i) is at L level, the control signal / Gcmp(i) is at L level, the control signal / Gel(i) is at H level, and the control signal / Gorst(i) is at L level. Therefore, in the pixel circuit 110, the transistor 122 maintains the ON state, the transistor 123 changes to the ON state, the transistor 124 maintains the OFF state, and the transistor 125 maintains the ON state.

[0123] Therefore, during the compensation period (D), as shown in FIG. 22, one end of the capacitive element 74, one end of the capacitive element 75, and the output end of the transmission gate 72 are maintained at the voltage Vref. In the pixel circuit 110, the capacitance element 140 holds a voltage (Vel-Vini) between the gate node and source node of the transistor 121 during the initialization period (A2), and in this state, when the transistors 122 and 123 are turned on, the transistor 121 enters a diode-connected state. Therefore, the gate node g of the transistor 121 converges to a voltage (Vel-Vth) corresponding to the threshold voltage Vth. Furthermore, in the compensation period (D), the data line 14b and the other end of the capacitive element 74 also converge to approach the voltage (Vel-Vth), so that the capacitive element 74 is charged to the voltage |Vel-Vth-Vref|. In the compensation period (D), in the pixel circuit 110, the transistor 125 maintains the on state, and therefore the reset voltage Vorst is applied to the pixel electrode 131.

[0124] During the compensation period (D), the control signals Sel(1) to Sel(q) sequentially and exclusively become H level. Furthermore, when, for example, the control signal Sel(j) among the control signals Sel(1) to Sel(q) becomes H level, the data signal output circuit 30 outputs data signals Vd(1) to Vd(3) of three pixels corresponding to the intersection of the scanning line 12 in the i-th row and the data line 14b belonging to the j-th group. When the control signals Sel(1) to Sel(q) sequentially and exclusively go to H level, the voltage of the data signal corresponding to each pixel is held in the capacitive elements 51 corresponding to the first to (3q)th columns. Fig. 22 shows a state in which the control signal Sel(j) corresponding to the jth group to which the pixel circuit 110 belongs goes to H level during the compensation period (D), and the voltage Vdata of the data signal Vd(1) is held in the capacitive elements 51.

[0125] During the gate writing period (E) of each horizontal scanning period (H), the control signal / Gini is at H level, the control signal Gref is at L level, and the control signal Gcp is at H level. As a result, the transistor 68 remains in the OFF state, the transmission gate 73 is turned OFF, and the transmission gate 72 is turned ON. Also, during the gate write period (E) of the horizontal scanning period (H) in which the i-th row is selected, the scanning signal / Gwr(i) is at L level, the control signal / Gcmp(i) is at H level, the control signal / Gel(i) is at H level, and the control signal / Gorst(i) is at L level. Therefore, in the pixel circuit 110, the transistor 122 maintains the ON state, the transistor 123 changes to the OFF state, the transistor 124 maintains the OFF state, and the transistor 125 maintains the ON state.

[0126] 23, one end of the capacitance element 74 changes from the voltage Vref in accordance with the voltage held at one end of the capacitance element 51. This voltage change is propagated to the gate node g via the capacitance element 74, the data line 14b, and the transistor 122 in this order. The voltage at the gate node g after this change is held in the capacitance element 140. In the gate writing period (E), in the pixel circuit 110, the transistor 125 maintains the on state, and therefore the reset voltage Vorst is applied to the pixel electrode 131.

[0127] During the drain writing period (F) of each horizontal scanning period (H), the control signal / Gini is at H level, the control signal Gref is at L level, and the control signal Gcp is at H level. As a result, the transistor 68 remains in the off state, the transmission gate 73 remains in the off state, and the transmission gate 72 remains in the on state. Furthermore, during the drain writing period (F) of the horizontal scanning period (H) in which the i-th row is selected, the scanning signal / Gwr(i) changes to H level, the control signal / Gcmp(i) changes to L level, and the control signal / Gel(i) maintains H level. As a result, in the pixel circuit 110, the transistor 122 changes to the OFF state, the transistor 123 changes to the ON state, and the transistor 124 maintains the OFF state.

[0128] Therefore, during the drain write period (F) of the horizontal scanning period (H) in which the i-th row is selected, as shown in Figure 24, the voltage at the other end of the capacitance element 74, i.e., the same voltage as the gate node g of the transistor 121 during the previous gate write period (E), is applied to the drain node d of the transistor 121 via the data line 14b and the on-state transistor 123 in that order.

[0129] After the drain writing period (F) ends, the light emission period (G) begins. In the second embodiment, as in the first embodiment, the control signal / Gel(i) becomes L level during the light emission period of the i-th row. Therefore, as shown in FIG. 25 , the transistor 121 passes a current Iel according to the voltage Vgs to the OLED 130. The current Iel is limited by the resistance between the source and drain of the transistor 124. Therefore, the OLED 130 emits light with a luminance according to the current Iel.

[0130] According to the second embodiment, as in the first embodiment, the same voltage as that applied to the gate node g of the transistor 121 is applied to the drain node d of the transistor 121 during the drain writing period (F), thereby suppressing black floating and suppressing the occurrence of display unevenness when the gradation level is medium or higher.

[0131] Furthermore, according to the second embodiment, the initialization periods (B) and (C) in the first embodiment are not provided, and therefore the compensation period (D) can be made longer accordingly. If the compensation period (D) is short, a situation may occur in which the voltage Vgs between the gate node and source node of the transistor 121 has not converged to the threshold voltage at the end of the compensation period (D). In a situation in which the voltage Vgs has not converged to the threshold voltage, the threshold of the transistor 121 cannot be accurately compensated, which causes variations in the brightness of the OLED 130 for each pixel circuit 110 and leads to a deterioration in display quality. According to the second embodiment, a longer compensation period (D) can be ensured, and therefore, compared to the first embodiment, the threshold value of the transistor 121 can be more accurately compensated. Therefore, according to the second embodiment, it is possible to further suppress degradation of display quality compared to the first embodiment.

[0132] In the second embodiment, the periods during which the reset voltage Vorst is applied to the pixel electrode 131, which is one end of the OLED 130, are the initialization period (A2), the compensation period (D), and the gate writing period (E), but are not limited to these periods. The period during which the reset voltage Vorst is applied to the pixel electrode 131 may be any period before the light-emitting period (G), and may be, for example, a part of the initialization period (A2), the compensation period (D), and the gate writing period (E), or may be the drain writing period (F). However, from the viewpoint of quickly resetting the charges held in the pixel electrodes 131 and turning off the OLED 130 in the horizontal scanning period (H) in which the i-th row is selected, for example, it is preferable to include the horizontal scanning period (A2).

[0133] <Modification> The first and second embodiments (hereinafter referred to as "embodiments") exemplified above may be modified in various ways. Specific modifications that may be applied to the embodiments are exemplified below. Two or more embodiments arbitrarily selected from the following examples may be combined to the extent that they are not mutually contradictory.

[0134] <Ternary control signal / Gel(1)~ / Gel(m)> In the embodiments, the control signals / Gel(1) to / Gel(m) are binary signals of L or H level, but as shown in Figure 26, an M level may be provided between the L and H levels, and the M level may be the light emitting period (G).

[0135] Figure 26 shows an example in which, after a horizontal scanning period (H) in which the i-th row is selected, four light-emitting periods (G) in which the control signal / Gel(i) is at M level occur at approximately equal intervals, and the duration of the period in which the control signal / Gel(i) is at M level is also set to approximately the same length. Even when the control signals / Gel(1) to / Gel(m) are ternary signals of L, M, and H levels, the occurrence of black floating can be suppressed in the same manner as in the embodiment. Note that one frame (V) in Figure 26 is written to indicate the length of the period from when the i-th row is horizontally scanned to when the i-th row is horizontally scanned again, and does not indicate the length from the start to the end of the vertical scanning period.

[0136] The reason for applying the M level to the gate node of the transistor 124 is to operate the transistor 124 in the saturation region, thereby maintaining the constant current characteristics of the transistor 121 regardless of the aging of the current-voltage characteristics of the OLED 130.

[0137] In detail, when the current Iel flows, the OLED 130 emits light with a luminance according to the current Iel. In the pixel circuit 110 of the embodiment, the voltage of the gate node g of the transistor 121 is held by the capacitance element 140, thereby ensuring the constant current of the current Iel flowing from the power supply line 116 to the OLED 130.

[0138] However, the OLED 130 has a characteristic that its element characteristics change over time as it emits light, and the potential of the anode (pixel electrode 131) required to pass a constant current gradually increases. When the potential of the anode in the OLED 130 increases, the equilibrium point of the potential in the path from the power supply line 116 to the common electrode 133 changes, and the potential of the source node of the transistor 124, i.e., the drain node of the transistor 121, increases. When the potential of the drain node of the transistor 121 increases, the voltage between the source node and drain node of the transistor 121 also fluctuates, and the current flowing to the drain node of the transistor 121 also fluctuates, resulting in a loss of constant current capability of the OLED 130.

[0139] Therefore, as a measure to prevent the constant current characteristic from being lost due to the aging of the element characteristics of the OLED 130, the M level is applied to the gate node of the transistor 124 to operate the transistor 124 in the saturation region. When the transistor 124 is operated in the saturation region, even if the potential of the anode in the OLED 130 changes, the transistor 124 is directly affected by the change. The transistor 121 is affected by the potential fluctuation at the drain node of the transistor 124, but the fluctuation in the drain current in the saturation region is small. Therefore, the influence of the fluctuation in the drain potential of the transistor 121 connected to the transistor 124, and therefore the fluctuation in the gate potential due to current leakage, is mitigated.

[0140] <Adding capacitance Cgd_1> Furthermore, the voltage change ΔVdr_d at the drain node d of the transistor 121 caused by the control signal / Gcmp changing from L to H level (caused by the transistor 123 changing from an on state to an off state) is expressed by the above-mentioned equation (8). Increasing the capacitance Cgd_1 in the denominator of equation (8) reduces the voltage change ΔVdr_d, making it possible to minimize the impact of push-up. In other words, when the voltage Vdr_d decreases due to a decrease in push-up, this acts to reduce the leakage current of the OLED 130, thereby suppressing black floating.

[0141] In order to increase the capacitance Cgd_1, instead of using only parasitic capacitance, a capacitance element Cadd formed of metal / insulator (dielectric) / metal, etc., can be separately provided between the gate node g and the drain node d of the transistor 121, as shown by the dashed line in Figure 13. That is, a capacitance element Cadd may be configured such that one end is electrically connected to the gate node g of the transistor 121 and the other end is electrically connected to the drain node d of the transistor 121, and an insulator is sandwiched between the electrode at one end and the electrode at the other end.

[0142] The voltage change ΔVdr_g at the gate node g of the transistor 121 is as shown in the above-mentioned formula (9). According to formula (9), when the voltage change ΔVdr_d becomes smaller, the voltage change ΔVdr_g also appears to become smaller. However, since this is caused by an increase in the capacitance Cgd_1, the voltage change ΔVdr_g may actually increase. As described above, an increase in the voltage Vdr_g acts in the direction of reducing the leakage current to the OLED 130, thereby preventing black floating.

[0143] <Narrowing of logic amplitude in control signal / Gcmp(1)~ / Gcmp> Furthermore, as can be seen from equation (8), when ΔVgcmp, which is the voltage difference between the L level and the H level of the control signal / Gcmp(i), is reduced, the voltage change ΔVdr_d of the drain node d of the transistor 121 is reduced. Therefore, by making the logical amplitude (difference between H level and L level) of the control signal / Gcmp(i) supplied to the gate node of transistor 123 smaller than, for example, the amplitude (difference between the highest value and the lowest value) of the control signal / Gel(i) supplied to the gate node of transistor 124, the voltage change ΔVdr_d is reduced, and black floating can be suppressed.

[0144] <Application of reset voltage Vorst> In the first embodiment, when the transistor 123 is turned on during the drain writing period (F), the transistor 67 may be turned on to apply the reset voltage Vorst to the drain node d of the transistor 121 via the data line 14b and the transistor 123 in the on state in that order. In this configuration, if the reset voltage Vorst is set to 0 to 1 volt as described above, the occurrence of black floating cannot be suppressed, so the reset voltage Vorst may be adjustable, for example, to about 5 to 6 volts. With this configuration, the voltage applied to the drain node d in the drain writing period (F) can be finely adjusted while checking the display state, so that the occurrence of black floating can be suppressed more effectively.

[0145] <Other> The channel types of the transistors 66, 67, 68, and 121 to 125 are not limited to those in the embodiments. For example, the transistor 67 in the first embodiment is preferably an N-channel type. This is because the reset voltage Vorst supplied by the power supply line 118 is a low voltage close to the L level. In a configuration in which the transistor 67 is an N-channel type, a positive logic control signal Gorst is supplied to the gate node, and the configuration in which the transistor 67 is an N-channel type allows the data line 14b to reach the reset voltage Vorst in a shorter time than a configuration in which the transistor 67 is a P-channel type. Furthermore, in the second embodiment, the transistors 125 in the pixel circuits 110 may be N-channel type. In a configuration in which the transistors 125 are N-channel type, signals obtained by logically inverting / Gorst(1) to / Gorst(m) may be supplied to the gate nodes of the transistors 125 in the pixel circuits 110 on the 1st to mth rows. The transmission gates 45, 72, and 73 may be replaced with single-channel transistors. The source and drain nodes of each transistor may be interchanged as appropriate depending on the embodiment.

[0146] In the embodiments and the like, the OLED 130 has been described as an example of a light-emitting element, but other light-emitting elements may be used. For example, the light-emitting element may be an inorganic EL element, or an LED, a mini LED, a micro LED, or the like.

[0147] <Electronic equipment> Next, an electronic device to which the electro-optical device 10 according to the embodiment is applied will be described. The electro-optical device 10 is suitable for applications requiring small-sized pixels and high-definition displays. Therefore, a head-mounted display will be used as an example of the electronic device.

[0148] FIG. 27 is a diagram showing the appearance of a head-mounted display, and FIG. 28 is a diagram showing its optical configuration. First, as shown in Fig. 27, the head mounted display 300 has temples 310, a bridge 320, and lenses 301L and 301R in appearance similar to ordinary eyeglasses. Furthermore, as shown in Fig. 28, the head mounted display 300 is provided with an electro-optical device 10L for the left eye and an electro-optical device 10R for the right eye near the bridge 320 and behind the lenses 301L and 301R (below in the figure). The image display surface of the electro-optical device 10L is disposed on the left side in FIG. 28. As a result, the image displayed by the electro-optical device 10L is emitted in the 9 o'clock direction in the figure via the optical lens 302L. The half mirror 303L reflects the image displayed by the electro-optical device 10L in the 6 o'clock direction while transmitting light incident from the 12 o'clock direction. The image display surface of the electro-optical device 10R is disposed on the right side, opposite the electro-optical device 10L. As a result, the image displayed by the electro-optical device 10R is emitted in the 3 o'clock direction in the figure via the optical lens 302R. The half mirror 303R reflects the image displayed by the electro-optical device 10R in the 6 o'clock direction while transmitting light incident from the 12 o'clock direction.

[0149] In this configuration, a person wearing the head-mounted display 300 can observe the images displayed by the electro-optical devices 10L and 10R in a see-through state in which the images are superimposed on the outside world. Furthermore, in this head-mounted display 300, when the electro-optical device 10L displays the image for the left eye and the electro-optical device 10R displays the image for the right eye among the binocular images with parallax, the wearer can perceive the displayed image as if it had depth and a three-dimensional effect.

[0150] In addition to the head-mounted display 300, electronic devices including the electro-optical device 10 can also be applied to electronic viewfinders in video cameras and interchangeable-lens digital cameras, personal digital assistants, display units in wristwatches, and light bulbs in projection projectors.

[0151] <Additional Notes> From the above description, for example, preferred embodiments of the present disclosure can be understood as follows: Note that, in order to facilitate understanding of each embodiment, reference numerals in the drawings are written in parentheses for convenience, but this is not intended to limit the present invention to the embodiments shown in the drawings.

[0152] <Appendix 1> An electro-optical device (10) according to one embodiment (embodiment 1) includes a pixel circuit (110) provided in correspondence with a scanning line (12) and a data line (14b), the pixel circuit (110) includes a first transistor (121) and a light-emitting element (130), the first transistor (121) is capable of supplying a current (Iel) to the light-emitting element (130) according to a voltage (Vgs) between a gate node of the first transistor (121) and a source node of the first transistor (121), the horizontal scanning period includes a compensation period (D), a gate writing period (E), and a drain writing period (F) in that order, and in the compensation period (D), The gate node of the first transistor (121) and the drain node of the first transistor (121) are electrically connected, and the voltage of the gate node of the first transistor (121) is set to a voltage (Vel-Vth) corresponding to the threshold voltage of the first transistor (121). During a gate write period (E), the voltage of the gate node of the first transistor (121) is changed from the voltage (Vel-Vth) corresponding to the threshold voltage to a voltage corresponding to the luminance of the light-emitting element (130). During a drain write period (F), a voltage corresponding to the luminance of the light-emitting element (130) is applied to the drain node of the first transistor (121).

[0153] According to aspect 1, during the compensation period (D), due to the electrical connection between the gate node and drain node of the first transistor (121), a voltage (Vel-Vth) corresponding to the threshold voltage of the first transistor (121) is maintained at the gate node as well as the drain node by parasitic capacitance or the like. During the gate write period (E), due to the electrical connection between the gate node and drain node of the first transistor (121) during the compensation period (D), not only the gate node but also the drain node changes from the voltage (Vel-Vth) corresponding to the threshold voltage to a voltage corresponding to the luminance of the light-emitting element (130). During the drain write period (E), a voltage corresponding to the luminance of the light-emitting element (130) is applied to the drain node of the first transistor (121), so the voltage change at the drain node is kept small. As a result, the influence of the voltage change at the drain node on adjacent pixel circuits is kept small, and the voltage change on the gate node of the first transistor in its own pixel circuit is also kept small. This reduces the influence on adjacent pixels and also prevents the black level in the pixel itself from floating. The transistor 121 is an example of a first transistor, and the OLED 130 is an example of a light-emitting element.

[0154] <Appendix 2> In an electro-optical device (10) according to a specific embodiment (embodiment 2) of embodiment 1, the pixel circuit (110) has a second transistor (122), a third transistor (123), and a fourth transistor (124), the second transistor (122) is provided between the data line (14b) and the gate node of the first transistor (121) and is turned on or off depending on the voltage of the scanning line (12), and the third transistor (123) is provided between the data line (14b) and the drain node of the first transistor (121). The fourth transistor (124) is provided between the drain node of the first transistor (121) and the light-emitting element (130), and during the compensation period (D), the second transistor (122) and the third transistor (123) are turned on, during the gate write period (E), the second transistor (122) is turned on and the third transistor (123) is turned off, and during the drain write period (F), the second transistor (122) is turned off and the third transistor (123) is turned on.

[0155] In aspect 2, during the compensation period (D), the on state of the third transistor (123) causes the first transistor (121) to be diode-connected, during the gate write period (E), the on state of the second transistor (122) causes a voltage corresponding to the luminance of the light-emitting element (130) to be applied to the gate node of the first transistor (121), and during the drain write period (E), a voltage corresponding to the luminance of the light-emitting element (130) is applied to the drain node of the first transistor (121). Therefore, according to aspect 2, the number of transistors in the pixel circuit (110) can be reduced to four, thereby avoiding a complex configuration. The transistor 122 is an example of a second transistor, the transistor 123 is an example of a third transistor, and the transistor 124 is an example of a fourth transistor.

[0156] <Appendix 3> In an electro-optical device (10) according to a specific embodiment (embodiment 3) of embodiment 1, the pixel circuit (110) has a second transistor (121), a third transistor (123), a fourth transistor (124), and a fifth transistor (125), the second transistor (122) is provided between a data line (14b) and a gate node of the first transistor (121) and is turned on or off depending on the voltage of the scanning line (12), the third transistor (123) is provided between the data line (14b) and a drain node of the first transistor (121), and the fourth transistor (124) is provided between the data line (14b) and a drain node of the first transistor (121). The fifth transistor (125) is disposed between one end of the light-emitting element (130) and a power supply line (118) that supplies a reset voltage (Vorst). During the compensation period (D), the second transistor (122) and the third transistor (123) are turned on. During the gate write period (E), the second transistor (122) is turned on and the third transistor (123) is turned off. During the drain write period (F), the second transistor (122) is turned off and the third transistor (123) is turned on.

[0157] According to the third aspect, it is possible to ensure a long compensation period (D) during which the third transistor (123) is in an on state. The transistor 125 is an example of a fifth transistor.

[0158] <Appendix 4> In an electro-optical device (10) according to a specific embodiment (embodiment 4) of embodiment 2 or 3, the pixel circuit (110) includes a capacitive element (Cadd) sandwiching an insulator between a first electrode and a second electrode, the first electrode being electrically connected to the gate node of the first transistor (121), and the second electrode being electrically connected to the drain node of the first transistor (121). According to the fourth aspect, when the third transistor changes from an on state to an off state, the voltage change at the drain node of the first transistor (121) can be kept small.

[0159] <Appendix 5> In an electro-optical device (10) according to a specific aspect (aspect 5) of any of aspects 2 to 4, in the pixel circuit 110, the logic amplitude of the control signal / Gcmp(i) supplied to the gate node of the third transistor (123) is smaller than the amplitude of the control signal / Gel(i) supplied to the gate node of the fourth transistor (124). According to the fifth aspect, similarly to the fourth aspect, it is possible to keep the voltage change at the drain node of the first transistor (121) small when the third transistor changes from an on state to an off state.

[0160] <Appendix 6> The electronic device (300) according to the sixth aspect includes the electro-optical device (10) according to any one of the first to fifth aspects. According to the sixth aspect, black floating is suppressed, and deterioration of display quality can be suppressed.

[0161] <Appendix 7> The electro-optical device (10) according to aspect 1 can be expressed as a method for driving the electro-optical device (10), as in aspect 7. That is, the method for driving the electro-optical device (10) according to aspect 7 is a method for driving an electro-optical device (10) including a pixel circuit (110) provided corresponding to a scanning line (12) and a data line (14b), the pixel circuit (110) having a transistor (121) and a light-emitting element (130), the transistor (121) being capable of supplying a current (Iel) to the light-emitting element (130) according to a voltage (Vgs) between a gate node of the transistor (121) and a source node of the transistor (121), the horizontal scanning period (H) including a compensation period (D), a gate writing period (E), and a drain writing period (F) in this order, During a gate write period (D), the gate node of the transistor (121) and the drain node of the transistor (121) are electrically connected, and the voltage of the gate node of the transistor (121) is set to a voltage (Vel-Vth) corresponding to the threshold voltage of the transistor (121). During a gate write period (E), the voltage of the gate node of the first transistor (121) is changed from the voltage (Vel-Vth) corresponding to the threshold voltage to a voltage corresponding to the luminance of the light-emitting element (130). During a drain write period (F), a voltage corresponding to the luminance of the light-emitting element (130) is applied to the drain node of the first transistor (121). [Explanation of symbols]

[0162] 10...electro-optical device, 12...scanning line, 14a...data relay line, 14b...data line, 100...display area, 110...pixel circuit, 118...power supply line, 121...transistor (first transistor), 122...transistor (second transistor), 123...transistor (third transistor), 124...transistor (fourth transistor), 125...transistor (fifth transistor), 130...OLED (light-emitting element), 131...pixel electrode.

Claims

1. pixel circuits provided corresponding to the scanning lines and the data lines; the pixel circuit includes a first transistor and a light emitting element; The first transistor is a current corresponding to a voltage between a gate node of the first transistor and a source node of the first transistor can be supplied to the light emitting element; the horizontal scanning period includes a compensation period, a first period, and a second period in this order; During the compensation period, electrically connecting a gate node of the first transistor and a drain node of the first transistor, and setting a voltage of the gate node of the first transistor to a voltage corresponding to a threshold voltage of the first transistor; In the first period, changing a voltage of a gate node of the first transistor from a voltage corresponding to the threshold voltage to a voltage according to the luminance of the light-emitting element; In the second period, applying a voltage corresponding to the luminance of the light-emitting element to a drain node of the first transistor; In a light emitting period after the second period, The first transistor supplies a current to the light emitting element according to a voltage between a gate node of the first transistor and a source node of the first transistor. Electro-optical device characterized by:

2. The pixel circuit a second transistor, a third transistor, and a fourth transistor; The second transistor is a gate electrode of the first transistor, the gate electrode being connected between the data line and the gate node of the first transistor, and being turned on or off depending on the voltage of the scan line; the third transistor is provided between the data line and a drain node of the first transistor; the fourth transistor is provided between a drain node of the first transistor and the light emitting element, During the compensation period, turning on the second transistor and the third transistor; In the first period, The second transistor is turned on and the third transistor is turned off; In the second period, The second transistor is turned off and the third transistor is turned on.

2. The electro-optical device according to claim 1.

3. The pixel circuit a second transistor, a third transistor, a fourth transistor, and a fifth transistor; The second transistor is a gate electrode of the first transistor, the gate electrode being connected between the data line and the gate node of the first transistor, and being turned on or off depending on the voltage of the scan line; the third transistor is provided between the data line and a drain node of the first transistor; the fourth transistor is provided between a drain node of the first transistor and the light emitting element, the fifth transistor is provided between one end of the light-emitting element and a power supply line that supplies a reset voltage, During the compensation period, turning on the second transistor and the third transistor; In the first period, The second transistor is turned on and the third transistor is turned off; In the second period, The second transistor is turned off and the third transistor is turned on.

2. The electro-optical device according to claim 1.

4. The pixel circuit a capacitance element having an insulator sandwiched between a first electrode and a second electrode; the first electrode is electrically connected to a gate node of a first transistor, and the second electrode is electrically connected to a drain node of the first transistor; 4. The electro-optical device according to claim 2 or 3.

5. The logic amplitude of the control signal supplied to the gate node of the third transistor is an amplitude smaller than that of the control signal supplied to the gate node of the fourth transistor; 5. The electro-optical device according to claim 2, wherein the first and second electrodes are electrically connected to each other.

6. 6. An electronic device comprising the electro-optical device according to claim 1.

7. pixel circuits provided corresponding to the scanning lines and the data lines; the pixel circuit includes a transistor and a light-emitting element; The transistor is a current corresponding to a voltage between a gate node of the transistor and a source node of the transistor can be supplied to the light emitting element; the horizontal scanning period includes a compensation period, a first period, and a second period in this order; During the compensation period, electrically connecting the gate node of the transistor and the drain node of the transistor, and setting the voltage of the gate node of the transistor to a voltage corresponding to the threshold voltage of the transistor; In the first period, changing a voltage of a gate node of the transistor from a voltage corresponding to the threshold voltage to a voltage according to the luminance of the light-emitting element; In the second period, applying a voltage corresponding to the luminance of the light-emitting element to a drain node of the transistor; In a light emitting period after the second period, The transistor supplies a current corresponding to a voltage between a gate node of the transistor and a source node of the transistor to the light emitting element. A driving method for an electro-optical device.

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