Stackable Multiphase Power Stage Controller with Current Matching

Abstract

The power stage controller (106A) includes a multi-phase pulse control circuit (124), a current sense circuit (204), a comparator (116), an error amplifier (108), and a mode controller (135). The mode controller includes a mode controller input (136) and a summing circuit (210). The summing circuit has a first summing circuit input (214), a second summing circuit input (212), and a summing circuit output (216), with the first summing circuit input (214) coupled to the error amplifier output (114) and the summing circuit output coupled to the first comparator input (118). The mode controller is configured to select one of the primary controller mode or the secondary controller mode in response to a mode control voltage at the mode controller input (136), bypass the summing circuit (210) in response to the selection of the primary controller mode, and enable the summing circuit in response to the selection of the secondary controller mode.

Description

[Technical Field]

[0001] The proliferation of electronic devices and integrated circuit (IC) technology has resulted in the commercialization of IC products. As new electronic devices are developed and IC technology advances, new IC products are commercialized. One example of an IC product for an electronic device is a power stage controller. An exemplary power stage controller provides multi-phase control signals. As the demand for higher currents increases in electronic devices (e.g., communication devices and servers), the number of phases required to support the higher currents increases. Also, as the number of supported phases increases, the pin count of the power stage controller increases, resulting in a larger package size. Efforts are underway to support higher currents and associated phases. Summary of the Invention

[0002] In at least one example, the power stage controller includes a multi-phase pulse control circuit having a control input and a multi-phase pulse output, each of the multi-phase pulse outputs adapted to be coupled to a respective switch control input of a respective power stage. The power stage controller also includes a current sense circuit having a current sense input and a current sense output, each of the current sense inputs adapted to be coupled to a respective current sense terminal of a respective power stage, the current sense circuit configured to provide a combined current sense voltage at the current sense output in response to a current sense voltage at the current sense input. The power stage controller also includes a comparator having a first comparator input, a second comparator input, and a comparator output, the first comparator input configured to receive the feedback voltage, the second comparator input coupled to the first current sense output, and the comparator output coupled to the control input. The power stage controller also includes an error amplifier having a first error amplifier input, a second error amplifier input, and an error amplifier output, the error amplifier configured to provide an error voltage at the error amplifier output in response to a first voltage at the first error amplifier input and a second voltage at the second error amplifier input. The power stage controller also includes a mode controller having a mode controller input and a summing circuit, the summing circuit having a first summing circuit input, a second summing circuit input, and a summing circuit output, the first summing circuit input coupled to the error amplifier output and the summing circuit output coupled to the first comparator input. The mode controller is configured to select one of the primary controller mode or the secondary controller mode in response to a mode control voltage at the mode controller input, to bypass the summing circuit in response to selection of the primary controller mode, and to enable the summing circuit in response to selection of the secondary controller mode.

[0003] In another example, a controller for a multiphase converter includes a main controller circuit having a first main controller input, a second main controller input, a current sense output terminal, and an error amplifier output terminal, where the first main controller input is adapted to be coupled to an output voltage terminal of the multiphase converter and the second main controller input is adapted to be coupled to a reference voltage terminal. The controller also includes a secondary controller circuit having a first secondary controller input and a second secondary controller input, where the first secondary controller input is coupled to the current sense output terminal and the second secondary controller input is coupled to the error amplifier output terminal. The secondary controller circuit includes a summing circuit having a first summing circuit input, a second summing circuit input, and a summing circuit output, where the first summing circuit input is coupled to the second secondary controller input. The secondary controller circuit also includes an integrator having a first integrator input, a second integrator input, and an integrator output, the first integrator input coupled to the first secondary controller input, the second integrator input configured to receive a combined current sense voltage associated with a power stage of a multi-phase converter controlled by the secondary controller circuit, and the integrator output coupled to the second summing circuit input.

[0004] In another example, a system includes a multi-phase converter adapted to be coupled to a load. The multi-phase converter has an output voltage terminal, parallel power stages each having a current sense output terminal, and a controller coupled to each of the power stages. The controller includes a primary controller circuit and a secondary controller circuit, the primary controller circuit coupled to some of the power stages, the primary controller circuit having a first primary controller input, a second primary controller input, a current sense output terminal, and an error amplifier output terminal, the first primary controller input adapted to be coupled to the output voltage terminal and the second primary controller input adapted to be coupled to a reference voltage terminal. The secondary controller circuit is coupled to the primary controller circuit and the other power stages, the secondary controller circuit having a first secondary controller input and a second secondary controller input, the first secondary controller input coupled to the current sense output terminal and the second secondary controller input adapted to be coupled to the error amplifier output terminal. [Brief explanation of the drawings]

[0005] [Figure 1] FIG. 1 is a block diagram of a system according to an example embodiment.

[0006] [Figure 2] FIG. 1 is a diagram of a power stage controller for a multi-phase converter, in accordance with an example embodiment.

[0007] [Figure 3] FIG. 2 is a diagram of current sharing loop circuitry of a power stage controller for a multi-phase converter, in accordance with an example embodiment.

[0008] [Figure 4] FIG. 1 is a diagram of a power stage controller for a multi-phase converter, in accordance with an example embodiment.

[0009] [Figure 5] FIG. 1 is a timing diagram showing waveforms of a multiphase converter without the described power stage controller.

[0010] [Figure 6] FIG. 1 is a timing diagram illustrating waveforms of a multiphase converter with an described power stage controller. DETAILED DESCRIPTION OF THE INVENTION

[0011] A controller for a multi-phase converter described herein includes a primary controller circuit configured to provide multi-phase pulses to a subset of the power stages of the multi-phase converter. The multi-phase converter also includes one or more secondary controller circuits coupled to the primary controller circuit, each configured to provide multi-phase pulses to a respective other subset of the power stages of the multi-phase converter. In described embodiments, the primary controller circuit and each secondary controller circuit include components for equalizing the respective current sense voltages provided to the input terminals, output terminals, and / or control loop comparators of the primary controller circuit and each secondary controller circuit. In this manner, even if the respective current sense voltages of the primary controller circuit and each secondary controller circuit are different, the respective control loop comparators will receive the same voltage difference. In some exemplary embodiments, each secondary controller circuit includes an integrator configured to compare the average or total current of the primary controller circuit and each secondary controller circuit, resulting in an adjusted off-time (TOFF) for each respective secondary controller circuit and equalized currents for the respective control loops of the primary controller circuit and each secondary controller circuit.

[0012] Without limitation to other embodiments, in some exemplary embodiments, the primary controller circuit and the secondary controller circuit have the same controller topology, and the controller circuit topology is configurable in primary controller mode or secondary controller mode. Thus, a controller for a multiphase converter includes stackable controller integrated circuits (ICs), with one of the controller ICs configured as the primary controller circuit and the other controller IC configured as the secondary controller circuit. As used herein, "stackable" refers to the ability of a multiphase converter to use an increased number of controller ICs as needed to support increased amounts of current output to the power stage and load. In different exemplary embodiments, a multiphase converter controller includes one primary controller IC and N secondary controller ICs, where N is an integer equal to 1 or more (e.g., N=1 to 10 or more).

[0013] While the controller topology for the stackable controller IC may vary, a stackable controller IC for power stages of a multi-phase converter may include a multi-phase pulse control circuit having a control input and a multi-phase output. In this example, each of the multi-phase pulse outputs may be adapted to be coupled to a respective switch control input of a respective power stage. The stackable controller IC also includes a current sense circuit having a current sense input and a power sense output. Each of the current sense inputs is adapted to be coupled to a respective current sense terminal of a respective power stage. The current sense circuit is also configured to provide a combined current sense voltage at the current sense output in response to a current sense voltage at the current sense input. The stackable controller IC also includes a comparator having a first comparator input, a second comparator input, and a comparator output. The first comparator input is configured to receive a feedback voltage, the second comparator voltage is coupled to the first current sense output, and the comparator output is coupled to the control input. The stackable controller IC also includes an error amplifier having a first error amplifier input, a second error amplifier input, and an error amplifier output. The error amplifier is configured to provide an error voltage at the error amplifier output in response to a first voltage at the first error amplifier input and a second voltage at the second error amplifier input. In some exemplary embodiments, the stackable controller IC also includes a mode controller having a mode controller input and a summing circuit. The summing circuit has a first summing circuit input, a second summing circuit input, and a summing circuit output, the first summing circuit input being coupled to the error amplifier output. The summing circuit output is coupled to the first comparator input. In operation, the mode controller is configured to select one of the primary controller mode or the secondary controller mode in response to a mode control voltage at the mode controller input, to bypass the summing circuit in response to selection of the primary controller mode, and to enable the summing circuit in response to selection of the secondary controller mode.

[0014] In some illustrative embodiments, the control loop of each secondary controller circuit in a controller for a multiphase converter includes an integrator to equalize the current sense voltages provided to the control loop comparators of the primary and secondary controller circuits, respectively. This illustrative embodiment achieves an overall improvement in the reliability of the multiphase converter (since all phases have the same current) without a significant increase in controller size or bill of materials (BOM). Also, the frequency of operation for the primary and each secondary controller circuit does not change. Also, additional compensation circuitry or external devices are avoided. Other controller topologies are possible with varying complexity, cost, and benefits.

[0015] FIG. 1 is a block diagram of a system 100 according to an example embodiment. In the example of FIG. 1, system 100 is a communications or server device (e.g., one or more processors and / or other components) that includes a load 194 powered by a multi-phase converter 102. As shown, multi-phase converter 102 includes a controller 104 coupled in parallel to power stages 190A-190N, and a power source 196 provides an input voltage (VIN) at a VIN terminal 197 that is coupled to power stages 190A-190N and controller 104 (e.g., VIN is received at a VIN input terminal 198 of controller 104 or a respective controller circuit). At the output of each of power stages 190A-190N is a respective inductor (L_A-L_N), each of L_A-L_N having a respective first side coupled to the respective power stage and a respective second side coupled to output terminal 192. As shown, the system 100 includes an output capacitor (COUT) in parallel with a load 194 between an output terminal 192 and ground 195. Ground 195 is also coupled to components of the multi-phase converter 102.

[0016] 1, controller 106 includes primary controller circuit 106 and secondary controller circuits 150 and 151A-151M, where primary controller circuit 106 provides pulses (a subset of pulses CP_A-CP_N) to a respective subset of power stages 190A-190N, and secondary controller circuits 150 and 151A-151M each provide a respective pulse (a respective subset of pulses CP_A-CP_N) to another respective subset of power stages 190A-190N. Pulses CP_A-CP_N provided to power stages 190A-190N control respective switches in power stages 190A-190N.

[0017] As shown, the main controller circuit 106 includes a multiphase pulse control (labeled "TON / TOFF control") having a control input 134 and multiphase pulse outputs 132A-132M. In operation, the multiphase pulse control circuit 124 controls the on-time (TON) and off-time (TOFF) of pulses 133A-133M provided to a respective subset of power stages 190A-190N. In some exemplary embodiments, each of the multiphase pulse outputs 132A-132M is adapted to be coupled to a respective subset of switch control inputs 191A-191N of a respective subset of power stages 190A-190N. In some exemplary embodiments, the control input 134 is a first control input, and the multiphase pulse control circuit 124 also includes a second control input 126, a third control input 128, and a fourth control input 130. In these illustrative embodiments, second control input 126 is configured to receive VOUT from output node 192, third control input 128 is configured to receive VIN from VIN terminal 197, and fourth control input 130 is configured to receive a ramp voltage (RAMP) from a RAMP source (not shown).

[0018] 2, a main controller circuit, such as main control circuit 106, also includes a current sense circuit (e.g., current sense circuit 204 in FIG. 2) having current sense inputs 206A-206N and a current sense output 208, each of current sense inputs 206A-206N adapted to be coupled to a respective subset of current sense terminals 193A-193N of a respective subset of power stages 190A-190N, and the current sense circuit configured to provide an average or total current sense voltage (VISUM_M in FIG. 2) at current sense output 208 in response to a current sense voltage (a subset of CS_A-CS_N in FIG. 1 or CSP1_M-CSPn_M in FIG. 2) at current sense inputs 206A-206N.

[0019] 1 and 2, the main controller circuit 106 also includes a pulse width modulation (PWM) comparator 116 having a first comparator input 118, a second comparator input 120, and a comparator output 122, where the first comparator input 118 is configured to receive a feedback voltage (e.g., VDROOP in FIG. 2), the second comparator input is coupled to the current sense output 208, and the comparator output 122 is coupled to the control input 134, and the PWM comparator 116 is configured to provide a voltage 123 at the comparator output 122 in response to the feedback voltage or error voltage 115 at the first comparator input 118 and the current sense voltage 121 at the second comparator input 120. The main controller circuit 106 also includes an error amplifier or integrator 108 having a first error amplifier or integrator input 110, a second error amplifier or integrator input 112, and an error amplifier or integrator output. The error amplifier or integrator 108 is configured to provide an error voltage 115 at an error amplifier or integrator output 114 in response to a first voltage 111 at the first error amplifier or integrator input 110 and a second voltage 113 at the second error amplifier or integrator input 113. In some examples, the first voltage 111 is an output voltage (VOUT) at an output node 192, and the second voltage 113 is a reference voltage provided by a reference voltage terminal 107 and an associated reference voltage source.

[0020] The primary controller circuit 106 also includes a mode controller (labeled "M / S") 135 having a mode controller input 136 and a summing circuit 210 (see, e.g., FIG. 2). The summing circuit 210 has a first summing circuit input 212, a second summing circuit input 214, and a summing circuit output 216. The first summing circuit input 212 is coupled to the error amplifier or integrator output 114, and the summing circuit output 216 is coupled to the first comparator input 118. In operation, the mode controller 135 is configured to select one of the primary controller mode or the secondary controller mode in response to a mode control voltage 137 at the mode controller input 136 (e.g., provided by a mode control pin or terminal 138). The mode control voltage 137 is selectable, for example, by a system designer. The mode controller 135 is also configured to bypass the summing circuit 210 in response to selection of the primary controller mode (resulting in the first comparator input 118 receiving the error voltage 115 from the error amplifier or integrator output 114) and to enable the summing circuit 210 in response to selection of the secondary controller mode (resulting in the first comparator input 118 receiving the voltage from the summing circuit output 216).

[0021] 1, when the primary controller mode is selected, mode controller 135 also outputs error voltage 115 from mode controller output 140 to error amplifier output terminal 142. In other exemplary embodiments, error voltage 115 is provided to error amplifier output terminal 142 regardless of the mode selected (e.g., error amplifier output 114 is coupled to error amplifier output terminal 142 directly or via mode controller 135). In some exemplary embodiments, primary controller circuit 106 is also configured to output an average or total current sense voltage (e.g., VISUM_M from current sense circuit 204 in FIG. 2) from a current sense output terminal (e.g., current sense output terminal 209 in FIG. 2) to each secondary controller circuit 150 and 151A-151M.

[0022] In some example embodiments, secondary controller circuit 150 is configured to receive error voltage 115 and an average or total power sense voltage (e.g., VISUM_M in FIG. 2 ) from primary controller circuit 106. In the example of FIG. 1 , secondary controller circuit 150 includes multiphase pulse control (labeled “TON / TOFF CONTROL”) circuit 170 having control input 168 and multiphase pulse outputs 178A-178M. In operation, multiphase pulse control circuit 170 controls the TON and TOFF of pulses 179A-179M provided to respective subsets of power stages 190A-190N. In some example embodiments, each of multiphase pulse outputs 179A-179M is adapted to be coupled to a respective subset of switch control inputs 191A-191N of a respective subset of power stages 190A-190N. In some exemplary embodiments, control input 168 is a first control input, and multiphase pulse control circuit 170 also includes a second control input 172, a third control input 174, and a fourth control input 176. In these exemplary embodiments, second control input 172 is configured to receive VOUT from output node 192, and third control input 174 is configured to receive VIN from VIN terminal 197. And fourth control input 176 is configured to receive RAMP from a RAMP source (not shown).

[0023] 2, a secondary controller circuit, such as secondary controller circuit 150, also includes a current sense circuit (see, e.g., current sense circuit 224 in FIG. 2) having current sense inputs 226A-226N and a current sense output 228. Each of current sense inputs 226A-226N is adapted to be coupled to a respective subset of current sense terminals 193A-193N of a respective subset of power stages 190A-190N. Current sense circuit 224 is also configured to provide a total or average current sense voltage (VISUM_S in FIG. 2) at current sense output 228 in response to a current sense voltage (a subset of CS_A-CS_N in FIG. 1 or CSP1_S-CSPn_S in FIG. 2) at current sense inputs 226A-226N.

[0024] 1 and 2, secondary controller circuit 150 also includes a PWM comparator 160 having a first comparator input 162, a second comparator input 164, and a comparator output 166. First comparator input 162 is configured to receive a feedback voltage, second comparator input 164 is coupled to current sense output 228, and comparator output 166 is coupled to control input 168. Secondary controller circuit 150 also includes an error amplifier or integrator 152 having a first error amplifier or integrator input 154, a second error amplifier or integrator input 156, and an error amplifier or integrator output 158. Error amplifier or integrator 152 is configured to provide an error voltage 159 at error amplifier output 158 ​​in response to a first voltage 155 at first error amplifier or integrator input 154 and a second voltage 157 at second error amplifier or integrator input 156. In some examples, the first voltage 155 is an average or total current sense voltage (e.g., VISUM_M in FIG. 2) provided by a current sense circuit (e.g., current sense circuit 204 in FIG. 2) of the primary controller circuit 106 and received by a current sense input terminal (e.g., current sense input terminal 240) of the secondary controller circuit 150. The second voltage 157 is an average or total current sense voltage (e.g., VISUM_S in FIG. 2) provided by a current sense circuit (e.g., current sense circuit 224 in FIG. 2) of the secondary controller circuit 150.

[0025] The secondary controller circuit 150 also includes a mode controller (labeled "M / S") 180 having a mode controller input 182 and a summing circuit 230 (see, e.g., FIG. 2). The summing circuit 230 has a first summing circuit input 232, a second summing circuit input 234, and a summing circuit output 236. The first summing circuit input 232 is coupled to the error amplifier or integrator output 158, and the summing circuit output 236 is coupled to the first comparator input 162. In operation, the mode controller 180 is configured to select one of the primary controller mode or the secondary controller mode in response to a mode control voltage 183 (e.g., provided by a mode control pin or terminal 188) at the mode controller input 182. The mode control voltage 183 is selectable, for example, by a system designer. The mode controller 180 is also configured to bypass the summing circuit 230 in response to the selection of the primary controller mode. The mode controller 180 is also configured to enable the summing circuit 230 in response to the selection of the secondary controller mode.

[0026] In some example embodiments, additional secondary controller circuits 151A-151M are present, each of which involves a topology and operation similar to that described for secondary controller circuit 150. In such examples, each of secondary controller circuits 151A-151M is configured to provide a respective subset of pulses CP_A-CP_N to a respective subset of power stages 190A-190N. When using multi-phase controller 102, the number of controller circuits is adjustable to support as many power stages as desired to supply current to load 194 at the target VOUT.

[0027] Without limitation to other options, primary controller circuit 106 and each of secondary controller circuits 150 and 151A-150M have the same topology, with input terminals (e.g., terminals 218, 138, 240), output terminals (e.g., terminals 209 and 142), and / or components that equalize the respective current sense voltages provided to the respective control loop comparators (e.g., comparators 116 and 160 in FIG. 1 ) of primary controller circuit 106 and each of secondary controller circuits 150 and 151A-151M. In this way, even if the respective current sense voltages of the primary controller circuit and each secondary controller circuit are different, each control loop comparator will receive the same voltage difference. As described herein, each of the secondary controller circuits 150 and 151A-151M includes an error amplifier or integrator (e.g., error amplifier or integrator 152 in FIG. 1) configured to compare the average or total current of the primary controller circuit and the respective secondary controller circuit, resulting in an adjusted TOFF for each secondary controller circuit and equalized currents for the respective control loops of the primary controller circuit 106 and each of the secondary controller circuits 150 and 151A-151M.

[0028] FIG. 2 is a diagram of a controller 200 for a multi-phase converter (e.g., multi-phase converter 102 in FIG. 1 ) according to an example embodiment. As shown, controller 200 includes a primary controller circuit 106A (an example of primary controller circuit 106 in FIG. 1 ), a secondary controller circuit 150A (an example of secondary controller circuit 150 in FIG. 1 ), and secondary controller circuits 151A-151M. In the example of FIG. 2 , primary controller circuit 106A includes many of the same components described for primary controller circuit 106 in FIG. 1 , including error amplifier or integrator 108 and associated inputs / outputs, PWM comparator 116 and associated inputs / outputs, multi-phase pulse control circuit 124 and associated inputs / outputs, and mode controller 135 and associated inputs / outputs. Primary controller circuit 106A also includes a current sense circuit 204 with current sense inputs 206A-206N and a current sense output 208.

[0029] In the example of FIG. 2 , several additional inputs, outputs, and / or components are depicted for the main controller circuit 106A, including a current sense output terminal 209 coupled to a current sense output 208. The main controller circuit 106A includes a ramp terminal 203 coupled to a fourth control input 130 of the multi-phase pulse control circuit 124 and configured to provide a ramp voltage. The main controller circuit 106A includes an error voltage input terminal 218 configured to receive an error voltage from another controller circuit (e.g., when the main controller circuit 106A is in a secondary controller mode). The main controller circuit 106A includes a summing circuit 210 having a first summing circuit input 212, a second summing circuit input 214, and a summing circuit output 216, the summing circuit 210 being part of the mode controller 135. For the mode controller 135 of FIG. 2 , the mode controller input 136 is a first mode controller input, and the mode controller 135 also includes a second mode controller input 217 and a third mode controller input 219. As shown, second mode controller input 217 is coupled to error amplifier or integrator output 114, and third mode controller input 219 is coupled to error voltage input terminal 218. In another example, mode controller 135 and summing circuit 210 are separate, and logic bypasses or enables summing circuit 210 based on the selected mode identified by mode controller 135. Primary controller circuit 106A includes a reference voltage terminal 215 configured to provide a reference voltage (VDAC) to first error amplifier or integrator input 110. In operation, primary controller circuit 106A performs the operations described for primary controller circuit 106 in FIG. 1 .

[0030] 2, secondary controller circuit 150A includes a current sense output terminal 229 coupled to current sense output 228. Secondary controller circuit 150A also includes a ramp terminal 223 coupled to fourth control input 176 of multiphase pulse control circuit 170 and configured to provide a ramp voltage (RAMP). Secondary controller circuit 150A includes an error voltage input terminal 238 configured to receive an error voltage from a primary controller circuit (e.g., primary controller circuit 106A in FIG. 2). Secondary controller circuit 150A includes a summing circuit 230 having a first summing circuit input 232, a second summing circuit input 234, and a summing circuit output 236, and summing circuit 230 is part of mode controller 180. Also, for mode controller 180 in FIG. 2, mode controller input 182 includes a first mode controller input, and mode controller 180 also includes a second mode controller input 237 and a third mode controller input 239. As shown, second mode controller input 237 is coupled to error amplifier or integrator output 158, and third mode controller input 239 is coupled to error voltage input terminal 238. In another example, mode controller 180 and summing circuit 230 are separate, and logic bypasses or enables summing circuit 230 based on the selected mode identified by mode controller 180. Secondary controller circuit 150A includes a current sense input terminal 240 configured to receive an average or total sensed current voltage (e.g., VISUM_M in FIG. 2 ) from current sense output terminal 209 of primary controller circuit 106A. In operation, secondary controller circuit 150A performs the operations described for secondary controller circuit 150 in FIG. 1 . Secondary controller circuits 151A-151M in FIG. 2 are similar to secondary controller circuit 150A and are similarly configured to perform the operations described for secondary controller circuit 150 in FIG. 1 .

[0031] 2 have the same topology, and the input terminals (e.g., terminals 218, 138, 215, 240), output terminals (e.g., terminals 209, 142, and 229), and / or components equalize the respective current sense voltages provided to the respective control loop comparators (e.g., comparators 116 and 160 in FIG. 1) of the primary controller circuit 106A and each of the secondary controller circuits 150A and 151A-151M. In this way, even if the respective current sense voltages of the primary controller circuit and each secondary controller circuit are different, each control loop comparator will receive the same voltage difference. As described herein, each of the secondary controller circuits 150A and 151A-151M includes an error amplifier or integrator (e.g., error amplifier or integrator 152 in FIG. 1) configured to compare the average or total current of the primary controller circuit and the respective secondary controller circuit, resulting in an adjusted TOFF for each secondary controller circuit and equalized currents for the respective control loops of the primary controller circuit 106A and each of the secondary controller circuits 150A and 151A-151M.

[0032] 3 is a diagram of current-sharing loop circuitry 300 operating in parallel with a primary controller circuit (e.g., primary controller circuit 106 in FIG. 1 or primary controller circuit 106A in FIG. 2) and each secondary controller circuit (e.g., each of secondary controller circuits 150 and 151A-151M in FIG. 1 or each of secondary controller circuits 150A and 151A-151M in FIG. 2) of a power stage controller (e.g., controller 104 in FIG. 1 or controller 200 in FIG. 2) for a multiphase converter (e.g., multiphase converter 102 in FIG. 1) according to an example embodiment. In operation, current-sharing loop circuitry 300 equalizes current across all phases, and current-sharing loop circuitry 300 has a significantly lower bandwidth than a current-mode control loop (e.g., each of primary controller circuit 106 and each of secondary controller circuits 150 and 151A-151M include a current-mode control loop). More specifically, the current sharing loop circuitry 300 compares the individual current sense voltages to the average current of all phases and adjusts TON.

[0033] As shown, current sharing loop circuitry 300 includes current sense inputs 304A-304F configured to receive current sense voltages (e.g., CSP-1 through CSP6 in FIG. 3 ) from respective subsets of power stages (e.g., power stages 190A-190N). Current sense inputs 304A-304F are coupled to respective delay filters 306A-306F (e.g., 5 μs delay filters). The outputs of delay filters 306A-306F are coupled to an averaging circuit 307 as well as respective multipliers 308A-308F. Each of respective multipliers 308A-308F multiplies the output of a respective one of delay filters 306A-306F by the average current (I AVG ) output from the multipliers 308A to 308F. AVG )~K×(I6~I AVG ) and the reference voltage (VDAC) are K × (I1 to I AVG )~K×(I6~I AVG) to a respective adder 310A-310F. The output of each adder 310A-310F is provided to a non-inverting input of a respective comparator 312A-312F. The inverting input of each comparator 312A-312F is coupled to a respective reference circuit, and each reference circuit is connected to a resistor R T(ON) and capacitor C T(ON) As shown in the figure, each R T(ON) The first side of each R is coupled to the V source or associated terminal. T(ON) The second side of each C is coupled to the inverting input of each of the comparators 312A to 312F. T(ON) The first side of each C is coupled to the inverting input of each of the comparators 312A-312F. T(ON) The second side of each of the comparators 312A-312F is coupled to ground. The outputs of the comparators 312A-312F are coupled to PWM output terminals 314A-314F to provide PWM pulses (PWM1-PWMF6). In summary, the primary controller circuit and each secondary controller circuit operate to control the PWM pulse output from the controller (e.g., controller 104 in FIG. 1 ) to a respective subset of power stages, as described herein. In parallel with the TOFF control provided by the primary controller circuit and each secondary controller circuit, each current sharing loop circuit element (e.g., one of the current sharing loop circuit elements 300 in FIG. 3 for the primary controller circuit and each secondary controller circuit) controls the T ON of the PWM pulse output from the controller (e.g., controller 104 in FIG. 1 ) to a respective subset of power stages, as described herein.

[0034] 4 is a diagram of a power stage controller 400 for a multi-phase converter (e.g., multi-phase converter 102 in FIG. 1) in accordance with an example embodiment. Power stage controller 400 is an alternative topology to the topologies shown in FIGS. 1, 2, and 3. As shown, power stage controller 400 includes a main controller circuit 401 comprising a delay filter 402, an integrator 404, a multiplier 406, and a comparator 408. More specifically, delay filter 402 is configured to receive a current sense signal (CSP1_m) and output an associated current sense signal (I1_m), which is an average current sense signal (I AVG_M The output of the integrator 404 is multiplied by I1_m-I AVG_M and is provided to a multiplier 406 that is configured to scale the output of the integrator 404 by a reference voltage (VDAC). The output of the multiplier 406 is coupled to the non-inverting input of a comparator 408, whose inverting input is coupled to a resistor (R T(ON) ) and capacitor (C T(ON) ) is coupled to a reference circuit having R T(ON) The first side of the VIN is connected to the source or associated terminal, and the R T(ON) The second side of C is coupled to the inverting input of the comparator 408. T(ON) The first side of C is coupled to the inverting input of comparator 408, T(ON) The second side of the comparator 408 is coupled to ground. The output of the comparator 408 is a PWM pulse (PWM_m). In Figure 4, the circuit elements of the main controller circuit 401 (e.g., delay filter 402, integrator 404, multiplier 406, and comparator 408) are repeated for each phase managed by the main controller circuit 401.

[0035] Secondary controller circuit 411 also includes a delay filter 412, an integrator 414, a multiplier 416, and a comparator 418. More specifically, delay filter 412 is configured to receive a current sense signal (CSP1_s) and output an associated current sense signal (I1_s), which is an average current sense signal (I AVG_M ) The output of the integrator 414 is multiplied by I1_s-I AVG_M and is provided to a multiplier 416 which scales the output of the integrator 414 by a reference voltage (VDAC). The output of the multiplier 416 is coupled to the non-inverting input of a comparator 418, whose inverting input is R T(ON) and C T(ON) As shown in the figure, R T(ON) The first side of the VIN is connected to the source or associated terminal, and the R T(ON) The second side of C is coupled to the inverting input of comparator 418. T(ON) The first side of C is coupled to the inverting input of comparator 418, T(ON) The second side of the comparator 418 is coupled to ground. The output of the comparator 418 is a PWM pulse (PWM_s). In Figure 4, the circuit elements of the secondary controller circuit 411 (e.g., delay filter 412, integrator 414, multiplier 416, and comparator 418) are repeated for each phase managed by each secondary controller circuit 411.

[0036] When using the topology of the power stage controller 400, the secondary controller circuit 411 can be replicated to support additional phases. Also, the current sharing loop, including the integrator and / or high gain in the path and the average current of the primary controller circuit, can be shared among all controller circuits or ICs. When using this topology, the loop has two poles due to the inductor (e.g., one of L_A through L_N) and the integrator. Therefore, additional loop compensation is required. Also, the described power stage controller 400 changes the TON of the IC, which changes the frequency of operation between the primary and secondary controller circuits. To solve this problem, a separate frequency control loop is required.

[0037] Another option involves using averaging circuitry that uses all phase currents of the primary and secondary controller circuits as inputs. The averaged output can then be provided to the current sharing loops of both the primary and each secondary controller circuit. Using this other option increases the bill of materials (BOM) / cost. Also, the TON may be altered, the gain may be limited, and the error may not be removed as much as desired.

[0038] 5 is a timing diagram 500 illustrating waveforms for a multi-phase converter without the described power stage controller. In timing diagram 500, waveforms are shown for VOUT, load current (I_LOAD), primary controller circuit current (I_M), and secondary controller circuit current (I_S). As shown, after VOUT reaches a target level, I_M and I_S are offset from each other, which reduces the stability / efficiency of the multi-phase converter (e.g., multi-phase converter 102 of FIG. 1) during transient conditions, such as when I_LOAD transitions from low to high.

[0039] For timing diagram 500 of FIG. 5, the controller topology of FIG. 2 is assumed, with error amplifier 152 omitted or disconnected, and an offset of approximately 350 μs applied between the control loops of primary controller circuit 106A and secondary controller circuits 150A and 151A-151M. As a result of the offset, I_M and I_S will differ from one another. The difference in I_M and I_S will result in the phases of the primary and secondary controller circuits having different currents, creating a thermal imbalance between the phases of the primary and secondary controller circuits. The difference in I_M and I_S will also reduce the reliability of the phases requiring higher current due to reduced durability of the power stages and / or inductors. The difference in I_M and I_S will also reduce efficiency at lower loads, resulting in heating losses (e.g., I 2 × Ron loss) occurs.

[0040] 6 is a timing diagram 600 illustrating waveforms of a multi-phase converter including an described power stage controller (e.g., controller 104 in FIG. 1 or controller 200 in FIG. 2). In timing diagram 600, waveforms for VOUT, I_LOAD, I_M, and I_S are shown. As shown, after VOUT reaches a target level, I_M and I_S are equal most of the time, improving the stability / efficiency of the multi-phase converter (e.g., multi-phase converter 102 in FIG. 1) during transient conditions, such as when I_LOAD transitions from low to high.

[0041] For timing diagram 600 of Figure 6, the controller topology of Figure 2 is assumed, where error amplifier 152 is connected and an offset is applied for approximately 350 μs between the control loops of primary controller circuit 106A and secondary controller circuits 150A and 151A-151M. Initially, after the offset is applied, I_M and I_S begin to deviate from each other, but the operation of error amplifier 152 returns I_M and I_S to the same value. This ensures that each phase of primary controller circuit 106A and secondary controller circuits 150A and 151A-151M draws the same current.

[0042] As used herein, the term "coupled" may encompass a connection, communication, or signal path that enables a functional relationship consistent with this specification. For example, if device A generates a signal to control device B to perform a certain action, then (a) in a first example, device A is coupled to device B by a direct connection; or (b) in a second example, device A is coupled to device B via an intervening component C such that device B is controlled by device A via a control signal generated by device A, where intervening component C does not change the functional relationship between device A and device B.

[0043] Variations are possible in the described embodiments and other embodiments are possible within the scope of the claims.

Claims

1. 1. A power stage controller comprising: a multi-phase pulse control circuit having a first control input and multi-phase pulse outputs, each of the multi-phase pulse outputs adapted to be coupled to a respective switch control input of a respective power stage; a current sense circuit having current sense inputs and current sense outputs, each of the current sense inputs adapted to be coupled to a respective current sense terminal of a respective power stage, the current sense circuit configured to provide a combined current sense voltage at the current sense output in response to a current sense voltage at the current sense inputs; a comparator having a first comparator input, a second comparator input, and a comparator output, the first comparator input configured to receive a feedback voltage, the second comparator input coupled to the current sense output, and the comparator output coupled to the first control input; an error amplifier having a first error amplifier input, a second error amplifier input, and an error amplifier output, the error amplifier configured to provide an error voltage at the error amplifier output in response to a first voltage at the first error amplifier input and a second voltage at the second error amplifier input; a mode controller having a mode controller input, the mode controller including a summing circuit having a first summing circuit input coupled to the error amplifier output, a second summing circuit input, and a summing circuit output coupled to the first comparator input; selecting one of a primary controller mode or a secondary controller mode in response to a mode control voltage at the mode controller input; bypassing the summing circuit in response to selecting the primary controller mode; enabling the summing circuit in response to selecting the secondary controller mode; the mode controller configured to a power stage controller.

2. 10. The power stage controller of claim 1, a power stage controller configured, in the primary controller mode, for the first error amplifier input to be coupled to an output voltage terminal, the second error amplifier input to be coupled to a reference voltage, and the first comparator input to receive the error voltage as the feedback voltage;

3. 3. The power stage controller of claim 2, The power stage controller further includes an error amplifier output terminal coupled to the error amplifier output, the error amplifier output terminal configured to provide the error voltage to another power stage controller.

4. 10. The power stage controller of claim 1, a power stage controller, wherein in the secondary controller mode, the first error amplifier input is adapted to be coupled to a current sense output terminal of another power stage controller, the second error amplifier input is adapted to be coupled to the current sense output, and the first comparator input is configured to receive a summed voltage from the summing circuit output in response to an error voltage at the first summing circuit input and an error voltage at the error amplifier output provided by another power stage controller in the primary controller mode.

5. 10. The power stage controller of claim 1, A power stage controller further comprising a current sense output terminal coupled to the current sense output, the current sense output terminal configured to provide the combined current sense voltage at the current sense output to another power stage controller.

6. 10. The power stage controller of claim 1, the multi-phase pulse control circuit further having a second control input coupled to an output voltage terminal, a third control input coupled to an input voltage terminal, and a fourth control input coupled to a lamp terminal, the multi-phase pulse control circuit configured to control the multi-phase pulse output in response to a voltage at the first control input, an output voltage at the second control input, an input voltage at the third control input, and a lamp voltage at the fourth control input.

7. 10. The power stage controller of claim 1, and wherein in the secondary controller mode, the error amplifier is configured to operate as an integrator in an off-time control loop to equalize a current of another power stage controller configured in a primary controller mode with a current of the power stage controller.

8. 1. A controller for a multi-phase converter, comprising: a main controller circuit having a first main controller input, a second main controller input, a current sense output terminal, and an error amplifier output terminal, the first main controller input adapted to be coupled to an output voltage terminal of the multi-phase converter and the second main controller input adapted to be coupled to a reference voltage terminal; a secondary controller circuit having a first secondary controller input coupled to the current sense output terminal and a second secondary controller input coupled to the error amplifier output terminal; a first summing circuit having a first summing circuit input, a second summing circuit input, and a summing circuit output, the first summing circuit input coupled to the second secondary controller input; an integrator having a first integrator input coupled to the first secondary controller input, a second integrator input, and an integrator output coupled to the second summing circuit input, the integrator configured to receive at the second integrator input a first combined current sense voltage for a power stage of the multi-phase converter controlled by the secondary controller circuit; the secondary controller circuit including: Including the controller.

9. 9. The controller of claim 8, the main controller circuit: a multi-phase pulse control circuit having a control input and multi-phase pulse outputs, each of the multi-phase pulse outputs adapted to be coupled to a respective switch control input of a respective power stage of the multi-phase converter; a current sense circuit having a current sense input and a current sense output, each of the current sense inputs adapted to be coupled to a respective current sense output terminal of a respective power stage of the multi-phase converter, the current sense circuit configured to provide a second combined current sense voltage at the current sense output in response to a current sense voltage at the current sense input; a comparator having a first comparator input, a second comparator input coupled to the current sense output, and a comparator output coupled to the control input, the comparator being configured to receive a feedback voltage at the first comparator input; an error amplifier having a first error amplifier input coupled to the first primary controller input, a second error amplifier input coupled to the second primary controller input, and an error amplifier output, the error amplifier configured to provide an error voltage at the error amplifier output in response to an output voltage at the first error amplifier input and a reference voltage at the second error amplifier input; Including the controller.

10. 9. The controller of claim 8, the main controller circuit: a second summing circuit; A mode controller having a mode controller input, selecting one of a primary controller mode or a secondary controller mode in response to a voltage at the mode controller input; bypassing the second summing circuit in response to selecting the primary controller mode; enabling the second summing circuit in response to selecting the secondary controller mode; the mode controller configured to Including the controller.

11. 9. The controller of claim 8, the secondary controller circuit: a multi-phase pulse control circuit having a control input and multi-phase pulse outputs, each of the multi-phase pulse outputs adapted to be coupled to a respective switch control input of a respective power stage of the multi-phase converter; a current sense circuit having current sense inputs and current sense outputs, each of the current sense inputs adapted to be coupled to a respective current sense output terminal of a respective power stage of the multi-phase converter, the current sense circuit configured to provide a combined current sense voltage at the current sense output in response to a current sense voltage at the current sense inputs; a comparator having a first comparator input, a second comparator input coupled to the current sense output, and a comparator output coupled to the control input, the comparator being configured to receive a feedback voltage at the first comparator input; The controller further includes:

12. 9. The controller of claim 8, A controller, wherein the primary controller circuit is part of a first integrated circuit (IC) and the secondary controller circuit is part of a second IC.

13. 9. The controller of claim 8, a controller further comprising a plurality of secondary controller circuits including the secondary controller circuit, each of the secondary controller circuits having a respective first secondary controller input and a respective second secondary controller input, each respective first secondary controller input coupled to the current sense output terminal and each respective second secondary controller input coupled to the error amplifier output terminal.

14. 14. The controller of claim 13, A controller wherein the primary controller circuit is part of a first integrated circuit (IC) and each secondary controller circuit is part of one or more other ICs.

15. An apparatus for controlling a multi-phase converter, comprising: a first controller circuit, a first error amplifier having a feedback input, a reference input, and a first error amplifier output; a first current sense circuit having a first current sense output, the first current sense circuit configured to generate a first current sense signal at the first current sense output representative of a first combined current; a first comparator having a first comparator input coupled to the first error amplifier output, a second comparator input coupled to the first current sense output, and a first comparator output; a first pulse generating circuit coupled to the first comparator output; the first controller circuit including: a second controller circuit, a second current sense circuit having a second current sense output, the second current sense circuit configured to generate a second current sense signal at the second current sense output representative of a second combined current; a second error amplifier having a first error amplifier input coupled to the first current sense output, a second error amplifier input coupled to the second current sense output, and a second error amplifier output; a summing circuit having a first summing input coupled to the first error amplifier output, a second summing input coupled to the second error amplifier output, and a summing output; a second comparator having a third comparator input coupled to the summing output, a fourth comparator input coupled to the second current sense output, and a second comparator output; a second pulse generating circuit coupled to the second comparator output, the second pulse generating circuit having a pulse generating output and configured to adjust a pulse to the multi-phase converter at the pulse generating output in response to a difference between the first and second combined currents; the second controller circuit including:

1. An apparatus comprising:

16. The apparatus of claim 15, the first current sense circuit further having a first current sense input, and the second current sense circuit further having a second current sense input; The device, a multi-phase converter having a converter output coupled to the feedback input and a converter input coupled to the pulse generation output, the multi-phase converter including parallel coupled power stages each having a respective current sense output; The apparatus, wherein some of the current sense outputs are coupled to the first current sense input and others of the current sense outputs are coupled to the second current sense input.

17. The apparatus of claim 16, The apparatus further includes a load coupled to the converter output.

18. The apparatus of claim 15, The apparatus, wherein one or both of the first error amplifier and the second error amplifier include a respective integrator.

19. The apparatus of claim 15, The apparatus, wherein the first controller circuit is part of a first integrated circuit and the second controller circuit is part of a second integrated circuit.

20. An apparatus for controlling parallel power stages of a multi-phase converter, comprising: a first controller circuit, a first error amplifier configured to generate a first error signal in response to a difference between a feedback signal from the multi-phase converter and a reference signal; a first current sense circuit configured to generate a first current sense output signal representative of a first combined current at the output of the first plurality of paralleled power stages; Including, the first controller circuit configured to provide a first pulse width modulated signal to the first plurality of parallel power stages in response to a difference between the first error signal and the first current sense output signal; a second controller circuit, a second current sense circuit configured to generate a second current sense output signal representative of a second combined current at the output of the second plurality of paralleled power stages; a second error amplifier configured to generate a second error signal in response to a difference between the first and second combined currents; a summing circuit configured to generate a summed signal in response to the first and second error signals; Including, the second controller circuit configured to provide a second pulse width modulated signal to the second plurality of paralleled power stages in response to a difference between the summed signal and the second current sense output signal; 1. An apparatus comprising:

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