Semiconductor Devices

Abstract

To provide a semiconductor device excellent in reliability.SOLUTION: A semiconductor device 100 comprises: a first nitride semiconductor layer 3; a second nitride semiconductor layer 4; a first electrode 5 and a second electrode 7 each electrically connected to the first nitride semiconductor layer 3; a gate electrode 6; a gate field plate electrode 8; a first field plate electrode 9; and a second field plate electrode 10. A distance d1 between a bottom face of the second field plate electrode 10 and the first nitride semiconductor layer 3 is shorter than a distance d2 between a bottom face of a portion which projects the most toward the second electrode 7 side of the gate field plate electrode 8 and the first nitride semiconductor layer 3, and is shorter than a distance d3 between a bottom portion of an end surface at the first electrode 5 side, of the first field plate electrode 9 and the first nitride semiconductor layer 3.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] FIELD An embodiment of the present invention relates to a semiconductor device. [Background technology]

[0002] Semiconductor elements such as transistors and diodes are used in circuits such as switching power supply circuits and inverter circuits. These semiconductor elements are required to have high breakdown voltage and low on-resistance. There is a trade-off between breakdown voltage and on-resistance that is determined by the element material.

[0003] Advances in technological development have enabled semiconductor devices to achieve low on-resistance close to the limits of silicon, the primary device material. To further improve breakdown voltage or further reduce on-resistance, a change in device material is necessary. By using nitride semiconductors such as gallium nitride and aluminum gallium nitride as the device material, the trade-off relationship determined by the device material can be improved. This makes it possible to dramatically increase the breakdown voltage and reduce the on-resistance of semiconductor devices.

[0004] Field plate electrodes are used to alleviate the lateral electric field concentration in nitride semiconductor transistors. However, even when field plate electrodes are used, the electric field concentration can still destroy the interlayer insulating film. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2015-170821 Summary of the Invention [Problem to be solved by the invention]

[0006] The problem to be solved by the present invention is to provide a highly reliable semiconductor device. [Means for solving the problem]

[0007] A semiconductor device according to an embodiment includes a first nitride semiconductor layer, a second nitride semiconductor layer located on the first nitride semiconductor layer and having a band gap larger than that of the first nitride semiconductor layer, a first electrode located on the second nitride semiconductor layer and electrically connected to the first nitride semiconductor layer, a second electrode located on the first nitride semiconductor layer and electrically connected to the first nitride semiconductor layer, a gate electrode located between the first electrode and the second electrode, a gate field plate electrode located on the gate electrode and electrically connected to the gate electrode, a first field plate electrode located on the second nitride semiconductor layer, between the gate field plate electrode and the second electrode and electrically connected to the first electrode, and a second field plate electrode located between the first field plate electrode and the gate field plate electrode and electrically connected to the first electrode. The distance between the bottom surface of the second field plate electrode and the first nitride semiconductor layer is shorter than the distance between the bottom surface of the portion of the gate field plate electrode that protrudes most toward the second electrode side and the first nitride semiconductor layer, and the distance between the bottom surface of the second field plate electrode and the first nitride semiconductor layer is shorter than the distance between the bottom of the end surface of the first field plate electrode on the first electrode side and the first nitride semiconductor layer. The distance between the bottom surface of the second field plate electrode and the first nitride semiconductor layer is shorter than the distance between the bottom of the first electrode-side end surface of the first field plate electrode and the first nitride semiconductor layer. The first electrode-side end surface of the second field plate electrode is located closer to the first electrode than the second electrode-side end surface of the gate field plate electrode. The second electrode-side end surface of the second field plate electrode is located closer to the second electrode than the first electrode-side end surface of the first field plate electrode. The second electrode-side end surface of the gate electrode is located between the first electrode-side end surface of the second field plate electrode and the second electrode-side end surface of the second field plate electrode. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a schematic cross-sectional view of a semiconductor device according to an embodiment; [Figure 2] 1 is a schematic cross-sectional view of a semiconductor device according to an embodiment; [Figure 3] 1 is a schematic cross-sectional view of a semiconductor device according to an embodiment; [Figure 4] 1 is a schematic cross-sectional view of a semiconductor device according to an embodiment; DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In the following description, the same or similar components will be denoted by the same reference numerals, and a description of a component that has already been described may be omitted.

[0010] In this specification, the term "nitride semiconductor layer" includes "GaN-based semiconductors." "GaN-based semiconductors" is a general term for semiconductors containing gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), and those with intermediate compositions.

[0011] In this specification, "undoped" means that the impurity concentration is 2×10 16 cm -3 This means that:

[0012] In this specification, in order to indicate the positional relationship of parts, etc., the upward direction of the drawing will be described as "up" and the downward direction of the drawing will be described as "down." In this specification, the concepts of "up" and "down" do not necessarily refer to the direction of gravity.

[0013] (First embodiment) The semiconductor device of the first embodiment includes a first nitride semiconductor layer, a second nitride semiconductor layer located on the first nitride semiconductor layer and having a band gap larger than that of the first nitride semiconductor layer, a first electrode located on the second nitride semiconductor layer and electrically connected to the first nitride semiconductor layer, a second electrode located on the first nitride semiconductor layer and electrically connected to the first nitride semiconductor layer, a gate electrode located between the first electrode and the second electrode, a gate field plate electrode located on the gate electrode and electrically connected to the gate electrode, a first field plate electrode located on the second nitride semiconductor layer, located between the gate field plate electrode and the second electrode and electrically connected to the first electrode, and a second field plate electrode located between the first field plate electrode and the gate field plate electrode and electrically connected to the first electrode.

[0014] 1 is a schematic cross-sectional view of a semiconductor device according to Embodiment 1. The semiconductor device is a HEMT (High Electron Mobility Transistor) 100 using a GaN-based semiconductor.

[0015] The HEMT100 includes a substrate 1, a buffer layer 2, a channel layer 3 (first nitride semiconductor layer), a barrier layer 4 (second nitride semiconductor layer), a source electrode 5 (first electrode), a gate electrode 6, a drain electrode 7 (second electrode), a gate field plate electrode 8, a first field plate electrode 9, a second field plate electrode 10, a third field plate electrode 11, and an interlayer insulating layer 12.

[0016] The substrate 1 is formed of, for example, silicon (Si). In addition to silicon, for example, sapphire (Al2O3) or silicon carbide (SiC) can also be applied.

[0017] The buffer layer 2 is provided on the substrate 1. The buffer layer 2 has a function of relaxing the lattice mismatch between the substrate 1 and the channel layer 3. The buffer layer 2 is formed, for example, of a multilayer structure of aluminum gallium nitride (Al W Ga 1-W N (0 < W ≤ 1)).

[0018] The channel layer 3 is provided on the buffer layer 2. The channel layer 3 is also referred to as an electron traveling layer. The channel layer 3 is, for example, undoped aluminum gallium nitride (Al X Ga 1-X N (0 ≤ X < 1)). More specifically, for example, it is undoped gallium nitride (GaN). The thickness of the channel layer 3 is, for example, 0.1 μm or more and 10 μm or less. In an embodiment, the thickness is the length (height) of each member in the stacking direction of the channel layer 3 and the barrier layer 4 including the channel layer 3.

[0019] The barrier layer 4 is provided on the channel layer 3. The barrier layer 4 is also referred to as an electron supply layer. The bandgap of the barrier layer 4 is larger than the bandgap of the channel layer 3. The barrier layer 4 is, for example, undoped aluminum gallium nitride (Al Y Ga 1-Y N (0 < Y ≤ 1, X < Y)). More specifically, for example, it is undoped Al 0.25 Ga 0.75 N. The thickness of the barrier layer 4 is, for example, 2 nm or more and 100 nm or less.

[0020] A heterojunction interface is formed between the channel layer 3 and the barrier layer 4. A two-dimensional electron gas (2DEG) is formed at the heterojunction interface and serves as a carrier for the HEMT 100.

[0021] The first electrode 5 is, for example, a source electrode. The source electrode 5 is provided on the channel layer 3 and the barrier layer 4. The source electrode 5 is electrically connected to the channel layer 3 and the barrier layer 4. The source electrode 5 is in direct contact with the barrier layer 4, for example.

[0022] The source electrode 5 is, for example, a metal electrode. The source electrode 5 has, for example, a laminated structure of titanium (Ti) and aluminum (Al). It is desirable that the source electrode 5 and the barrier layer 4 are in ohmic contact.

[0023] The gate electrode 6 is provided on the channel layer 3 and the barrier layer 4. The gate electrode 6 is electrically connected to the channel layer 3 and the barrier layer 4. The gate electrode 6 is in direct contact with the barrier layer 4, for example. The gate electrode 6 is provided between the source electrode 5 and the drain electrode 7.

[0024] The gate electrode 6 is made of, for example, titanium nitride (TiN).

[0025] Gate electrode 6 and barrier layer 4 A gate insulating film (not shown) may be provided between the gate insulating layer 102 and the gate insulating layer 104, thereby making the semiconductor device 100 a metal insulator semiconductor (MIS) HEMT. The gate insulating layer may be, for example, an oxide or an oxynitride. The gate insulating layer may be, for example, silicon oxide, aluminum oxide, silicon oxynitride, or aluminum oxynitride.

[0026] The drain electrode 7 is provided on the channel layer 3 and the barrier layer 4. The drain electrode 7 is electrically connected to the channel layer 3 and the barrier layer 4. The drain electrode 7 is in contact with the barrier layer 4, for example.

[0027] The drain electrode 7 is, for example, a metal electrode. The drain electrode 7 has, for example, a laminated structure of titanium (Ti) and aluminum (Al). It is desirable that the drain electrode 7 and the barrier layer 4 are in ohmic contact.

[0028] The distance between the source electrode 5 and the drain electrode 7 is, for example, not less than 5 μm and not more than 30 μm.

[0029] The source electrode 5 and the drain electrode 7 may be configured to be in direct contact with the channel layer 3 .

[0030] The gate field plate electrode 8 is located on the gate electrode 6. The gate field plate electrode 8 is connected to the gate electrode 6. By providing the gate field plate electrode 8, the electric field concentration in the lateral direction of the gate electrode 6 can be alleviated.

[0031] The gate field plate electrode 8 is not a flat conductive film but has steps. The gate field plate electrode 8 includes a portion that is spaced upward from the gate electrode 6. The side surface of the gate field plate electrode 8 on the second field plate electrode 10 side (the drain electrode 7 side) is a stepped, non-flat surface.

[0032] The gate field plate electrode 8 can have two stages as shown in Fig. 2, or three or more stages. In the embodiment, the bottom surface (the surface facing the channel layer 3) of the portion of the gate field plate electrode 8 that protrudes toward the drain electrode 7 is spaced above the gate electrode 6. When the gate field plate electrode 8 has three or more stages, the number of bottom surfaces of the gate field plate electrode 8 spaced from the gate electrode 6 is two or more.

[0033] 1, the side surface of the portion of the gate field plate electrode 8 that protrudes toward the drain electrode 7 (the surface facing the drain electrode 7) is located closer to the source electrode 5 than the side surface of the gate electrode 6 that faces the second field plate electrode 10. Also, in the embodiment of FIG. 1, the side surface of the portion of the gate field plate electrode 8 that protrudes toward the source electrode 5 (the surface facing the source electrode 5) is located closer to the source electrode 5 than the side surface of the gate electrode 6 that faces the source electrode 5.

[0034] The first field plate electrode 9 is located on the barrier layer 4. The first field plate electrode 9 is spaced apart from the barrier layer 4, and the bottom surface of the first field plate electrode 9 is located above the barrier layer 4, for example, on the third field plate electrode 11 side.

[0035] The first field plate electrode 9 is electrically connected to the source electrode 5. The first field plate electrode 9 relaxes the electric field in the lateral direction. In FIG. 1, the first field plate electrode 9 is connected to the barrier layer 4. Not in contact 1 may be interposed between the barrier layer 4 and the first field plate electrode 9. The first field plate electrode 9 is physically separated from the gate electrode 6 and the drain electrode 7. The first field plate electrode 9 is located between the gate electrode 6 and the drain electrode 7 and closer to the drain electrode 7 than the second field plate electrode 10.

[0036] The second field plate electrode 10 is electrically connected to the source electrode 5. The second field plate electrode 10 has a portion that extends toward the barrier layer 4 between the gate field plate electrode 8 and the first field plate electrode 9. The bottom surface of the second field plate electrode 10 is the bottom surface of the extended portion, and is located between the gate field plate electrode 8 and the first field plate electrode 9. The bottom surface of the second field plate electrode 10 is spaced apart from the barrier layer 4.

[0037] The distance between the bottom of second field plate electrode 10 and channel layer 3 is d1, the distance between the bottom of the portion of gate field plate electrode 8 that protrudes most toward drain electrode 7 and channel layer 3 is d2, and the distance between the bottom of the end face of first field plate electrode 9 on the source electrode 5 side and channel layer 3 is d3. In this case, d1 is preferably shorter than d2 and d1 is preferably shorter than d3.

[0038] Without the second field plate electrode 10, electric field concentration is likely to occur at the end of the gate electrode 6 facing the first field plate electrode 9, the end of the gate field plate electrode 8 facing the first field plate electrode 9, and the gate electrode 6 side of the first field plate electrode 9. Therefore, by providing a second field plate electrode 10 electrically connected to the source electrode 5 between the gate field plate electrode 8 and the first field plate electrode 9, all of these electric field concentrations can be alleviated. However, when d1 is equal to or greater than d2 or d3, the electric field concentration at the end of the gate electrode 6 is not alleviated very much. Therefore, by making the thickness of the interlayer insulating film 12 between the second field plate electrode 10 and the barrier layer 4 very thin and making d1 shorter than d2 and d1 shorter than d3, the electric field concentration at the end of the gate electrode 6 can be effectively alleviated.

[0039] When the end of the gate electrode 6 on the drain electrode 7 side is located between the end of the bottom surface of the second field plate electrode 10 on the source electrode 5 side and the end of the bottom surface of the second field plate electrode 10 on the drain electrode 7 side, the provision of the second field plate electrode 10 gate This makes it possible to more effectively reduce the electric field concentration on the end surface of electrode 6 on the drain electrode 7 side.

[0040] If the end face of the second field plate electrode 10 on the drain electrode 7 side is located closer to the drain electrode 7 than the end face of the first field plate electrode 9 on the source electrode 5 side, the electric field concentration on the gate electrode 6 side of the first field plate electrode 9 can be more effectively alleviated.

[0041] The distance between the upper end surface of the second field plate electrode 10 and the channel layer 3 is set to be equal to the distance between the upper end surface of the second field plate electrode 10 and the channel layer 3. 10 If the distance is longer than the distance between the upper end surface on the drain electrode 7 side and the channel layer 3, electric field concentration at the upper end of the gate field plate electrode 8 on the drain electrode 7 side can be effectively alleviated.

[0042] If the distance between the upper end surface of the second field plate electrode 10 and the channel layer 3 is longer than the distance between the upper end surface of the first field plate electrode 9 and the channel layer 3, the electric field concentration at the end of the first field plate electrode 9 on the source electrode 5 side can be effectively alleviated.

[0043] The third field plate electrode 11 is electrically connected to the source electrode 5, extends toward the drain electrode 7, and is located above the gate electrode 6. The third field plate electrode 11 relieves the electric field in the lateral direction. 1 has the same potential as the source electrode 5. The gate electrode 5, the first field plate electrode 9, and the second field plate electrode 10 are located between the extending portion of the third field plate electrode 11 and the second nitride semiconductor layer 4. In the stacking direction of the channel layer 3 and the barrier layer 4, the second field plate electrode 10 is located between the first field plate electrode 9 and the third field plate electrode 11. The end face of the third field plate electrode 11 on the drain electrode 7 side is connected to the first field plate electrode 9 The end face of third field plate electrode 11 on the drain electrode 7 side is located closer to the drain electrode 7 than the end face of second field plate electrode 10 on the drain electrode 7 side.

[0044] The first to third field plate electrodes of the embodiment are not directly connected to each other in the cross section shown in Fig. 1. The cross section shown in Fig. 1 is a plane parallel to the thickness direction of the substrate 1 (a plane perpendicular to the surface of the channel layer 3 on the barrier layer 4 side, which includes a line segment extending from the source electrode 5 to the drain electrode 7), and the gate electrode 6, the first field plate electrode 9, and the second field plate electrode10 The source electrode 5 is connected to a source pad (not shown), and the field plate electrode shown in the embodiment is connected to the source pad, for example.

[0045] The interlayer insulating film 12 is made of, for example, an oxide or a nitride. The interlayer insulating film 12 is made of, for example, silicon oxide (SiO2), silicon nitride (SiN), or a high-dielectric-constant (high-k) material. An example of a high-k material is hafnium oxide (HfO2).

[0046] The element types and element concentrations of semiconductor layers and semiconductor regions can be measured using, for example, SIMS (Secondary Ion Mass Spectrometry) and EDX (Energy Dispersive X-ray Spectroscopy). Furthermore, the relative levels of element concentrations can be determined from the carrier concentrations determined using, for example, SCM (Scanning Capacitance Microscopy). Furthermore, the depth, thickness, width, spacing, and other distances of impurity regions can be determined using, for example, SIMS. Furthermore, the depth, thickness, width, spacing, and other distances of impurity regions can also be determined from, for example, comparative images of SCM images and atom probe images.

[0047] Gate field plate electrode 8, first field plate electrode 9, and second field plate electrode 10 In comparison with the comparative example in which no gate electrode exists, the electric field concentration on the gate electrode 6 is alleviated.

[0048] (Second embodiment) The semiconductor device of the second embodiment is a modification of the semiconductor device of the first embodiment. Fig. 2 shows a schematic cross-sectional view of the semiconductor layer 101 of the second embodiment. The semiconductor device 101 of the second embodiment has multiple stages of gate field plate electrodes 8, multiple stages of first field plate electrodes 9, and the extended portion of the second field plate electrode 10 toward the barrier layer 4 is U-shaped and extends toward the drain electrode 7 side beyond the first field plate electrode 9, and a fourth field plate electrode 1 is provided between the first field plate electrode 9 and the drain electrode 7 3 It is common with the semiconductor device 100 of the first embodiment except that it has an insulating film 12 thereon. In embodiments including modifications of the first embodiment, some or all of the modified or added configurations can be adopted in other embodiments. The description of the content common among the embodiments will be omitted. Also in the second embodiment, similar to the first embodiment, a semiconductor device 101 with reduced lateral electric field concentration and excellent reliability can be provided.

[0049] The gate field plate electrode 8 can be made multi-stage, or the first field plate electrode 9 can be made multi-stage. By making the field plate electrode multi-stage, the electrolytic concentration can be further alleviated. When the gate field plate electrode 8 is multi-stage, the distance between the bottom surface of the uppermost stage and the channel layer 3 is d2. Also, when the first field plate electrode 9 is multi-stage, the distance between the bottom surface of the lowermost stage of the first field plate electrode 9 and the channel layer 3 is d3.

[0050] Even if the extended portion of the second field plate electrode 10 toward the barrier layer 4 is U-shaped, since the extended portion is very deep toward the gate electrode 6 side, d1 < d2 and d1 < d3 are satisfied, and the electric field concentration of the gate electrode 6, the gate field plate electrode 8, and the first field plate electrode 9 can be alleviated.

[0051] Fig 2In the semiconductor device 101, the end of the second field plate electrode 10 on the drain electrode 7 side is located closer to the drain electrode 7 than the end of the first field plate electrode 9 on the drain electrode 7 side. By extending the second field plate electrode 10 toward the drain electrode 7 side or by providing a fourth field plate electrode 13 between the first field plate electrode 9 and the drain electrode 7, electric field concentration can be alleviated and the capacitance between the gate and the drain can be reduced. Furthermore, this configuration stabilizes high-speed operation. The fourth field plate electrode 13 is electrically connected to the source electrode 5 and may also be connected to the second field plate electrode 10.

[0052] (Third embodiment) The semiconductor device of the third embodiment is a modification of the semiconductor device of the first embodiment or the semiconductor device of the second embodiment. FIG. 3 shows a schematic cross-sectional view of a semiconductor layer 102 of the third embodiment. The semiconductor device 102 of the third embodiment is common to the semiconductor device 100 of the first embodiment or the semiconductor device 101 of the second embodiment, except that the second field plate electrode 10 extends toward the source electrode 5. In the embodiments including the modification of the first embodiment, some or all of the modified or added configurations can be adopted in other embodiments. Descriptions of common features between the embodiments will be omitted. In the third embodiment, as in the first embodiment, a semiconductor device 102 with excellent reliability due to reduced lateral electric field concentration can be provided.

[0053] 3, the end of the second field plate electrode 10 on the source electrode 5 side is located closer to the source electrode 5 than the end of the gate field plate electrode 8 on the source electrode 5 side. If the second field plate electrode 10 is extended toward the source electrode 5, the capacitance between the gate and source increases, but the potential becomes stable. The second field plate electrode 10 may be extended further and connected to the source electrode 5 or the third field plate electrode 11.

[0054] (Fourth embodiment) The semiconductor device of the fourth embodiment is a modification of the semiconductor device of the first to third embodiments. FIG. 4 shows a schematic cross-sectional view of a semiconductor layer 103 of the fourth embodiment. The semiconductor device 103 of the fourth embodiment has a trench (recess) in which the bottom surface of the gate electrode 6 is located in the channel layer 3, and further includes a gate insulating film 14 between the gate electrode 6 and the barrier layer 4. The gate electrode 6 is located in the trench. The trench bottom being located in the channel layer 3 eliminates two-dimensional electron gas below the gate electrode 6. This configuration enables the semiconductor device 103 to achieve normally-off operation. Even in the fourth embodiment, in which the structure of the gate electrode 6 is different, a semiconductor device 104 can be provided that has excellent reliability due to reduced lateral electric field concentration, as in the first embodiment.

[0055] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments may be embodied in various other forms, and various omissions, substitutions, and modifications may be made without departing from the spirit of the invention. For example, components of one embodiment may be replaced or changed with components of another embodiment. These embodiments and modifications thereof are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0056] 100 Semiconductor device 1 board 2. Buffer layer 3. Channel layer (first nitride semiconductor layer, nitride semiconductor layer) 4. Barrier layer (second nitride semiconductor layer, nitride semiconductor layer) 5. Source electrode (first electrode) 6 gate electrode 7 Drain electrode (second electrode) 8 Gate field plate electrode 9 First field plate electrode 10 Second field plate electrode 11 Third field plate electrode 12 Interlayer insulating film 13 Fourth field plate electrode 14 Gate insulating film 100~103 Semiconductor devices

Claims

[Claim 1] a first nitride semiconductor layer; a second nitride semiconductor layer located on the first nitride semiconductor layer and having a band gap larger than that of the first nitride semiconductor layer; a first electrode located on the second nitride semiconductor layer and electrically connected to the first nitride semiconductor layer; a second electrode located on the first nitride semiconductor layer and electrically connected to the first nitride semiconductor layer; a gate electrode located between the first electrode and the second electrode; a gate field plate electrode located on the gate electrode and electrically connected to the gate electrode; a first field plate electrode located on the second nitride semiconductor layer, between the gate field plate electrode and the second electrode, and electrically connected to the first electrode; a second field plate electrode located between the first field plate electrode and the gate field plate electrode and electrically connected to the first field plate electrode; Equipped with a distance between a bottom surface of the second field plate electrode and the first nitride semiconductor layer is shorter than a distance between a bottom surface of a portion of the gate field plate electrode that protrudes most toward the second electrode side and the first nitride semiconductor layer; a distance between a bottom surface of the second field plate electrode and the first nitride semiconductor layer is shorter than a distance between a bottom portion of an end surface of the first field plate electrode on the first electrode side and the first nitride semiconductor layer; an end face of the second field plate electrode on the first electrode side is located closer to the first electrode than an end face of the gate field plate electrode on the second electrode side; an end face of the second field plate electrode on the second electrode side is located closer to the second electrode than an end face of the first field plate electrode on the first electrode side, a second electrode side end of the gate electrode located between an end of the bottom surface of the second field plate electrode on the first electrode side and an end of the bottom surface of the second field plate electrode on the second electrode side;

Images