Reference potential generating circuit and semiconductor memory device

Abstract

To provide a reference potential generation circuit and a semiconductor storage device capable of generating a reference potential of a sense amplifier that can reduce influence of temperature, increase a read margin, and operate with high reliability.SOLUTION: A reference potential generation circuit of the embodiment includes an original reference potential generation unit for generating an original reference potential and a reference potential correction unit for lowering the original reference potential according to the temperature rising and outputting the potential to a sense amplifier as a reference potential.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] FIELD Embodiments of the present invention relate to a reference potential generating circuit and a semiconductor memory device. [Background technology]

[0002] In semiconductor memory devices, when reading data, the sense amplifier is activated after the bit line reaches a potential sufficient to determine the sense amplifier output. At this time, the reference potential of the sense amplifier is set to absorb the characteristic variations of the transistors used in the sense amplifier and to ensure that the level of the read signal can be determined reliably. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2012-113769 Summary of the Invention [Problem to be solved by the invention]

[0004] Incidentally, the change in the potential of the read signal varies depending on the temperature, such as the ambient temperature. If the reference potential of the sense amplifier is the same, when the value of the memory cell is "0", the higher the temperature, the smaller the read margin (the difference between the level of the signal to be read and the level of the reference signal used for judgment), and when the value of the memory cell is "1", the lower the temperature, the smaller the data read margin.

[0005] An object of one embodiment of the present invention is to provide a reference potential generating circuit and a semiconductor memory device capable of generating a reference potential for a sense amplifier that can reduce the influence of temperature, increase a read margin, and perform highly reliable operation. [Means for solving the problem]

[0006] The reference potential generating circuit of the embodiment includes an original reference potential generating unit that generates an original reference potential, and a reference potential correcting unit that reduces the original reference potential as the temperature rises and outputs the reduced original reference potential to a sense amplifier as a reference potential. The reference potential correction unit receives a reference current control potential for controlling the enable timing of the sense amplifier as a control signal that varies with the temperature rise, and lowers the original reference potential based on the control signal. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is an explanatory diagram of a schematic configuration of a semiconductor memory device according to an embodiment. [Figure 2] FIG. 2 is an explanatory diagram of an example of the configuration of the main part of a sense amplifier circuit. [Figure 3] FIG. 3 is an explanatory diagram of the conventional problems. [Figure 4] FIG. 4 is a diagram illustrating the operation of the embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0008] The semiconductor memory device of the embodiment will be described in detail below with reference to the drawings. However, the present invention is not limited to these embodiments.

[0009] FIG. 1 is an explanatory diagram of a schematic configuration of a semiconductor memory device according to an embodiment. The semiconductor device 10 is configured as a NOR type flash memory, and as shown in FIG. 1, includes a memory cell array 11, a row decoder 12, a column decoder 13, a reference potential generating circuit 14, a sense amplifier circuit 15, a data output circuit 16, and a control circuit 17.

[0010] The memory cell array 11 includes a plurality of memory cells MC arranged in a grid pattern. The memory cell array also includes a plurality of word lines WL, a plurality of source lines SL, and a plurality of bit lines BL.

[0011] For ease of understanding, FIG. 1 shows only one memory cell MC in a selected state, and only the word line WL, source line SL, and bit line BL corresponding to that memory cell.

[0012] Here, the memory cell MC includes a memory cell transistor TR having a source terminal connected to a source line SL, a gate terminal connected to a word line WL, and a drain terminal connected to a bit line BL.

[0013] Under the control of the control circuit 17, the row decoder 12 enables the word line WL corresponding to the memory cell MC to be read. Under the control of the control circuit 17, the column decoder 13 enables the source line SL and bit line BL corresponding to the memory cell MC to be read.

[0014] The reference potential generating circuit 14 generates and supplies a reference potential to the sense amplifier circuit 15 . The sense amplifier circuit 15 compares the potential of the bit line corresponding to the selected memory cell MC with a reference potential at a predetermined timing to determine the data of the memory cell MC and outputs the determination result to the data output circuit 16.

[0015] The data output circuit 16 outputs read data DOUT based on the output of the sense amplifier circuit 15. The control circuit 17 controls the row decoder 12, the column decoder 13, and the sense amplifier circuit 15 to write, read, or erase data to the corresponding memory cells MC based on a clock signal CLK, command data CMD, and address data ADD from a host device (e.g., an MPU) not shown.

[0016] Next, the configuration of the sense amplifier circuit 15 will be described. FIG. 2 is an explanatory diagram of an example of the configuration of the main part of a sense amplifier circuit. The sense amplifier circuit 15 includes a sense amplifier 151 , a sense timing generation circuit 152 , a reference current generation circuit 153 , and a reference potential generation circuit 154 .

[0017] In this case, the sense amplifiers 151 and the sense timing generation circuits 152 are provided corresponding to the plurality of blocks BLK, respectively. In this case, the sense timing generation circuit 152 can be shared by a plurality of sense amplifiers 151.

[0018] In the above configuration, the reference current generating circuit 153 generates a reference current control potential IREF and outputs it to the sense timing generating circuit 152 and the reference potential generating circuit 154 . The reference potential generating circuit 154 generates a reference potential Vref corresponding to the ambient temperature based on the reference current control potential IREF and outputs it to the inverting input terminal of the sense amplifier 151 .

[0019] The sense timing generation circuit 152 has one or more delay circuits (not shown) and outputs a sense amplifier enable signal SAE that enables the sense amplifier 151 at a timing corresponding to the current value of the reference current control potential IREF input from the reference current generation circuit 153.

[0020] As a result, when the sense amplifier 151 receives an input signal IN from the bit line BL of each block BLK at its non-inverting input terminal, receives a reference potential Vref at its inverting input terminal, and the sense amplifier enable signal SAE from the sense timing generation circuit 152 is in an enabled state, the sense amplifier 151 outputs an output signal OUT at an "H" level when the input signal IN is at a voltage higher than the reference potential Vref.

[0021] Furthermore, the sense amplifier 151 outputs an output signal OUT at an "L" level when the sense amplifier enable signal SAE from the sense timing generation circuit 152 is in an enable state and the input signal IN has a voltage lower than the reference potential Vref.

[0022] The reference current generating circuit 153 is roughly divided into a current value setting unit 153A, a current mirror 153B, and a current source 153C.

[0023] The current value setting unit 153A includes n (n is an integer equal to or greater than 2) N-channel MOS transistors TT1 to TTn for trimming, which are connected in parallel and whose number of parallel connections is variable by setting the gate terminals to "H" level or "L" level based on trimming information read from fuses or flash memory.

[0024] The current mirror 153B includes a P-channel MOS transistor PM1 having a source terminal connected to the high potential power supply VDD, a drain terminal connected to the current setting unit 153A, and a drain terminal connected to a gate terminal, and a P-channel MOS transistor PM2 having a source terminal connected to the high potential power supply VDD, a drain terminal connected to the current source 153C, and a gate terminal connected to the gate terminal of the P-channel MOS transistor.

[0025] The current source 153C includes an N-channel MOS transistor whose drain terminal and gate terminal are connected (diode-connected).

[0026] In the above configuration, the drain-source current of the trimming N-channel MOS transistors TT1 to TTn in the on state is set to have a positive temperature coefficient, and the higher the temperature, the larger the drain-source current.

[0027] The current flowing through the P-channel MOS transistor PM1 has a current value proportional to the current value of the current flowing through all of the trimming N-channel MOS transistors TT1 to TTn of the current value setting unit 153A whose gates are set to the “H” level.

[0028] Therefore, the current value of the current flowing through the P-channel MOS transistor PM2, i.e., the current value of the current of the reference current control potential IREF, is also proportional to the current value of the current flowing through all of the trimming N-channel MOS transistors TT1 to TTn of the current value setting unit 153A whose gates are set to the “H” level. Here, the reference current control potential IREF functions as a control signal.

[0029] As a result, in the current value setting unit 153A, a reference current proportional to the number of trimming N-channel MOS transistors TT connected in parallel after trimming flows between the drain terminal and source terminal of the P-channel MOS transistor PM1 of the current mirror 153B.

[0030] As a result, a current proportional to the number of trimming N-channel MOS transistors TT connected in parallel also flows between the drain terminal and source terminal of the P-channel MOS transistor PM2 after trimming, and this current is output to the sense timing generation circuit 152 as a reference current control potential IREF that functions as a control signal.

[0031] The sense timing generation circuit 152 changes the sense timing according to the reference current control potential IREF, so that the larger the reference current control potential, the earlier the sense timing, and the smaller the reference current control potential IREF, the later the sense timing. Trimming is set for each chip and the reference current control potential IREF is adjusted so that the sense timing is constant regardless of process variations.

[0032] As a result, the sense timing generation circuit 152 receives the reference current control potential IREF with process variations absorbed, and enables the sense amplifier enable signal at a timing according to the current value of the reference current control potential IREF.

[0033] Next, the configuration of the reference potential generating circuit 154 will be described. The reference potential generating circuit 154 includes an original reference voltage generating unit 154A that generates and outputs an original reference potential Vref0, and a reference voltage correcting unit 154B that performs temperature compensation on the original reference potential Vref0 based on the reference current control potential IREF and outputs the result as a reference potential Vref to the inverting input terminal of the sense amplifier 151. The original reference voltage generating unit 154A includes a resistor R1 having one end connected to the high potential power supply VDD and a resistor R2 having one end connected to the other end of the resistor R1 and the other end connected to the low potential power supply VSS, and divides the difference voltage between the voltage of the high potential power supply VDD and the voltage of the low potential power supply VSS to output the original reference potential Vref0. The reference voltage correction unit 154B has an N-channel MOS transistor NM1 whose drain terminal is connected to the connection point between the resistors R1 and R2, whose source terminal is connected to the low potential side power supply VSS, and whose gate terminal is connected to the gate terminal of the N-channel MOS transistor that constitutes the current source 153C.

[0034] In this case, the reference current control potential IREF is supplied as a control signal to the gate terminal of the N-channel MOS transistor NM1, and a bias voltage corresponding to the reference current control potential IREF is applied. As a result, the N-channel MOS transistor NM1 is turned on, which corresponds to the bias voltage, and pulls down the original reference potential Vref0, outputting it to the inverting input terminal of the sense amplifier 151 as the desired reference potential Vref.

[0035] Next, the operation of the embodiment will be described. First, prior to the operation of the embodiment, the problems of the prior art will be explained. FIG. 3 is an explanatory diagram of the conventional problems. In conventional sense amplifiers, the input reference potential is constant.

[0036] Incidentally, when reading from a flash memory that is compatible with a wide temperature range (for example, −40 to 175° C.), the fluctuation state of the read voltage differs depending on the value stored in the memory cell and the temperature.

[0037] More specifically, when the threshold voltage Vth of the memory cell transistor TR constituting the memory cell MC is high, even if the word line WL becomes "H" level, the memory cell transistor TR remains in the off state, and the potential of the bit line BL remains at approximately the power supply potential.

[0038] However, the potential of the bit line BL gradually drops slightly due to the leakage current of the memory cell transistor TR. Generally, the leakage current of the memory cell transistor TR tends to increase as the temperature increases. Therefore, as the temperature increases, the potential of the bit line BL decreases more rapidly when reading the value = 0 stored in the memory cell MC, as shown in Figure 3.

[0039] Therefore, the higher the operating temperature range, the less likely the data read margin MG0 for the reference potential Vref becomes to be sufficient, which may result in erroneous read data.

[0040] On the other hand, when the threshold voltage Vth of the memory cell transistor TR constituting the memory cell MC is low, when the word line WL becomes high level, the memory cell transistor TR turns on, an on-current flows from the bit line BL to the source line SL, and the potential of the bit line BL gradually decreases.

[0041] Generally, the on-current of the memory cell transistor TR tends to decrease as the temperature drops, so the lower the temperature, the slower the drop in the potential of the bit line BL when reading the value = 1 stored in the memory cell MC, as shown in Figure 3.

[0042] Therefore, the lower the operating temperature range, the less likely the data read margin MG1 for the reference potential Vref becomes to be sufficient, which may result in erroneous read data.

[0043] Next, the operation of the embodiment will be described with reference again to FIG. FIG. 4 is a diagram illustrating the operation of the embodiment. In this case, the reference potential Vref output from the reference potential generating section 154 is set to decrease as the temperature increases. That is, as shown in FIG. 4, the reference potential VrefH at a predetermined high temperature is lower than the reference potential VrefL at a predetermined low temperature.

[0044] More specifically, the drain-source current of the trimming N-channel MOS transistors TT1 to TTn in the on state increases as the temperature increases, and at temperatures higher than a predetermined reference temperature, the current value is higher than the current value at the predetermined reference temperature.

[0045] Therefore, the current value of the current flowing through the P-channel MOS transistor PM2, i.e., the current value of the current of the reference current control potential IREF, also becomes higher than the current value at the predetermined reference temperature when the temperature is higher than the predetermined reference temperature.

[0046] In parallel with this, the original reference voltage generating unit 154A of the reference potential generating circuit 154 divides the voltage corresponding to the difference potential between the high potential power supply VDD and the low potential power supply VSS, and generates and outputs the original reference potential Vref0.

[0047] At this time, the reference voltage corrector 154B corrects the reference potential Vref by performing temperature compensation based on the voltage corresponding to the reference current control potential IREF.

[0048] That is, when the temperature is higher than the predetermined reference temperature, the current value of the reference current control potential IREF is higher than the current value at the predetermined reference temperature, and when the temperature is lower than the predetermined reference temperature, the current value is lower than the current value at the predetermined reference temperature.

[0049] As a result, the on-resistance of the N-channel MOS transistor constituting the reference voltage correction unit 154B is lower than the on-resistance at the predetermined reference temperature when the temperature is higher than the predetermined reference temperature, and is higher than the on-resistance at the predetermined reference temperature when the temperature is lower than the predetermined reference temperature.

[0050] The reference potential Vref output to the inverting input terminal of the sense amplifier 151 becomes the high temperature reference potential VrefH, which is lower than the reference potential at a predetermined reference temperature, at high temperatures, and becomes the low temperature reference potential VrefL (>VrefH), which is higher than the reference potential at a predetermined reference temperature, at low temperatures.

[0051] Therefore, when the value stored in the memory cell is read out as 0 and the temperature is high, the reference potential Vref becomes equal to the reference potential VrefH. As a result, even if the read voltage drops significantly due to the current flowing between the drain and source of the transistor that constitutes the memory cell being read, as shown by the signal waveform HT0 in Figure 4, at the time when the sense amplifier enable signal SAE, shown by the vertical dashed line in Figure 4, becomes enabled, a sufficiently large data read margin MGH0 from the reference potential VrefH can be ensured, and the read data will not be erroneous. However, if the reference potential VrefH is too low, when reading the value = 1 stored in the memory cell at high temperature, the data read margin MGH1 decreases, and there is a risk that the read data will be erroneous. For this reason, in this embodiment, the on-resistance of the N-channel MOS transistor NM1 constituting the reference voltage correction unit 154B is set to an appropriate value so that the data read margin MGH1 does not fall below the data read margin MGH0.

[0052] Furthermore, when the value stored in the memory cell is read out as 1 and the temperature is low, the reference potential Vref is equal to the reference potential VrefL. As a result, as shown in the signal waveform LT1 in Figure 4, even if the drop in read voltage due to the current flowing between the drain and source of the transistor that constitutes the memory cell to be read becomes small, a sufficiently large data read margin MGL1 from the reference potential VrefL can be ensured, and the read data will not be erroneous.

[0053] As described above, according to this embodiment, when the temperature rises depending on the ambient temperature, the reference potential Vref is lowered, thereby ensuring a sufficiently large data read margin MGH0 when determining whether the value stored in the memory cell is 0. Furthermore, when the temperature drops depending on the ambient temperature, the reference potential Vref is increased to ensure a sufficiently large data read margin MGL1 when determining whether the value stored in the memory cell is 1. Therefore, the reference potential Vref can be set to an optimum value depending on the ambient temperature, and stable and reliable determination can be made. However, if the reference potential VrefL is too high, when reading the value=0 stored in the memory cell at low temperature, the data read margin MGL0 decreases, and there is a risk that the read data will be erroneous. For this reason, in this embodiment, the on-resistance of the N-channel MOS transistor NM1 constituting the reference voltage correction unit 154B is set to an appropriate value so that the data read margin MGL0 does not fall below the data read margin MGL1.

[0054] In the above explanation, the current value setting unit 153A is configured to include n (n is an integer of 2 or more) trimming N-channel MOS transistors TT1 to TTn connected in parallel, but it is also possible to connect multiple resistors with the same resistance value or multiple resistors with different resistance values ​​(for example, resistance values ​​r, 2r, 4r, 8r, ...) in parallel and change the combined resistance value of the resistors connected to the current mirror circuit 153B by trimming to set the current value.

[0055] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0056] 10. Semiconductor memory device 11 Memory Cell Array 12 Row Decoder 13 Column Decoder 14 Reference potential generation circuit 15 Sense amplifier circuit 16 Data output circuit 17 Control circuit 151 Sense Amplifier 152 Sense timing generation circuit 153 Reference current generation circuit 153A current value setting section 153B Current Mirror 153C current source 154 Reference potential generation circuit 154A Reference voltage generator 154B Reference voltage correction unit BLK Block BL, BL0 to BLk bit lines IN Input signal IREF Reference current control potential (control signal) HT0, HT1 signal waveform (at high temperature) LT0, LT1 signal waveform (at low temperature MGL data read margin MgH data read margin MT memory cell NM1 N-channel MOS transistor (pull-down transistor) OUT Output signal SAE Sense amplifier enable signal TT1 to TTn Trimming N-channel MOS transistors VDD High potential side power supply VSS Low potential side power supply Vref Reference potential VrefH Reference potential (at high temperature) VrefL Reference potential (at low temperature) WL, WL0 to WL63 word lines

Claims

1. an original reference potential generating unit that generates an original reference potential; a reference potential correction unit that reduces the original reference potential as the temperature rises and outputs the reduced original reference potential to the sense amplifier as a reference potential; a reference current control potential for controlling an enable timing of the sense amplifier is applied and input to the reference potential correction unit as a control signal that varies with the temperature rise, and the reference potential correction unit reduces the original reference potential based on the control signal; Reference potential generation circuit.

2. a reference current generating circuit that generates and outputs the reference current control potential; a sense timing generation circuit that outputs a sense amplifier enable signal that sets the sense amplifier in an enable state using a timing corresponding to the current value of the reference current control potential input from the reference current generation circuit as the enable timing.

2. The reference potential generating circuit according to claim 1.

3. a current value of the current caused by application of the reference current control potential is higher than the current value at the predetermined reference temperature when the temperature is higher than the predetermined reference temperature, and is lower than the current value at the predetermined reference temperature when the temperature is lower than the predetermined reference temperature; 3. The reference potential generating circuit according to claim 2.

4. the reference potential correction unit sets the reference potential to a high-temperature reference potential that is lower than the reference potential at the predetermined reference temperature when the temperature is higher than a predetermined reference temperature, and sets the reference potential to a low-temperature reference potential that is higher than the reference potential at the predetermined reference temperature when the temperature is lower than the reference temperature; 2. The reference potential generating circuit according to claim 1.

5. the reference potential correction unit includes a MOS transistor having a gate terminal to which the reference current control potential is applied as a bias voltage, and which pulls down the original reference potential to the reference potential.

2. The reference potential generating circuit according to claim 1.

6. a memory cell for storing data; a bit line for transmitting a signal read from the memory cell; a sense amplifier circuit that detects data stored in the memory cell based on a signal transmitted through the bit line; The sense amplifier circuit a sense amplifier that compares the signal transmitted through the bit line with a reference potential and outputs a data detection signal; a reference current generating circuit that generates and outputs a reference current control potential; a sense timing generation circuit that controls, based on the reference current control potential, the timing at which a sense amplifier enable signal that enables the sense amplifier is output from an output terminal; a reference potential generating circuit including an original reference potential generating unit that generates an original reference potential, and a reference potential correcting unit that reduces the original reference potential as the temperature rises and outputs the reduced original reference potential as the reference potential; Semiconductor memory device.

7. the reference potential correction unit reduces the original reference potential in accordance with the temperature rise based on the reference current control potential; 7. The semiconductor memory device according to claim 6.

8. the reference current generating circuit includes a current value setting unit that varies a set current value by trimming; a current mirror circuit that replicates a current corresponding to the set current value set by a current value setting unit and outputs the replicated current as the reference current control potential; 7. The semiconductor memory device according to claim 6, comprising:

9. a reference current control potential for controlling an enable timing of the sense amplifier is applied to the reference potential correction unit as a control signal; 8. The semiconductor memory device according to claim 7.

10. A reference current generating circuit that generates and outputs the reference current control potential; a sense timing generation circuit that outputs a sense amplifier enable signal that sets the sense amplifier in an enable state using a timing corresponding to the current value of the reference current control potential input from the reference current generation circuit as the enable timing.

10. The semiconductor memory device according to claim 9.

11. a current value of the current caused by application of the reference current control potential is higher than the current value at the predetermined reference temperature when the temperature is higher than the predetermined reference temperature, and is lower than the current value at the predetermined reference temperature when the temperature is lower than the predetermined reference temperature; 11. The semiconductor memory device according to claim 10.

12. the reference potential correction unit sets the reference potential to a high-temperature reference potential that is lower than the reference potential at the predetermined reference temperature when the temperature is higher than a predetermined reference temperature, and sets the reference potential to a low-temperature reference potential that is higher than the reference potential at the predetermined reference temperature when the temperature is lower than the reference temperature; 7. The semiconductor memory device according to claim 6.

13. the reference potential correction unit includes a MOS transistor having a gate terminal to which the reference current control potential is applied as a bias voltage, and which pulls down the original reference potential to the reference potential.

7. The semiconductor memory device according to claim 6.

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