Semiconductor Devices

Abstract

To provide a semiconductor device capable of reducing a switching loss and increasing a breakdown immunity.SOLUTION: A semiconductor device includes a semiconductor part, first to fourth electrodes, and a control electrode. The first electrode is provided on a back surface of the semiconductor part, and the second electrode is provided on a front surface thereof at a side opposite to the back surface. The third electrode is provided between the first electrode and the second electrode and is located in the semiconductor part so as to be electrically insulated from the semiconductor part. The control electrode extends in the semiconductor part from the front surface side of the semiconductor part and is located between the second electrode and the third electrode so as to be electrically insulated from the semiconductor part. The fourth electrode extends in the semiconductor part from the front surface side of the semiconductor part and is located between the second electrode and the third electrode. The fourth electrode is located between the semiconductor part and the control electrode and is electrically connected to the third electrode.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The embodiments relate to a semiconductor device. [Background technology]

[0002] It is desirable for power control semiconductor devices to have reduced switching loss and improved breakdown resistance. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2019-12813 Summary of the Invention [Problem to be solved by the invention]

[0004] The embodiments provide a semiconductor device that reduces switching loss and improves breakdown resistance. [Means for solving the problem]

[0005] The semiconductor device according to the embodiment includes a semiconductor portion, a first electrode, a second electrode, a third electrode, a control electrode, and a fourth electrode. The first electrode is provided on a back surface of the semiconductor portion. The second electrode is provided on a surface of the semiconductor portion opposite the back surface. The third electrode is provided between the first electrode and the second electrode, is located within the semiconductor portion, and is electrically insulated from the semiconductor portion by a first insulating film. The control electrode extends from the front surface side of the semiconductor portion into the semiconductor portion, is located between the second electrode and the third electrode, and faces the third electrode via a second insulating film. The first insulating film extends between the semiconductor portion and the control electrode, electrically insulating the control electrode from the semiconductor portion. The fourth electrode extends from the front surface side of the semiconductor portion into the semiconductor portion, is located between the second electrode and the third electrode, and is located between the semiconductor portion and the control electrode. The first insulating film extends between the semiconductor portion and the fourth electrode, and the second insulating film extends between the third electrode and the fourth insulating film. The fourth electrode faces the control electrode via the third insulating film and is electrically connected to the third electrode. [Brief explanation of the drawings]

[0006] [Figure 1] 1 is a schematic cross-sectional view showing a semiconductor device according to an embodiment; [Figure 2] 1 is a schematic plan view showing a semiconductor device according to an embodiment; [Figure 3] FIG. 2 is another schematic cross-sectional view showing the semiconductor device according to the embodiment. [Figure 4] FIG. 10 is a schematic cross-sectional view showing yet another semiconductor device according to the embodiment. [Figure 5] 4 is a time chart showing the operation of the semiconductor device according to the embodiment. [Figure 6] 5A to 5C are schematic cross-sectional views showing a manufacturing process of the semiconductor device according to the embodiment. [Figure 7] 7A to 7C are schematic cross-sectional views showing the manufacturing process following FIG. 6. [Figure 8] 8A to 8C are schematic cross-sectional views showing the manufacturing process following FIG. 7. [Figure 9]FIG. 10 is a schematic cross-sectional view showing a semiconductor device according to a first modified example of the embodiment. [Figure 10] FIG. 10 is a schematic plan view showing a semiconductor device according to a second modified example of the embodiment. [Figure 11] FIG. 10 is a schematic cross-sectional view showing a semiconductor device according to a third modified example of the embodiment. [Figure 12] FIG. 10 is a schematic cross-sectional view showing a semiconductor device according to a fourth modified example of the embodiment. [Figure 13] 10A to 10C are schematic cross-sectional views showing a manufacturing process of a semiconductor device according to a fourth modified example of the embodiment. [Figure 14] 14A to 14C are schematic cross-sectional views showing the manufacturing process following FIG. 13. [Figure 15] FIG. 10 is a schematic cross-sectional view showing a semiconductor device according to a fifth modified example of the embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, embodiments will be described with reference to the drawings. Identical parts in the drawings are assigned the same numbers, and detailed descriptions thereof will be omitted as appropriate, and different parts will be described. Note that the drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between parts, etc., are not necessarily the same as those in reality. Furthermore, even when the same part is shown, the dimensions and ratios may be expressed differently depending on the drawing.

[0008] Furthermore, the arrangement and configuration of each part will be explained using the X-axis, Y-axis, and Z-axis shown in each figure. The X-axis, Y-axis, and Z-axis are mutually perpendicular and represent the X-direction, Y-direction, and Z-direction, respectively. In addition, the Z-direction may be explained as upward and the opposite direction as downward.

[0009] 1 is a schematic cross-sectional view showing a semiconductor device 1 according to an embodiment. The semiconductor device 1 is, for example, an IGBT (Insulated Gate Bipolar Transistor).

[0010] 1, the semiconductor device 1 includes a semiconductor portion 10, a first electrode 20, a second electrode 30, a control electrode 40, a third electrode 50, and a fourth electrode 60. The semiconductor portion 10 is made of, for example, silicon.

[0011] The semiconductor portion 10 is provided between a first electrode 20 and a second electrode 30. The first electrode 20 is, for example, a collector electrode and is provided on a back surface 10B of the semiconductor portion 10. The second electrode 30 is, for example, an emitter electrode and is provided on a front surface 10F of the semiconductor portion 10 opposite to the back surface 10B.

[0012] The control electrode 40, the third electrode 50, and the fourth electrode 60 are located, for example, between the first electrode 20 and the second electrode 30. 10 has, for example, a gate trench GT provided on the front surface 10F side, and the control electrode 40, the third electrode 50, and the fourth electrode 60 are provided inside the gate trench GT.

[0013] The control electrode 40 is, for example, a gate electrode. The control electrode 40 extends from the front surface 10F side of the semiconductor portion 10 into the semiconductor portion 10. The control electrode 40 is electrically insulated from the semiconductor portion 10 by the first insulating film 21. The first insulating film 21 is, for example, a gate insulating film.

[0014] The third electrode 50 is provided in the semiconductor portion 10 and is electrically insulated from the semiconductor portion 10 by, for example, a first insulating film 21. The first insulating film 21 extends between the semiconductor portion 10 and the third electrode 50. The third electrode 50 is located between the first electrode 20 and the control electrode 40. The control electrode 40 is provided between the second electrode 30 and the third electrode 50. The control electrode 40 faces the third electrode 50 via a second insulating film 23. The control electrode 40 is electrically insulated from the third electrode 50 by the second insulating film 23.

[0015] The fourth electrode 60 also extends from the front surface 10F side of the semiconductor portion 10 into the semiconductor portion 10. The fourth electrode 60 is provided between the second electrode 30 and the third electrode 50. The second insulating film 23 extends between the third electrode 50 and the fourth electrode 60, and the fourth electrode 60 faces the third electrode 50 with the second insulating film 23 interposed therebetween.

[0016] Furthermore, the fourth electrode 60 is located between the semiconductor portion 10 and the control electrode 40. The first insulating film 21 extends between the semiconductor portion 10 and the fourth electrode 60, and electrically insulates the fourth electrode 60 from the semiconductor portion 10. The fourth electrode 60 faces the control electrode 40 via a third insulating film 25. The fourth electrode 60 is electrically insulated from the control electrode 40 by the third insulating film 25. The fourth electrode 60 is electrically connected to the third electrode 50 (see FIG. 4(b)).

[0017] The control electrode 40 and the fourth electrode 60 are electrically insulated from the second electrode 30 by a fourth insulating film 27. The fourth insulating film 27 is, for example, an interlayer insulating film. The third electrode 50 and the fourth electrode 60 function as, for example, a second control electrode.

[0018] 1, the semiconductor portion 10 includes a first semiconductor layer 11 of a first conductivity type, a second semiconductor layer 13 of a second conductivity type, a third semiconductor layer 15 of the first conductivity type, and a fourth semiconductor layer 17 of the second conductivity type. In the following description, the first conductivity type is defined as n-type and the second conductivity type is defined as p-type, but the embodiment is not limited to this.

[0019] The first semiconductor layer 11 is, for example, an n-type base layer. The first semiconductor layer 11 extends between the first electrode 20 and the second electrode 30. The third electrode 50 is located in the first semiconductor layer 11 and faces the first semiconductor layer 11 with the first insulating film 21 interposed therebetween.

[0020] The second semiconductor layer 13 is, for example, a p-type base layer. The second semiconductor layer 13 is provided between the first semiconductor layer 11 and the second electrode 30. The second semiconductor layer 13 faces the control electrode 40 with the first insulating film 21 interposed therebetween.

[0021] 1, the semiconductor portion 10 further includes another second semiconductor layer 13, and the control electrode 40 and the fourth electrode 60 are located between the second semiconductor layer 13 and the another second semiconductor layer 13. The another second semiconductor layer 13 faces the fourth electrode 60 with the first insulating film 21 interposed therebetween.

[0022] The third semiconductor layer 15 is, for example, an n-type emitter layer. The third semiconductor layer 15 is provided partially on the second semiconductor layer 13 between the second semiconductor layer 13 and the second electrode 30. The third semiconductor layer 15 is provided so as to be in contact with the first insulating film 21.

[0023] The second electrode 30 is provided so as to cover the surface 10F of the semiconductor portion 10 and the fourth insulating film 27. The second electrode 30 is electrically connected to, for example, the second semiconductor layer 13 and the third semiconductor layer 15 on the surface 10F of the semiconductor portion 10.

[0024] The fourth semiconductor layer 17 is, for example, a p-type collector layer. The fourth semiconductor layer 17 is provided between the first semiconductor layer 11 and the first electrode 20. The first electrode 20 is in contact with the fourth semiconductor layer 17 and is electrically connected thereto, for example.

[0025] 2 is a schematic plan view showing the semiconductor device 1 according to the embodiment, and is a plan view showing the front surface 10F side of the semiconductor portion 10. As shown in FIG.

[0026] 2, a second electrode 30, a first control pad 70, a second control pad 80, a first wiring 75, and a second wiring 85 are provided on the front surface 10F of the semiconductor portion 10. The first control pad 70 and the second control pad 80 are spaced apart from each other and from the second electrode 30. The first control pad 70, the second control pad 80, the first wiring 75, and the second wiring 85 are provided on the front surface 10F of the semiconductor portion 10, for example, with a fourth insulating film 27 interposed therebetween.

[0027] The gate trench GT extends, for example, in the Y direction below the second electrode 30. The control electrode 40, the third electrode 50, and the fourth electrode 60 each extend continuously in the gate trench GT, for example, in the Y direction.

[0028] The first control pad 70 is electrically connected to the control electrode 40 via a first wiring 75 (see FIG. 3(b)). The second control pad 80 is electrically connected to the third electrode 50 and the fourth electrode 60 via a second wiring 85 (see FIG. 4(b)). The first control pad 70 and the first wiring 75 are electrically insulated from the second control pad 80 and the second wiring 85.

[0029] 3(a) and 3(b) are another schematic cross-sectional view showing the semiconductor device 1 according to the embodiment. Fig. 3(a) is a cross-sectional view showing the gate trench GT in the contact region CA shown in Fig. 2. Fig. 3(b) is a cross-sectional view taken along line AA shown in Fig. 3(a).

[0030] 3A, the first wiring 75 extends in a direction intersecting the gate trench GT on the fourth insulating film 27. The first wiring 75 is connected to the control electrode 40 via a contact hole CH1 provided in the fourth insulating film 27.

[0031] 3(b), the control electrode 40 and the third electrode 50 extend in the Y direction. At their respective ends, the control electrode 40 is connected to the first wiring 75, and the third electrode 50 is connected to the second wiring 85. The third electrode 50 is drawn out at the end of the gate trench GT to the same level as the surface 10F of the semiconductor portion 10, and the second wiring 85 is connected to the third electrode 50 via a contact hole CH2 provided in the fourth insulating film 27.

[0032] 4(a) and 4(b) are still other schematic cross-sectional views showing the semiconductor device according to the embodiment. Fig. 4(a) is the same cross-sectional view as the cross-sectional view of the gate trench GT shown in Fig. 3(a). Fig. 4(b) is a cross-sectional view taken along line BB shown in Fig. 4(a).

[0033] 4(b), the third electrode 50 is drawn out to the same level as the surface 10F of the semiconductor portion 10 at the end of the gate trench GT. The fourth electrode 60 is connected to the drawn-out portion 50e of the third electrode 50 at the end of the gate trench GT. The second wiring 85 is connected to the drawn-out portion 50e of the third electrode 50 via a contact hole CH2 provided in the fourth insulating film 27.

[0034] 5 is a time chart showing the operation of the semiconductor device 1 according to the embodiment. The horizontal axis represents time T, and the vertical axis represents gate voltages VG1, VG2, and VG3. Two control examples using the gate voltages VG1 to VG3 shown in FIG. 5 will be described below.

[0035] (First control example) A gate voltage VG1 is applied between the second electrode 30 and the first control pad 70. A gate voltage VG2 is applied between the second electrode 30 and the second control pad 80. The gate voltage VG1 is applied to the control electrode 40 via the first control pad 70. The gate voltage VG2 is applied to the third electrode 50 and the fourth electrode 60 via the second control pad 80. In this example, a gate voltage VG3 is not applied to any of the control electrode 40, the third electrode 50, or the fourth electrode 60.

[0036] As shown in FIG. 5, at time T1, the voltages of the control electrode 40, the third electrode 50, and the fourth electrode 60 are increased from, for example, −15 V to 15 V, which is higher than the threshold voltage. This induces an inversion layer of the first conductivity type at the interface between the second semiconductor layer 13 and the first insulating film 21, which faces the control electrode 40 and the fourth electrode 60, and the semiconductor device 1 transitions from the OFF state to the ON state (turns on). At time T2, which is after time T1, the voltage applied to the control electrode 40 is returned to −15 V, which is lower than the threshold voltage. Furthermore, at time T3, which is after time T1 and immediately before time T2, the voltages of the third electrode 50 and the fourth electrode 60 are returned to −15 V. This causes the inversion layer of the first conductivity type induced at the interface between the second semiconductor layer 13 and the first insulating film 21 to disappear.

[0037] The semiconductor device 1 transitions from the on state to the off state (turns off) at time T2 when the inversion layer induced at the interface between the second semiconductor layer 13 and the first insulating film 21 completely disappears. Meanwhile, at time T3 immediately before time T2, an inversion layer of the second conductivity type is induced at the interface between the first semiconductor layer 11 and the first insulating film 21, which faces the third electrode 50. This makes it possible to discharge holes in the first semiconductor layer 11 to the second electrode 30 via the second semiconductor layer 13 before the start of turn-off at time T2, thereby shortening the turn-off time. As a result, switching loss in the turn-off process of the semiconductor device 1 can be reduced.

[0038] Furthermore, in this example, the first semiconductor layer 11 and First insulating film 21 The same bias as that applied to the third electrode 50 is applied to the fourth electrode 60 so that holes move more smoothly from the inversion layer of the second conductivity type induced at the interface between the fourth electrode 60 and the third electrode 50 to the second semiconductor layer 13. This reduces the discharge resistance of holes caused by the avalanche phenomenon in the first semiconductor layer 11 facing the bottom of the gate trench GT, and also improves the avalanche resistance.

[0039] (Second control example) The semiconductor device 1 may be configured to independently control the third electrode 50 and the fourth electrode 60. That is, the fourth electrode 60 is not connected to the third electrode 50, but is electrically connected to a third control pad (not shown) separate from the first control pad 70 and the second control pad 80.

[0040] A gate voltage VG1 is applied to the control electrode 40 via a first control pad 70. A gate voltage VG2 is applied to the fourth electrode 60 via a third control pad (not shown). A gate voltage VG3 is applied to the third electrode 50 via a second control pad 80.

[0041] In this example, at time T1, the voltages of the control electrode 40 and the fourth electrode 60 are increased from −15 V to 15 V. At this time, the voltage of the third electrode 50 is 0 V. As a result, an inversion layer of the first conductivity type is induced between the second semiconductor layer 13 and the first insulating film 21, and the semiconductor device 1 transitions from an off state to an on state.

[0042] In the first control example, when the control electrode 40 and the fourth electrode 60 are turned on at time T1, the third electrode 50 has the same potential as the fourth electrode 60, and the potential rises from −15 V to 15 V during the turn-on operation. Therefore, when the third electrode 50 is at a negative potential, a p-type inversion layer is induced at the interface between the first semiconductor layer 11 and the first insulating film 21. As the potential of the third electrode 50 rises, the p-type inversion layer disappears, and the potential eventually becomes positive, forming an n-type accumulation layer. In contrast, in the second control example, the voltage of the third electrode 50 is 0 V, and neither a p-type inversion layer nor an n-type accumulation layer is induced. This stabilizes the flow of carriers through the first semiconductor layer 11 near the first insulating film 21, resulting in stable turn-on characteristics.

[0043] Next, at time T2, the gate voltage VG1 is reduced from 15V to -15V, thereby initiating the turn-off process. Furthermore, at time T3, immediately before time T2, the gate voltage VG2 is reduced from 15V to -15V, and the gate voltage VG3 is reduced from 0V to -15V. This induces a p-type inversion layer at the interface between the first semiconductor layer 11 and the first insulating film 21, facilitating the discharge of holes. As a result, the switching loss during the turn-off process of the semiconductor device 1 can be reduced.

[0044] In the embodiment, the third electrode 50 is provided at the bottom of each of the gate trenches GT, and therefore the electric field at the bottom of each gate trench GT is made uniform. This makes it possible to avoid element breakdown caused by localized avalanche current concentration due to non-uniformity of the electric field between the bottoms of the trench gates GT.

[0045] Next, a method for manufacturing the semiconductor device 1 will be described with reference to Figures 6(a) to 8(c). Figures 6(a) to 8(c) are schematic cross-sectional views showing the manufacturing process of the semiconductor device 1 according to the embodiment. Figures 6(a) to 8(c) show a method for forming the control electrode 40, the third electrode 50, and the fourth electrode 60 in the gate trench GT.

[0046] 6(a), a gate trench GT is formed on the front surface 100F side of the semiconductor wafer 100. The semiconductor wafer 100 is, for example, n-type silicon. The gate trench GT is formed by selectively removing the gate trench GT by, for example, anisotropic reactive ion etching (RIE) using an etching mask (not shown).

[0047] 6(b), a first insulating film 21 is formed to cover the inner surface of the gate trench GT. The first insulating film 21 is, for example, a silicon oxide film. The first insulating film 21 is formed by thermally oxidizing the semiconductor wafer 100.

[0048] As shown in FIG. 6(c), a conductive film 103 is formed on the first insulating film 21. The conductive film 103 is formed so as to fill the gate trench GT. The conductive film 103 is, for example, a polysilicon film having conductivity. The conductive film 103 is formed by, for example, CVD (Chemical Vapor Deposition).

[0049] As shown in FIG. 7(a), the conductive film 103 is removed, leaving a portion formed at the bottom of the gate trench GT. A first space SP1 is formed above the gate trench GT. The conductive film 103 is removed by, for example, isotropic dry etching. The portion of the conductive film 103 left at the bottom of the gate trench GT becomes the third electrode 50.

[0050] 7(b), in the first space SP1, a second insulating film 23 is formed on the third electrode 50. The second insulating film 23 is, for example, a silicon oxide film. The second insulating film 23 is formed by, for example, thermally oxidizing the third electrode 50.

[0051] As shown in FIG. 7(c), a conductive film 105 is formed to cover the inner surface of the first space SP1. The conductive film 105 is formed inside the gate trench GT, leaving the second space SP2. The conductive film 105 is, for example, a polysilicon film having conductivity. The conductive film 105 is formed using, for example, CVD.

[0052] 8(a), the portion of the conductive film 105 formed on the inner wall of the gate trench GT is left, and the portion formed on the second insulating film 23 is removed. The conductive film 105 is removed through the second space SP2 by, for example, anisotropic RIE.

[0053] 8(b), the third insulating film 25 is formed so as to fill the second space SP2. The third insulating film 25 is, for example, a silicon oxide film. The third insulating film 25 is formed by using, for example, CVD.

[0054] 8(c), the third insulating film 25 and the conductive film 105 are removed, leaving portions of the conductive film 105 formed inside the gate trench GT. The third insulating film 25 and the conductive film 105 are removed by, for example, isotropic dry etching or CMP (Chemical Mechanical Polishing). The portions of the conductive film 105 formed inside the gate trench GT become the control electrode 40 and the fourth electrode 60.

[0055] The above manufacturing method is merely an example, and the embodiment is not limited thereto. For example, the conductive film 105 shown in FIG. 7(c) may be formed to fill the first space SP1 in the gate trench GT. Then, the second space SP2 may be formed by selective etching using an etching mask.

[0056] 9(a) and 9(b) are schematic cross-sectional views showing semiconductor devices 2 and 3 according to a first modification of the embodiment.

[0057] 9(a), in two adjacent gate trenches GT1 and GT2, two fourth electrodes 60 are provided to face each other with the second semiconductor layer 13 interposed therebetween. Alternatively, two control electrodes 40 may be configured to face each other with the second semiconductor layer 13 interposed therebetween. In this way, the positional relationship between the control electrode 40 and the fourth electrode 60 in the X direction can be selected as appropriate.

[0058] In the semiconductor device 3 shown in Figure 9(b), the third semiconductor layer 15 is arranged to face the control electrode 40 via the first insulating film 21, and no other third semiconductor layer 15 (see Figure 1) is arranged to face the fourth electrode 60 via the first insulating film.

[0059] Fig. 10 is a schematic plan view showing a semiconductor device 4 according to a second modified example of the embodiment. Fig. 10 is a plan view showing the front surface 10F side of the semiconductor portion 10. Note that the second electrode 30 is omitted in Fig. 10.

[0060] 10, a plurality of control electrodes 40 and a plurality of fourth electrodes 60 may be arranged in one gate trench GT. In the gate trench GT, the control electrodes 40 and the fourth electrodes 60 are arranged alternately in the Y direction. In addition, in the X direction, the control electrodes 40 are arranged to face the fourth electrodes 60 in some regions, and the fourth electrodes 60 are arranged to face each other in other regions. The third electrodes 50 extend continuously in the Y direction in the lower part of the gate trench GT.

[0061] Furthermore, the first wiring 75 extends in the X direction and is connected to the control electrode 40 via a contact hole CH1. The second wiring 85 also extends in the X direction and is connected to the fourth electrode 60 via a contact hole CH2. In this case, the first wiring 75 and the second wiring 85 are interlayer wirings provided between the semiconductor portion 10 and the second electrode 30.

[0062] 11 is a schematic cross-sectional view showing a semiconductor device 5 according to a third modification of the embodiment. In the semiconductor device 5, a third gate trench GT3 is provided between the gate trench GT1 and the gate trench GT2 adjacent to each other.

[0063] Provided inside the gate trenches GT1 and GT2 are a control electrode 40, a third electrode 50, and a fourth electrode 60. On the other hand, a fifth electrode 90 is provided inside the gate trench GT3.

[0064] The gate trench GT3 extends from the front surface 10F side of the semiconductor portion 10 into the first semiconductor layer 11. The fifth electrode 90 faces the first semiconductor layer 11 with a fifth insulating film 29 interposed therebetween. The fifth electrode 90 is also provided to face the second semiconductor layer 13 with the fifth insulating film 29 interposed therebetween. The fifth electrode 90 is made of, for example, conductive polysilicon. The fifth electrode 90 may be electrically connected to the second electrode 30, or may be controlled independently of the other electrodes.

[0065] It should be noted that the manufacturing method according to the embodiment is not limited to this example. In the semiconductor device 5, at least one gate trench GT3 is provided between the gate trench GT1 and the gate trench GT2.

[0066] 12(a) and 12(b) are schematic cross-sectional views showing semiconductor devices 6 and 7 according to a fourth modification of the embodiment. As shown in Figs. 12(a) and 12(b), in this example, the fourth electrode 60 is not provided.

[0067] 12(a), the gate trench GT includes a control electrode 40 and a third electrode 50. The control electrode 40 is provided between the second electrode 30 and the third electrode 50. The third electrode 50 has an extension portion 50f that extends between the control electrode 40 and the second semiconductor layer 13. The extension portions 50f of the control electrode 40 and the third electrode 50 are aligned, for example, in the X direction.

[0068] The control electrode 40 faces the third electrode 50 via the second insulating film 23, and is electrically insulated from the third electrode 50 by the second insulating film 23. The control electrode 40 and the third electrode 50 are also electrically insulated from the semiconductor portion 10 by the first insulating film 21. The extending portion 50f of the third electrode 50 faces the second semiconductor layer 13 via the first insulating film 21.

[0069] 12(b), in two adjacent gate trenches GT1 and GT2, the extensions 50f of the two third electrodes 50 are provided to face each other with the second semiconductor layer 13 interposed therebetween. Alternatively, the two control electrodes 40 may be configured to face each other with the second semiconductor layer 13 interposed therebetween.

[0070] In the semiconductor devices 6 and 7, too, an inversion layer of the second conductivity type can be induced at the interface between the first semiconductor layer 11 and the first insulating film 21 facing the third electrode 50, facilitating the discharge of holes from the first semiconductor layer 11 to the second electrode 30. Furthermore, the extension 50f of the third electrode 50 extending between the control electrode 40 and the second semiconductor layer 13 connects the inversion layer of the second conductivity type to the second semiconductor layer 13, facilitating the discharge of holes. This further improves the avalanche resistance. The semiconductor devices 6 and 7 may be configured to further include a fifth electrode 90 (see FIG. 11).

[0071] 13(a) to 14(c) are schematic cross-sectional views showing a manufacturing process of a semiconductor device 6 according to a fourth modified example of the embodiment. Fig. 13(a) to Fig. 14(c) show a method for forming the control electrode 40 and the third electrode 50 in the gate trench GT.

[0072] As shown in Fig. 13(a), a conductive film 103 is formed on the first insulating film 21. The conductive film 103 is formed so as to fill the gate trench GT (see Figs. 6(a) to 6(c)).

[0073] 13(b), the conductive film 103 is removed, leaving a portion formed inside the gate trench GT. The conductive film 103 is removed by, for example, isotropic dry etching or CMP.

[0074] 13(c), an etching mask EM1 is formed on the front surface 100F of the semiconductor wafer 100, and a portion of the conductive film 103 in the gate trench GT is selectively removed. This allows a third space SP3 to be formed in the gate trench GT, and also allows a third electrode 50 to be formed. In this process, a portion of the first insulating film 21 may be removed.

[0075] 14(a), the third electrode 50 is thermally oxidized to form the second insulating film 23. The exposed portion of the semiconductor wafer 100 is also thermally oxidized to form the sixth insulating film 31. The sixth insulating film 31 is, for example, a silicon oxide film, and is connected to and integrated with the first insulating film 21.

[0076] 14(b), a conductive film 107 is formed on the front surface 100F of the semiconductor wafer 100. The conductive film 107 is, for example, a conductive polysilicon film, and is formed by CVD. The conductive film 107 is formed so as to fill the third space SP3.

[0077] As shown in FIG. 14(c), the portions of the conductive film 107 formed on the surface of the semiconductor wafer 100 and on the gate trench GT are removed. As a result, the control electrode 40 is formed inside the third space SP3 (see FIG. 14(a)). The conductive film 107 is partially removed by, for example, isotropic dry etching or CMP. At this time, a portion of the first insulating film 21 and a portion of the second insulating film 23 may also be removed, exposing the surface 100F of the semiconductor wafer 100 and the upper surfaces of the control electrode 40 and the third electrode 50.

[0078] 15(a) to 15(d) are schematic cross-sectional views showing semiconductor devices 8a, 8b, and 9a according to a fifth modified example of the embodiment. 15(a) to 15(d) are plan views showing the front surface 10F side of the semiconductor portion 10. Note that the fourth electrode 60 shown in 15(a) to 15(d) may be the extension 50f of the third electrode 50 (see FIG. 12).

[0079] 15(a) and 15(b), a plurality of control electrodes 40 are spaced apart in the Y direction. The fourth electrode 60 includes, for example, a first portion 60a and a second portion 60b. The first portion 60a is located between two control electrodes 40 adjacent to each other in the Y direction. The second portion 60b of the fourth electrode 60 extends, for example, in the Y direction and is arranged to be aligned with the control electrode 40 in the X direction. The second portion 60b is arranged to extend from the first portion 60a in the Y direction or the opposite direction. The first portion 60a is arranged on the surface 10F of the semiconductor portion 10 so as to face the second semiconductor layer 13 with the first insulating film 21 interposed therebetween.

[0080] In the semiconductor device 8a shown in FIG. 15(a), the third semiconductor layer 15 is provided to face the control electrode 40 with the first insulating film 21 interposed therebetween. Another third semiconductor layer 15 is provided to face the second portion 60b of the fourth electrode 60 with the first insulating film interposed therebetween. The third semiconductor layer 15 and the other third semiconductor layer 15 are aligned in the X direction, with the control electrode 40 and the second portion 60b of the fourth electrode 60 aligned therebetween. The third semiconductor layer 15 is provided so as not to face the first portion 60a of the fourth electrode 60.

[0081] In the semiconductor device 8b shown in Figure 15(b), the third semiconductor layer 15 is arranged to face the control electrode 40 with the first insulating film 21 interposed therebetween, but is not arranged in a position facing the fourth electrode 60 with the first insulating film 21 interposed therebetween.

[0082] 15(c) and (d), the second portion 60b of the fourth electrode 60 and the control electrode 40 are arranged side by side in the Y direction, with the first portion 60a of the fourth electrode 60 sandwiched between them. The second portion 60b of the fourth electrode 60 and the control electrode 40 are also arranged side by side in the X direction. The second portion 60b is arranged to extend from the first portion 60a in the Y direction or the opposite direction. The first portion 60a is arranged on the surface 10F of the semiconductor portion 10 so as to face the second semiconductor layer 13 with the first insulating film 21 interposed therebetween.

[0083] In the semiconductor device 9a shown in FIG. 15(c), the third semiconductor layer 15 is provided to face the control electrode 40 with the first insulating film 21 interposed therebetween. Another third semiconductor layer 15 is provided to face the second portion 60b of the fourth electrode 60 with the first insulating film interposed therebetween. The third semiconductor layer 15 and another third semiconductor layer 15 are aligned in the X direction, with the control electrode 40 and the second portion 60b of the fourth electrode 60 aligned therebetween. The third semiconductor layer 15 is provided so as not to face the first portion 60a of the fourth electrode 60.

[0084] In the semiconductor device 9b shown in Figure 15(d), the third semiconductor layer 15 is arranged to face the control electrode 40 with the first insulating film 21 interposed therebetween, but is not arranged in a position facing the fourth electrode 60 with the first insulating film 21 interposed therebetween.

[0085] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims.

[0086] (Appendix 1) A semiconductor part; a first electrode provided on a rear surface of the semiconductor portion; a second electrode provided on a surface of the semiconductor portion opposite to the back surface; a third electrode provided between the first electrode and the second electrode and positioned in the semiconductor portion, the third electrode being electrically insulated from the semiconductor portion by a first insulating film; a control electrode extending from the front surface side of the semiconductor portion into the semiconductor portion, being located between the second electrode and the third electrode, and facing the third electrode via a second insulating film, wherein the first insulating film extends between the semiconductor portion and the control electrode and electrically insulates the control electrode from the semiconductor portion; a fourth electrode extending from the front surface side of the semiconductor portion into the semiconductor portion, being located between the second electrode and the third electrode, and being located between the semiconductor portion and the control electrode, wherein the first insulating film extends between the semiconductor portion and the fourth electrode, the second insulating film extends between the third electrode and the fourth electrode, and the fourth electrode faces the control electrode via a third insulating film and is electrically connected to the third electrode; A semiconductor device comprising: (Appendix 2) A semiconductor part; a first electrode provided on a rear surface of the semiconductor portion; a second electrode provided on a surface of the semiconductor portion opposite to the back surface; a third electrode provided between the first electrode and the second electrode and positioned in the semiconductor portion, the third electrode being electrically insulated from the semiconductor portion by a first insulating film; a control electrode extending from the front surface side of the semiconductor portion into the semiconductor portion, being located between the second electrode and the third electrode, and facing the third electrode via a second insulating film, wherein the first insulating film extends between the semiconductor portion and the control electrode and electrically insulates the control electrode from the semiconductor portion; Equipped with a semiconductor device in which the third electrode includes an extension portion extending between the semiconductor portion and the control electrode, the first insulating film extends between the semiconductor portion and the extension portion, and the control electrode faces the extension portion via the second insulating film. (Appendix 3) 3. The semiconductor device according to claim 1, wherein the control electrode and the extension of the third electrode or the fourth electrode is electrically insulated from the second electrode by a fourth insulating film. (Appendix 4) the semiconductor portion includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, a third semiconductor layer of the first conductivity type, and a fourth semiconductor layer of the second conductivity type; the first semiconductor layer extends between the first electrode and the second electrode, and the third electrode faces the first semiconductor layer via the first insulating film; the second semiconductor layer is provided between the first semiconductor layer and the second electrode, and faces the control electrode via the first insulating film; the third semiconductor layer is partially provided on the second semiconductor layer between the second semiconductor layer and the second electrode so as to be in contact with the first insulating film; 4. The semiconductor device according to claim 1, wherein the fourth semiconductor layer is provided between the first semiconductor layer and the first electrode. (Appendix 5) 5. The semiconductor device according to claim 4, wherein the third semiconductor layer faces the control electrode via the first insulating film. (Appendix 6) a fifth electrode extending from the front surface side of the semiconductor portion into the first semiconductor layer between the first electrode and the second electrode and electrically insulated from the semiconductor portion by a fifth insulating film; 6. The semiconductor device according to claim 4, wherein the second semiconductor layer and the third semiconductor layer are provided between the control electrode and the fifth electrode. (Appendix 7) 7. The semiconductor device according to claim 6, wherein the fifth electrode is electrically connected to the second electrode. (Appendix 8) a first control pad provided on the front surface side of the semiconductor layer, spaced apart from the second electrode, and electrically connected to the control electrode via a first wiring; a second control pad provided on the front surface side of the semiconductor layer, spaced apart from the second electrode and the first control pad, and electrically connected to the third electrode via a second wiring; 8. The semiconductor device according to claim 1, further comprising: (Appendix 9) a second third electrode provided between the first electrode and the second electrode and located in the semiconductor portion, the second third electrode being electrically insulated from the semiconductor portion by a second first insulating film; a second control electrode extending from the front surface side of the semiconductor portion into the semiconductor portion, being located between the second electrode and the third electrode, and facing the second third electrode via a second second insulating film, wherein the second first insulating film extends between the semiconductor portion and the second control electrode and electrically insulates the second control electrode from the semiconductor portion; a second fourth electrode extending from the front surface side of the semiconductor portion into the semiconductor portion, being located between the second electrode and the third electrode, and being located between the semiconductor portion and the second control electrode, wherein the second first insulating film extends between the semiconductor portion and the second fourth electrode, the second second insulating film extends between the second third electrode and the second fourth electrode, and the second fourth electrode faces the second control electrode via the second third insulating film and is electrically connected to the second third electrode; Furthermore, 2. The semiconductor device according to claim 1, wherein the second fourth electrode faces the fourth electrode via the semiconductor portion. (Appendix 10) a second third electrode provided between the first electrode and the second electrode and located in the semiconductor portion, the second third electrode being electrically insulated from the semiconductor portion by a second first insulating film; a second control electrode extending from the front surface side of the semiconductor portion into the semiconductor portion, being located between the second electrode and the third electrode, and facing the second third electrode via a second second insulating film, wherein the second first insulating film extends between the semiconductor portion and the second control electrode and electrically insulates the second control electrode from the semiconductor portion; a second fourth electrode extending from the front surface side of the semiconductor portion into the semiconductor portion, being located between the second electrode and the third electrode, and being located between the semiconductor portion and the second control electrode, wherein the second first insulating film extends between the semiconductor portion and the second fourth electrode, the second second insulating film extends between the second third electrode and the second fourth electrode, and the second fourth electrode faces the second control electrode via the second third insulating film and is electrically connected to the second third electrode; Furthermore, 2. The semiconductor device according to claim 1, wherein the second control electrode faces the control electrode via the semiconductor portion. (Appendix 11) a second third electrode provided between the first electrode and the second electrode and located in the semiconductor portion, the second third electrode being electrically insulated from the semiconductor portion by a second first insulating film; a second control electrode extending from the front surface side of the semiconductor portion into the semiconductor portion, being located between the second electrode and the third electrode, and facing the third electrode via a second insulating film, wherein the second insulating film extends between the semiconductor portion and the second control electrode and electrically insulates the second control electrode from the semiconductor portion; Furthermore, the second third electrode includes a second extension portion extending between the semiconductor portion and the second control electrode, the second first insulating film extends between the semiconductor portion and the second extension portion, and the second control electrode faces the second extension portion via the second second insulating film; 3. The semiconductor device according to claim 2, wherein the second extension portion of the second third electrode faces the extension portion of the third electrode via the semiconductor portion. (Appendix 12) a second third electrode provided between the first electrode and the second electrode and located in the semiconductor portion, the second third electrode being electrically insulated from the semiconductor portion by a second first insulating film; a second control electrode extending from the front surface side of the semiconductor portion into the semiconductor portion, being located between the second electrode and the third electrode, and facing the third electrode via a second insulating film, wherein the second insulating film extends between the semiconductor portion and the second control electrode and electrically insulates the second control electrode from the semiconductor portion; Furthermore, the second third electrode includes a second extension portion extending between the semiconductor portion and the second control electrode, the second first insulating film extends between the semiconductor portion and the second extension portion, and the second control electrode faces the second extension portion via the second second insulating film; 3. The semiconductor device according to claim 2, wherein the second control electrode faces the control electrode via the semiconductor portion. (Appendix 13) In a plan view parallel to the surface of the semiconductor portion, the fourth electrode has a first portion and a second portion extending from the first portion, 11. The semiconductor device according to claim 1, wherein the second portion of the fourth electrode is aligned with the control electrode in a direction intersecting the extension direction of the fourth electrode. (Appendix 14) In a plan view parallel to the surface of the semiconductor portion, the extension portion of the third electrode has a first extension portion and a second extension portion extending from the first extension portion, 13. The semiconductor device according to claim 2, wherein the second extension portion is aligned with the control electrode in a direction intersecting the extension direction of the second extension portion. [Explanation of symbols]

[0087] 1 to 7...semiconductor device, 10...semiconductor portion, 10B...rear surface, 10F, 100F...front surface, 11...first semiconductor layer, 13...second semiconductor layer, 15...third semiconductor layer, 17...fourth semiconductor layer, 20...first electrode, 21...first insulating film, 23...second insulating film, 25...third insulating film, 27...fourth insulating film, 29...fifth insulating film, 31...sixth insulating film, 30...second electrode, 40...control electrode, 50...third electrode, 50e...drawing portion, 50f...extension portion, 60...fourth electrode, 60a...first portion, 60b...second portion, 70...first control pad, 75...first wiring, 80...second control pad, 85...second wiring, 90...fifth electrode, 100...semiconductor wafer, 103, 105, 107...conductive film, CA...contact area, CH1, CH2...contact hole, EM1...etching mask, GT, GT1, GT2, GT3...gate trench, SP1, SP2, SP3...space

Claims

1. A semiconductor part; a first electrode provided on a rear surface of the semiconductor portion; a second electrode provided on a surface of the semiconductor portion opposite to the back surface; a third electrode provided between the first electrode and the second electrode and positioned in the semiconductor portion, the third electrode being electrically insulated from the semiconductor portion by a first insulating film; a control electrode extending from the front surface side of the semiconductor portion into the semiconductor portion, being located between the second electrode and the third electrode, and facing the third electrode via a second insulating film, wherein the first insulating film extends between the semiconductor portion and the control electrode and electrically insulates the control electrode from the semiconductor portion; a fourth electrode extending from the front surface side of the semiconductor portion into the semiconductor portion, being located between the second electrode and the third electrode, and being located between the semiconductor portion and the control electrode, wherein the first insulating film extends between the semiconductor portion and the fourth electrode, the second insulating film extends between the third electrode and the fourth electrode, and the fourth electrode faces the control electrode via a third insulating film and is electrically connected to the third electrode; A semiconductor device comprising:

2. A semiconductor device as described in claim 1, further comprising wiring provided on the surface of the semiconductor portion, the wiring being electrically connected to the third electrode and the fourth electrode, and the end of the second insulating film being located below the wiring.

3. A semiconductor part; a first electrode provided on a rear surface of the semiconductor portion; a second electrode provided on a surface of the semiconductor portion opposite to the back surface; a third electrode provided between the first electrode and the second electrode and positioned in the semiconductor portion, the third electrode being electrically insulated from the semiconductor portion by a first insulating film; a control electrode extending from the front surface side of the semiconductor portion into the semiconductor portion, being located between the second electrode and the third electrode, and facing the third electrode via a second insulating film, wherein the first insulating film extends between the semiconductor portion and the control electrode and electrically insulates the control electrode from the semiconductor portion; a fourth electrode extending from the front surface side of the semiconductor portion into the semiconductor portion, being located between the second electrode and the third electrode, and being located between the semiconductor portion and the control electrode, wherein the first insulating film extends between the semiconductor portion and the fourth electrode, the second insulating film extends between the third electrode and the fourth electrode, the fourth electrode faces the control electrode via a third insulating film, and is electrically insulated from the control electrode and the third electrode; A semiconductor device comprising:

4. A semiconductor part; a first electrode provided on a rear surface of the semiconductor portion; a second electrode provided on a surface of the semiconductor portion opposite to the back surface; a third electrode provided between the first electrode and the second electrode and positioned in the semiconductor portion, the third electrode being electrically insulated from the semiconductor portion by a first insulating film; a control electrode extending from the front surface side of the semiconductor portion into the semiconductor portion, being located between the second electrode and the third electrode, and facing the third electrode via a second insulating film, wherein the first insulating film extends between the semiconductor portion and the control electrode and electrically insulates the control electrode from the semiconductor portion; Equipped with the third electrode includes an extension portion extending between the semiconductor portion and the control electrode, the first insulating film extends between the semiconductor portion and the extension portion, and the control electrode faces the extension portion via the second insulating film; In a plan view parallel to the surface of the semiconductor portion, the extension portion of the third electrode has a first extension portion and a second extension portion extending from the first extension portion, the second extending portion is aligned with the control electrode in a direction intersecting the extending direction of the second extending portion, The semiconductor device, wherein the second extension portion and the control electrode are arranged side by side in the extension direction with the first extension portion interposed therebetween.

5. The semiconductor device according to claim 4 , wherein the control electrode and the extension of the third electrode are electrically insulated from the second electrode by a fourth insulating film.

6. the semiconductor portion includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, a third semiconductor layer of the first conductivity type, and a fourth semiconductor layer of the second conductivity type; the first semiconductor layer extends between the first electrode and the second electrode, and the third electrode faces the first semiconductor layer via the first insulating film; the second semiconductor layer is provided between the first semiconductor layer and the second electrode, and faces the control electrode via the first insulating film; the third semiconductor layer is partially provided on the second semiconductor layer between the second semiconductor layer and the second electrode so as to be in contact with the first insulating film; The semiconductor device according to claim 1 , wherein the fourth semiconductor layer is provided between the first semiconductor layer and the first electrode.

7. The semiconductor device according to claim 6 , wherein the third semiconductor layer faces the control electrode via the first insulating film.

8. a fifth electrode extending from the front surface side of the semiconductor portion into the first semiconductor layer between the first electrode and the second electrode and electrically insulated from the semiconductor portion by a fifth insulating film; The semiconductor device according to claim 6 , wherein the second semiconductor layer and the third semiconductor layer are provided between the control electrode and the fifth electrode.

9. The semiconductor device according to claim 8 , wherein the fifth electrode is electrically connected to the second electrode.

10. A first control pad provided on the surface side of the semiconductor portion, spaced apart from the second electrode, and electrically connected to the control electrode via a first wiring; a second control pad provided on the front surface side of the semiconductor portion, spaced apart from the second electrode and the first control pad, and electrically connected to the third electrode via a second wiring; The semiconductor device according to claim 1 , further comprising:

11. a second third electrode provided between the first electrode and the second electrode and positioned in the semiconductor portion, the second third electrode being electrically insulated from the semiconductor portion by a second first insulating film; a second control electrode extending from the front surface side of the semiconductor portion into the semiconductor portion, being located between the second electrode and the second third electrode, and facing the second third electrode via a second second insulating film, wherein the second first insulating film extends between the semiconductor portion and the second control electrode and electrically insulates the second control electrode from the semiconductor portion; a second fourth electrode extending from the front surface side of the semiconductor portion into the semiconductor portion, and positioned between the second electrode and the second third electrode, and positioned between the semiconductor portion and the second control electrode, wherein the second first insulating film extends between the semiconductor portion and the second fourth electrode, the second second insulating film extends between the second third electrode and the second fourth electrode, and the second fourth electrode faces the second control electrode via the second third insulating film and is electrically connected to the second third electrode; Furthermore, The semiconductor device according to claim 1 , wherein the second fourth electrode faces the fourth electrode via the semiconductor portion.

12. a second third electrode provided between the first electrode and the second electrode and positioned in the semiconductor portion, the second third electrode being electrically insulated from the semiconductor portion by a second first insulating film; a second control electrode extending from the front surface side of the semiconductor portion into the semiconductor portion, being located between the second electrode and the second third electrode, and facing the second third electrode via a second second insulating film, wherein the second first insulating film extends between the semiconductor portion and the second control electrode and electrically insulates the second control electrode from the semiconductor portion; a second fourth electrode extending from the front surface side of the semiconductor portion into the semiconductor portion, and positioned between the second electrode and the second third electrode, and positioned between the semiconductor portion and the second control electrode, wherein the second first insulating film extends between the semiconductor portion and the second fourth electrode, the second second insulating film extends between the second third electrode and the second fourth electrode, and the second fourth electrode faces the second control electrode via the second third insulating film and is electrically connected to the second third electrode; Furthermore, The semiconductor device according to claim 1 , wherein the second control electrode faces the control electrode via the semiconductor portion.

13. a second third electrode provided between the first electrode and the second electrode and positioned in the semiconductor portion, the second third electrode being electrically insulated from the semiconductor portion by a second first insulating film; a second control electrode extending from the front surface side of the semiconductor portion into the semiconductor portion, being located between the second electrode and the second third electrode, and facing the second third electrode via a second second insulating film, wherein the second first insulating film extends between the semiconductor portion and the second control electrode and electrically insulates the second control electrode from the semiconductor portion; Furthermore, the second third electrode includes a second extension portion extending between the semiconductor portion and the second control electrode, the second first insulating film extends between the semiconductor portion and the second extension portion, and the second control electrode faces the second extension portion via the second second insulating film; The semiconductor device according to claim 4 , wherein the second extension portion of the second third electrode faces the extension portion of the third electrode via the semiconductor portion.

14. a second third electrode provided between the first electrode and the second electrode and positioned in the semiconductor portion, the second third electrode being electrically insulated from the semiconductor portion by a second first insulating film; a second control electrode extending from the front surface side of the semiconductor portion into the semiconductor portion, being located between the second electrode and the second third electrode, and facing the second third electrode via a second second insulating film, wherein the second first insulating film extends between the semiconductor portion and the second control electrode and electrically insulates the second control electrode from the semiconductor portion; Furthermore, the second third electrode includes a second extension portion extending between the semiconductor portion and the second control electrode, the second first insulating film extends between the semiconductor portion and the second extension portion, and the second control electrode faces the second extension portion via the second second insulating film; The semiconductor device according to claim 4 , wherein the second control electrode faces the control electrode via the semiconductor portion.

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