Electro-optical device, electronic device, and driving method

Abstract

To provide an electro-optical device capable of minimizing motion picture blur.SOLUTION: An electro-optical device 15 includes plural digital scan lines, s digital signal line, and plural pixel circuits 30. Each of the pixel circuits 30 is connected onto a digital scan line out of the plural digital scan lines and to the digital signal line. Each of the pixel circuits 30 includes a light emitting element and digital drive circuit. The digital drive circuit performs digital driving of allowing display data to be written from the digital signal line when the digital drive circuit is selected by means of the digital scan line, and supplying a drive current to the light emitting element during an ON period whose length depends on a gray-scale value of the display data. A field that is a period during which one image is formed includes an entire pixel extinguishment period during which the plural pixel circuits 30 extinguish the light emitting elements and a digital drive period during which the digital drive circuits perform digital driving subsequently to the entire pixel extinguishment period.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to an electro-optical device, an electronic device, a driving method, and the like. [Background technology]

[0002] Patent Documents 1 and 2 disclose a method for displaying grayscales as a time average in a display device using light-emitting elements in pixels by causing the pixels to emit light for a time period weighted according to each bit of display data. Patent Documents 1 and 2 also disclose a method for selecting multiple scanning lines one by one from the top, writing a first bit to the pixels connected to each scanning line, and then similarly selecting multiple scanning lines one by one from the top, writing a second bit to the pixels connected to each scanning line, and continuing this process up to the MSB. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2019-132941 [Patent Document 2] Japanese Patent Application Laid-Open No. 2008-281827 Summary of the Invention [Problem to be solved by the invention]

[0004] In the driving methods of Patent Documents 1 and 2, the timing of switching from displaying the previous frame to displaying the next frame differs for each scanning line. For example, when the first bit of display data for the second frame is written to pixels connected to the first scanning line, pixels connected to the second and subsequent scanning lines are displaying display data for the first frame, which precedes the second frame. Driving methods in which images of different frames are simultaneously displayed like this can cause video blur. For example, video blur may occur when a fast-moving video is displayed or when the user moves their head in an AR display on a head-mounted display. [Means for solving the problem]

[0005] One aspect of the present disclosure relates to an electro-optical device including a plurality of digital scanning lines, a digital signal line, and each pixel circuit including a digital scanning line included in the plurality of digital scanning lines and a plurality of pixel circuits connected to the digital signal line, each pixel circuit including a light-emitting element and a digital drive circuit that, when selected by the digital scanning line, writes display data from the digital signal line and performs digital driving to supply a drive current to the light-emitting element during an on period having a length corresponding to a gradation value of the display data, and a field, which is a period that constitutes one image, includes an all-pixel off period during which the plurality of pixel circuits turn off the light-emitting elements, and a digital drive period after the all-pixel off period during which the digital drive circuit performs the digital driving.

[0006] Another aspect of the present disclosure relates to an electronic device including the electro-optical device described above.

[0007] Yet another aspect of the present disclosure relates to a driving method for driving an electro-optical device including a plurality of digital scanning lines, digital signal lines, and a plurality of pixel circuits, the driving method comprising: turning off a light-emitting element included in each pixel circuit of the plurality of pixel circuits during an all-pixel-off period included in a field, which is a period that constitutes one image; digitally driving each of the pixel circuits during a digital driving period that is included in the field and that follows the all-pixel-off period; and in the digital driving, when each of the pixel circuits is selected by the digital scanning lines, display data is written from the digital signal lines, and a drive current is supplied to the light-emitting element during an on period having a length that corresponds to the gradation value of the display data. [Brief explanation of the drawings]

[0008] [Figure 1] 1 shows an example of a driving method for a conventional display device. [Figure 2] 1 shows a first configuration example of an electro-optical device and a display system. [Figure 3] 1 shows a first configuration example of a pixel circuit. [Figure 4] 5A and 5B are diagrams illustrating a driving method of an electro-optical device. [Figure 5] The first example of a driving technique. [Figure 6] The first example of a driving technique. [Figure 7] 10 shows an example of a signal waveform in a first configuration example of an electro-optical device. [Figure 8] 10 shows an example of a signal waveform in a first configuration example of an electro-optical device. [Figure 9] Second example of driving technique. [Figure 10] Second example of driving technique. [Figure 11] Third example of drive method. [Figure 12] Third example of drive method. [Figure 13] Fourth example of driving technique. [Figure 14] Fourth example of driving technique. [Figure 15] 10 shows a second configuration example of an electro-optical device and a display system. [Figure 16] 10 shows a second configuration example of a pixel circuit. [Figure 17] 1 shows a first example of an analog drive circuit configuration. [Figure 18] 10 shows an example of a signal waveform in a second configuration example of an electro-optical device. [Figure 19] 10 shows an example of a signal waveform in a second configuration example of an electro-optical device. [Figure 20] 10 shows a third configuration example of an electro-optical device and a display system. [Figure 21] 2 shows a second configuration example of an analog drive circuit. [Figure 22] 10 shows an example of a signal waveform in a third configuration example of an electro-optical device. [Figure 23] An example of the configuration of electronic devices. DETAILED DESCRIPTION OF THE INVENTION

[0009] Preferred embodiments of the present disclosure will be described in detail below. Note that the embodiments described below do not unduly limit the scope of the claims, and not all of the configurations described in the embodiments are necessarily essential components.

[0010] 1. Display device driving method Fig. 1 shows a driving method for a liquid crystal display device as an example of a driving method for a conventional display device. Here, an example is shown in which a panel conforming to the full high-definition standard is driven. In Fig. 1, lines 1 to 1080 indicate scanning lines.

[0011] In the driving method of a liquid crystal display device, the scan line driver selects line 1, and the data line driver writes a data voltage to the pixels of line 1. In Figure 1, the hatched area indicates the writing of the data voltage. Next, the scan line driver selects line 2, and the data line driver writes a data voltage to the pixels of line 2. This process is repeated up to line 1080 within one horizontal scanning period, and lines 1 to 1080 are driven in the same way in the next horizontal scanning period.

[0012] In this way, the data line driver writes data voltages sequentially to lines 1 to 1080, so when display of frame F2 begins on line 1, frame F1, which precedes frame F2, is being displayed on lines 2 to 1080. As soon as display of frame F2 begins on line 1080, the next horizontal scanning period begins and display of frame F3 begins on line 1. For this reason, the same frame F2 is displayed on all lines 1 to 1080 for only a short time during the horizontal scanning period.

[0013] For example, when a fast-moving object is displayed in a video, the display position of the object is different between frames F1 and F2. Therefore, the object appears blurred during the period when the display of frame F1 and the display of frame F2 are mixed. In this way, a driving method that displays a mixed frame has the problem of blurring the video when displaying a fast-moving video.

[0014] Furthermore, if the display is turned on only during the period in which the same frame is displayed in order to reduce moving image blur, it is difficult to ensure sufficient display brightness because the period is short.

[0015] Furthermore, because the driving method for LCD devices writes analog data voltages to pixels, sufficient writing time is required to accurately display gradations, making it difficult to shorten the writing time per line and ensure a sufficient period for displaying the same frame.

[0016] Furthermore, the above-mentioned Patent Documents 1 and 2 employ digital driving. In digital driving, display data is written to pixels one bit at a time, resulting in a bit "0" or "1" being written to each pixel. However, in the above-mentioned Patent Documents 1 and 2, multiple scan lines are selected one by one from the top, and bits are written to the pixels connected to each scan line. In other words, when the first bit of the second frame is written to the first scan line, the second and subsequent scan lines are already displaying the first frame, resulting in a mixed frame display. This can result in video blur, similar to the drive method for liquid crystal display devices.

[0017] 2. First Configuration Example of Electro-Optical Device and Display System 2 shows a first configuration example of an electro-optical device 15 and a display system 10 according to this embodiment. The display system 10 includes a display controller 60 and an electro-optical device 15. The electro-optical device 15 includes a circuit device 100 and a pixel array 20.

[0018] The display controller 60 outputs display data and controls display timing to the circuit device 100. The display controller 60 includes a display signal supply circuit 61 and a VRAM circuit 62.

[0019] The VRAM circuit 62 stores display data to be displayed on the pixel array 20. For example, when the VRAM circuit 62 stores image data for one image, it stores display data for each pixel of the pixel array 20.

[0020] The display signal supply circuit 61 generates control signals for controlling display timing. The control signals include, for example, a vertical synchronization signal, a horizontal synchronization signal, and a clock signal. The display signal supply circuit 61 reads display data from the VRAM circuit 62 in accordance with the display timing, and outputs the display data and control signals to the circuit device 100.

[0021] The electro-optical device 15 is a self-luminous display device equipped with light-emitting elements, such as an organic EL display device or a micro LED display device. The electro-optical device 15 is also called an electro-optical element, a display element, an electro-optical panel, a display panel, an electro-optical device, or a display device. The electro-optical device 15 includes a semiconductor substrate (not shown), on which a pixel array 20 and a circuit device 100 are formed. Alternatively, the pixel array 20 may be formed on a glass substrate, and the circuit device 100 may be configured as an integrated circuit device.

[0022] The circuit device 100 drives the pixel array 20 based on display data and control signals from the display controller 60, causing the pixel array 20 to display an image. The circuit device 100 includes a scanning line driving circuit 110, a digital signal line driving circuit 120, and a control line driving circuit 130.

[0023] The pixel array 20 includes a plurality of pixel circuits 30 arranged in a matrix of k rows and m columns, where k and m are integers equal to or greater than 2. The pixel array 20 also includes digital scan lines LDSC1 to LDSCk, enable signal lines LEN1 to LENk, digital signal lines LDDT1 to LDDTm, a power supply line LVD, and ground lines LVS1 and LVS2.

[0024] The digital scan line LDSC1 and the enable signal line LEN1 are connected to the pixel circuits 30 in the first row. The scan line drive circuit 110 outputs a digital selection signal DSC1 to the digital scan line LDSC1. The control line drive circuit 130 outputs an enable signal EN1 to the enable signal line LEN1. Similarly, the digital scan lines LDSC2 to LDSCk and the enable signal lines LEN2 to LENk are connected to the pixel circuits 30 in the second to k-th rows. The scan line drive circuit 110 outputs the digital selection signals DSC2 to DSCk to the digital scan lines LDSC2 to LDSCk. The control line drive circuit 130 outputs the enable signals EN2 to ENk to the enable signal lines LEN2 to LENk.

[0025] The digital signal line LDDT1 is connected to the pixel circuits 30 in the first column. The digital signal line drive circuit 120 outputs a digital data signal DDT1 to the digital signal line LDDT1. The digital data signal DDT1 is a signal of any one bit out of n bits of display data, where n is an integer equal to or greater than 2. Similarly, the digital signal lines LDDT2 to LDDTm are connected to the pixel circuits 30 in the second to m-th columns. The digital signal line drive circuit 120 outputs the digital data signals DDT2 to DDTm to the digital signal lines LDDT2 to LDDTm.

[0026] The power supply line LVD and ground lines LVS1 and LVS2 are connected to all pixel circuits 30. A power supply voltage VDD is supplied to the power supply line LVD from a power supply circuit (not shown). A first ground voltage VSS1 is supplied to the first ground line LVS1 from a power supply circuit (not shown), and a second ground voltage VSS2 is supplied to the second ground line LVS2 from a power supply circuit (not shown). The ground lines LVS1 and LVS2 may be a single common ground line.

[0027] 3 shows a first configuration example of a pixel circuit 30. The pixel circuit 30 includes a digital drive circuit 36, a light emitting element 31, and a transistor TENGL. Note that in FIG. 3, the 1 to k and 1 to m in DSC1 to DSCk, DDT1 to DDTm, etc. are omitted. For example, DSC is any one of DSC1 to DSCk.

[0028] The digital drive circuit 36 ​​receives the digital data signal DDT when the digital scan line LDSC is selected and stores the digital data signal DDT. When the digital data signal DDT is active, the digital drive circuit 36 ​​passes a drive current from the power supply line LVD to the node NDQ, and when the digital data signal DDT is inactive, the digital drive circuit 36 ​​cuts off the drive current. In the following, active is represented by a bit "0" or a low level, and inactive is represented by a bit "1" or a high level.

[0029] The transistor TENGL is a P-type transistor. The source of the transistor TENGL is connected to the node NDQ, the drain is connected to the node NENGL, and the gate is connected to the global enable signal line LENGL. Although not shown in FIG. 2, the global enable signal line LENGL is connected to all of the pixel circuits 30 in FIG. 2. The control line drive circuit 130 outputs the global enable signal ENGL to the global enable signal line LENGL. The transistor TENGL passes a drive current from the node NDQ to the node NENGL when the global enable signal ENGL is enabled, and cuts off the drive current when the global enable signal ENGL is disabled. In the following, enable is defined as bit "0" or low level, and disable is defined as bit "1" or high level.

[0030] The light-emitting element 31 is, for example, an OLED or a micro LED. OLED stands for Organic Light Emitting Diode, and LED stands for Light Emitting Diode. A micro LED is an inorganic LED integrated on a substrate. The anode of the light-emitting element 31 is connected to the node NENGL, and the cathode is connected to the second ground line LVS2. When the digital data signal DDT stored in the digital drive circuit 36 ​​is "0," a drive current flows through the light-emitting element 31, and the light-emitting element 31 emits light at a brightness corresponding to the current value of the drive current. When the digital data signal DDT stored in the digital drive circuit 36 ​​is "1," the light-emitting element 31 is turned off. The above applies when the transistor TENGL is on; when the transistor TENGL is off, the light-emitting element 31 is turned off. Note that, hereinafter, the light-emitting state of the light-emitting element 31 is also referred to as "on," and the light-off state of the light-emitting element 31 is also referred to as "off."

[0031] A detailed description will be given of the configuration of the digital drive circuit 36. The digital drive circuit 36 ​​includes a memory circuit 33 and P-type transistors TA, TB1, and TB2.

[0032] One of the source or drain of the P-type transistor TA is connected to the digital signal line LDDT, the other of the source or drain is connected to the input node NI of the memory circuit 33, and the gate is connected to the digital scanning line LDSC.

[0033] The source of P-type transistor TB2 is connected to the power supply line LVD, its drain is connected to the source of P-type transistor TB1, and its gate is connected to enable signal line LEN. The drain of P-type transistor TB1 is connected to node NDQ, and its gate is connected to output node NQ of memory circuit 33. P-type transistor TB1 is a drive transistor that is turned on or off based on output signal MCQ from memory circuit 33, and when on, outputs a drive current to node NDQ.

[0034] The memory circuit 33 is a memory cell that stores one bit of data. When the P-type transistor TA is on, the memory circuit 33 stores the digital data signal DDT input to the input node NI from the digital signal line LDDT, and outputs the stored signal to the output node NQ as the output signal MCQ. The memory circuit 33 includes P-type transistors TC1 and TC3 and N-type transistors TC2, TC4, and TC5.

[0035] P-type transistor TC1 and N-type transistor TC2 form a first inverter, and P-type transistor TC3 and N-type transistor TC4 form a second inverter. The first inverter and second inverter are supplied with a power supply voltage VDD and a first ground voltage VSS1. The input node of the first inverter is connected to an input node NI of the memory circuit 33, the output node NC of the first inverter is connected to an input node of the second inverter, and the output node of the second inverter is connected to an output node NQ of the memory circuit 33. One of the source or drain of the N-type transistor TC5 is connected to the input node NI, and the other of the source or drain is connected to the output node NQ.

[0036] Assume that transistor TENGL is on. When "0" is written to memory circuit 33, output signal MCQ is low level, and when "1" is written, output signal MCQ is high level. When output signal MCQ and enable signal EN of memory circuit 33 are low level, P-type transistors TB1 and TB2 are on, drive current ID flows to light-emitting element 31, and light-emitting element 31 emits light. When at least one of output signal MCQ of memory circuit 33 or enable signal EN is high level, at least one of P-type transistors TB1 or TB2 is off, drive current ID does not flow to light-emitting element 31, and light-emitting element 31 does not emit light.

[0037] The configuration of the digital drive circuit 36 ​​is not limited to that shown in FIG. 3. For example, a capacitor may be provided instead of the memory circuit 33, and the capacitor may hold the digital data signal DDT. Alternatively, the N-type transistor TC5 of the memory circuit 33 may be omitted, and the input node NI of the first inverter and the output node NQ of the second inverter may be directly connected. Alternatively, the ground lines LVS1 and LVS2 may be used as a common ground line, and a ground voltage may be supplied to the light-emitting element 31 and the memory circuit 33 from the common ground line.

[0038] 4 is a diagram illustrating a driving method for the electro-optical device 15 in this embodiment. FR1 is the first field, and FR2 is the second field following the first field FR1. Here, one field constitutes one frame. That is, a field is a period that constitutes one image, and more specifically, a period required to write display data corresponding to one image to all pixels of the electro-optical device 15.

[0039] Each field is divided into an all-pixel-off period Toff and a subsequent digital drive period TDD. That is, after the digital drive period TDD of the first field FR1 ends, the all-pixel-off period Toff of the second field FR2 is inserted, followed by the digital drive period TDD. During the all-pixel-off period Toff, also known as a black insertion period, the electro-optical device 15 turns off the light-emitting elements 31 of all pixels included in the pixel array 20. During the digital drive period TDD, digital driving is performed using the display data of that field. That is, the electro-optical device 15 displays the image of the first field FR1 in the first field FR1 and the image of the second field FR2 in the second field FR2. During one digital drive period TDD, the image of one field is displayed; images from multiple fields are not displayed together. This type of driving is also called frame sequential driving. A specific example of this driving method will be described with reference to Figure 5 and subsequent figures.

[0040] In the above-described embodiment, the electro-optical device 15 includes a plurality of digital scanning lines LDSC1 to LDSCk, a digital signal line LDDT, and a plurality of pixel circuits 30. The digital signal line LDDT is one of LDDT1 to LDDTk. Each pixel circuit 30 is connected to a digital scanning line LDSC included in the plurality of digital scanning lines LDSC1 to LDSCk and a digital signal line LDDT. The digital scanning line LDSC is one of LDSC1 to LDSCk. Each pixel circuit 30 includes a light-emitting element 31 and a digital drive circuit 36. When selected by the digital scanning line LDSC, display data is written to the digital drive circuit 36 ​​from the digital signal line LDDT, and the digital drive circuit 36 ​​supplies a drive current ID to the light-emitting element 31 during an on-period corresponding to the gradation value of the display data. This is called digital drive. A field, which is a period constituting one image, includes an all-pixel off period Toff during which the plurality of pixel circuits 30 turn off the light-emitting elements 31, and a digital drive period TDD after the all-pixel off period Toff during which the digital drive circuit 36 ​​performs digital drive.

[0041] Specifically, the field FR is divided into an all-pixel off period Toff and a digital drive period TDD after the all-pixel off period Toff. Specifically, the field FR is composed of the all-pixel off period Toff and the digital drive period TDD, but may also include other periods.

[0042] According to this embodiment, an image is displayed on the electro-optical device 15 during a digital drive period TDD, and an all-pixel-off period Toff is inserted between that digital drive period TDD and the next digital drive period TDD. As a result, the image display in one field and the image display in the next field are separated by the all-pixel-off period Toff, thereby reducing motion blur compared to the conventional drive method described in FIG. 1. Furthermore, a field is a period that constitutes one image, and one image in that field is displayed during the digital drive period TDD. As a result, images from different fields are not mixed together, and the images of each field are displayed separated in time, thereby reducing motion blur compared to the conventional drive method described in FIG. 1.

[0043] In this embodiment, the pixel circuits 30 perform digital driving based on display data of an image displayed in the first field FR1 during the digital driving period TDD of the first field FR1. The pixel circuits 30 perform digital driving based on display data of an image displayed in the second field FR2 during the digital driving period TDD of the second field FR2.

[0044] According to this embodiment, digital driving of each field is performed based on the display data of the image displayed in each field. As a result, the images of each field are displayed in the digital driving period of each field without being mixed together, which reduces motion blur compared to the conventional driving method described in FIG.

[0045] 3. First example of driving method 5 and 6 show a first example of a driving method in this embodiment. Here, an example will be described in which the total number of scanning lines included in the pixel array 20 is k=16 and the number of bits of the display data is n=4. The first to fourth bits are taken from the LSB side of the display data. Note that when simply referring to the first to sixteenth scanning lines, this refers to the pixel circuits in the first to sixteenth rows in the pixel array. The digital scanning lines connected to the pixel circuits in the first to sixteenth rows are referred to as the first to sixteenth digital scanning lines.

[0046] In Figures 5 and 6, the horizontal axis of the table represents the selection order, with one selection order corresponding to the selection of one digital scanning line. In other words, one selection order corresponds to one horizontal scanning period. Figures 5 and 6 show two rows of selection orders, with the first row representing the selection order throughout the field FR and the second row representing the selection order during the all-pixel off period Toff and the digital driving period TDD. Hereinafter, the length of one horizontal scanning period corresponding to one selection order will also be referred to as 1h. The vertical axis of the table represents the scanning line number, which runs from 1 to 16 in the vertical scanning direction.

[0047] The numbers in each cell in the table indicate the gradation value of each bit of the display data. That is, 1, 2, 4, and 8 represent the first, second, third, and fourth bits, respectively. Cells surrounded by dotted lines represent the scanning line selection period in digital driving. That is, a number surrounded by a dotted line indicates that the bit corresponding to that number is written to the pixel circuit connected to the selected digital scanning line. Cells that are not surrounded by a dotted line and are not hatched represent the display period in digital driving. Furthermore, hatched cells, both those surrounded by dotted lines and those not surrounded by dotted lines, represent periods during which the light-emitting element 31 of the pixel is turned off.

[0048] A driving method for the all-pixel off period Toff is shown in Fig. 5. The length of the all-pixel off period Toff is (k-1)h, and in the first example, the length of the all-pixel off period Toff is 15h.

[0049] The control line driving circuit 130 disables the global enable signal ENGL during the all-pixel-off period Toff, thereby turning off all pixels of the 1st to 16th scanning lines. Note that the control line driving circuit 130 may also turn off all pixels of the 1st to 16th scanning lines by disabling the enable signals EN1 to EN16 during the all-pixel-off period Toff. In that case, the global enable signal line LENGL may be omitted. In the following, it is assumed that all pixels are turned off using the global enable signal ENGL.

[0050] In selection order 1, the scanning line driving circuit 110 selects the first digital scanning line, and the digital signal line driving circuit 120 outputs the fourth bit of the display data as digital data signals DDT1 to DDTm, thereby writing the fourth bit of the display data to the digital driving circuits 36 of the pixels of the first scanning line.

[0051] Similarly, the scanning line driving circuit 110 selects the second to fifteenth digital scanning lines in selection orders 2 to 15. The digital signal line driving circuit 120 outputs the fourth bit of display data in selection orders 2 to 8, the third bit of display data in selection orders 9 to 12, the second bit of display data in selection orders 13 and 14, and the first bit of display data in selection order 15 as digital data signals DDT1 to DDTm. As a result, the fourth bit of display data is written to the digital driving circuits 36 for the pixels of the second to eighth scanning lines, the third bit of display data is written to the digital driving circuits 36 for the pixels of the ninth to twelfth scanning lines, the second bit of display data is written to the digital driving circuits 36 for the pixels of the thirteenth and fourteenth scanning lines, and the first bit of display data is written to the digital driving circuit 36 ​​for the pixel of the fifteenth scanning line.

[0052] As explained in Fig. 4, one image is displayed per field FR. The display data written to the digital drive circuit 36 ​​during the all-pixel-off period Toff is display data for the image displayed in field FR, and does not include display data for fields other than field FR.

[0053] 6 shows a driving method in the digital driving period TDD. In the first example, the length of the digital driving period TDD is 64h, and the length of the field FR is 15h+64h=79h. The calculation method for these will be described later. The selection orders 1 to 64 in the digital driving period TDD correspond to the selection orders 16 to 79 in the field FR. The following explanation will be given using the selection order in the digital driving period TDD.

[0054] First, the operation of one scan line will be described using the first scan line as an example. The fourth bit of display data is written to the digital drive circuit 36 ​​of the pixel on the first scan line during the all-pixel-off period Toff. In the selection orders 1 to 4 of the digital drive period TDD, the pixel circuit 30 turns on or off the light-emitting element 31 based on the fourth bit stored in the digital drive circuit 36.

[0055] Next, in selection order 5, the scanning line driving circuit 110 selects the first digital scanning line, and the digital signal line driving circuit 120 outputs the first bit of display data. This causes the first bit to be written to the digital driving circuit 36. In the subsequent selection orders 6 to 9, the pixel circuit 30 turns on or off the light-emitting element 31 based on the first bit held in the digital driving circuit 36.

[0056] Similarly, in selection orders 10, 19, and 36, the scanning line driving circuit 110 selects the first digital scanning line, and the digital signal line driving circuit 120 outputs the second, third, and fourth bits. As a result, the second, third, and fourth bits are written to the digital driving circuit 36 ​​in selection orders 10, 19, and 36. In the subsequent selection orders 11 to 18, 20 to 35, and 37 to 64, the pixel circuit 30 turns on or off the light-emitting element 31 based on the second, third, and fourth bits held in the digital driving circuit 36. Note that the fourth bit written to the digital driving circuit 36 ​​in selection order 36 is the same as the fourth bit written to the digital driving circuit 36 ​​in selection order 1 during the all-pixel off period Toff.

[0057] In the above, in the digital drive period TDD within one field, first to fourth scanning line selection periods and first to fourth display periods are provided corresponding to the first to fourth bits. For the first scanning line, the first to fourth scanning line selection periods are periods corresponding to the selection orders 5, 10, 19, and 36. The first to third display periods are periods corresponding to the selection orders 6 to 9, 11 to 18, and 20 to 35. The fourth display period is a period corresponding to the selection orders 1 to 4 and 37 to 64. The lengths of the first to fourth display periods are 4 hours, 8 hours, 16 hours, and 32 hours. Although which selection order corresponds to the scanning line selection period and display period differs for each scanning line, first to fourth scanning line selection periods and first to fourth display periods are provided for each scanning line.

[0058] Next, the operation when scanning 16 scanning lines will be described. The digital driving period TDD of field FR includes subfields SF1 to SF16 corresponding to the 16 scanning lines. When the length of the scanning line selection period is 1 hour, the length of each subfield is 4 hours corresponding to the 4-bit number of display data.

[0059] In each subfield, the scanning line driving circuit 110 selects a scanning line group to be selected from the first to sixteenth digital scanning lines. In FIG. 6, the scanning line group is four digital scanning lines, the same as the four bits of the display data. A first bit is written to the pixel circuit 30 connected to one of the four digital scanning lines, a second bit is written to the pixel circuit 30 connected to another digital scanning line, a third bit is written to the pixel circuit 30 connected to yet another digital scanning line, and a fourth bit is written to the pixel circuit 30 connected to yet another digital scanning line. For example, in subfield SF1, the scanning line group is the sixteenth, fifteenth, thirteenth, and ninth digital scanning lines, and the first, second, third, and fourth bits are written to the pixel circuits 30 connected to them, respectively.

[0060] The four digital scanning lines belonging to a scanning line group are selected in different selection orders. In subfield SF1 in Fig. 6, the 16th, 15th, 13th, and 9th digital scanning lines belonging to the scanning line group are selected in selection orders 1, 2, 3, and 4 in the digital driving period TDD.

[0061] As the subfield advances by one, the numbers of the digital scan lines belonging to the scan line group increase by one. That is, the selection order pattern in the subfield shifts by one scan line downward on the screen. This pattern shift is performed cyclically. That is, the selection order pattern for the 16th scan line in a certain subfield becomes the selection order pattern for the 1st scan line in the next subfield. For example, in subfield SF2, the scan line group consists of the 1st, 16th, 14th, and 10th digital scan lines, and the 1st, 2nd, 3rd, and 4th bits are written to the pixel circuits 30 connected to these lines, respectively. This is the same as the selection order pattern in subfield SF1 shifted cyclically downward by one scan line.

[0062] In subfield SF1, the first to fourth bits are written to the 16th, 15th, 13th, and 9th scan lines. In terms of the intervals between scan lines, the 15th scan line is one line before the 16th scan line, the 13th scan line is two lines before the 15th scan line, and the 9th scan line is four lines before the 13th scan line. In the next subfield SF2, the first bit is written to the first scan line, which is eight lines before the 9th scan line. This results in first to fourth display periods whose lengths are proportional to the grayscale values.

[0063] Specifically, we will focus on the display period for the 16th scanning line. First, in selection order 2, the second bit is written to the 15th scanning line, but this selection order pattern moves to the 16th scanning line one subfield later. The subfield length is 4h, and the first display period for the 16th scanning line begins with selection order 2, so the length of the first display period is 1 × 4h. Next, in selection order 7, the third bit is written to the 14th scanning line, but this selection order pattern moves to the 16th scanning line two subfields later. The second display period for the 16th scanning line begins with selection order 7, so the length of the second display period is 2 × 4h = 8h. Similarly, the length of the third display period is 4 × 4h, and the length of the fourth display period is 8 × 4h.

[0064] Since there are a total of 16 scan lines and 4 bits need to be written per scan line, the total number of scan line selections in the digital drive period TDD is 16 x 4 = 64. As explained in Figure 5, the length of the all-pixel off period Toff is 15 hours. Therefore, the length of the field FR explained in Figures 5 and 6 is 15 hours + 64 hours = 79 hours. The same 79-hour selection order pattern as in Figures 5 and 6 is repeated in subsequent frames. The exact formula for the total number of scan line selections will be described later.

[0065] In the first example above, the ratio of the digital drive period TDD to the field FR is 64h / 79h = 0.81. By performing frame sequential driving and ensuring a sufficient digital drive period TDD, which is the lighting period or display period, it is possible to reduce motion blur and achieve a high-brightness display at the same time.

[0066] 7 and 8 show examples of signal waveforms in the first configuration example of the electro-optical device 15. Note that the signal waveforms are shown in outline here, and the lengths of the periods do not necessarily correspond to the actual lengths.

[0067] FIG. 7 shows an example of a signal waveform on the 16th scan line in the first example of the driving method. During the all-pixel-off period Toff, the control line driving circuit 130 outputs a disable global enable signal ENGL. As a result, the transistors TENGL are turned off in all pixel circuits 30, and the light-emitting elements 31 are turned off. During the digital driving period TDD, the control line driving circuit 130 outputs an enable global enable signal ENGL. As a result, the transistors TENGL are turned on in all pixel circuits 30, and digital driving is enabled.

[0068] In the digital driving period TDD, the digital driving circuit 36 ​​performs digital driving. Here, an example will be described in which the first bit of the display data is DDT[0]=1, the second bit is DDT[1]=0, the third bit is DDT[2]=1, and the fourth bit is DDT[3]=0.

[0069] During the scan line selection period TS1, the digital selection signal DSC is at a low level. At this time, the P-type transistor TA of the digital drive circuit 36 ​​is on, and the N-type transistor TC5 is off. As a result, the first bit DDT[0]=1 is input to the memory circuit 33, and the memory circuit 33 outputs a high-level output signal MCQ. The enable signal EN is at a high level. As a result, the P-type transistors TB1 and TB2 are off, and the light-emitting element 31 is off.

[0070] During the display period TD1, the digital selection signal DSC is at a high level. At this time, the P-type transistor TA is off and the N-type transistor TC5 is on. As a result, the memory circuit 33 holds the first bit DDT[0]=1 and holds the output signal MCQ at a high level. The enable signal EN is at a low level. As a result, the P-type transistor TB1 is off and the P-type transistor TB2 is on, so the light-emitting element 31 is off.

[0071] In the scanning line selection period TS2 and the display period TD2, the pixel circuit 30 operates in the same manner as described above, but since DDT[1]=0, the light-emitting element 31 is on in the display period TD2, and a drive current flows to the light-emitting element 31. Similarly, since DDT[2]=1 and DDT[3]=0, the light-emitting element 31 is off and on in the display periods TD3 and TD4, and a drive current flows to the light-emitting element 31 in the display period TD4.

[0072] The length of display period TD2 is twice the length of display period TD1. Similarly, the lengths of display periods TD3 and TD4 are twice the lengths of display periods TD2 and TD3. In other words, the lengths of display periods TD1, TD2, TD3, and TD4 are proportional to the gradation values ​​1, 2, 4, and 8 of the first, second, third, and fourth bits.

[0073] 8 shows an example of signal waveforms of the digital selection signals DSC1 to DSC16 for the first to sixteenth scanning lines in the first example of the driving method. The following description will be given using the selection order in the digital driving period TDD.

[0074] The scanning line driving circuit 110 sets the digital selection signal DSC1 to low level in selection order 1. This causes writing to the digital driving circuit 36 ​​for the pixels of the first scanning line. Similarly, the digital selection signals DSC2 to DSC16 are set to low level in selection orders 2 to 16. This causes writing to the digital driving circuit 36 ​​for the pixels of the second to sixteenth scanning lines.

[0075] 5 and 6, selection orders 1 to 15 are the all-pixel off period Toff, and selection order 16 is the first selection order in the digital drive period TDD. Selection orders 16 to 79 correspond to selection orders 1 to 64 in the digital drive period TDD, and the digital drive described in FIG. 6 is performed.

[0076] In the above-described embodiment, the ith pixel circuit of the first to kth pixel circuits that are the plurality of pixel circuits 30 is connected to the ith digital scanning line LDSCi of the first to kth digital scanning lines LDSC1 to LDSCk that are the plurality of digital scanning lines. k is an integer of 2 or more, and i is an integer of 1 to k. The first to kth pixel circuits are pixel circuits 30 that are connected to any one digital signal line LDDT of the digital signal lines LDDT1 to LDDTm. During the all-pixel-off period Toff, the first to k-1st digital scanning lines LDSC1 to LDSCk-1 are sequentially selected, and display data of an image to be displayed in the field FR is written from the digital signal line LDDT to the first to k-1st pixel circuits. During the digital drive period TDD, the first to k-1st pixel circuits are digitally driven based on the display data written during the all-pixel-off period Toff.

[0077] In the first example of the driving method, k=16. As described in FIG. 5, during the all-pixel-off period Toff, the first to fifteenth digital scanning lines LDSC1 to LDSC15 are sequentially selected, and display data for the image displayed in the field FR is written from the digital signal line LDDT to the first to fifteenth pixel circuits. More specifically, of the first to fourth bits of the display data, the bits displayed in the first to fifteenth pixel circuits during the first scanning line selection period TDD of the field FR are written to the first to fifteenth pixel circuits during the all-pixel-off period Toff. For example, in FIG. 6, in selection order 1 of the digital driving period TDD, the fourth bit is displayed in the pixel circuits of the first to eighth scanning lines, the third bit is displayed in the pixel circuits of the ninth to twelfth scanning lines, the second bit is displayed in the pixel circuits of the thirteenth and fourteenth scanning lines, and the first bit is displayed in the pixel circuit of the fifteenth scanning line. At this time, as shown in FIG. 5, during the all-pixel-off period Toff, the fourth bit is written to the pixel circuits of the first to eighth scanning lines, the third bit is written to the pixel circuits of the ninth to twelfth scanning lines, the second bit is written to the pixel circuits of the thirteenth and fourteenth scanning lines, and the first bit is written to the pixel circuit of the fifteenth scanning line.

[0078] According to this embodiment, during the all-pixel-off period Toff, display data for the image to be displayed in that field FR can be written to the pixel circuit 30. As a result, during the digital drive period TDD of that field FR, digital driving is performed based on the display data for the image to be displayed in that field FR. As a result, images from each field are displayed during the digital drive period of each field without being mixed together, thereby reducing moving image blur compared to the conventional driving method described with reference to FIG.

[0079] In this embodiment, in the first scanning line selection period of the digital drive period TDD, the kth digital scanning line is selected and display data of the image to be displayed in the field FR is written from the digital signal line LDDT to the kth pixel circuit.

[0080] In the first example of the driving method, k=16. Of the first to fourth bits of the display data, the bit displayed in the 16th pixel circuit in the second scanning line selection period of the digital driving period TDD is written to the 16th pixel circuit in the first scanning line selection period of the digital driving period TDD. For example, in FIG. 6, in selection order 2 of the digital driving period TDD, the first bit is displayed in the pixel circuit of the 16th scanning line. At this time, in selection order 1 of the digital driving period TDD, the first bit is written to the pixel circuit of the 16th scanning line.

[0081] According to this embodiment, during the all-pixel-off period Toff and the first scanning line selection period of the digital drive period TDD, display data of an image to be displayed in the field FR is written to the 1st to kth pixel circuits. As a result, during the digital drive period TDD of the field FR, digital driving is performed based on the display data of the image to be displayed in the field FR.

[0082] In this embodiment, the digital driving period TDD of the field FR includes a plurality of subfields SF1 to SF16. The scanning line driving circuit 110 selects a scanning line group to be selected from the plurality of digital scanning lines LDSC1 to LDSCk once in a subfield included in the plurality of subfields SF1 to SF16.

[0083] In the aforementioned Patent Documents 1 and 2, multiple scan lines are selected one by one from top to bottom, and after a bit is written to a pixel connected to each scan line, a period in which no scan lines are selected occurs between the start of writing the next bit. Because the length of one frame is determined by the frame rate, the period in which scan lines are not selected poses a problem of increasing the scan line drive frequency. According to this embodiment, a group of scan lines to be selected is selected in each subfield. This reduces the non-scanning period in which scan lines are not selected, thereby enabling a lower scan line drive frequency compared to conventional methods. Lowering the scan line drive frequency reduces power consumption during scan line drive and enables reliable data writing to pixel circuits. Alternatively, considering the same scan line drive frequency as conventional methods, more scan lines can be selected in one frame. In other words, a higher-resolution electro-optical device can be driven without increasing the scan line drive frequency compared to conventional methods.

[0084] Furthermore, in this embodiment, the electro-optical device 15 includes a scanning line driving circuit 110 that drives a plurality of digital scanning lines LDSC1 to LDSCk. The digital driving period TDD includes first to nth scanning line selection periods in which the first to nth bits of display data are written to the pixel circuits 30, and first to nth display periods in which the light-emitting element 31 is turned on or off depending on the first to nth bits written to the pixel circuits 30. The on period is a display period in which the light-emitting element 31 is on among the first to nth display periods.

[0085] In the first example of the driving method, n=4, TS1 to TS4 correspond to the first to fourth scanning line selection periods, and TD1 to TD4 correspond to the first to fourth display periods. The second display period TD2 and the fourth display period TD4, during which the light emitting element 31 is on, are on periods whose lengths correspond to the gradation value of the display data.

[0086] According to this embodiment, during the digital drive period TDD, the light emitting element 31 emits light during an on period whose length corresponds to the gradation value of the display data. The time-averaged light emission luminance over one frame is determined by the proportion of the on period in one frame, and is therefore the luminance obtained by dividing the maximum luminance by the gradation value.

[0087] In this embodiment, the scanning line group includes a digital scanning line connected to a pixel circuit 30 to which the i-th bit is written in a subfield, and a digital scanning line connected to a pixel circuit 30 to which the j-th bit is written in a subfield, where i is an integer between 1 and n, and j is an integer between 1 and n but different from i.

[0088] For example, if i=1 and j=2, in subfield SF1 in Fig. 6, the first bit is written to the 16th scan line and the second bit is written to the 15th scan line. That is, the scan line group in subfield SF1 includes the 16th scan line and the 15th scan line.

[0089] According to this embodiment, in one subfield, the i-th bit is written to one scanning line and the j-th bit is written to another scanning line, which reduces the non-scanning period during which no scanning lines are selected, and allows for a lower scanning line drive frequency than conventional methods.

[0090] Here, the multiple subfields SF1 to SF16 are subfields included in the digital drive period TDD of the field FR. Specifically, the multiple subfields are obtained by dividing the digital drive period TDD of the field FR into multiple periods. The multiple digital scanning lines are used to form a scanning line selection sequence pattern, and the number of lines is not limited to the number of scanning lines actually present in the electro-optical device. In FIG. 6, the scanning line selection sequence pattern is formed by 16 scanning lines. The number of scanning lines actually present in the electro-optical device may be 16 or fewer. For example, if the electro-optical device actually has 14 scanning lines, the internal processing of the circuit device 100 may include a selection sequence pattern for the first to sixteenth scanning lines, but the fifteenth and sixteenth scanning lines are not actually driven. Selecting a scanning line group once in a subfield means selecting each digital scanning line belonging to the scanning line group once in the subfield. In this case, only one scanning line is selected in the same selection sequence, and two or more scanning lines are not selected simultaneously.

[0091] In this embodiment, each of the subfields SF1 to SF16 has the same period length. In each subfield, the scanning line driving circuit 110 selects, as a scanning line group, n digital scanning lines from the digital scanning line connected to the pixel circuit 30 to which the first bit is written to the digital scanning line connected to the pixel circuit 30 to which the nth bit is written.

[0092] 6, the first, second, third, and fourth bits are written to the 16th, 15th, 13th, and 9th scanning lines. That is, the scanning line group in subfield SF1 is the 16th, 15th, 13th, and 9th scanning lines, which is four scanning lines.

[0093] The fact that each subfield has a period of the same length means that the number of scanning lines in the scanning line group selected in each subfield is the same. Then, scanning lines of the same number as the number of bits of the display data are selected with a shift for each subfield, and by completing one cycle, the first to n-th bits are written to all scanning lines in one frame. In Figure 6, four scanning lines are selected in each subfield, and this pattern is shifted by one scanning line for each subfield, and by completing one cycle in 16 subfields, the first to fourth bits are written to 16 scanning lines in one frame.

[0094] 4. Examples 2 to 4 of drive methods 9 and 10 show a second example of a driving method in this embodiment. Here, an example will be described in which the total number of scanning lines included in the pixel array 20 is k=31 and the number of bits of display data is n=4.

[0095] 9 shows a driving method during the all-pixel off period Toff. In the second example, the length of the all-pixel off period Toff is 30 h. The control line driving circuit 130 disables the global enable signal ENGL during the all-pixel off period Toff, thereby turning off all pixels of the 1st to 31st scanning lines.

[0096] In the second example, the fourth bit of display data is written to the digital drive circuits 36 for the pixels on the first to sixteenth scan lines. The third bit of display data is written to the digital drive circuits 36 for the pixels on the seventeenth to twenty-fourth scan lines. The second bit of display data is written to the digital drive circuits 36 for the pixels on the twenty-fifth to twenty-eighth scan lines. The first bit of display data is written to the digital drive circuits 36 for the pixels on the twenty-ninth and thirtyth scan lines.

[0097] The display data written to the digital drive circuit 36 ​​during the all-pixel off period Toff is display data for an image displayed in the field FR, and does not include display data for fields other than the field FR.

[0098] Fig. 10 shows a driving method in the digital driving period TDD. In the first example described above, the display period of the first bit was 4 hours, which corresponds to one subfield, but in the second example, it is 2 × 4 hours, which corresponds to two subfields.

[0099] In the second example, there are 31 scanning lines, and the total number of scanning line selections in the digital driving period TDD is 31 lines x 4 bits = 124 times. The number of subfields is the same as the number of scanning lines, 31. The length of the field FR is 30h + 124h = 154h. The selection orders 1 to 124 in the digital driving period TDD correspond to the selection orders 31 to 154 in the field FR.

[0100] The formula for calculating the total number Nfr of selected scanning lines in the field FR will be explained below: First, the total number Ndd of selected scanning lines in the digital driving period TDD is calculated.

[0101] The length of the display period of the first bit divided by the length of the subfield is taken as multiple a. a is an integer equal to or greater than 1. In the first example, a=1, and in the second example, a=2. The number of bits of the display data is taken as n. In both the first and second examples, n=4. In this case, the following equation (1) holds true. Ndd=((2 n -1)×a+1)×n (1)

[0102] The number k of scanning lines is given by the following equation (2). k=Ndd / n=(2 n -1)×a+1 (2)

[0103] Since the number of selected scanning lines in the all-pixel off period Toff is k-1, the total number of selected scanning lines Nfr in the field FR is given by the following equation (3). Nfr=k-1+Ndd=k-1+((2 n -1)×a+1)×n (3)

[0104] Applying n=4 and a=2 in the second example, Ndd=((2 4-1)×2+1)×4=124, k=124 / 4=31, Nfr=31-1+124=154, which is consistent with Figures 9 and 10. In the first example, n=4 and a=1, so Ndd=((2 4 -1)×1+1)×4=64, k=64 / 4=16, Nfr=16-1+64=79, which is consistent with Figures 5 and 6.

[0105] In the second example, the ratio of the digital driving period TDD to the field FR is 124h / 154h=0.81, which ensures a sufficient digital driving period TDD, which is the lighting period or display period. In addition, by adjusting the number of bits n and the multiple a of the display data in the above equations (1) to (3), it is possible to accommodate electro-optical devices with various numbers of scanning lines.

[0106] 11 and 12 show a third example of the driving method in this embodiment. Here, an example will be described in which the total number of scanning lines included in the pixel array 20 is k=32, the number of bits of the display data is n=5, and the multiple is a=1.

[0107] 11 shows a driving method during the all-pixel off period Toff. In the third example, the length of the all-pixel off period Toff is 31 h. The control line driving circuit 130 disables the global enable signal ENGL during the all-pixel off period Toff, thereby turning off all pixels of the 1st to 32nd scanning lines.

[0108] In the third example, the fifth bit of display data is written to the digital drive circuits 36 for the pixels on the first to sixteenth scan lines. The fourth bit of display data is written to the digital drive circuits 36 for the pixels on the seventeenth to twenty-fourth scan lines. The third bit of display data is written to the digital drive circuits 36 for the pixels on the twenty-fifth to twenty-eighth scan lines. The second bit of display data is written to the digital drive circuits 36 for the pixels on the twenty-ninth and thirtyth scan lines. The first bit of display data is written to the digital drive circuit 36 ​​for the pixel on the thirty-first scan line.

[0109] The display data written to the digital drive circuit 36 ​​during the all-pixel off period Toff is display data for an image displayed in the field FR, and does not include display data for fields other than the field FR.

[0110] FIG. 12 shows a driving method in the digital driving period TDD. When n=5 and a=1 in the third example are substituted into the above equations (1) to (3), Ndd=((2 5 -1)×1+1)×5=160, k=160 / 5=32, Nfr=32-1+160=191. Thus, in the third example, there are 32 scanning lines, the length of the digital driving period TDD is 160h, and the length of the field FR is 191h. The number of subfields is 32, the same as the number of scanning lines. The selection orders 1 to 160 in the digital driving period TDD correspond to the selection orders 32 to 191 in the field FR.

[0111] In the third example, the ratio of the digital driving period TDD in the field FR is 160h / 191h=0.84, which ensures a sufficient digital driving period TDD, which is the lighting period or display period. In addition, the first to third examples are examples in which the number of bits n and the multiple a of the display data in the above formulas (1) to (3) are different, and it can be seen that by adjusting these parameters, it is possible to accommodate electro-optical devices with various numbers of scanning lines.

[0112] 13 and 14 show a fourth example of the driving method according to this embodiment. In the fourth example, the number of scanning lines is adjusted by adding a turn-off period to the digital driving period TDD. Here, as in the first example, the number of bits of the display data is n=4 and the multiple a=1. In the fourth example, the number of scanning lines is increased from k=16 in the first example to k=17.

[0113] 13 shows a driving method during the all-pixel off period Toff. In the fourth example, the length of the all-pixel off period Toff is 16 h. The control line driving circuit 130 disables the global enable signal ENGL during the all-pixel off period Toff, thereby turning off all pixels on the 1st to 17th scanning lines.

[0114] In the fourth example, the fourth bit of display data is written to the digital drive circuits 36 of the pixels on the first to ninth scan lines. Since the digital drive period TDD of the first scan line starts with an off period as shown in FIG. 14, writing does not have to be performed on the digital drive circuits 36 of the pixels on the first scan line during the all-pixel off period Toff. The third bit of display data is written to the digital drive circuits 36 of the pixels on the tenth to thirteenth scan lines. The second bit of display data is written to the digital drive circuits 36 of the pixels on the fourteenth and fifteenth scan lines. The first bit of display data is written to the digital drive circuits 36 of the pixels on the sixteenth scan line.

[0115] The display data written to the digital drive circuit 36 ​​during the all-pixel off period Toff is display data for an image displayed in the field FR, and does not include display data for fields other than the field FR.

[0116] FIG. 14 shows a driving method in the digital drive period TDD. As explained in the first example, the digital drive period TDD includes first to fourth scan line selection periods and first to fourth display periods. In the fourth example, the digital drive period TDD further includes an off period of one subfield. In FIG. 14, hatched boxes that are not surrounded by dotted lines indicate off periods. The boxes surrounded by dotted lines are scan line selection periods in which bits are written to pixel circuits. During these scan line selection periods, the light-emitting elements are also turned off. However, here, the "off period" refers to an off period that is newly provided other than the scan line selection period in which bits are written to pixel circuits. Although FIG. 14 shows an example in which an off period is provided between the fourth display period and the first scan line selection period, the timing of the off period may be arbitrary.

[0117] The first scan line will be taken as an example. In selection orders 1 to 4 of the digital drive period TDD, the control line drive circuit 130 outputs a disable enable signal EN1. This disables the digital drive circuit 36 ​​for the first scan line and does not output a drive current, so the pixels on the first scan line are turned off.

[0118] Next, in selection order 5, the scanning line driving circuit 110 selects the first digital scanning line, and the digital signal line driving circuit 120 outputs the first bit of display data. This causes the first bit to be written to the digital driving circuit 36. In the subsequent selection orders 6 to 9, the pixel circuit 30 turns on or off the light-emitting element 31 based on the first bit held in the digital driving circuit 36.

[0119] Similarly, in selection orders 10, 19, and 36, the scanning line driving circuit 110 selects the first digital scanning line, and the digital signal line driving circuit 120 outputs the second, third, and fourth bits. As a result, the second, third, and fourth bits are written to the digital driving circuit 36 ​​in selection orders 10, 19, and 36. In the subsequent selection orders 11 to 18, 20 to 35, and 37 to 68, the pixel circuit 30 turns on or off the light-emitting element 31 based on the second, third, and fourth bits held in the digital driving circuit 36.

[0120] Let b be the number obtained by dividing the length of the off period included in the digital driving period TDD by the length of the subfield. In this case, the total number of selected scanning lines Ndd in the digital driving period TDD is given by the following formula (4), the number of scanning lines k is given by the following formula (5), and the total number of selected scanning lines Nfr in the field FR is given by the following formula (6). Ndd=((2 n -1)×a+1)×n+b×n (4) k=((2 n -1)×a+1)+b (5) Nfr=k-1+((2 n -1)×a+1)×n+b×n (6)

[0121] Applying n=4, a=1, and b=1 in the fourth example, Ndd=((24 -1)×1+1)×4+1×4=68, k=68 / 4=17, Nfr=17-1+68=84, which matches Figures 13 and 14. Note that b can be any integer greater than or equal to 0, and b=0 means that no light-out period is provided in the digital drive period TDD. In the first to third examples, b=0.

[0122] In the fourth example, the ratio of the digital driving period TDD to the field FR is 68h / 84h=0.81, which ensures a sufficient digital driving period TDD, which is the lighting period or display period. Furthermore, by providing the parameter b for the lighting-off period in the above equations (4) to (6), the number of scanning lines can be finely adjusted. This allows for the reduction of dummy scanning lines that operate within the electro-optical device 15 but do not actually display. An example including dummy scanning lines is shown in the fifth example.

[0123] In the above embodiment, the length of the first display period is a times the length of the subfield. The number of times the scanning line is selected in the digital driving period TDD is Ndd, the number of bits of the display data is n, and the length of the extinguishing period in the digital driving period TDD is b times the length of the subfield. In this case, Ndd=((2 n -1)×a+1)×n+b×n.

[0124] According to this embodiment, the number of bits n of the display data, the multiple a indicating the length of the display period of the first bit, and the parameter b indicating the length of the off period in the digital drive period can be freely adjusted within the range where the number of scanning lines k can be an integer, thereby making it possible to support display panels with various numbers of pixels.

[0125] In this embodiment, the number of scan line selections in the field FR is Nfr, and the number of digital scan lines LDSC1 to LDSCk is k. In this case, Nfr≧Ndd+k−1. Note that in the first to fourth examples, Nfr=Ndd+k−1. An example where Nfr>Ndd+k−1 will be described later in the seventh example.

[0126] According to this embodiment, the length of the all-pixel off period Toff is (k-1)h or more. As a result, during the all-pixel off period Toff, image data of the image to be displayed in that frame can be written to the digital drive circuits 36 of the pixels of the 1st to kth scanning lines. As a result, images of each field are displayed in the digital drive period of each field without being mixed.

[0127] 5.Other examples of driving methods The fifth example is an example that complies with the full high-definition standard. The number of bits of display data is n=5, and the multiple is a=35. From the above equations (1) to (3), the total number of selected scan lines in the digital driving period TDD is Ndd=5430, the number of scan lines is k=1086, and the total number of selected scan lines in the field FR is Nfr=6515. Since the number of scan lines in the full high-definition standard is 1080, six of the k=1086 scan lines are dummy scan lines that operate inside the electro-optical device 15 but are not actually displayed.

[0128] In the fifth example, the ratio of the digital driving period TDD in the field FR is 5430h / 6515h=0.83, and the digital driving period TDD, which is the lighting period or display period, can be sufficiently secured.

[0129] The sixth example is an example that complies with the Super Hi-Vision standard. Let the number of bits of display data be n=12, the multiple a=1, and the parameter for the off period b=2688. From the above equations (4) to (6), the total number of selected scan lines in the digital driving period TDD is Ndd=51840, the number of scan lines k=4320, and the total number of selected scan lines in the field FR is Nfr=56159. The number of scan lines in the Super Hi-Vision standard is 4320, and by adjusting the parameter b for the off period, the Super Hi-Vision standard can be supported without adding dummy scan lines.

[0130] In the sixth example, the ratio of the digital driving period TDD in the field FR is 51840h / 56159h=0.92, which means that the digital driving period TDD, which is the lighting period or display period, is sufficiently secured.Compared with the other examples, it can be seen that the proportion of the lighting period tends to increase as the number of scanning lines increases.

[0131] The seventh example is an example in which the on-time is intentionally shortened by extending the all-pixel off period Toff. From the viewpoint of display brightness, a longer on-time period is preferable, but from the viewpoint of reducing motion blur, a shorter on-time period may be better. For example, when moving the head in an AR display on a head-mounted display, a shorter on-time period can reduce motion blur.

[0132] Let the number of bits of display data be n=4, the multiple a=1, and the all-pixel-off period Toff be extended by 40h. This is an example in which the all-pixel-off period Toff of the first example is extended by 40h. From the above equations (1) and (2), the total number of selected scan lines in the digital drive period TDD is Ndd=64, and the number of scan lines is k=16. The length of the all-pixel-off period Toff is (16-1)h+40h=55h, so the total number of selected scan lines in the field FR is Nfr=55+64=119.

[0133] In the seventh example, the ratio of the digital drive period TDD to the field FR is 64h / 119h=0.54, which is a shorter lighting period than 0.81 in the first example. According to the electro-optical device 15 of this embodiment, it is possible to perform a high-brightness display by lengthening the lighting period as in the first example, and it is also possible to perform a display with further reduced motion blur by shortening the lighting period as in the seventh example. In other words, according to the electro-optical device 15 of this embodiment, the selection order pattern can be adjusted according to various usage situations.

[0134] 6. Second Configuration Example of Electro-Optical Device and Display System 15 shows a second configuration example of the electro-optical device 15 and display system 10 of this embodiment. In the second configuration example, the display system 10 further includes a sensor 70. The second configuration example is a configuration example in which the pixel circuit 30 does not perform threshold compensation. Note that the same components as those already described are assigned the same reference numerals, and descriptions of those components will be omitted as appropriate.

[0135] The display signal supply circuit 61 outputs an analog data voltage VADT to the circuit device 100 based on environmental brightness information. The sensor 70 is a sensor that detects environmental brightness information, and is, for example, a photodiode or an image sensor. The display signal supply circuit 61 controls the analog data voltage VADT so that the current value of the drive current decreases as the environmental brightness decreases. Note that, although an example in which the display signal supply circuit 61 outputs the analog data voltage VADT has been described here, a voltage generation circuit or the like built into an electronic device incorporating the electro-optical device 15 may also output the analog data voltage VADT.

[0136] The circuit device 100 further includes an analog signal line driving circuit 140. The pixel array 20 further includes analog scanning lines LASC1 to LASCk, analog inverted scanning lines LXASC1 to LXASCk, and analog signal lines LADT1 to LADTm.

[0137] The analog scanning line LASC1 and the analog inversion scanning line LXASC1 are connected to the pixel circuits 30 in the first row. The scanning line driving circuit 110 outputs an analog selection signal ASC1 to the analog scanning line LASC1, and outputs an analog inversion selection signal XASC1, which is a logical inversion signal of the analog selection signal ASC1, to the analog inversion scanning line LXASC1. Similarly, the analog scanning lines LASC2 to LASCk and the analog inversion scanning lines LXASC2 to LXASCk are connected to the pixel circuits 30 in the second to k-th rows. The scanning line driving circuit 110 outputs the analog selection signals ASC2 to ASCk to the analog scanning lines LASC2 to LASCk, and outputs analog inversion selection signals XASC2 to XASCk, which are logical inversion signals of the analog selection signals ASC2 to ASCk, to the analog inversion scanning lines LXASC2 to LXASCk.

[0138] The analog signal line LADT1 is connected to the pixel circuits 30 in the first column. The analog signal line drive circuit 140 generates a threshold-compensated analog data voltage ADT1 from the analog data voltage VADT and outputs the analog data voltage ADT1 to the analog signal line LADT1. Similarly, the analog signal lines LADT2 to LADTm are connected to the pixel circuits 30 in the second to m-th columns. The analog signal line drive circuit 140 generates threshold-compensated analog data voltages ADT2 to ADTm from the analog data voltage VADT and outputs the analog data voltages ADT2 to ADTm to the analog signal lines LADT2 to LADTm.

[0139] Here, threshold compensation refers to compensating for variations in the threshold value of a transistor that generates a drive current for a light-emitting element, thereby compensating for variations in the drive current. The analog signal line drive circuit 140 stores k×m compensation values ​​corresponding to the pixel circuits 30 in k rows and m columns, and generates analog data voltages ADT1 to ADTm by compensating the analog data voltage VADT using the m compensation values ​​corresponding to the m pixel circuits 30 connected to a selected analog scan line.

[0140] Fig. 16 shows a second configuration example of the pixel circuit 30. The pixel circuit 30 further includes an analog drive circuit 35. Note that in Fig. 16, 1 to k and 1 to m in ASC1 to ASCk, DSC1 to DSCk, ADT1 to ADTm, DDT1 to DDTm, etc. are omitted.

[0141] When the analog scan line LASC and the analog inversion scan line LXASC are selected, the analog drive circuit 35 receives an analog data voltage ADT and holds the analog data voltage ADT. The analog drive circuit 35 passes a drive current having a current value specified by the held analog data voltage ADT from the power supply line LVD to the node NAQ. Hereinafter, the operation of setting this drive current will be referred to as "analog current setting." In this embodiment, all pixel circuits 30 simultaneously perform analog current setting during the all-pixel off period Toff.

[0142] The digital drive circuit 36 ​​is the same as that in Figure 3, except that the source of the P-type transistor TB2 is connected to the node NAQ.

[0143] 17 shows a first configuration example of the analog drive circuit 35. The analog drive circuit 35 includes P-type transistors TE1 and TF, an N-type transistor TE2, and a capacitor CF. Note that in FIG. 17, the 1 to k and 1 to m in ASC1 to ASCk, ADT1 to ADTm, etc. are omitted.

[0144] P-type transistor TE1 and N-type transistor TE2 form a switch circuit provided between the analog signal line LADT and one end of capacitor CF. Specifically, one of the source or drain of P-type transistor TE1 or N-type transistor TE2 is connected to the analog signal line LADT, and the other is connected to the gate of P-type transistor TF. The gate of P-type transistor TE1 is connected to the analog scan line LASC, and the gate of N-type transistor TE2 is connected to the analog inverted scan line LXASC. The source of P-type transistor TF is connected to the power supply line LVD, and the drain is connected to node NAQ. One end of capacitor CF is connected to the gate of P-type transistor TF, and the other end is connected to the source of P-type transistor TF.

[0145] The capacitor CF holds the analog data voltage ADT input from the analog signal line LADT. The P-type transistor TF is a current supply transistor, and supplies the digital drive circuit 36 ​​with a drive current corresponding to the analog data voltage ADT held in the capacitor CF.

[0146] 18 and 19 show examples of signal waveforms in the second configuration example of the electro-optical device 15. Note that the signal waveforms are shown in outline here, and the lengths of the periods do not necessarily correspond to the actual lengths.

[0147] The driving method related to digital driving is the same as the driving method described in the first configuration example of the electro-optical device 15. In the second configuration example of the electro-optical device 15, analog driving is further combined with these. In FIGS. 18 and 19, signal waveform examples in which analog driving is combined with the first example of the driving method described in FIGS. 5 and 6 will be described.

[0148] FIG. 18 shows a signal waveform example in which analog driving is combined with the signal waveform of FIG. 7. FIG. 19 shows a signal waveform example in which analog driving is combined with the signal waveform of FIG. 8.

[0149] The current setting period TAD is included in the all-pixel extinction period Toff. FIGS. 18 and 19 show an example in which the length of the current setting period TAD is the same as that of the all-pixel extinction period Toff, but the length of the current setting period TAD may be shorter than the length of the all-pixel extinction period Toff. FIG. 18 shows a signal waveform example of the 16th scanning line. As shown in FIG. 19, in all of the 1st to 16th scanning lines, the current setting period TAD is set to the same period.

[0150] FIG. 18 shows an example in which the current value of the driving current ID is set to IDA < IDmax. During the current setting period TAD, the analog driving circuit 35 outputs an analog data voltage ADT = VA corresponding to the current value IDA. Also, the scanning line driving circuit 110 outputs a low-level analog selection signal ASC and a high-level analog inversion selection signal XASC. At this time, the P-type transistor TE1 and the N-type transistor TE2 of the analog driving circuit 35 are on, and the voltage AQ at one end of the capacitor CF becomes the analog data voltage ADT = VA. At the end of the current setting period TAD, the scanning line driving circuit 110 sets the analog selection signal ASC to a high level and the analog inversion selection signal XASC to a low level. At this time, the P-type transistor TE1 and the N-type transistor TE2 turn off, and the voltage AQ = VA is held at one end of the capacitor CF.

[0151] When the digital drive circuit 36 ​​passes a drive current to the light-emitting element 31 during the digital drive period TDD, the analog drive circuit 35 passes a drive current ID=IDA corresponding to the analog data voltage ADT=VA, and therefore the drive current ID=IDA flows to the light-emitting element 31. In the example of Fig. 18, the drive current ID=IDA flows to the light-emitting element 31 during the display periods TD2 and TD4.

[0152] According to this embodiment, the display brightness of the entire screen can be adjusted by analog driving while displaying the gradation of an image by digital driving. For example, when the analog data voltage ADT is controlled by 3-bit brightness adjustment data, the drive current ID flowing through the light-emitting element 31 is controlled to 1 / 8, 2 / 8, . . . , or 8 / 8 times the maximum current IDmax. This controls the display brightness to eight gradations. For example, by setting the display brightness to maximum brightness in a bright environment and setting the display brightness to low brightness in a dark environment, the visibility of the displayed image can be ensured in environments with various brightness levels.

[0153] Furthermore, by performing analog current setting during the all-pixel off period Toff, a current setting period TAD long enough to write the analog data voltage ADT can be ensured. Also, since there is no need to perform analog current setting during the digital drive period TDD, control is simplified.

[0154] 20 shows a third configuration example of the electro-optical device 15 and the display system 10. In the third configuration example, the pixel circuit 30 performs threshold compensation, and the analog drive circuit 35 is omitted. Below, differences from the second configuration example will be mainly described, and descriptions of similar parts to the second configuration example will be omitted as appropriate.

[0155] The pixel array 20 includes pixel circuits 30 arranged in k rows and m columns, compensation control signal lines LDS1 to LDSk, LAZ1 to LAZk, reference voltage lines LVRF1 to LVRFm, analog scanning lines LASC1 to LASCk, digital scanning lines LDSC1 to LDSCk, enable signal lines LEN1 to LENk, analog signal lines LADT1 to LADTm, digital signal lines LDDT1 to LDDTm, a power supply line LVD, and ground lines LVS1 and LVS2.

[0156] One end of each of the analog signal lines LADT1 to LADTm is commonly connected to a node of the analog data voltage VADT, that is, a common analog data voltage VADT is applied to the analog signal lines LADT1 to LADTm.

[0157] The compensation control signal lines LDS1 and LAZ1 are connected to the pixel circuits 30 in the first row, and the control line drive circuit 130 outputs a compensation control signal DS1 to the compensation control signal line LDS1 and a compensation control signal AZ1 to the compensation control signal line LAZ1. Similarly, the compensation control signal lines LDS2 to LDSk and LAZ2 to LAZk are connected to the pixel circuits 30 in the second to k-th rows, and the control line drive circuit 130 outputs compensation control signals DS2 to DSk to the compensation control signal lines LDS2 to LDSk and outputs compensation control signals AZ2 to AZk to the compensation control signal lines LAZ2 to LAZk.

[0158] The reference voltage line LVRF1 is connected to the pixel circuits 30 in the first column. Similarly, the reference voltage lines LVRF2 to LVRFm are connected to the pixel circuits 30 in the second to m-th columns. The display signal supply circuit 61 outputs a reference voltage VFR. One end of the reference voltage lines LVRF1 to LVRFm is commonly connected to a node of the reference voltage VFR, and a common reference voltage VFR is applied to the reference voltage lines LVRF1 to LVRFm. Note that, similar to the analog data voltage VADT, a voltage generation circuit (not shown) or the like may output the reference voltage VRF.

[0159] The pixel circuit 30 in this configuration example is basically the same as that in FIG. 16, but the detailed configuration of the analog drive circuit 35 in this configuration example differs from that in FIG. 17. Figure 21 shows a second configuration example of the analog drive circuit 35. The analog drive circuit 35 includes P-type transistors TG1, TG2, TH1, and TH2 and capacitors CH1 and CH2. Note that in FIG. 21, the 1 to k and 1 to m in ASC1 to ASCk, ADT1 to ADTm, etc. are omitted.

[0160] The P-type transistor TG1 is a switch circuit provided between the analog signal line LADT and one end of the capacitor CH2. Specifically, one of the source or drain of the P-type transistor TG1 is connected to the analog signal line LADT, and the other is connected to the gate of the P-type transistor TH2 and one end of the capacitor CH2. The gate of the P-type transistor TG1 is connected to the analog scan line LASC.

[0161] One of the source and drain of the P-type transistor TG2 is connected to the reference voltage line LVRF, and the other is connected to the node NAQ. The gate of the P-type transistor TG1 is connected to the compensation control signal line LAZ.

[0162] The source of P-type transistor TH1 is connected to the power supply line LVD, and its drain is connected to the source of P-type transistor TH2 and the other end of capacitor CH2. One end of capacitor CH1 is connected to the drain of P-type transistor TH1 and the other end of capacitor CH2, and the other end is connected to the power supply line LVD. The drain of P-type transistor TH2 is connected to node NAQ.

[0163] The capacitor CH2 holds the analog data voltage VADT. The P-type transistor TH2 is a current supply transistor, and supplies the digital drive circuit 36 ​​with a drive current that corresponds to the analog data voltage VADT held in the capacitor CH2.

[0164] 22 shows an example of a signal waveform in the third configuration example of the electro-optical device 15. Note that the signal waveform is shown here as an outline, and the length of each period does not necessarily correspond to the actual length.

[0165] The driving method in the third configuration example of the electro-optical device 15 is basically the same as the driving method described in the second configuration example of the electro-optical device 15. However, in the third configuration example of the electro-optical device 15, threshold compensation is performed during the current setting period TAD. In Figure 22, differences from the signal waveform example in Figure 18 will be mainly described, and descriptions of similar parts will be omitted as appropriate.

[0166] During the current setting period TAD, the control line drive circuit 130 outputs a low-level compensation control signal AZ, which turns on the P-type transistor TG2 and applies the reference voltage VFR to the node NAQ.

[0167] The current setting period TAD is divided into a threshold compensation period TC and a subsequent write period TW. During the threshold compensation period TC, the analog data voltage VADT is first set to the offset voltage Vofs. At this time, the control line drive circuit 130 outputs a low-level compensation control signal DS. This turns on the P-type transistor TH1, and the power supply voltage VDD is applied to the other end of the capacitor CH2. In this state, the scan line drive circuit 110 changes the analog selection signal ASC from high to low. The P-type transistor TG1 changes from off to on, and the offset voltage Vofs is applied to one end of the capacitor CH2. The scan line drive circuit 110 changes the analog selection signal ASC from low to high, which turns the P-type transistor TG1 from on to off, and the capacitor CH2 maintains the potential difference VDD - Vofs. After this, the control line drive circuit 130 changes the compensation control signal DS from low to high. This turns the P-type transistor TH1 from on to off. Because an offset voltage Vofs is applied to the gate of the P-type transistor TH2, current flows through the P-type transistor TH2, the source voltage of the P-type transistor TH2 drops, and the gate voltage coupled by the capacitor CH2 also drops. At this time, a charge reflecting the threshold voltage of the P-type transistor TH2 is held in the capacitors CH1 and CH2.

[0168] During the write period TW, the analog data voltage VADT is set to VA. The scan line driving circuit 110 changes the analog selection signal ASC from high to low. The P-type transistor TG1 changes from off to on, and the analog data voltage VADT = VA is applied to one end of the capacitor CH2. The scan line driving circuit 110 changes the analog selection signal ASC from low to high, and the P-type transistor TG1 changes from on to off. After this, the control line driving circuit 130 changes the compensation control signal DS from high to low. This causes the P-type transistor TH1 to change from off to on. During this process, the capacitors CH1 and CH2 hold a charge that reflects the threshold voltage of the P-type transistor TH2, and as a result, the gate voltage of the P-type transistor TH2 becomes the threshold-compensated analog data voltage.

[0169] At the end of the current setting period TAD, the control line drive circuit 130 changes the compensation control signal AZ from low level to high level, which causes the P-type transistor TG2 to change from on to off.

[0170] In the above embodiment, the electro-optical device 15 includes a plurality of analog scanning lines LASC1 to LASCk and an analog signal line LADT. The analog signal line LADT is one of LADT1 to LADTk. Each pixel circuit 30 is connected to an analog scanning line LASC included in the plurality of analog scanning lines LASC1 to LASCk, and an analog signal line LADT. The analog scanning line LASC is one of LASC1 to LASCk. Each pixel circuit 30 includes an analog drive circuit 35. When selected by the analog scanning line LASC, an analog data voltage ADT is written from the analog signal line LADT to the analog drive circuit 35, and the analog drive circuit 35 variably sets the current value of the drive current ID based on the analog data voltage ADT. This is called analog current setting.

[0171] According to this embodiment, the analog drive circuit 35 variably adjusts the drive current ID, and the digital drive circuit 36 ​​digitally drives the light-emitting element 31 using the drive current ID. This adjusts the light emission luminance when the light-emitting element 31 is on, making it possible to use all gradations from 0 to 255 even in a dark environment, achieving both adjustment of the display luminance according to the brightness of the environment and good gradation display. Furthermore, because the display luminance is adjusted by analog drive independently of the gradation display by digital drive, the drive current ID is such that the light-emitting element 31 emits light stably even in a dark environment.

[0172] In this embodiment, the analog drive circuits 35 of the plurality of pixel circuits 30 perform analog current setting during the all-pixel off period Toff.

[0173] Since analog driving adjusts the display brightness of the entire screen, the analog data voltage is the same across the entire screen for the display image of the same frame. In this embodiment, the display frame switches simultaneously for all scanning lines, making it possible to simultaneously set analog currents for all scanning lines. Furthermore, since the analog current setting is performed during the all-pixel off period Toff, a period for setting analog currents is not required during the digital drive period TDD, simplifying drive control. Furthermore, since the all-pixel off period Toff provides sufficient time for writing analog data voltages, sufficient time for writing analog data voltages can be ensured even in high-resolution display panels, etc.

[0174] In this embodiment, during the all-pixel off period Toff, the analog drive circuit 35 of the plurality of pixel circuits 30 performs analog current setting and also performs threshold compensation for the transistor TH2 that passes that current value.

[0175] According to this embodiment, analog current setting and threshold compensation can be performed during the all-pixel-off period Toff. In this embodiment, since the display frame changes simultaneously for all scanning lines, analog current setting and threshold compensation can be performed simultaneously for all scanning lines. Furthermore, the all-pixel-off period Toff provides sufficient time for writing analog data voltages and threshold compensation, so that sufficient time for writing analog data voltages and threshold compensation can be ensured even in high-resolution display panels, etc.

[0176] 7.Electronic equipment 23 shows a configuration example of an electronic device 300 including electro-optical devices 15a and 15b. Each of the electro-optical devices 15a and 15b corresponds to the electro-optical device 15 shown in FIG. 2, 15, or 20. Here, the electronic device is described as a head-mounted display, but the present invention is not limited to this. Various devices that display images using electro-optical devices can be used as the electronic device. For example, the electronic device may be an electronic viewfinder, a projector, a head-up display, a personal digital assistant, a television, an in-vehicle display, or the like.

[0177] The head-mounted display has an appearance similar to glasses, and allows a user wearing the head-mounted display to view image light superimposed on external light. The electronic device 300, which is a head-mounted display, includes transparent members 303a and 303b, a frame 302, projectors 305a and 305b, and a sensor 70.

[0178] The frame 302 supports transparent members 303a and 303b and projection devices 305a and 305b. When the frame 302 is worn on the user's head, the head-mounted display is worn on the user's head. Transparent member 303a is provided in the right eye portion of the frame 302, and transparent member 303b is provided in the left eye portion of the frame 302. External light passes through the transparent members 303a and 303b, allowing the user to see the external light. Projection device 305a is provided from the right temple portion of the frame 302 to the right eye portion, and projection device 305b is provided from the left temple portion of the frame 302 to the left eye portion. When the projection devices 305a and 305b irradiate image light onto the user's eyes, the user sees the image light superimposed on the external light.

[0179] The projection device 305a includes an electro-optical device 15a. As described in FIG. 2, the electro-optical device 15a includes a circuit device 100 and a pixel array 20. The projection device 305a includes an optical system (not shown) that directs an image displayed on the pixel array 20 toward the user's eyes. The optical system includes, for example, a lens and a light-guiding member that reflects image light on its inner surface. The projection device 305a is configured so that the image light is focused by refraction by the lens and curvature of the reflecting surface of the light-guiding member. Similarly, the projection device 305b includes an electro-optical device 15b and an optical system (not shown).

[0180] The sensor 70 measures luminance information of the environment. The sensor 70 is provided, for example, at a connection portion connecting the right eye portion and the left eye portion of the frame 302. The sensor 70 is, for example, a photodiode, but an image sensor provided for photography may also serve as the sensor 70. In this case, luminance information is obtained from an image captured by the image sensor. Note that when the electro-optical device 15 of FIG. 2 is employed, the sensor 70 may be omitted.

[0181] The electro-optical device of the present embodiment described above includes a plurality of digital scanning lines, a digital signal line, and a plurality of pixel circuits. Each pixel circuit of the plurality of pixel circuits is connected to a digital scanning line and a digital signal line included in the plurality of digital scanning lines. Each pixel circuit includes a light-emitting element and a digital drive circuit. When selected by a digital scanning line, the digital drive circuit writes display data from the digital signal line and performs digital drive by supplying a drive current to the light-emitting element during an on-period having a length corresponding to the gradation value of the display data. A field, which is a period that constitutes one image, includes an all-pixel off period during which the plurality of pixel circuits turn off their light-emitting elements, and a digital drive period after the all-pixel off period during which the digital drive circuit performs digital drive.

[0182] According to this embodiment, an image is displayed on the electro-optical device during a digital driving period, and an all-pixel-off period is inserted between that digital driving period and the next digital driving period. This separates the image display in one field from the image display in the next field by the all-pixel-off period, thereby reducing motion blur compared to conventional driving methods. Furthermore, a field is a period that constitutes one image, and one image in that field is displayed during the digital driving period. This prevents images from being mixed in different fields, and allows the images of each field to be displayed separately in time, thereby reducing motion blur compared to conventional driving methods.

[0183] In this embodiment, the pixel circuits may be digitally driven during a digital drive period of a first field based on display data of an image displayed in the first field, and the pixel circuits may be digitally driven during a digital drive period of a second field based on display data of an image displayed in the second field.

[0184] According to this embodiment, digital driving of each field is performed based on the display data of the image displayed in each field, and as a result, the images of each field are displayed in the digital driving period of each field without being mixed together, thereby reducing motion blur compared to conventional driving methods.

[0185] Furthermore, in this embodiment, the ith pixel circuit of the first pixel circuit to the kth pixel circuit, which are the plurality of pixel circuits, may be connected to the ith digital scanning line of the first digital scanning line to the kth digital scanning line, which are the plurality of digital scanning lines. k is an integer of 2 or more, and i is an integer of 1 to k, both inclusive. During the all-pixel-off period, the first digital scanning line to the k-1th digital scanning line may be sequentially selected, and display data of an image to be displayed in a field may be written from the digital signal line to the first pixel circuit to the k-1th pixel circuit. During the digital drive period, the first pixel circuit to the k-1th pixel circuit may be digitally driven based on the display data written during the all-pixel-off period.

[0186] According to this embodiment, during an all-pixel-off period, display data for an image to be displayed in that field can be written to the pixel circuit. As a result, during the digital drive period of that field, digital drive is performed based on the display data for the image to be displayed in that field. As a result, images from each field are displayed during the digital drive period of each field without being mixed together, thereby reducing motion blur compared to conventional drive methods.

[0187] In this embodiment, in the first scanning line selection period of the digital driving period, the kth digital scanning line may be selected, and display data of the image to be displayed in the field may be written from the digital signal line to the kth pixel circuit.

[0188] According to this embodiment, in the all-pixel-off period and the first scanning line selection period of the digital drive period, display data of an image to be displayed in a field is written to the 1st to kth pixel circuits, whereby, in the digital drive period of that field, digital driving is performed based on the display data of the image to be displayed in that field.

[0189] In this embodiment, the electro-optical device may include a plurality of analog scanning lines and analog signal lines. Each pixel circuit may be connected to an analog scanning line and an analog signal line included in the plurality of analog scanning lines. Each pixel circuit may include an analog drive circuit. When selected by the analog scanning line, an analog data voltage is written to the analog drive circuit from the analog signal line, and the analog drive circuit may perform analog current setting that variably sets the current value of the drive current based on the analog data voltage.

[0190] According to this embodiment, the analog drive circuit variably adjusts the drive current, and the digital drive circuit digitally drives the light-emitting element using that drive current. This adjusts the light emission luminance when the light-emitting element is on, making it possible to use all gradations even in a dark environment, and achieving both adjustment of the display luminance according to the brightness of the environment and good gradation display.

[0191] In this embodiment, the analog drive circuits of the plurality of pixel circuits may perform analog current setting during the all-pixel off period.

[0192] According to this embodiment, since the display frame is switched simultaneously for all scanning lines, it is possible to simultaneously set analog currents for all scanning lines. Furthermore, since the all-pixel off period has sufficient time for writing analog data voltages, sufficient time for writing analog data voltages can be ensured even in high-resolution display panels.

[0193] In this embodiment, during the all-pixel-off period, the analog drive circuits of the plurality of pixel circuits may perform analog current setting and may also perform threshold compensation for the transistors that pass the current.

[0194] According to this embodiment, since the display frame is switched simultaneously for all scanning lines, it is possible to simultaneously perform analog current setting and threshold compensation for all scanning lines. Furthermore, since the all-pixel off period has sufficient time for writing analog data voltages and compensating threshold values, it is possible to ensure sufficient time for writing analog data voltages and compensating threshold values ​​even in high-resolution display panels.

[0195] In this embodiment, a field may be made up of an all-pixel off period and a digital drive period following the all-pixel off period.

[0196] According to this embodiment, a field is composed of an all-pixel-off period and a digital drive period in which one image is displayed by digital drive. As a result, one image is displayed during the digital drive period of a certain field, followed by an all-pixel-off period of the next frame, followed by a digital drive period in which one image is displayed. As a result, images from different fields are not mixed together, and the images from each field are displayed separately in time, thereby reducing video blur compared to conventional drive methods.

[0197] In this embodiment, the digital driving period of a field may include a plurality of subfields, and the scanning line driving circuit may select a group of scanning lines to be selected from among the plurality of digital scanning lines once in a subfield included in the plurality of subfields.

[0198] According to this embodiment, a group of scanning lines to be selected is selected in each subfield, which makes it possible to reduce the non-scanning period during which no scanning lines are selected, and thus makes it possible to lower the scanning line driving frequency compared to the methods in Patent Documents 1 and 2 described above.

[0199] In this embodiment, each of the plurality of subfields may have the same length of period.

[0200] The fact that each subfield has the same period length means that the number of scanning lines in the scanning line group selected in each subfield is the same. Then, scanning lines of the same number as the number of bits of the display data are selected in a shifted manner for each subfield, and by completing one cycle, the first to nth bits are written to all scanning lines in one frame.

[0201] In this embodiment, the electro-optical device may include a scanning line driving circuit that drives a plurality of digital scanning lines. The digital driving period may include a first scanning line selection period through an n-th scanning line selection period in which the first bit through the n-th bit of display data are written to the pixel circuits, and a first display period through an n-th display period in which the light-emitting element is turned on or off according to the first bit through the n-th bit written to the pixel circuits. n is an integer of 2 or greater. The on period may be a display period in which the light-emitting element is on among the first display period through the n-th display period.

[0202] According to this embodiment, during a digital driving period, a light-emitting element emits light during an ON period whose length corresponds to the gradation value of the display data. The time-averaged emission luminance in one frame is determined by the ratio of the ON period to the frame, and is therefore the luminance obtained by dividing the maximum luminance by the gradation value.

[0203] In this embodiment, the scanning line group may include a digital scanning line connected to a pixel circuit to which the i-th bit of the 1st to n-th bits of the display data is written in a subfield, and a digital scanning line connected to a pixel circuit to which the j-th bit of the 1st to n-th bits of the display data is written in a subfield, where i is an integer between 1 and n, and j is an integer between 1 and n but different from i.

[0204] According to this embodiment, in one subfield, the i-th bit is written to one scanning line and the j-th bit is written to another scanning line, which makes it possible to reduce the non-scanning period in which no scanning lines are selected, and thus makes it possible to lower the scanning line driving frequency compared to the methods in Patent Documents 1 and 2.

[0205] In this embodiment, the length of the first display period may be a times the length of the subfield, where a is an integer equal to or greater than 1. The number of scan line selections in the digital drive period may be Ndd, the number of bits of display data may be n, and the length of the extinguishing period in the digital drive period may be b times the length of the subfield. n is an integer equal to or greater than 2, and b is an integer equal to or greater than 0. In this case, Ndd=((2 n It may also be −1)×a+1)×n+b×n.

[0206] According to this embodiment, the number of bits n of the display data, the multiple a indicating the length of the display period of the first bit, and the parameter b indicating the length of the off period in the digital drive period can be freely adjusted within the range where the number of scanning lines k can be an integer, thereby making it possible to support display panels with various numbers of pixels.

[0207] In this embodiment, the number of times a scanning line is selected in a field may be Nfr, and the number of digital scanning lines may be k, where k is an integer equal to or greater than 2. In this case, Nfr≧Ndd+k−1 may be satisfied.

[0208] According to this embodiment, the length of the all-pixel-off period is (k-1)h or more. As a result, during the all-pixel-off period, image data of the image to be displayed in that frame can be written to the digital drive circuits of the pixels on the 1st to kth scan lines. As a result, images from each field are displayed during the digital drive period of each field without being mixed together.

[0209] Moreover, the electronic equipment of the present embodiment includes any of the electro-optical devices described above.

[0210] Furthermore, a driving method of this embodiment is a method for driving an electro-optical device including a plurality of digital scanning lines, digital signal lines, and a plurality of pixel circuits. The driving method includes turning off light-emitting elements included in each of the plurality of pixel circuits during an all-pixel-off period included in a field, which is a period for forming one image. The driving method also includes digitally driving each pixel circuit during a digital driving period included in the field and following the all-pixel-off period. The driving method includes, in the digital driving, writing display data from the digital signal lines to each pixel circuit when selected by the digital scanning lines, and supplying a drive current to the light-emitting element during an on-period having a length corresponding to the gradation value of the display data.

[0211] Although the present embodiment has been described in detail above, it will be readily apparent to those skilled in the art that many modifications are possible without substantially departing from the novel features and advantages of the present disclosure. Therefore, all such modifications are intended to be included within the scope of the present disclosure. For example, a term described at least once in the specification or drawings together with a different term having a broader or equivalent meaning may be replaced with that different term anywhere in the specification or drawings. Furthermore, all combinations of the present embodiment and modifications are also included within the scope of the present disclosure. Furthermore, the configurations and operations of the circuit device, pixel array, display controller, display system, sensor, electro-optical device, electronic device, etc. are not limited to those described in the present embodiment, and various modifications are possible. [Explanation of symbols]

[0212] 10...display system, 15, 15a, 15b...electro-optical device, 20...pixel array, 30...pixel circuit, 31...light-emitting element, 33...memory circuit, 35...analog driving circuit, 36...digital driving circuit, 60...display controller, 61...display signal supply circuit, 62...VRAM circuit, 70...sensor, 100...circuit device, 110...scanning line driving circuit, 120...digital signal line driving circuit, 130...control line driving circuit, 140...analog signal line driving circuit, 300...electronic device, 302...frame, 303a, 303b...transparent member, 305a, 305b...projection device, ADT...analog data voltage , ASC...analog selection signal, DDT...digital data signal, DSC...digital selection signal, EN...enable signal, ENGL...global enable signal, FR...field, LADT...analog signal line, LASC...analog scanning line, LDDT...digital signal line, LDSC...digital scanning line, LEN...enable signal line, LENGL...global enable signal line, SF1 to SF32...subfield, TAD...current setting period, TD1 to TD4...display period, TDD...digital driving period, TS1 to TS4...scanning line selection period, TW...write period, Toff...all pixel off period

Claims

1. a plurality of digital scan lines; A digital signal line; Each pixel circuit is connected to a digital scanning line included in the plurality of digital scanning lines and a plurality of pixel circuits connected to pixel signal lines; Including, Each pixel circuit is A light-emitting element; When selected by the digital scanning lines, display data is written from the digital signal lines. and a driving current is supplied to the light emitting element during an ON period of a length corresponding to the gradation value of the display data. a digital driving circuit for performing digital driving to supply the digital signal to the child; Including, The field, which is the period that makes up one image, is an all-pixel off period in which the plurality of pixel circuits turn off the light-emitting elements; and a digital driving period in which the digital driving circuit performs the digital driving after the digital driving period. fruit, The i-th pixel circuit (k is 2) among the first pixel circuit to the k-th pixel circuit, which are the plurality of pixel circuits. and i is an integer between 1 and k, and k is an integer between 1 and k, the i-th digital scanning line among the digital scanning lines to the k-th digital scanning line, During the all-pixel off period, the first to k-1th digital scanning lines are sequentially Next, the selected digital signal line is transmitted to the first pixel circuit to the k-1th pixel circuit. the display data of the image to be displayed in the field is written; During the digital driving period, the first pixel circuit to the k-1th pixel circuit performing the digital driving based on the display data written during a pixel extinguishing period; In the first scanning line selection period of the digital driving period, the kth digital scanning line is selected. and a digital signal is transmitted from the digital signal line to the k-th pixel circuit in the field. An electro-optical device, wherein the display data of the image to be displayed is written.

2. 2. The electro-optical device according to claim 1, The plurality of pixel circuits In the digital driving period of the first field, The digital driving is performed based on display data of an image to be displayed, In the digital driving period of the second field, an electro-optical device, wherein the digital driving is performed based on display data of an image to be displayed; 。

3. 3. The electro-optical device according to claim 1, a plurality of analog scan lines; An analog signal line; Including, Each pixel circuit is an analog scanning line included in the plurality of analog scanning lines and connected to the analog signal line; And, Each pixel circuit is When selected by the analog scan lines, the analog data signals are output from the analog signal lines. The voltage is written to the drive current, and the current value of the drive current is variably set based on the analog data voltage. and an analog driving circuit for setting an analog current for the electro-optical device.

4. 4. The electro-optical device according to claim 3, During the all-pixel-off period, the analog drive circuits of the pixel circuits An electro-optical device characterized by performing logarithmic current setting.

5. 5. The electro-optical device according to claim 4, During the all-pixel-off period, the analog drive circuits of the pixel circuits Analog current setting is performed, and threshold compensation of the transistor that flows the current value is performed. An electro-optical device characterized by:

6. 6. The electro-optical device according to claim 1, The field is the all-pixel-off period and the digital driving period after the all-pixel-off period. An electro-optical device comprising:

7. 7. The electro-optical device according to claim 1, a scanning line driving circuit for driving the plurality of digital scanning lines; the digital driving period of the field includes a plurality of sub-fields; The scanning line driving circuit In each of the plurality of subfields, The digital scanning lines belonging to the scanning line group to be selected are selected once for each line. Electro-optical device.

8. 8. The electro-optical device according to claim 7, Each subfield of the plurality of subfields comprises: An electro-optical device characterized in that the periods are of the same length.

9. 9. The electro-optical device according to claim 7, The digital driving period is The first bit to the n-th bit (n is an integer of 2 or more) of the display data are written to the pixel circuit. a first scanning line selection period to an n-th scanning line selection period, and the first scanning line selection period written to the pixel circuit. The first display period to the nth display period in which the light emitting element is turned on or off depending on the nth bit to the nth bit. and a display period, The on-period is The display period in which the light-emitting element is on is one of the first display period to the nth display period. Electro-optical device.

10. 10. The electro-optical device according to claim 9, The group of scan lines is In the subfield, the first bit to the nth bit of the display data The digital signal connected to the pixel circuit to which the i-th bit (i is an integer between 1 and n) is written a scanning line and the first bit to the nth bit of the display data in the subfield; The jth bit (j is an integer between 1 and n, and different from i) of the and a connected digital scan line.

11. 11. The electro-optical device according to claim 9, The length of the first display period is a times (a is an integer equal to or greater than 1) the length of the subfield. can be, The number of times of scanning line selection in the digital driving period is Ndd, and the number of bits of the display data is Ndd. The number of lights is n (n is an integer of 2 or more), and the length of the off period in the digital driving period is When the length of the subfield is b times (b is an integer equal to or greater than 0), Ndd=((2n-1)×a+1)×n+b×n An electro-optical device characterized by:

12. 12. The electro-optical device according to claim 11, The number of times of scanning line selection in the field is Nfr, and When the number is k (k is an integer of 2 or more), Nfr≧Ndd+k-1 An electro-optical device characterized by:

13. An electro-optical device comprising the electro-optical device according to any one of claims 1 to 12. Child equipment.

14. A plurality of digital scanning lines, a digital signal line, and a plurality of pixel circuits, The i-th pixel circuit (k is an integer of 2 or more, i is 1) among the first pixel circuit to the k-th pixel circuit (an integer equal to or larger than k) is the first digital scanning line to the k-th digital scanning line, which are the plurality of digital scanning lines. a driving method for driving an electro-optical device connected to an ith digital scanning line among digital scanning lines; So, In an all-pixel off period included in a field which is a period constituting one image, turning off a light-emitting element included in each pixel circuit of the plurality of pixel circuits; In a digital driving period included in the field and following the all-pixel off period, Each pixel circuit is digitally driven; In the digital driving, each pixel circuit is selected by the digital scanning line. At this time, display data is written from the digital signal line, and a signal is output in accordance with the grayscale value of the display data. supplying a drive current to the light emitting element during an on-period having a predetermined length; During the all-pixel off period, the first to k-1th digital scanning lines are sequentially Next, the selected digital signal line is transmitted to the first pixel circuit to the k-1th pixel circuit. the display data of the image to be displayed in the field is written; During the digital driving period, the first pixel circuit to the k-1th pixel circuit performing the digital driving based on the display data written during a pixel extinguishing period; In the first scanning line selection period of the digital driving period, the kth digital scanning line is selected. and a digital signal is transmitted from the digital signal line to the k-th pixel circuit in the field. a driving method, characterized in that the display data of the image to be displayed is written.

Images