Semiconductor device manufacturing method

Abstract

To suppress the development of slip defects in a semiconductor wafer.SOLUTION: Provided is a semiconductor device manufacturing method including a step of annealing a semiconductor wafer in a state in which a supported portion on a lower surface of the semiconductor wafer is supported by using a supporting portion. The semiconductor device manufacturing method includes: a region formation step of forming impurity regions including a first impurity in a region which is overlapped with the supported portion in a top view and which is apart from an edge of the semiconductor wafer; an annealing step of annealing the semiconductor wafer in a state in which the lower surface of the semiconductor wafer is supported by the supporting portion; and a removal step of removing the impurity regions by removing a region including the lower surface of the semiconductor wafer.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to a method for manufacturing a semiconductor device. [Background technology]

[0002] BACKGROUND ART Conventionally, it has been known to form a semiconductor device using a semiconductor wafer such as silicon (see, for example, Patent Documents 1 to 3). Patent Document 1: Japanese Patent Application Laid-Open No. 5-62867 Patent Document 2: Japanese Patent Application Laid-Open No. 9-190954 Patent Document 3: Japanese Patent Application Laid-Open No. 2005-64524 Summary of the Invention [Problem to be solved by the invention]

[0003] In a semiconductor wafer, it is preferable that there are few defects in the region where the semiconductor device is formed. [Means for solving the problem]

[0004] One aspect of the present invention provides a method for manufacturing a semiconductor device, which includes a step of annealing a semiconductor wafer while a supported portion on the underside of the semiconductor wafer is supported using a support. The manufacturing method may include a region forming step of forming an impurity region containing a first impurity in a region that overlaps the supported portion in a top view and is away from the edge of the semiconductor wafer. The manufacturing method may include an annealing step of annealing the semiconductor wafer while the underside of the semiconductor wafer is supported by the support. The manufacturing method may include a removal step of removing a region including the underside of the semiconductor wafer to remove the impurity region.

[0005] In the annealing step, a plurality of supported portions may be supported by a plurality of supporting portions. In the region forming step, an impurity region may be formed for each supported portion. The impurity regions may be separated from each other.

[0006] The impurity regions formed in the region formation step may be exposed at the underside of the semiconductor wafer.

[0007] The manufacturing method may include a reference detection step of detecting a reference point on the semiconductor wafer, and in the region formation step, the position at which the impurity region is formed may be controlled based on the position of the reference point.

[0008] In the region formation step, at least one of the range in which the impurity region is formed and the impurity concentration in the impurity region may be controlled based on the thickness of the semiconductor wafer.

[0009] In the region formation step, at least one of the range in which the impurity region is formed and the impurity concentration in the impurity region may be controlled based on the oxygen concentration of the semiconductor wafer.

[0010] In the region formation step, at least one of the range in which the impurity region is formed and the impurity concentration in the impurity region may be controlled based on the number of supported portions.

[0011] In the region formation step, the shape of the range in which the impurity region is to be formed may be controlled based on the crystal orientation of the semiconductor wafer.

[0012] In the region forming step, impurity regions may be formed at a plurality of positions in the thickness direction of the semiconductor wafer.

[0013] In the region formation step, the impurity region may be formed over a wider range as viewed from above, the greater the distance from the bottom surface of the semiconductor wafer.

[0014] The first impurity may be oxygen.

[0015] After the annealing step, the maximum concentration of the first impurity in the impurity region is 1×10 18 / cm 3 It may be more than that.

[0016] After the annealing step, the concentration of the first impurity in the impurity region is 1×10 20 / cm 3 It may be less than.

[0017] In the region forming step, a first impurity may be implanted from the bottom surface of the semiconductor wafer.

[0018] After the annealing step, the impurity region may have a depth width of 100 μm or less.

[0019] In the annealing step, the semiconductor wafer may be heated to 1000° C. or higher.

[0020] The impurity region may be 400 μm or more away from the top surface of the semiconductor wafer.

[0021] In the region forming step, an oxide film may be formed on the underside of the semiconductor wafer, and a resist film may be formed on the oxide film. In the region forming step, openings may be formed in the resist film at positions corresponding to the supported portions. In the region forming step, a first impurity may be implanted through the openings, and the resist film and the oxide film may be removed.

[0022] The above summary of the invention does not list all of the features of the present invention, and subcombinations of these features may also be inventions. [Brief explanation of the drawings]

[0023] [Figure 1] 1 shows a process of annealing a semiconductor wafer 100. [Figure 2] FIG. 2 is an enlarged view of an area A in FIG. [Figure 3] FIG. 1 is a diagram illustrating one embodiment of the present invention. [Figure 4] 1 is a flowchart illustrating an example of a method for manufacturing a semiconductor device. [Figure 5] 10A and 10B are diagrams illustrating a region forming step S410, an upper surface side structure forming step S420, and an annealing step S430. [Figure 6] 10A and 10B are diagrams illustrating a removing step S440 and a lower surface side structure forming step S450. [Figure 7]1 shows an example of the impurity concentration distribution in the depth direction of the semiconductor wafer 100. [Figure 8] FIG. 10 is a diagram showing an example of processing in the area formation step S410. [Figure 9] 10 is a diagram showing another example of the configuration of the impurity region 140. FIG. [Figure 10] 10 is a diagram showing an example of the arrangement of the supported portion 102 and the impurity region 140 on the lower surface 23. FIG. [Figure 11] 10A and 10B are diagrams showing other examples of the shape of the impurity region 140. FIG. [Figure 12] 10 is a diagram showing another example of the arrangement of the supported portion 102 and the impurity region 140 on the lower surface 23. FIG. [Figure 13] 10A and 10B are diagrams showing other examples of the shape of the impurity region 140. FIG. DETAILED DESCRIPTION OF THE INVENTION

[0024] The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the scope of the invention according to the claims. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0025] In this specification, one side in a direction parallel to the depth direction of a semiconductor wafer is referred to as "upper" and the other side as "lower." Of the two main surfaces of a wafer, substrate, layer, or other member, one surface is referred to as the upper surface and the other surface is referred to as the lower surface. The directions of "upper" and "lower" are not limited to the direction of gravity or the directions when the semiconductor device is mounted.

[0026] In this specification, technical matters may be explained using the Cartesian coordinate axes of the X-axis, Y-axis, and Z-axis. The Cartesian coordinate axes merely identify the relative positions of components and do not limit a specific direction. For example, the Z-axis does not limit the height direction relative to the ground. Note that the +Z-axis direction and the -Z-axis direction are opposite directions. When the Z-axis direction is written without specifying positive or negative, it means the direction parallel to the +Z-axis and -Z-axis.

[0027] In this specification, the orthogonal axes parallel to the top and bottom surfaces of the semiconductor wafer are referred to as the X-axis and Y-axis. The axis perpendicular to the top and bottom surfaces of the semiconductor wafer is referred to as the Z-axis. In this specification, the direction of the Z-axis may be referred to as the depth direction. In this specification, the direction parallel to the top and bottom surfaces of the semiconductor wafer, including the X-axis and Y-axis, may be referred to as the horizontal direction.

[0028] The region from the center to the top surface of the semiconductor wafer in the depth direction may be referred to as the top side of the semiconductor wafer. Similarly, the region from the center to the bottom surface of the semiconductor wafer in the depth direction may be referred to as the bottom side of the semiconductor wafer.

[0029] In this specification, when we say "same" or "equal," it may include cases where there is an error due to manufacturing variations, etc. The error is, for example, within 10%.

[0030] When charged particles such as ions or electrons are implanted into a semiconductor wafer at a predetermined acceleration energy, the particles have a predetermined distribution in the depth direction. In this specification, the peak position of the distribution may be referred to as the position where the particles are implanted, the implantation depth, or the like.

[0031] FIG. 1 is a diagram illustrating an example of a manufacturing process for a semiconductor device. The semiconductor device includes semiconductor elements such as transistors or diodes. The semiconductor device is formed on a semiconductor wafer 100. The semiconductor wafer 100 is formed of a semiconductor material such as silicon, silicon carbide, or gallium nitride. The semiconductor wafer 100 is, for example, disk-shaped when viewed from above in the Z-axis direction. In FIG. 1, the semiconductor wafer 100 is, for example, rectangular when viewed in cross section in the Y-axis direction. In FIG. 1, the edge of the semiconductor wafer 100 is not chamfered, but the edge of the semiconductor wafer 100 may be chamfered. Multiple semiconductor devices (semiconductor chips) may be formed on the semiconductor wafer 100. Multiple semiconductor devices can be manufactured by dicing the semiconductor wafer 100 into individual pieces.

[0032] FIG. 1 shows a process for annealing a semiconductor wafer 100. For example, in the manufacturing process of a semiconductor device, the semiconductor wafer 100 may be annealed at a predetermined temperature for a predetermined time after impurities are implanted into the semiconductor wafer 100. By annealing the semiconductor wafer 100, the impurities can be diffused and activated as donors or acceptors. When annealing the semiconductor wafer 100, a transfer boat 200 carrying the semiconductor wafer 100 is loaded into an annealing furnace. A plurality of semiconductor wafers 100 may be placed on the transfer boat 200.

[0033] 2 is an enlarged view of region A in FIG. 1. Region A includes the area where the semiconductor wafer 100 and the transfer boat 200 contact each other. The semiconductor wafer 100 has an upper surface 21, a lower surface 23, and an edge 27. The upper surface 21 and the lower surface 23 are the two main surfaces of the semiconductor wafer 100. In other words, the upper surface 21 and the lower surface 23 are the two surfaces of the semiconductor wafer 100 with the largest areas. The edge 27 is a side surface between the upper surface 21 and the lower surface 23.

[0034] In this example, a portion of the lower surface 23 of the semiconductor wafer 100 is supported by the support portion 110 of the transfer boat 200. The portion of the lower surface 23 of the semiconductor wafer 100 that comes into contact with the support portion 110 of the transfer boat 200 is referred to as the supported portion 102. In the example of FIG. 2, the support portion 110 has a cone shape, and the support portion 110 and the supported portion 102 come into contact at a point. In other examples, the support portion 110 and the supported portion 102 may come into contact along a line or a surface.

[0035] When the lower surface 23 of the semiconductor wafer 100 is supported, stress is generated near the supported portion 102 due to the weight of the semiconductor wafer 100. If the semiconductor wafer 100 is annealed in this state, defects may occur in the supported portion 102. In this specification, these defects are referred to as slips 120. These defects are distortions in the crystal structure of the semiconductor wafer 100 (i.e., crystal defects). The slips 120 progress in the direction from the supported portion 102 toward the upper surface 21, as shown by the arrow in FIG. 2.

[0036] The semiconductor wafer 100 includes an element region 130 in which a semiconductor element is formed. In this example, the element region 130 is in contact with the upper surface 21 of the semiconductor wafer 100. The element region 130 is a region that remains as a semiconductor device. Regions of the semiconductor wafer 100 other than the element region 130 are removed during the manufacturing process. For example, to prevent damage during the manufacturing process, the semiconductor wafer 100 is formed thicker than the semiconductor substrate of the semiconductor device that is finally manufactured. At the end of the manufacturing process, the thickness of the semiconductor wafer 100 is adjusted according to the withstand voltage of the semiconductor device, for example. For example, the thickness of the semiconductor wafer 100 is adjusted by grinding the lower surface 23 side of the semiconductor wafer 100. FIGS. 1 and 2 show the semiconductor wafer 100 before the thickness is adjusted.

[0037] If the slips 120 described above progress to the element region 130, they will affect the characteristics of the semiconductor element. For example, the leakage current of the semiconductor element may increase, and the breakdown voltage may decrease. The higher the annealing temperature, the more likely the slips 120 are to occur and progress. In particular, when the annealing temperature is high, such as 1000°C or higher, the occurrence of the slips 120 becomes more pronounced, and the possibility that the slips 120 will reach the element region 130 increases.

[0038] On the other hand, in the manufacturing process of a semiconductor device, the semiconductor wafer 100 may be annealed at a high temperature. For example, if impurities implanted into the element region 130 of the semiconductor wafer 100 are to be diffused to a position away from the implantation position, the annealing temperature becomes high. In such a case, the possibility that the slips 120 will reach the element region 130 increases. Although the occurrence and progression of the slips 120 can be suppressed by annealing at a low temperature, attempting to sufficiently diffuse the impurities results in a long annealing time, which reduces the throughput of the manufacturing process.

[0039] Furthermore, when the diameter of the semiconductor wafer 100 is 300 mm or more, the occurrence of slips 120 becomes significant, and the possibility that the slips 120 will reach the element region 130 increases. This is thought to be because the weight of the semiconductor wafer 100 increases, increasing the stress in the vicinity of the supported portion 102.

[0040] In addition, the oxygen concentration contained in the semiconductor wafer 100 from the beginning is 8×10 17 / cm 3 Below this level, the occurrence of slips 120 becomes significant, and the possibility that the slips 120 will reach the element region 130 increases. This is thought to be because the slips 120 are more likely to progress as the oxygen concentration decreases.

[0041] FIG. 3 is a diagram illustrating one embodiment of the present invention. In this example, an impurity region 140 containing a first impurity is formed in advance in the semiconductor wafer 100 before the step of annealing the semiconductor wafer 100 at a high temperature (for example, 1000° C. or higher). In this specification, the impurity that forms the impurity region 140 is referred to as the first impurity. The impurity region 140 is disposed on the lower surface 23 side of the semiconductor wafer 100. The lower surface 23 side refers to the region between the center in the depth direction of the semiconductor wafer 100 and the lower surface 23. The impurity region 140 has a higher atomic concentration of the first impurity per unit volume (atoms / cm) than other regions. 3 ) is a region where the atomic concentration of impurities per unit volume is locally high. In this specification, the atomic concentration of impurities per unit volume is simply referred to as the impurity concentration ( / cm 3 The impurity concentration can be measured by a known method such as SIMS (secondary ion mass spectrometry).

[0042] The progress of the slips 120 that reach the impurity region 140 from the lower surface 23 is suppressed by the first impurity contained in the impurity region 140. For example, when the slips 120 that have progressed through the silicon crystal come into contact with the first impurity, it is considered that the slips 120 cannot bypass the first impurity and are suppressed from progressing toward the upper surface 21. As a result, the impurity region 140 suppresses the progress of the slips 120 from the lower surface 23 toward the upper surface 21 beyond the impurity region 140.

[0043] The first impurity contained in the impurity region 140 at a high concentration is, for example, oxygen. However, the first impurity is not limited to oxygen. The first impurity may be any element that can suppress or inhibit the progression of the slip 120. The first impurity may be nitrogen, hydrogen, carbon, or another element. The first impurity is an element different from the semiconductor material that forms the semiconductor wafer.

[0044] The entire impurity region 140 is disposed closer to the lower surface 23 than the element region 130. This makes it possible to prevent the slips 120 from reaching the element region 130. Furthermore, by removing the region closer to the lower surface 23 than the element region 130, unnecessary impurity region 140 can be removed.

[0045] The impurity region 140 is arranged so as to overlap at least the supported portion 102 in the XY plane parallel to the lower surface 23 (i.e., when viewed from above). The impurity region 140 is preferably arranged so as to cover the entire supported portion 102. The impurity region 140 is also arranged in a region away from the edge 27 of the semiconductor wafer 100. The range of the impurity region 140 in the XY plane may refer to a region having an impurity concentration equal to or greater than half the peak value of the impurity concentration in the impurity region 140, a region having an impurity concentration equal to or greater than 10% of the peak value, or a region having an impurity concentration equal to or greater than 1% of the peak value. When multiple supported portions 102 are supported by multiple supporting portions 110, the impurity region 140 is arranged so as to overlap the multiple supported portions 102. The impurity region 140 may be arranged discretely in the XY plane for each supported portion 102, or one impurity region 140 arranged continuously in the XY plane may cover multiple supported portions 102.

[0046] By arranging the impurity region 140 in a region away from the edge 27, a region where the impurity region 140 is not formed can be provided, thereby suppressing the total amount of the first impurity contained in the semiconductor wafer 100. This makes it possible to suppress warping of the semiconductor wafer 100 during the manufacturing process of the semiconductor device. For example, if oxygen is implanted into the entire surface of the semiconductor wafer 100 and then annealed, oxygen may precipitate during annealing, causing the semiconductor wafer 100 to warp. In contrast, by locally providing the impurity region 140, it is possible to suppress warping of the semiconductor wafer 100 during the manufacturing process of the semiconductor device. The distance between the edge 27 and the impurity region 140 may be 10 mm or more, 20 mm or more, or 30 mm or more.

[0047] Furthermore, by providing the impurity regions 140 discretely for each supported portion 102, the area of ​​the impurity regions 140 in the XY plane can be further reduced, and the total amount of the first impurity can be further reduced. The area in the XY plane where the impurity regions 140 are provided may be half or less, one-fourth or less, or one-tenth or less of the area of ​​the lower surface 23 of the semiconductor wafer 100.

[0048] 4 is a flowchart showing an example of a method for manufacturing a semiconductor device. The manufacturing method of this example includes a region formation step S410, an annealing step S430, and a removal step S440. The manufacturing method may further include an upper surface-side structure formation step S420 and a lower surface-side structure formation step S450. The annealing step S430 of this example is included in the upper surface-side structure formation step S420.

[0049] 5 is a diagram illustrating the region formation step S410, the upper surface side structure formation step S420, and the annealing step S430. The explanation of each step in FIG. 5 and elsewhere shows the structure in the vicinity of region A. The semiconductor wafer 100 in this example is an N-type wafer. That is, donors such as phosphorus are distributed almost uniformly throughout the semiconductor wafer 100 immediately after it is cut from the ingot. In this specification, donors distributed almost uniformly throughout the initial semiconductor wafer 100 may be referred to as bulk donors.

[0050] In the region formation step S410, an impurity region 140 is formed on the lower surface 23 of the semiconductor wafer 100. In this example, the impurity region 140 is formed by implanting ions of a first impurity, such as oxygen ions, from the lower surface 23 of the semiconductor wafer 100. The impurity region 140 is a region that overlaps with the supported portion 102 in a top view and is spaced apart from the edge 27 of the semiconductor wafer 100. The ions of the first impurity are implanted locally from the lower surface 23. The impurity region 140 is formed at a predetermined depth from the lower surface 23 so as to overlap with the entire supported portion 102. The impurity region 140 may be formed so as to be exposed at the lower surface 23 of the semiconductor wafer 100. The position on the Z axis where the impurity region 140 is formed can be adjusted by the acceleration energy of the impurity ions.

[0051] Next, in the top-side structure formation step S420, at least a portion of the structure of the semiconductor element (sometimes referred to as the top-side structure) is formed on the top surface 21 side of the impurity region 140. The semiconductor element in this example is a trench-gate transistor. The top-side structure in this example includes an emitter region 12, a base region 14, and a gate trench 40. FIG. 5 schematically illustrates the top-side structure. The emitter region 12 is an N+ type region provided in contact with the top surface 21 of the semiconductor wafer. The base region 14 is a P-type region provided below the emitter region 12. An N- type drift region 18 is provided below the base region 14. The impurity concentration of the drift region 18 may be approximately the same as the concentration of the bulk donor. In other words, the drift region 18 may be a remaining region without the emitter region 12, base region 14, and other regions being formed.

[0052] The gate trench 40 extends from the upper surface 21 of the semiconductor wafer 100 to the drift region 18. The gate trench 40 includes a gate electrode 44 and a gate insulating film 42. The gate electrode 44 is formed of a conductive material such as impurity-doped polysilicon. The gate insulating film 42 is provided between the gate electrode 44 and the semiconductor wafer 100 to electrically insulate them. The gate insulating film 42 is, for example, an oxide film. The emitter region 12 and the base region 14 contact the side surfaces of the gate trench 40. When a predetermined gate voltage is applied to the gate electrode 44, the base region 14 at the boundary with the gate trench 40 is inverted to N-type, forming a channel. This allows current to flow between the emitter region 12 and the drift region 18. In other words, the transistor is turned on.

[0053] The upper surface side structure may include an interlayer insulating film 38 and an emitter electrode 52. The emitter electrode 52 is an electrode containing a metal such as aluminum. The emitter electrode 52 is connected to the emitter region 12. The interlayer insulating film 38 electrically insulates the gate electrode 44 from the emitter electrode 52. The interlayer insulating film 38 may be provided on the upper surface 21 of the semiconductor wafer 100 so as to cover the gate trench 40.

[0054] The emitter region 12 and the base region 14 may be formed by implanting impurities into the semiconductor wafer 100 and then annealing the semiconductor wafer 100. This annealing may correspond to the annealing step S430. In this annealing, the semiconductor wafer 100 is annealed while the supported portion 102 on the lower surface 23 of the semiconductor wafer 100 is supported using the support portion 110 of the transfer boat 200.

[0055] As described above, in the annealing step S430, slips 120 may occur on the lower surface 23 of the semiconductor wafer 100. In this example, even if slips 120 occur, the impurity region 140 can suppress the progression of the slips 120. Therefore, the progression of the slips 120 to the element region 130 can be suppressed.

[0056] FIG. 6 is a diagram illustrating the removal step S440 and the underside structure formation step S450. In the removal step S440, a region including the underside 23 of the semiconductor wafer 100 is removed. In this example, the underside 23 of the semiconductor wafer 100 is ground using a method such as CMP. In the removal step S440, the region including the underside 23 of the semiconductor wafer 100 is removed, thereby removing the entire impurity region 140. For example, the underside 23 of the semiconductor wafer 100 is ground at least until the upper end of the impurity region 140 is reached. This removes the region where the slip 120 occurred. After the removal step S440 is performed, the semiconductor wafer 100 has a underside 25. The underside 25 is positioned closer to the upper side 21 than the original underside 23.

[0057] In the bottom-side structure formation step S450, after the removal step S440, at least a portion of the structure of the semiconductor element (referred to as the bottom-side structure) is formed on the bottom surface 25 of the semiconductor wafer 100. The semiconductor element shown in FIG. 6 is an IGBT (Insulated Gate Bipolar Transistor). The bottom-side structure in this example includes a collector region 22 and a collector electrode 24. The bottom-side structure may further include a buffer region 20. The collector region 22 is a P-type region provided in contact with the bottom surface 25. The collector electrode 24 is an electrode containing a metal such as aluminum provided on the bottom surface 25. Whether or not a current flows between the emitter electrode 52 and the collector electrode 24 can be controlled by the gate voltage applied to the gate electrode 44. The buffer region 20 is an N-type region provided between the drift region 18 and the collector region 22. The donor concentration of the buffer region 20 is higher than the donor concentration of the drift region 18. The buffer region 20 functions as a field stop layer that prevents the depletion layer extending from the PN junction between the base region 14 and the drift region 18 from reaching the collector region 22 .

[0058] 5 and 6, even in the manufacturing process including the high-temperature annealing step S430, it is possible to prevent the slips 120 from reaching the element region 130. Therefore, it is possible to manufacture a semiconductor device with fewer defects while increasing the throughput of the manufacturing process.

[0059] Fig. 7 shows an example of the impurity concentration distribution in the depth direction of the semiconductor wafer 100. Fig. 7 shows the concentration distribution of the first impurity, such as oxygen, implanted into the impurity region 140, and does not include the concentrations of other impurities. Fig. 7 also shows the concentration distribution after the annealing step S430.

[0060] The maximum value of the first impurity concentration of the impurity region 140 is designated as P1. In this example, the first impurity, such as oxygen ions, is implanted at a depth position Z1 to form the impurity region 140. Therefore, the impurity concentration distribution exhibits a peak having an apex at the depth position Z1. The maximum value P1 in this example is the first impurity concentration at the apex of the peak.

[0061] The maximum value P1 is 1 x 10 18 / cm 3 It is preferable that the maximum value P1 is 1×10 18 / cm 3 By setting the value to 5×10 or more, it was possible to prevent the slips 120 from reaching the element region 130 even when the annealing temperature was 1000° C. or more. 18 / cm 3 May be greater than or equal to 1 x 10 19 / cm 3 It may be more than that.

[0062] The first impurity such as oxygen may be distributed throughout the semiconductor wafer 100. For example, when a semiconductor ingot is formed, the first impurity is contained throughout the ingot. Since the semiconductor wafer 100 is cut from the ingot, the first impurity may be contained throughout the semiconductor wafer 100. As an example, the semiconductor wafer 100 cut from an ingot formed by the MCZ method contains 4×10 17 / cm 3The following oxygen is included. In this example, the concentration of the first impurity distributed over the entire semiconductor wafer 100 is defined as D. The concentration D may be the average value of the concentration of the first impurity over the entire semiconductor wafer 100. The maximum value P1 may be 5 times or more, 10 times or more, or 50 times or more of the concentration D. The concentration D in this example is 4×10 17 / cm 3 The impurity region 140 is not formed, and the average oxygen concentration is 4×10 17 / cm 3 In the following semiconductor wafers, the growth of the slips 120 could not be suppressed.

[0063] The concentration of the first impurity in the impurity region 140 is 1×10 20 / cm 3 In other words, the maximum value P1 may be less than 1×10 20 / cm 3 If the concentration of the first impurity in the impurity region 140 is too high, the first impurity may diffuse into the element region 130, which may affect the characteristics of the semiconductor device. The concentration of the first impurity in the impurity region 140 may be less than 5×10 19 / cm 3 may be less than or equal to 1 x 10 19 / cm 3 It may be the following:

[0064] In this example, the center position in the depth direction of the semiconductor wafer 100 is defined as depth position Zc. Depth position Z1 is located between the bottom surface 23 and depth position Zc. When impurities are implanted by ion implantation, the impurity concentration distribution has a peak near depth position Z1. The full width at half maximum range of the peak in the depth direction is defined as width W1 of the impurity region 140 in the depth direction. Width W1 may be 100 μm or less. The impurity region 140 does not need to be formed over such a wide depth range to achieve the effect of suppressing the progression of the slip 120. Width W1 may be 50 μm or less, 20 μm or less, or 10 μm or less. Width W1 may be 1 μm or more, 2 μm or more, or 5 μm or more. Width W1 may be 10% or less, 5% or less, or 1% or less of the thickness T of the semiconductor wafer 100 (the distance from the top surface 21 to the bottom surface 23).

[0065] The distance between the impurity region 140 and the lower surface 23 is defined as L1. The distance L1 may be 100 μm or less, 50 μm or less, or 20 μm or less. The distance L1 may even be 0 μm. In other words, the impurity region 140 may be exposed to the lower surface 23. By reducing the distance L1, the distance in the Z direction over which the slip 120 advances can be shortened.

[0066] The distance between the impurity region 140 and the upper surface 21 is defined as L2. The distance L2 may be 400 μm or more. By ensuring the distance L2, the element region 130 can be ensured. The distance L2 may be 200 μm or more. The distance L2 can be set depending on the thickness of the element region 130 to be formed. The distance between the element region 130 and the impurity region 140 may be 0 μm or more, 10 μm or more, or 100 μm or more.

[0067] Note that the greater the thickness T of the semiconductor wafer 100, the greater the stress in the supported portion 102, making it easier for slips 120 to occur. Furthermore, the greater the thickness T, the more easily the generated slips 120 spread in the XY plane. In the region formation step S410, the impurity concentration P1 in the impurity region 140 may be adjusted based on the thickness T of the semiconductor wafer 100. For example, the greater the thickness T of the semiconductor wafer 100, the greater the impurity concentration P1. This makes it easier to suppress the progression of the slips 120. In the region formation step S410, the range in which the impurity region 140 is formed in the XY plane may be adjusted based on the thickness T of the semiconductor wafer 100. For example, the greater the thickness T of the semiconductor wafer 100, the greater the range in which the impurity region 140 is formed. This makes it easier for the impurity region 140 to inhibit the slips 120, which spread in the XY plane and spread in the Z-axis direction. The size of the impurity region 140 in the XY plane may be adjusted based on the distance of the impurity region 140 from the lower surface 23. For example, the impurity region 140 may be formed larger as the distance from the lower surface 23 increases. This makes it easier for the impurity region 140 to inhibit the slip 120 that spreads in the XY plane and progresses in the Z-axis direction.

[0068] Furthermore, the likelihood of the occurrence and progression of slips 120 may vary depending on the oxygen concentration D throughout the semiconductor wafer 100. In the region formation step S410, the impurity concentration P1 in the impurity region 140 may be adjusted based on the oxygen concentration D throughout the semiconductor wafer 100. For example, the lower the oxygen concentration D, the lower the impurity concentration P1. The impurity concentration P1 can be adjusted by the dose of the first impurity to be implanted. This makes it possible to suppress the progression of slips 120 while preventing excessive implantation of the first impurity. In the region formation step S410, the range in which the impurity region 140 is formed in the XY plane may be adjusted based on the oxygen concentration D throughout the semiconductor wafer 100. For example, the higher the oxygen concentration D, the larger the range in which the impurity region 140 is formed. This makes it possible to suppress the progression of slips 120 while preventing excessive implantation of the first impurity.

[0069] 8 is a diagram showing an example of processing in the region formation step S410. The region formation step S410 of this example includes an oxide film formation step S802, a resist film formation step S804, an impurity implantation step S806, and a film removal step S808.

[0070] In oxide film formation step S802, an oxide film 300 is formed on at least the lower surface 23 of the semiconductor wafer 100. The oxide film 300 covers the entire lower surface 23. In this example, the oxide film 300 is formed on the entire surface of the semiconductor wafer 100. In oxide film formation step S802 of this example, the semiconductor wafer 100 is placed in a diffusion furnace, and the entire surface of the semiconductor wafer 100 is thermally oxidized to form the oxide film 300.

[0071] Next, in resist film formation step S804, a resist film 302 is formed on the oxide film 300. The resist film 302 is laminated on the oxide film 300 formed on the underside 23 of the semiconductor wafer 100. In resist film formation step S804, an opening 304 is formed in the resist film 302 at a position corresponding to the supported portion 102. The opening 304 overlaps the entire supported portion 102 in the XY plane. In resist film formation step S804, the opening 304 may be formed by photolithography. Note that the opening 304 does not need to expose the underside 23 of the semiconductor wafer 100. In other words, in resist film formation step S804, the opening 304 may be formed so that the oxide film 300 remains.

[0072] Next, in impurity implantation step S806, a first impurity is implanted through opening 304 to form impurity region 140. In impurity implantation step S806, a depth position Z1 (see FIG. 7) at which the impurity is implanted into oxide film 300 may be set, or a depth position Z1 at which the impurity is implanted may be set at the boundary between oxide film 300 and bottom surface 23 of semiconductor wafer 100, or a depth position Z1 at which the impurity is implanted into semiconductor wafer 100 may be set. In impurity implantation step S806 of this example, impurity region 140 is formed in a region including bottom surface 23 of semiconductor wafer 100. A portion of impurity region 140 may be formed in oxide film 300.

[0073] Next, in film removal step S808, resist film 302 and oxide film 300 are removed. Through these steps, impurity region 140 can be formed in semiconductor wafer 100. In this example, impurity region 140 is exposed on underside 23 of semiconductor wafer 100. Impurity region 140 may be exposed on underside 23 of semiconductor wafer 100 as a result of diffusion of the first impurity in annealing step S430. Furthermore, providing oxide film 300 can protect semiconductor wafer 100 in the step of forming impurity region 140. Furthermore, implanting the first impurity through oxide film 300 makes it easier to maintain implantation accuracy of the first impurity even when dirt or the like is attached to underside 23 of semiconductor wafer 100.

[0074] In the impurity implantation step S806 of this example, the acceleration energy of the first impurity ions may be adjusted depending on the thickness of the oxide film 300. For example, the greater the thickness of the oxide film 300, the greater the acceleration energy of the first impurity ions. This allows the first impurity to be implanted into the semiconductor wafer 100 covered with the oxide film 300 while protecting the semiconductor wafer 100 with the oxide film 300.

[0075] FIG. 9 is a diagram showing another example of the configuration of the impurity region 140. FIG. 9 shows the vicinity of region A. In the region formation step S410 of this example, the impurity regions 140 are formed at multiple positions in the thickness direction (Z-axis direction) of the semiconductor wafer 100. Other structures are similar to any of the examples described with reference to FIGS. 3 to 8. FIG. 9 shows an example in which the impurity region 140-1 and the impurity region 140-2 are formed, but three or more impurity regions 140 may be formed. The depth position at which the impurity region 140 is formed can be controlled by the acceleration energy of the first impurity ions.

[0076] According to this example, it is easy to ensure the width W1 of the impurity region 140 in the Z-axis direction. In addition to the effect of suppressing the growth of the slip 120, the impurity region 140 can also have a gettering effect of capturing unnecessary components in the vicinity and bonding them with the first impurity. By ensuring the width W1, the gettering effect can also be improved. The gettering effect is the effect of capturing and fixing impurities that exist in the semiconductor wafer 100 and cause metal contamination, etc.

[0077] For example, depending on the type of impurity or the acceleration energy of the impurity ions, the full width at half maximum of one concentration peak may be small. Even in this case, the width W1 of the impurity region 140 can be ensured by implanting ions of the first impurity at multiple depths. The concentration peaks of the first impurity implanted at each depth may overlap or may be separated. Separated concentration peaks refer to the concentration of the valley between the two peaks being less than half the concentration at the peaks. The concentrations of the first impurity at each depth may be the same or different. Furthermore, the first impurity of the same element may be implanted at each depth, or different first impurities of different elements may be implanted. For example, oxygen may be implanted at each depth, or oxygen may be implanted at one depth and nitrogen may be implanted at another depth. Implanting first impurities of different elements can achieve gettering effects for various components.

[0078] Furthermore, in the region formation step S410, the impurity region 140 may be formed over a wider range in the XY plane (i.e., when viewed from above) as the impurity region 140 is farther from the lower surface 23 of the semiconductor wafer 100 in the Z-axis direction. In the example of FIG. 9, the impurity region 140-2, which is farther from the lower surface 23, is formed over a wider range than the impurity region 140-1, which is closer to the lower surface 23. The slips 120 (see FIG. 3) generated in the supported portion 102 tend to spread in the XY direction as the impurity region 140 moves farther from the lower surface 23 in the Z-axis direction. By forming the impurity region 140 closer to the lower surface 23 smaller, the dosage of the first impurity can be reduced while suppressing the growth of the slips 120. This makes it possible to suppress warping of the semiconductor wafer 100.

[0079] The impurity region 140-1 may be exposed at the lower surface 23. In the XY plane, the area of ​​the impurity region 140-2 may be 1.2 times or more, 1.5 times or more, or even 2 times or more, that of the impurity region 140-1.

[0080] 10 is a diagram showing an example of the arrangement of the supported portion 102 and the impurity region 140 on the lower surface 23. The impurity region 140 may or may not be exposed on the lower surface 23. FIG. 10 shows the position of the impurity region 140 projected onto the lower surface 23.

[0081] The semiconductor wafer 100 of this example has a plurality of supported portions 102 that are supported by a plurality of supporting portions 110 (see FIG. 3) in the annealing step S430 and the like. In the region forming step S410, an impurity region 140 is formed for each supported portion 102. As shown in FIG. 10, each impurity region 140 is formed so as to cover the entire corresponding supported portion 102. Furthermore, each impurity region 140 is arranged apart from one another.

[0082] The semiconductor wafer 100 may have a reference point 104 for positioning. The reference point 104 may be a notch provided on the edge of the semiconductor wafer 100. However, the reference point 104 is not limited to a notch. The reference point 104 may be anything that can be detected from an image of the semiconductor wafer 100.

[0083] The manufacturing method may include a reference detection step of detecting a reference point 104. In the reference detection step, the reference point 104 is detected from an image of the semiconductor wafer 100. In the region formation step S410, the position at which the impurity region 140 is formed may be controlled based on the position of the reference point 104. It is preferable that the relative position of the supported portion 102 with respect to the reference point 104 is set in advance in a manufacturing device or the like.

[0084] The impurity region 140 may be rectangular in the XY plane. The impurity region 140 may be formed using, for example, open frame exposure. In open frame exposure, a resist film applied to the semiconductor wafer 100 is exposed to a predetermined pattern without forming a mask on the resist film. Alternatively, for example, a reticle having a light-transmitting pattern formed thereon may be used to shape the light to expose the resist film. The impurity region 140 is formed by injecting a first impurity through an opening formed in the resist film.

[0085] 11 is a diagram showing another example of the shape of the impurity region 140. In this example, the impurity region 140 has a circular shape in the XY plane. The impurity region 140 may be formed using, for example, a resist mask. That is, a mask with a predetermined pattern may be formed on a resist film applied to the semiconductor wafer 100, and the resist film may be exposed to light.

[0086] Fig. 12 is a diagram showing another example of the arrangement of the supported portions 102 and the impurity regions 140 on the lower surface 23. While four supported portions 102 and four impurity regions 140 are arranged in Figs. 10 and 11, three supported portions 102 and three impurity regions 140 are arranged in the semiconductor wafer 100 of this example.

[0087] In the region formation step S410, at least one of the range in which the impurity regions 140 are formed and the impurity concentration in the impurity regions 140 may be controlled based on the number of supported portions 102 on the lower surface 23. The weight of the semiconductor wafer 100 applied to each supported portion 102 varies depending on the number of supported portions 102. Therefore, the likelihood of a slip 120 occurring or the likelihood of the slip 120 progressing in each supported portion 102 may change depending on the number of supported portions 102. By controlling the size or impurity concentration of the impurity regions 140 depending on the number of supported portions 102, it is possible to form impurity regions 140 with appropriate sizes and impurity concentrations. In the region formation step S410, the smaller the number of supported portions 102, the larger or higher the impurity concentration of each impurity region 140 may be.

[0088] 13 is a diagram showing another example of the shape of the impurity region 140. In the examples of FIGS. 10 to 12, the shape of the impurity region 140 in the XY plane is a regular polygon or a perfect circle. The impurity region 140 in this example may have a longitudinal direction (or major axis) in either direction in the XY plane. For example, the impurity region 140 is rectangular.

[0089] If there is a direction in which the slips 120 tend to grow in the XY plane, the impurity regions 140 may be formed in that direction in the region formation step S410. The direction in which the slips 120 tend to grow may be detected from past manufacturing results or estimated from other conditions. For example, the direction in which the slips 120 tend to grow may differ depending on the crystal orientation. In the region formation step S410, the shape of the impurity regions 140 may be controlled based on the crystal orientation of the semiconductor wafer 100.

[0090] Furthermore, when there are multiple directions in which the slip 120 tends to progress, the impurity region 140 may have its longitudinal axes in multiple directions in the XY plane. For example, the impurity region 140 may have a cross shape (i.e., two rectangles that intersect at right angles) in the XY plane. When the semiconductor wafer 100 is a silicon wafer with a (100) crystal plane orientation, the impurity region 140 may have a cross shape with its longitudinal axes in two directions, the (001) and (010) crystal orientations that intersect at right angles.

[0091] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the claims that such modifications and improvements can also be included within the technical scope of the present invention. [Explanation of symbols]

[0092] 12 emitter region, 14 base region, 18 drift region, 20 buffer region, 21 upper surface, 22 collector region, 23 lower surface, 24 collector electrode, 25 lower surface, 27 edge, 38 interlayer insulating film, 40 gate trench, 42 gate insulating film, 44 gate electrode, 52 emitter electrode, 100 semiconductor wafer, 102 supported portion, 104 reference point, 110 supporting portion, 120 slip, 130 element region, 140 impurity region, 200 transfer boat, 300 oxide film, 302 resist film, 304 opening

Claims

1. A method for manufacturing a semiconductor device, comprising a step of annealing a semiconductor wafer in a state where a supported portion on the underside of the semiconductor wafer is supported using a supporting portion, a region forming step of forming an impurity region including a first impurity in a region overlapping the supported portion in a top view and spaced from an edge of the semiconductor wafer; an annealing step of annealing the semiconductor wafer while the lower surface of the semiconductor wafer is supported by the support; a removing step of removing the impurity region by removing a region including the lower surface of the semiconductor wafer; Equipped with In the annealing step, a plurality of the supported portions are supported by a plurality of the supporting portions; In the region forming step, the impurity regions are formed for the respective supported portions, The impurity regions are separated from each other. A method for manufacturing a semiconductor device.

2. A method for manufacturing a semiconductor device, comprising a step of annealing a semiconductor wafer while supporting a supported portion on the underside of the semiconductor wafer using a supporting portion, a fiducial detection step of detecting a fiducial point on the semiconductor wafer; a region forming step of forming an impurity region including a first impurity in a region overlapping the supported portion in a top view and spaced from an edge of the semiconductor wafer; an annealing step of annealing the semiconductor wafer while the lower surface of the semiconductor wafer is supported by the support; a removing step of removing the impurity region by removing a region including the lower surface of the semiconductor wafer; Equipped with In the region forming step, a position where the impurity region is formed is controlled based on the position of the reference point. A method for manufacturing a semiconductor device.

3. A method for manufacturing a semiconductor device, comprising a step of annealing a semiconductor wafer while supporting a supported portion on the underside of the semiconductor wafer using a supporting portion, a region forming step of forming an impurity region including a first impurity in a region overlapping the supported portion in a top view and spaced from an edge of the semiconductor wafer; an annealing step of annealing the semiconductor wafer while the lower surface of the semiconductor wafer is supported by the support; a removing step of removing the impurity region by removing a region including the lower surface of the semiconductor wafer; Equipped with In the region forming step, at least one of the range in which the impurity region is formed and the impurity concentration in the impurity region is controlled based on the thickness of the semiconductor wafer. A method for manufacturing a semiconductor device.

4. A method for manufacturing a semiconductor device, comprising a step of annealing a semiconductor wafer while using a supporting portion to support a supported portion on the underside of the semiconductor wafer, a region forming step of forming an impurity region including a first impurity in a region overlapping the supported portion in a top view and spaced from an edge of the semiconductor wafer; an annealing step of annealing the semiconductor wafer while the lower surface of the semiconductor wafer is supported by the support; a removing step of removing the impurity region by removing a region including the lower surface of the semiconductor wafer; Equipped with In the region forming step, at least one of the range in which the impurity region is formed and the impurity concentration in the impurity region is controlled based on the number of the supported portions. A method for manufacturing a semiconductor device.

5. A method for manufacturing a semiconductor device, comprising a step of annealing a semiconductor wafer while supporting a supported portion on the underside of the semiconductor wafer using a supporting portion, a region forming step of forming an impurity region including a first impurity in a region overlapping the supported portion in a top view and spaced from an edge of the semiconductor wafer; an annealing step of annealing the semiconductor wafer while the lower surface of the semiconductor wafer is supported by the support; a removing step of removing the impurity region by removing a region including the lower surface of the semiconductor wafer; Equipped with In the region forming step, the shape of the area in which the impurity region is to be formed is controlled based on the crystal orientation of the semiconductor wafer. A method for manufacturing a semiconductor device.

6. A method for manufacturing a semiconductor device, comprising a step of annealing a semiconductor wafer while using a supporting portion to support a supported portion on the underside of the semiconductor wafer, a region forming step of forming an impurity region including a first impurity in a region overlapping the supported portion in a top view and spaced from an edge of the semiconductor wafer; an annealing step of annealing the semiconductor wafer while the lower surface of the semiconductor wafer is supported by the support; a removing step of removing the impurity region by removing a region including the lower surface of the semiconductor wafer; Equipped with In the region forming step, the impurity regions are formed at a plurality of positions in the thickness direction of the semiconductor wafer. A method for manufacturing a semiconductor device.

7. In the region forming step, the impurity region is formed over a wider range in a top view as the impurity region is located at a greater distance from the bottom surface of the semiconductor wafer. The method for manufacturing a semiconductor device according to claim 6 .

8. A method for manufacturing a semiconductor device, comprising the step of annealing a semiconductor wafer while using a support portion to support a supported portion on the underside of the semiconductor wafer, a region forming step of forming an impurity region including a first impurity in a region overlapping the supported portion in a top view and spaced from an edge of the semiconductor wafer; an annealing step of annealing the semiconductor wafer while the lower surface of the semiconductor wafer is supported by the support; a removing step of removing the impurity region by removing a region including the lower surface of the semiconductor wafer; Equipped with The impurity region is at least 400 μm away from the upper surface of the semiconductor wafer. A method for manufacturing a semiconductor device.

9. The impurity region formed in the region forming step is exposed on the bottom surface of the semiconductor wafer. The method for manufacturing a semiconductor device according to claim 1 .

10. In the region forming step, at least one of the range in which the impurity region is formed and the impurity concentration in the impurity region is controlled based on the oxygen concentration of the semiconductor wafer. The method for manufacturing a semiconductor device according to claim 1 .

11. The first impurity is oxygen. The method for manufacturing a semiconductor device according to claim 1 .

12. After the annealing step, the maximum concentration of the first impurity in the impurity region is 1×10 １８ / cm ３ That's all The method for manufacturing a semiconductor device according to claim 1 .

13. After the annealing step, the concentration of the first impurity in the impurity region is 1×10 ２０ / cm ３ is less than The method for manufacturing a semiconductor device according to claim 12.

14. In the region forming step, the first impurity is implanted from the bottom surface of the semiconductor wafer. The method for manufacturing a semiconductor device according to claim 1 .

15. After the annealing step, the impurity region has a depth width of 100 μm or less. The method for manufacturing a semiconductor device according to claim 1 .

16. In the annealing step, the semiconductor wafer is heated to 1000° C. or higher. The method for manufacturing a semiconductor device according to claim 1 .

17. In the region forming step, an oxide film is formed on the lower surface of the semiconductor wafer, a resist film is formed on the oxide film, an opening is formed in the resist film at a position corresponding to the supported portion, the first impurity is injected through the opening, and the resist film and the oxide film are removed. The method for manufacturing a semiconductor device according to claim 1 .

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