Systems and methods for the integration of thin film optical materials in silicon photonics

Abstract

A method of fabricating a photonics stack includes providing a silicon photonics structure (302, 362) including a silicon substrate (306, 366), an oxide layer (308, 368), and an epitaxial silicon layer (310, 370) having one or more active devices (128, 228). The method also includes providing an interposer structure (106, 206, 304, 364) and attaching the silicon photonics structure and the interposer structure. The method further includes removing the silicon substrate from the silicon photonics structure and removing at least a portion of the oxide layer from the silicon photonics structure. Additionally, the method includes disposing a thin-film lithium niobate coupon (104, 204, 320, 380) on or within the silicon photonics structure and encapsulating the thin-film lithium niobate coupon with an optical material (108, 208, 332, 392).

Description

[Technical Field]

[0001] The present disclosure is directed generally to optical systems and, more particularly, to systems and methods for the integration of thin film optical materials in silicon photonics. [Background technology]

[0002] Advances in silicon photonics have led to the first realization of millimeter-scale optical chips containing large numbers of devices. These chips can support diverse optical functions, such as polarization management, management of programmable optical filter banks, and high-speed modulators and photodetectors that operate at performance levels approaching or exceeding those of discrete optical devices. In some cases, multiple waveguide systems can be supported by complementary metal-oxide-semiconductor (CMOS) fabrication process flows that can enable low-loss optics for interfacing with external devices, such as III-V-based lasers and optical fibers. Summary of the Invention

[0003] The present disclosure relates to systems and methods for the integration of thin film optical materials in silicon photonics.

[0004] In a first embodiment, a photonics device includes a silicon waveguide structure disposed in a first plane. The photonics device also includes a plurality of modulator electrodes, at least a portion of each of the modulator electrodes disposed in the first plane. The photonics device further includes an optical material disposed in a second plane adjacent to the first plane.

[0005] In a second embodiment, the photonics stack includes a silicon layer having active devices disposed in a first plane, the active devices being disposed at lateral positions of the silicon layer, and the photonics stack also includes a lithium niobate structure positioned in a second plane adjacent to the first plane, the lithium niobate structure being disposed at the lateral position.

[0006] In a third embodiment, a method for fabricating a photonics stack includes providing a silicon photonics structure including a silicon substrate, an oxide layer, and an epitaxial silicon layer having one or more active devices. The method also includes providing an interposer structure and attaching the silicon photonics structure to the interposer structure. The method further includes removing the silicon substrate from the silicon photonics structure and removing at least a portion of the oxide layer from the silicon photonics structure. In addition, the method includes disposing a thin-film lithium niobate coupon on or within the silicon photonics structure and encapsulating the thin-film lithium niobate coupon with an optical material.

[0007] Other technical features may be readily apparent to those skilled in the art from the following drawings, descriptions, and claims. [Brief explanation of the drawings]

[0008] For a more complete understanding of the present disclosure, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:

[0009] [Figure 1A] 1A and 1B illustrate cross-sectional views of an embodiment of a photonics device having a thin film photonics structure according to the present disclosure. [Figure 1B] 1A and 1B illustrate cross-sectional views of an embodiment of a photonics device having a thin film photonics structure according to the present disclosure. [Figure 2] 1 illustrates a cross-sectional view of an example photonics device having an optically active photonics structure in accordance with the present disclosure. [Figure 3A] 3A through 3M illustrate an example technique for fabricating a photonics stack according to the present disclosure. [Figure 3B] 3A through 3M illustrate an example technique for fabricating a photonics stack according to the present disclosure. [Figure 3C] 3A through 3M illustrate an example technique for fabricating a photonics stack according to the present disclosure. [Figure 3D] 3A through 3M illustrate an example technique for fabricating a photonics stack according to the present disclosure. [Figure 3E] 3A through 3M illustrate an example technique for fabricating a photonics stack according to the present disclosure. [Figure 3F] 3A through 3M illustrate an example technique for fabricating a photonics stack according to the present disclosure. [Figure 3G] 3A through 3M illustrate an example technique for fabricating a photonics stack according to the present disclosure. [Figure 3H] 3A through 3M illustrate an example technique for fabricating a photonics stack according to the present disclosure. [Figure 3I] 3A through 3M illustrate an example technique for fabricating a photonics stack according to the present disclosure. [Figure 3J] 3A through 3M illustrate an example technique for fabricating a photonics stack according to the present disclosure. [Figure 3K] 3A through 3M illustrate an example technique for fabricating a photonics stack according to the present disclosure. [Figure 3L] 3A through 3M illustrate an example technique for fabricating a photonics stack according to the present disclosure. [Figure 3M] 3A through 3M illustrate an example technique for fabricating a photonics stack according to the present disclosure. [Figure 4A]4A and 4B illustrate diagrams of example embodiments of waveguide and modulator electrodes and related details within a silicon photonics structure of a photonics device according to the present disclosure. [Figure 4B] 4A and 4B illustrate diagrams of example embodiments of waveguide and modulator electrodes and related details within a silicon photonics structure of a photonics device according to the present disclosure. [Figure 5A] 5A through 5C illustrate the operating characteristics of an embodiment of a silicon photonics modulator according to the present disclosure. [Figure 5B] 5A through 5C illustrate the operating characteristics of an embodiment of a silicon photonics modulator according to the present disclosure. [Figure 5C] 5A through 5C illustrate the operating characteristics of an embodiment of a silicon photonics modulator according to the present disclosure. [Figure 6A] 6A through 6E illustrate exemplary optical waveguides and associated operational characteristics according to the present disclosure. [Figure 6B] 6A through 6E illustrate exemplary optical waveguides and associated operational characteristics according to the present disclosure. [Figure 6C] 6A through 6E illustrate exemplary optical waveguides and associated operational characteristics according to the present disclosure. [Figure 6D] 6A through 6E illustrate exemplary optical waveguides and associated operational characteristics according to the present disclosure. [Figure 6E] 6A through 6E illustrate exemplary optical waveguides and associated operational characteristics according to the present disclosure. [Figure 7A] 7A and 7B illustrate the properties of an embodiment of a silicon photonics modulator according to the present disclosure. [Figure 7B] 7A and 7B illustrate the properties of an embodiment of a silicon photonics modulator according to the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0010] 1A through 7B described below and the various embodiments used to explain the principles of the present disclosure are exemplary only and should not be construed as limiting the scope of the present disclosure. Those skilled in the art will understand that the principles of the present disclosure may be implemented in any type of suitably arranged device or system.

[0011] As discussed above, advances in silicon photonics have led to the first realization of millimeter-scale optical chips containing large numbers of devices. These chips can support diverse optical functions, such as polarization management, management of programmable optical filter banks, and high-speed modulators and photodetectors that operate at performance levels approaching or exceeding those of discrete optical devices. In some cases, multiple waveguide systems can be supported by complementary metal-oxide-semiconductor (CMOS) fabrication process flows that can enable low-loss optics for interfacing with external devices, such as III-V-based lasers and optical fibers.

[0012] While silicon photonics has experienced widespread adoption in lightwave communications (where discrete digital transceiver optics have been easily replaced by chip-scale counterparts), the use of silicon photonics in microwave and / or analog applications has been limited. Among other reasons, this deficiency is driven by the poor noise figure (NF) of silicon photonics transceivers, which remains at least an order of magnitude higher than that of state-of-the-art discrete photonics microwave transceivers. This deficiency stems from (i) two-photon absorption (TPA), which imposes strict power limitations, and (ii) excessive losses due to free-carrier absorption (FCA) in silicon modulators. Furthermore, the intrinsic nonlinearity of silicon modulators leads to their square-root tuning characteristics (their phase shift, φ, is proportional to V 1 / 2 The distortion is defined by the modulation error (proportional to ) and typically requires a significant reduction in modulation to suppress the distortion, which fundamentally degrades the noise figure of silicon-based photonics microwave links.

[0013] Lithium niobate (LN) integration into silicon photonics platforms can combine the benefits of high-density integration with the linear and power-scalable modulation enabled by ceramic material systems. Current LN integration process flows can involve bonding thin-film lithium niobate (TFLN) chiplets onto the front side of a patterned silicon-on-insulator or silicon nitride-on-insulator (SOI or SNOI) substrate via plasma-activated direct bonding or polymer-assisted bonding, followed by removal of the TFLN substrate. Optical waveguides on or within the LN film can be formed by partially etching it using argon ion beam milling or by evanescently coupling to silicon / silicon nitride strips to form hybrid guided modes. Finally, metal can be deposited and patterned on top of the TFLN to form the modulator's radio frequency (RF) electrodes and, optionally, direct current (DC) bias electrodes.

[0014] Unfortunately, these approaches suffer from several significant drawbacks. First, they may require that the area bonded to the TFLN be devoid of other optical or electrical devices. The TFLN layer typically needs to be close (within about 200 nanometers) to the underlying waveguide for low-loss mode transitions, which precludes co-location of the TFLN with active photonic and electrical devices, which may include contacts and metallization at that location. Because lithium niobate modulators can be on the order of several centimeters in size, this constraint can severely impact integration density. Additionally, low local metal density can result in non-uniform metal sheet resistance due to dishing and non-uniform etch rates. Low local metal density further impacts manufacturability, and large variations in metal density across the chip can increase the effective thermal expansion coefficient (C TEThis can induce significant stress on the back-end-of-the-line dielectric, such as due to mismatches in the dielectric thickness. Additionally, significant dielectric film and metal trace thickness deviations can occur in the area near the TFLN junction window due to dishing, which can affect manufacturing yield and degrade performance. Second, because the electrodes and waveguides are patterned separately on or in the lithium niobate, each photolithography step must be performed with high precision (e.g., alignment tolerances of less than 100 nanometers). Lack of precise alignment can result in significant loss or significant modulation efficiency imbalance between the modulator arms.

[0015] The present disclosure provides various systems and methods for the integration of thin-film optical materials in silicon photonics. For example, embodiments of the present disclosure enable the integration of nonlinear, active, and / or emissive optical materials (such as lithium niobate) in silicon photonics, which can gain functionality, reduce noise figure, provide improved linearity, and / or provide improved bandwidth performance compared to silicon photonics transceivers and processors. In various embodiments of the present disclosure, the disclosed systems and methods can reduce the size, weight, and / or power (SWaP) metrics of state-of-the-art silicon photonics devices by at least an order of magnitude. In some cases, the disclosed systems and methods can enable silicon photonics modulators to handle power in excess of 300 milliwatts, rivaling the power handling capabilities offered by discrete optical modulators. Furthermore, embodiments of the present disclosure can enable high-density integration, thereby achieving integration densities comparable to state-of-the-art silicon photonics circuits.

[0016] 1A and 1B illustrate cross-sectional views of example photonics devices 100 and 100′ having thin-film photonics structures in accordance with the present disclosure. More specifically, FIGS. 1A and 1B illustrate cross-sectional views of example silicon photonics devices having thin-film lithium niobate (TFLN) photonics structures. As shown in FIG. 1A, photonics device 100 may include a silicon photonics structure 102 and a TFLN photonics structure 104. However, in other embodiments, TFLN photonics structure 104 may be replaced with other optical materials or structures, such that the optical materials or structures are optically coupled to silicon photonics structure 102. For example, other implementations of photonics structure 104 may use different nonlinear optical materials.

[0017] In this example, the silicon photonics structure 102 may include a modulator electrode 124, a waveguide 126, and one or more active devices 128. The modulator electrode 124 represents the electrical connection of the silicon photonics modulator and may be formed using any suitable conductive material(s), such as one or more metals. The waveguide 126 represents a path for the optical signal and may be formed using any suitable optically transporting material(s), such as crystalline silicon, polysilicon, silicon nitride, or silicon oxynitride. The active devices 128 represent one or more semiconductor devices formed within the silicon photonics structure 102, such as one or more germanium-based photodiodes or other suitable semiconductor devices. Each active device 128 is disposed at a defined lateral position within the silicon layer of the silicon photonics structure 102.

[0018] The TFLN photonics structure 104 can be bonded or otherwise attached to the backside of the silicon photonics structure 102, allowing for the co-location of the modulator electrodes 124, waveguides 126, and active devices 128 adjacent to the TFLN photonics structure 104. In this manner, a relatively high level of integration density can be achieved compared to current approaches for integrating silicon photonics devices with thin-film lithium niobate devices. The waveguides 126 present in the silicon photonics structure 102 can be optically coupled to the TFLN layer 114 in the TFLN photonics structure 104, such as through a polymer dielectric 120 (which, as the name suggests, comprises an electrically insulating polymer). The TFLN layer 114 represents a thin film formed using lithium niobate, although other materials, as discussed above, can be used. The TFLN layer 114 here is located at the same lateral location(s) as the active device(s) 128.

[0019] By including the modulator electrode 124 and the waveguide 126 in the silicon photonics structure 102, the optical mode 127 and the modulation field can be self-aligned. This self-alignment can be achieved due to the proximity of the modulator electrode 124, which generates the modulation field in the TFLN layer 114, to the waveguide 126. Even if the TFLN layer 114 shifts due to misalignment, the optical mode 127 and the modulation field can still remain aligned. The inherent self-alignment of the electro-optic structure in the disclosed systems and methods can reduce or eliminate the in-plane misalignment bottlenecks present in current approaches. This can allow silicon photonics modulator performance, such as insertion loss and modulation efficiency, to be less affected by the placement of the TFLN photonics structure 104 or the tuning tolerances associated with the TFLN photonics structure 104. This self-alignment can also allow for relatively relaxed tuning tolerances between the TFLN photonics structure 104 and the silicon photonics structure 102. Additionally, this self-alignment can reduce or eliminate the precision alignment tolerances used in current approaches to integrating silicon photonics devices with thin-film lithium niobate devices.

[0020] In this example, the TFLN photonics structure 104 also includes a handle substrate 110 and an insulator layer 112. The insulator layer 112 represents an oxide insulating material or other electrically insulating material(s). In some embodiments, the insulator layer 112 represents a buried silicon oxide (BOX) layer 112. The handle substrate 110 is positioned over the insulator layer 112. In some embodiments, the handle substrate 110 may represent a composite substrate, such as one formed using a semi-transparent material. The TFLN photonics structure 104 can be encapsulated by an encapsulation layer 108. In some embodiments, the encapsulation layer 108 may be formed using one or more bonding polymer materials. In other embodiments, the encapsulation layer 108 may be formed using one or more optical adhesive materials.

[0021] The silicon photonics structure 102 may also include an insulator layer 116, which may be formed using any suitable electrically insulating material(s). In some embodiments, the insulator layer 116 may be formed using silicon oxide. In various embodiments, the encapsulation layer 108 of the TFLN photonics structure 104 (which may in some cases be formed using a bonding polymer material or an optical adhesive material) may have a refractive index that matches or nearly matches the refractive index of the insulator layer 116 of the silicon photonics structure 102 (which may in some cases be formed using an oxide layer). The silicon photonics structure 102 may also include at least one undoped silicon waveguide 118 and at least one silicon nitride (SiN) region 122, which may be used to transport optical signals.

[0022] In the illustrated embodiment, at least one of the active devices 128 (e.g., at least one germanium photodiode) may include a germanium (Ge) region 130, a heavily doped n-region 132, and a heavily doped p-region 134. Regions 132 and 134 represent areas of a semiconductor substrate or other structure doped with appropriate n-type material(s) and p-type material(s), respectively. The silicon photonics structure 102 may also include one or more heavily doped silicon regions 144. In some embodiments, the heavily doped silicon regions 144 may represent silicide regions. Additionally, the silicon photonics structure 102 may include various metal layers 142, which are used for interconnections. The metal layers 142 may be formed using any suitable material(s), such as one or more metals, such as copper or aluminum. In some embodiments, an interposer structure 106 may be coupled to the silicon photonics structure 102. The interposer structure 106 may include through-silicon vias (TSVs) 136 or other conductive vias that may electrically connect various electrodes (including the modulator electrodes 124) of the silicon photonics structure 102 to solder bumps 138 or other electrical connections. In some cases, the solder bumps 138 may provide electrical and mechanical connections to a module substrate 140, which may be formed using any suitable material(s) and may be used to carry the various components of the photonics device 100.

[0023] As shown in Figure 1B, the photonics device 100' is similar to the photonics device 100 of Figure 1A. However, in Figure 1B, in some embodiments, the insulator layer 116 may be completely removed. In this particular configuration, the insulator layer 116 is completely removed from the silicon photonics structure 102 to form a planarized bonding or other attachment surface on the backside of the silicon photonics structure 102.

[0024] 2 illustrates a cross-sectional view of an example photonics device 200 having an optically active photonics structure in accordance with the present disclosure. As shown in FIG. 2, photonics device 200 can include a silicon photonics structure 202 and an optically active photonics structure 204, which can provide optical gain in the context of photonics device 200. By way of example, optically active photonics structure 204 can include at least one indium phosphide (InP) stack 214.

[0025] Silicon photonics structure 202 may include at least one waveguide 226 and one or more active devices 228. Each waveguide 226 represents a path for an optical signal and may be formed using any suitable optical transport material(s), such as polysilicon, silicon nitride, or silicon oxynitride. Active devices 228 represent one or more semiconductor devices formed within silicon photonics structure 202, such as one or more germanium-based photodiodes or other suitable semiconductor devices. Each active device 228 is disposed at a defined lateral location within a silicon layer of silicon photonics structure 202.

[0026] The optically active photonics structure 204 can be bonded or otherwise attached to the backside of the silicon photonics structure 202, allowing for the co-location of waveguide(s) 226 and active devices 228 adjacent to the optically active photonics structure 204. In this manner, a relatively high level of integration density can be achieved compared to current approaches for integrating silicon photonics devices with optically active photonics devices. The waveguide(s) 226 present in the silicon photonics structure 202 can be optically coupled to the InP stack(s) 214 to form at least one hybrid InP-Si waveguide 229. By including deep-silicon vias (DSVs) 224 or other conductive vias and the waveguide(s) 226 in the silicon photonics structure 202, the optical mode 227 can undergo gain, phase modulation, or amplitude modulation.

[0027] The optically active photonics structure 204 may include a polymer layer 212, such as benzocyclobutene (BCB), and an interconnect layer 205 that provides electrical interconnects to the optically active photonics structure 204. The optically active photonics structure 204 may be encapsulated within an encapsulation layer 208. In some embodiments, the encapsulation layer 208 may be formed using one or more bonding polymer materials. In other embodiments, the encapsulation layer 208 may be formed using one or more optical adhesive materials.

[0028] The silicon photonics structure 202 may include an insulator layer 216, which may be formed using any suitable electrically insulating material(s). In some embodiments, the insulator layer 216 may be formed using silicon oxide. In various embodiments, the encapsulation layer 208 (which may in some cases be formed using a bonding polymer material or an optical adhesive material of the optically active photonics structure 204) may have a refractive index that matches or nearly matches the refractive index of the insulator layer 216 (which may in some cases be formed using an oxide layer) of the silicon photonics structure 202. The silicon photonics structure 202 may also include at least one undoped silicon waveguide 218 and at least one silicon nitride region 222, which may be used to transport optical signals.

[0029] In the illustrated embodiment, at least one of the active devices 228 (e.g., at least one germanium photodiode) may include a germanium region 230, a heavily doped n-region 232, and a heavily doped p-region 234. Regions 232 and 234 represent areas of a semiconductor substrate or other structure doped with appropriate n-type material(s) and p-type material(s), respectively. Silicon photonics structure 202 may also include one or more heavily doped silicon regions 244. In some embodiments, heavily doped silicon region 244 may represent a silicide region. Additionally, silicon photonics structure 202 may include various metal layers 242, which are used for interconnections. Metal layers 242 may be formed using any suitable material(s), such as one or more metals, such as copper or aluminum. In some embodiments, an interposer structure 206 may be coupled to silicon photonics structure 202. The interposer structure 206 may include through-silicon vias 206 or other conductive vias that may electrically connect the various electrodes of the silicon photonics structure 202 (including the deep-silicon vias 224) to solder bumps 238 or other electrical connections. In some cases, the solder bumps 238 may provide electrical and mechanical connections to a module substrate 240, which may be formed using any suitable material(s) and may be used to carry the various components of the photonics device 200.

[0030] 1A, 1B, and 2 illustrate examples of cross-sectional views of photonics devices 100, 100', and 200, various modifications can be made to FIGS. 1A, 1B, and 2. For example, each photonics device 100, 100', and 200 can include any suitable number of each of the illustrated components in any suitable arrangement. Also, depending on particular needs, one or more components of each photonics device 100, 100', and 200 can be omitted, or one or more additional components can be added. Additionally, the various sizes, shapes, and dimensions of photonics devices 100, 100', and 200 and their individual components can be varied as needed or desired.

[0031] 3A through 3M illustrate example techniques for fabricating photonics stacks according to the present disclosure. More specifically, FIGS. 3A through 3F illustrate an example technique for fabricating a first photonics stack, FIG. 3G illustrates an example technique for fabricating a photonics stack, and FIGS. 3H through 3M illustrate an example technique for fabricating a second photonics stack.

[0032] As shown in Figure 3A, the fully processed silicon photonics wafer 302 and the interposer wafer 304 can be bonded or otherwise attached. As will be apparent to those skilled in the art, A silicon photonics wafer 302 can be fabricated and then The active region(s) of the silicon photonics wafer 302 is / are positioned facing the interposer wafer 304 (or vice versa). )antiThe silicon photonics wafer 302 can be transferred onto a silicon substrate 306. The silicon photonics wafer 302 can include a silicon substrate 306, an oxide layer 308 (such as a buried oxide layer), and a silicon layer 310 (such as an epitaxial silicon layer), along with active and passive devices. In some embodiments, the interposer wafer 304 can include through-silicon vias 309 or other conductive vias. In other embodiments, the interposer wafer 304 may not include TSVs, and the TSVs or other conductive vias can be formed in the silicon photonics wafer 302. The interposer wafer 304 can be used to provide mechanical support, and the through-silicon vias 309 or other conductive vias can be used for electrical connections with various electrodes in the silicon photonics wafer 302.

[0033] As shown in Figure 3B, the silicon photonics wafer 302 and the interposer wafer 304 can be bonded or otherwise attached to form a mechanically inseparable and electrically connected stack 312. Figure 3B also illustrates the removal of the silicon substrate 306 of the silicon photonics wafer 302, such as by using a chemical mechanical polishing (CMP) process 314. However, it should be noted that any other suitable process, such as a grinding process or other suitable process, can be used to remove the silicon substrate 306. In this example embodiment, the removal process for the silicon substrate 306 can stop at the interface between the oxide layer 308 and the silicon substrate 306.

[0034] As shown in FIG. 3C , a photoresist layer 316 is deposited and patterned, and a plasma etching process or other suitable etching process 318 is utilized to open a receiving window 319 in the oxide layer 308. The etching process 318 removes at least a portion of the oxide layer 308 in at least one location to form the receiving window 319. In some embodiments, after the etching process 318, a thin oxide layer remains in the receiving window 319, which may have a thickness of less than about 100 nanometers, for example. However, other values ​​for the thickness of the remaining oxide layer can be used. Also, in some embodiments, removing the illustrated portion of the oxide layer 308 can be performed by a preferential etching process, such as a reactive ion etch followed by a buffered oxide etch process. As illustrated in FIG. 3C , the photoresist layer 316 is used to mask the remainder of the structure during the etching of the receiving window 319.

[0035] As shown in FIG. 3D , a bonding or other attachment process is shown for attaching one or more TFLN chiplets 320 to the resulting photonics stack 330. As illustrated in FIG. 3D , prior to attachment, the TFLN wafer may be coated with a bonding polymer layer 328 and diced into TFLN chiplets 320. In some embodiments, the thickness of the bonding polymer layer 328 may be, for example, about 40 nanometers to about 100 nanometers. However, other suitable thickness values ​​may be used. In various embodiments, the bonding polymer layer 328 may include any suitable polymer material(s), such as benzocyclobutene. Each TFLN chiplet 320 may include a substrate 322, a dielectric layer 324 formed using at least one dielectric material (such as silicon oxide), a thin-film lithium niobate layer 326, and the bonding polymer layer 328. In some embodiments, each TFLN chiplet 320 may have a length, for example, about 1 millimeter to about 2 millimeters. However, other suitable lengths may be used. 3D, a TFLN chiplet 320 is selected and placed into a receiving window 319, and the TFLN chiplet 320 is then pressed or otherwise attached to the photonics stack 330. Note, however, that in other embodiments, the TFLN chiplet 320 may be bonded to the photonics stack 330 without the bonding polymer layer 328, such as through the use of direct bonding.

[0036] At this point, there may be no electrical connection between the TFLN chiplet 320 and the photonics stack 330. In some embodiments, a thin oxide layer (such as a thin portion of the oxide layer 308) may remain in the receiving window 319. However, this thin oxide layer may not affect the subsequently established electric field, at least to a significant extent. The alignment tolerance for aligning the TFLN chiplet 320 to the photonics stack 330 may be relatively relaxed. For example, in some embodiments, the alignment tolerance may be ±5 microns. In the disclosed systems and methods, these relatively relaxed alignment tolerances are achievable because the modulator electrodes and waveguides are formed within the silicon photonics structure, and thus the resulting optics and electric fields are aligned. This can allow the TFLN chiplet 320 to have relatively relaxed alignment tolerances with respect to the waveguide, since misalignment of the TFLN chiplet 320 to the photonics stack 330 again does not affect the alignment of the optics and electric field, at least to a significant extent.

[0037] As shown in FIG. 3E, the receiving window 319 is sealed, such as with a near-infrared (NIR) transparent polymer or other polymer 332, which fills the location between the receiving window 319 and the sidewalls of the TFLN chiplet 320 and the oxide layer 308. In some embodiments, the refractive index of the polymer 332, which may be referred to as an optical adhesive, can match or nearly match the refractive index of the oxide layer 308. As a specific example, both may have refractive indices of about 1.4 to about 1.6. As shown in FIG. 3F, solder bumps 334 can be formed on the bonded wafer 331. In some cases, the solder bump wafer 331 can be diced or otherwise separated and connected to a module substrate 336.

[0038] It should be appreciated that the specific steps illustrated in Figures 3A through 3F provide a particular technique for fabricating a first silicon photonics stack in accordance with the present disclosure. However, other sequences of steps may be performed by other embodiments of the present disclosure. For example, other embodiments of the present disclosure may perform the steps outlined above in a different order. Moreover, any or all of the individual steps illustrated in Figures 3A through 3F may include multiple sub-steps that may be performed in various sequences as appropriate for the individual step(s). Furthermore, additional steps may be added or steps may be removed depending on the particular application. Those skilled in the art will recognize many variations, modifications, and alternatives.

[0039] As shown in FIG. 3G, a method for fabricating a photonics stack includes, in step 340, providing a silicon photonics structure, such as one including a silicon substrate, an oxide layer, and a silicon layer, having one or more active devices. As illustrated in FIG. 1A, the silicon photonics structure 102 may include one or more active devices 128, such as one or more germanium photodiodes having one or more germanium regions 130, one or more highly doped n-regions 132, and one or more highly doped p-regions 134. The silicon photonics structure 102 may also include highly doped silicon regions 144, such as silicide regions. The silicon photonics structure 102 may further include polysilicon, silicon nitride, silicon oxynitride, or other dielectric material(s) suitable for optical waveguide formation. The silicon photonics structure 102 may include various metal and conductive thin film layers used for interconnections.

[0040] In step 342, an interposer structure is provided, and in step 344, a silicon photonics structure is glued or otherwise attached to the interposer structure. As illustrated in FIG. 1A, for example, the interposer structure 106 may include TSVs 136 or other conductive vias used to connect various electrodes in the silicon photonics structure 102 to solder bumps. In step 346, the silicon substrate is removed from the silicon photonics structure, and in step 348, at least a portion of the buried oxide layer or other oxide layer is removed from the silicon photonics structure to define a receiving cavity. In some embodiments, removing the silicon substrate 306 is performed using a chemical mechanical polishing process. Also, in some embodiments, removing the buried oxide layer or other oxide layer 308 is performed using a reactive ion etch followed by a buffered oxide etch.

[0041] In step 350, a thin film lithium niobate coupon (such as TFLN chiplet 320) is placed into the receiving cavity, and in step 352, the receiving cavity is sealed with an optical adhesive. In some embodiments, the thin film lithium niobate coupon can include an insulator layer, such as a buried silicon oxide layer, and a handle substrate. The sealing adhesive can have a refractive index that matches or nearly matches the refractive index of the insulator layer of the silicon photonics structure 102.

[0042] It should be appreciated that the specific steps illustrated in FIG. 3G provide a particular technique for fabricating a silicon photonics stack in accordance with the present disclosure. However, other sequences of steps may be performed by other embodiments of the present disclosure. For example, other embodiments of the present disclosure may perform the steps outlined above in a different order. Moreover, any or all of the individual steps illustrated in FIG. 3G may include multiple sub-steps that may be performed in various sequences as appropriate for the individual step(s). Furthermore, additional steps may be added or steps may be removed depending on the particular application. Those skilled in the art will recognize many variations, modifications, and alternatives.

[0043] As shown in Figure 3H, the fully processed silicon photonics wafer 362 and the interposer wafer 364 can be bonded or otherwise attached. As will be apparent to those skilled in the art, A silicon photonics wafer 362 can be fabricated and then The active region(s) of the silicon photonics wafer 362 are positioned facing the interposer wafer 364 (or vice versa). )anti The silicon photonics wafer 362 may include a silicon substrate 366, an oxide layer 368 (such as a buried oxide layer), and a silicon layer 370 (such as an epitaxial silicon layer), along with active and passive devices. In some embodiments, the interposer wafer 364 may include through-silicon vias 369 or other conductive vias. In other embodiments, the interposer wafer 364 may not include TSVs, and the TSVs or other conductive vias may be formed in the silicon photonics wafer 362. The interposer wafer 364 may be used to provide mechanical support, and the through-silicon vias 369 or other conductive vias may be used for electrical connections with various electrodes in the silicon photonics wafer 362.

[0044] As shown in Figure 3I, silicon photonics wafer 362 and interposer wafer 364 can be bonded or otherwise attached to form a mechanically inseparable and electrically connected stack 372. Figure 3I also illustrates the removal of silicon substrate 366 of silicon photonics wafer 362, such as by using a chemical mechanical polishing process 374. However, it should be noted that any other suitable process, such as a grinding process or other suitable process, can be used to remove silicon substrate 366. In this example embodiment, silicon substrate 366 is removed by process 374, and the entire oxide layer 368 can also be removed from silicon photonics wafer 362.

[0045] As shown in FIG. 3J, a bonding polymer layer 376 can be spin-coated or otherwise deposited on the resulting photonics stack 390. As shown in FIG. 3K, the bonding polymer layer 376 can be used to bond or otherwise attach the photonics stack 390 to a thin-film lithium niobate chiplet 380. In some embodiments, the thickness of the bonding polymer layer 376 can be, for example, about 40 nanometers to about 100 nanometers. However, other suitable thickness values ​​can be used. In various embodiments, the bonding polymer layer 376 can include any suitable polymer material(s), such as benzocyclobutene. In FIG. 3K, the TFLN chiplet 380 (or wafer) can be bonded or otherwise attached to the photonics stack 390 using the bonding polymer layer 376. However, it should be noted that in other embodiments, the TFLN chiplet 380 can be bonded to the photonics stack 390 without the bonding polymer layer 376, such as through the use of direct bonding. In some embodiments, the TFLN chiplet 380 may have a length of, for example, about 1 millimeter to about 2 millimeters, although other suitable lengths may be used.

[0046] As shown in FIG. 3L, the bonded photonics structure is encapsulated, such as with a near-infrared transparent polymer or other polymer 392. In some embodiments, the refractive index of polymer 392 can be from about 1.4 to about 1.6. In some embodiments, the bonded photonics structure can also be encapsulated using an inorganic dielectric material, such as silicon dioxide. As shown in FIG. 3M, solder bumps 394 can be formed on the bonded wafer 391. In some cases, the solder bump wafer 391 can be diced or otherwise separated and connected to a module substrate 396.

[0047] It should be appreciated that the specific steps illustrated in Figures 3H through 3M provide a particular technique for fabricating a second silicon photonics stack in accordance with the present disclosure. However, other sequences of steps may be performed by other embodiments of the present disclosure. For example, other embodiments of the present disclosure may perform the steps outlined above in a different order. Moreover, any or all of the individual steps illustrated in Figures 3H through 3M may include multiple sub-steps that may be performed in various sequences as appropriate for the individual step(s). Furthermore, additional steps may be added or steps may be removed depending on the particular application. Those skilled in the art will recognize many variations, modifications, and alternatives.

[0048] While Figures 3A through 3M illustrate examples of techniques for fabricating photonics stacks, various modifications may be made to Figures 3A through 3M. For example, each photonics device may include any suitable number of each of the illustrated components in any suitable arrangement. Also, depending on particular needs, one or more components of each photonics device may be omitted, or one or more additional components may be added. Furthermore, the various sizes, shapes, and dimensions of the photonics devices and their individual components may be varied as needed or desired. Additionally, any other suitable techniques may be used to fabricate each photonics device.

[0049] 4A and 4B illustrate diagrams of example embodiments of waveguides and modulator electrodes within a silicon photonics structure of a photonics device 400, and related details, in accordance with the present disclosure. As shown in FIG. 4A, the photonics device 400 can include (i) a TFLN chip 412 encapsulated by a transparent polymer 402, and (ii) a silicon photonics structure 404 having a waveguide 408. The waveguide 408 is adjacent to a modulator electrode 410. The silicon photonics structure 404 can also include multiple metal layers, such as a “metal 1” layer 418, a “metal 2” layer 420, and a “metal 3” layer 422. The metal layers 418, 420, and 422 can be used for interconnection and to provide electrical drive to the modulator electrode 410. As can be seen in FIG. 4A, portions of the waveguide 408 and the modulator electrode 410 can be disposed in a common plane, and the TFLN chip 412 can be disposed in an adjacent plane.

[0050] The modulator electrode 410 can be proximate to the waveguide 408 and can be used to generate the electric field present in the TFLN chip 412. As can be seen, because the modulator electrode 410 and the waveguide 408 are formed within the silicon photonics structure 404, the resulting optical mode 416 and electric field 406 are aligned. Even if the TFLN chip 412 shifts to position 414 due to misalignment or the like, the optical mode 416 and electric field 406 still remain aligned. Thus, the inherent self-alignment of the electro-optical structure in the disclosed systems and methods can eliminate obstacles due to in-plane misalignment present in current approaches. These obstacles can include, for example, increased losses due to increased metal-optical mode overlap, reduced effective index modulation due to optical mode and electric field misalignment, and polarization and intensity modulation due to electric field vector mismatch that converts input transverse electric and transverse magnetic (TE / TM) modes into mixed TE+TM modes. As an example, using the previous approach, a 0.5 micron misalignment between the TFLN chip and the silicon photonics structure may produce a loss of approximately 2.66 dB / cm. In contrast, using embodiments of the present disclosure, a 0.5 micron misalignment between the TFLN chip 412 and the silicon photonics structure 404 may result in no loss.

[0051] As shown in FIG. 4B, a graph illustrates a curve 432 specifying the electric field strength as a function of the misalignment offset for the photonics structure in FIG. 4A. As can be seen, when the TFLN chip 412 is centered over the waveguide 408, this results in a zero misalignment offset in FIG. 4B. As can be seen in FIG. 4B, the electric field strength is relatively high and constant at locations where the misalignment offset is within ±5 microns of the location of the waveguide 408. Thus, the electric field strength is shown to be approximately 140 KV / m for misalignment offset values ​​of −5 microns to +5 microns around a portion of the waveguide 408.

[0052] While Figures 4A and 4B illustrate examples of diagrams of waveguides 408 and modulator electrodes 410 within silicon photonics structure 404 of photonics device 400 and related details, various modifications can be made to Figures 4A and 4B. For example, photonics device 400 can include any suitable number of each of the illustrated components in any suitable arrangement. Also, the various sizes, shapes, and dimensions of the photonics device and its individual components can be varied as needed or desired. Additionally, the graph in Figure 4B is merely exemplary, and the electric field strength can readily vary based on the particular implementation of photonics device 400.

[0053] 5A through 5C illustrate the operating characteristics of an embodiment of a silicon photonics modulator according to the present disclosure. More specifically, FIG. 5A illustrates the forward voltage gain factor (S) as a function of frequency for a modulator arm length of 1 centimeter. 21 ) is plotted on a graph. 21 The coefficients represent the electro-optic frequency response of the modulator. As can be seen in Figure 5A, S 21 The coefficient has a relatively high value across the frequency spectrum, which is beneficial to the performance of the modulator. Figure 5B shows the input port reflection (S) as a function of frequency for the modulator of Figure 5A. 11 ) coefficients. 11 The coefficients represent the input reflections of the optical signal provided to the modulator. As can be seen in Figure 5B, S 11 The coefficients have relatively low values ​​across the frequency spectrum. 11 A relatively low value for the coefficient can improve power efficiency and group delay variation due to reflections. The graphs show that the modulation bandwidth of the modulator can go up to 100 GHz.

[0054] FIG. 5C includes a graph plotting the phase shift as a function of bias voltage for the modulator of FIG. 5A. As illustrated in FIG. 5C, as the bias voltage increases, the phase shift increases linearly along line 508, eventually reaching a phase shift of π radians / cm at a bias voltage of about 4 volts. The phase shift as a function of bias voltage is an indicator of the electro-optic modulation efficiency of the device. In particular, the device is more efficient when a lower voltage can be used to reach a π radian phase shift per unit length. As shown in FIG. 5C, the phase shift reaches a value of π radians / cm at a relatively low value of bias voltage.

[0055] 5A through 5C illustrate example performance characteristics of a silicon photonics modulator, various modifications can be made to FIGS. 5A through 5C. For example, the performance characteristics shown in FIGS. 5A through 5C are exemplary only and do not limit the present disclosure to any particular implementation or performance characteristics of a silicon photonics modulator. As a specific example, modulation efficiency values ​​for silicon photonics modulators are not limited to the results shown in FIG. 5C and, in various embodiments, can be better than those shown in the graph of FIG. 5C.

[0056] 6A through 6E illustrate an example optical waveguide 600 and associated operational features according to the present disclosure. The optical waveguide 600 herein may be used in one or more of the photonics devices described above, such as in the silicon photonics structure 202. As shown in FIG. 6A , a plan view of the optical waveguide 600 is shown, and the optical waveguide 600 may include a silicon waveguide 602, an LN-Si hybrid waveguide 604, and a TFLN layer 606. In this example, the silicon waveguide 602 is positioned directly below the LN-Si hybrid waveguide 604, and the edge of the TFLN layer 606 is identified by location 608. In the illustrated embodiment, a four-stage taper design is used within the region where the waveguide 600 expands and tapers.

[0057] FIG. 6B illustrates an example of the optical field intensity within the propagation cross-section of the waveguide of FIG. 6A. As shown in FIG. 6B, the optical field intensity is greatest in the center of FIG. 6B and significantly weakens along the top and bottom edges of FIG. 6B. FIG. 6C illustrates a cross-sectional view of an example of an optical mode input into silicon waveguide 602, and FIG. 6D illustrates a cross-sectional view of an example of an optical mode output by hybrid waveguide 604. As illustrated in FIGS. 6C and 6D, embodiments of the present disclosure have the ability to overcome the model mismatch between silicon and hybrid waveguide modes and the index mismatch caused by the coupling of encapsulating polymer (having a refractive index n of about 1.44 to about 1.45) and lithium niobate (having a refractive index n of about 2.2).

[0058] FIG. 6E illustrates waveguide loss as a function of wavelength for different amounts of waveguide misalignment. As shown in FIG. 6E, an example of a perfectly aligned waveguide, which is the nominal case, is illustrated by curve 614. For a perfectly aligned waveguide, the waveguide loss varies from approximately 0.06 dB at a wavelength of 1500 nanometers, decreases slightly at a wavelength of 1560 nanometers, and increases to approximately 0.07 dB at a wavelength of 1600 nanometers. Curve 616 illustrates an example of misalignment of a TFLN chiplet with a silicon waveguide by 10 microns (e.g., ±5 microns of misalignment). As can be seen from the difference between curves 614 and 616, the difference in waveguide loss is less than 0.01 dB, regardless of the value of misalignment between the silicon waveguide and the TFLN chiplet across the entire wavelength range.

[0059] In some embodiments, PIN diodes may be introduced into the silicon waveguide 602 to increase the power handling capability of the silicon waveguide 602. Using the disclosed systems and methods, the introduction of PIN diodes can be achieved because active devices can be co-located with TFLNs, whereas using conventional techniques the introduction of PIN diodes into waveguides is difficult, if not prohibited.

[0060] 6A through 6E illustrate one example of optical waveguide 600 and associated operational features, various modifications may be made to FIGS. 6A through 6E. For example, the various sizes, shapes, and dimensions of optical waveguide 600 and its individual components may be varied as needed or desired. Additionally, the operational features shown in FIGS. 6B through 6E are exemplary only and do not limit the present disclosure to any particular implementation or operational characteristics of an optical waveguide.

[0061] 7A and 7B illustrate the characteristics of an example silicon photonics modulator according to the present disclosure. In some embodiments, the use of multiple metal layers within a photonics structure can enable advanced microwave engineering techniques. For example, FIG. 7A illustrates a graph having a curve 712 plotting response as a function of frequency for a silicon push-pull modulator, which may be implemented as shown in FIG. 1A and may utilize multiple metal layers.

[0062] 7B illustrates a graph with curve 714 plotting the input port reflection coefficient as a function of frequency for the silicon push-pull modulator of FIG. 1A, which again utilizes multi-metal layers. As shown in FIGS. 7A and 7B, the 3 dB bandwidth can be increased to 40 GHz, representing a 30% increase over the bandwidth that can be achieved using conventional techniques. Furthermore, multi-layer metals in silicon photonics devices can be employed for group velocity matching between electrical signal propagation along coplanar waveguides and optical field propagation in hybrid waveguides.

[0063] 7A and 7B illustrate example properties of a silicon photonics modulator, various modifications can be made to Figures 7A and 7B. For example, the properties shown in Figures 7A and 7B are examples only and do not limit the present disclosure to any particular implementation or properties of a silicon photonics modulator.

[0064] In some embodiments, the disclosed systems and methods for integrating nonlinear optical materials in silicon photonics can enable significant mitigation of mode mismatch losses between single-mode waveguides and modulator hybrid modes. In some cases, even when significant misalignment (such as ±10 microns) is present, this can enable coupling efficiencies of over 98% with less than 0.1 dB of excess loss between the silicon waveguide and the modulator block in the TFLN. Moreover, in various embodiments, the disclosed systems and methods can enable the integration of nonlinear optical materials in silicon photonics using existing silicon photonics manufacturing flows, thereby enabling the reuse of existing photonics process development kits (PDKs). Furthermore, the disclosed systems and methods can enable high-density, multi-function photonics integrated circuit (PIC) devices. For example, these devices can include, but are not limited to, fiber and laser coupling devices, polarization management devices, nonlinear loss-managed waveguides, waveguide transitions, coherent receivers, photodetectors, or digital silicon modulators. In some embodiments, application-specific PICs can be fabricated using a 0.1 cm 3 This allows for the inclusion of more than 300 devices in a volume of less than 0.1 cm utilized by circuits implemented according to embodiments of the present disclosure. 3 This contrasts with the device density characteristics of discrete optical devices implementing the same circuitry, which currently may typically occupy a space 100,000 times larger than the volume of the silicon photonics chip. Those skilled in the art will recognize that other modifications to the systems and methods of the present disclosure can be made to implement various applications of the systems and methods to support the integration of thin film nonlinear optical materials in silicon photonics without departing from the scope of the present disclosure.

[0065] It may be advantageous to set forth definitions of certain words and phrases used throughout this patent document. The terms "include" and "comprise," as well as their derivatives, mean including without limitation. The term "or" is inclusive and / or. The word "associated with," and its derivatives, may mean including, contained within, interconnected with, containing, housed within, connected to or with, coupled to or with, communicable with, associated with, interleaved with, juxtaposed with, proximate to, bound to or with, having, having properties of, relating to or with, and the like. The phrase "at least one of," when used in conjunction with a list of items, means that different combinations of one or more of the listed items may be used, or that only one item in the list may be required. For example, "at least one of A, B, and C" includes any of the following combinations: A, B, C, A and B, A and C, B and C, and A, B, and C.

[0066] Nothing in this disclosure should be read as implying that any particular element, step, or function is a required or critical element required for inclusion within the scope of a claim. The scope of patented subject matter is defined solely by the scope of the allowed claims. Furthermore, no claim shall invoke 35 U.S.C. § 112(f) with respect to any of the appended claims or claim elements unless the precise phrase "means for" or "step for" is expressly used in a particular claim, followed by a participial phrase identifying the function. Use of terms such as "mechanism," "module," "device," "unit," "component," "element," "member," "apparatus," "machine," "system," "processor," or "controller" in the claims is understood to and intended to refer to structures known to those skilled in the art, as further modified or enhanced by features of the claims themselves, and is not intended to invoke 35 U.S.C. § 112(f).

[0067] While this disclosure has described particular embodiments and generally associated methods, alterations and permutations of these embodiments and methods will be apparent to those skilled in the art. Accordingly, the above description of exemplary embodiments does not define or constrain the disclosure. Other changes, substitutions, and alterations are possible without departing from the spirit and scope of the disclosure, as defined by the following claims.

Claims

1. a silicon layer, a silicon waveguide structure disposed in a first plane within the silicon layer; a silicon layer including a plurality of modulator electrodes, at least a portion of each of the modulator electrodes being disposed in the first plane; an optical material disposed in a second plane adjacent to the first plane; Equipped with the modulator electrode is configured to generate a modulated electric field within the optical material; Photonics devices.

2. The photonics device of claim 1 , wherein the optical material comprises a nonlinear optical material.

3. The photonics device of claim 2 , wherein the nonlinear optical material comprises lithium niobate.

4. A photonics device as described in claim 1, further comprising one or more active devices positioned adjacent to the optical material and at least partially within the first plane.

5. The photonics device of claim 4 , wherein the one or more active devices include one or more germanium-based diodes.

6. The photonics device of claim 4 , wherein the one or more active devices include at least one highly doped n-region and at least one highly doped p-region.

7. The photonics device of claim 1 , wherein the optical material forms at least a portion of an indium phosphide device.

8. A photonics device as described in claim 7, further comprising one or more active devices positioned adjacent to the optical material and at least partially within the first plane.

9. 10. The photonics device of claim 8, wherein the one or more active devices include one or more germanium-based diodes.

10. 10. The photonics device of claim 8, wherein the one or more active devices include at least one highly doped n-region and at least one highly doped p-region.

11. a silicon layer including a waveguide, a plurality of modulator electrodes, and an active device, the waveguide, at least a portion of each of the modulator electrodes, and at least a portion of the active device being positioned in a first plane within the silicon layer; a lithium niobate structure positioned in a second plane adjacent to the first plane, the lithium niobate structure being positioned opposite the waveguide, the plurality of modulator electrodes, and the active device; Equipped with the modulator electrode is configured to generate a modulated electric field within the lithium niobate structure. Photonics stack.

12. The photonics stack of claim 11 , wherein the active device comprises a germanium-based diode.

13. The photonics stack of claim 11 , wherein the active device comprises at least one highly doped n-region and at least one highly doped p-region.

14. The photonics stack of claim 11 , wherein the silicon layer further comprises one or more silicon nitride regions.

15. 1. A method of manufacturing a photonics stack, comprising: providing a silicon photonics structure including a silicon substrate, an oxide layer, and a silicon layer; providing an interposer structure; attaching the silicon photonics structure and the interposer structure; removing the silicon substrate from the silicon photonics structure; removing at least a portion of the oxide layer from the silicon photonics structure; disposing a thin film lithium niobate structure on or within the silicon photonics structure; encapsulating the thin film lithium niobate structure with an optical material; Including, the silicon layer includes a waveguide, a plurality of modulator electrodes, and an active device; the waveguide, at least a portion of each of the modulator electrodes, and at least a portion of the active device are positioned in a first plane within the silicon layer; the thin-film lithium niobate structure is positioned in a second plane adjacent to the first plane so as to face the waveguide, the plurality of modulator electrodes, and the active device; the modulator electrode is configured to generate a modulated electric field within the thin film lithium niobate structure. method.

16. The method of claim 15 , wherein the optical material has a refractive index that substantially matches the refractive index of the oxide layer.

17. removing the silicon substrate is performed using chemical mechanical polishing; and Removing the oxide layer is performed using a reactive ion etch followed by a buffered oxide etch.

16. The method of claim 15, wherein at least one of

18. The active device comprises: one or more germanium-based photodiodes; and at least one highly doped n-region and at least one highly doped p-region; 16. The method of claim 15, comprising at least one of:

19. The silicon layer further comprises: at least one silicon nitride region; and one or more metal interconnect layers; 16. The method of claim 15, comprising at least one of:

20. The thin film lithium niobate structure comprises: an insulating layer, a handle substrate, and polymer dielectrics, 16. The method of claim 15, comprising at least one of:

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