TFT substrate and method for manufacturing the same

Abstract

To provide a TFT substrate and a manufacturing method for the TFT substrate, in which the characteristic variation of thin film transistors using an oxide semiconductor can be suppressed.SOLUTION: A TFT substrate includes: a substrate; a plurality of transistors provided on the substrate and including oxide semiconductor layers; a plurality of scan lines electrically connected to gates of the plurality of transistors and extending in a first direction; a plurality of signal lines electrically connected to the oxide semiconductor layers of the plurality of transistors and extending in a second direction intersecting with the first direction; an insulating film covering the plurality of signal lines and the oxide semiconductor layers; and a connection wire provided on the insulating film. At least one signal line is separated in the second direction through a slit. The connection wire electrically connects one signal line and another signal line that are adjacent in the second direction through the slit.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The present invention relates to a TFT (Thin Film Transistor) substrate and a method for manufacturing a TFT substrate. [Background technology]

[0002] A TFT substrate having a plurality of thin film transistors (TFTs) arranged on a substrate is used in display devices, detection devices, etc. Known semiconductor materials used in thin film transistors include oxide semiconductors (see Patent Documents 1 and 2). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2007-123861 [Patent Document 2] Japanese Patent Application Laid-Open No. 2007-96055 Summary of the Invention [Problem to be solved by the invention]

[0004] In a TFT substrate having thin film transistors using an oxide semiconductor, it is required to suppress variations in the characteristics of the thin film transistors.

[0005] An object of the present invention is to provide a TFT substrate capable of suppressing variations in the characteristics of thin film transistors using oxide semiconductors, and a method for manufacturing the TFT substrate. [Means for solving the problem]

[0006] A TFT substrate according to one embodiment of the present invention includes a substrate, a plurality of transistors provided on the substrate and including an oxide semiconductor layer, a plurality of scanning lines electrically connected to gates of the plurality of transistors and extending in a first direction, a plurality of signal lines electrically connected to the oxide semiconductor layers of the plurality of transistors and extending in a second direction intersecting the first direction, an insulating film covering the plurality of signal lines and the oxide semiconductor layer, and connection wiring provided on the insulating film, wherein at least one of the signal lines is separated in the second direction by a slit, and the connection wiring electrically connects adjacent signal lines in the second direction via the slit.

[0007] A method for manufacturing a TFT substrate according to one embodiment of the present invention includes the steps of stacking a plurality of scanning lines, an oxide semiconductor layer, and a plurality of signal lines in this order on a substrate, and forming a slit in at least one of the signal lines to separate the signal line in the extension direction; forming an insulating film that covers the oxide semiconductor layer and the plurality of signal lines, and forming contact holes in the insulating film in regions that overlap one signal line and the other signal line adjacent to each other via the slit; and forming connection wiring on the insulating film, and electrically connecting the one signal line and the other signal line via the contact hole. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is an explanatory diagram illustrating an example of a display device having a TFT substrate according to the first embodiment. [Figure 2] FIG. 2 is a block diagram illustrating an example of a display device system. [Figure 3] FIG. 3 is a circuit diagram showing an example of the configuration of a pixel of a display device. [Figure 4] FIG. 4 is a cross-sectional view showing an example of a display unit. [Figure 5] FIG. 5 is a plan view schematically showing the relationship between transistors, scanning lines, and signal lines of the TFT substrate according to the first embodiment. [Figure 6] FIG. 6 is an enlarged plan view of region A shown in FIG. [Figure 7] FIG. 7 is a cross-sectional view taken along line VII-VII' in FIG. [Figure 8] FIG. 8 is a cross-sectional view taken along line VIII-VIII' in FIG. [Figure 9] FIG. 9 is a cross-sectional view schematically showing a method for manufacturing the TFT substrate according to the first embodiment. [Figure 10] FIG. 10 is an explanatory diagram for explaining the method for manufacturing the TFT substrate according to the first embodiment. [Figure 11] FIG. 11 is a graph schematically showing the variation in characteristics of the transistors of the TFT substrate according to the first embodiment. [Figure 12] FIG. 12 is an explanatory diagram for explaining a method for manufacturing a TFT substrate according to a comparative example. [Figure 13] FIG. 13 is a graph schematically showing the variation in characteristics of the transistors of the TFT substrate according to the comparative example. [Figure 14] FIG. 14 is a plan view schematically showing the relationship between transistors, scanning lines, and signal lines of a TFT substrate according to a modified example of the first embodiment. [Figure 15] FIG. 15 is a cross-sectional view taken along the line XV-XV' in FIG. [Figure 16] FIG. 16 is a plan view showing an example of a detection device having a TFT substrate according to the second embodiment. [Figure 17] FIG. 17 is a circuit diagram showing a detection element of the TFT substrate according to the second embodiment. [Figure 18] FIG. 18 is a cross-sectional view schematically showing a TFT substrate according to the second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] Modes (embodiments) for carrying out the present invention will be described in detail with reference to the drawings. The present disclosure is not limited to the contents described in the following embodiments. Furthermore, the components described below include those that can be easily imagined by a person skilled in the art and those that are substantially identical. Furthermore, the components described below can be combined as appropriate. Note that the disclosure is merely an example, and any appropriate modifications that a person skilled in the art can easily make while maintaining the gist of the present disclosure are naturally included within the scope of the present disclosure. Furthermore, for clarity of explanation, the drawings may schematically depict the width, thickness, shape, etc. of each part compared to the actual embodiment. However, these are merely examples and are not intended to limit the interpretation of the present disclosure. Furthermore, in this disclosure and each figure, elements similar to those previously described with reference to the preceding figures may be designated by the same reference numerals, and detailed descriptions may be omitted as appropriate.

[0010] In this specification and claims, when expressing an aspect of placing another structure on top of a certain structure, the term "on top" is used, unless otherwise specified, to include both a case in which another structure is placed directly on top of a certain structure so as to be in contact with the certain structure, and a case in which another structure is placed above a certain structure via yet another structure.

[0011] (First embodiment) Fig. 1 is an explanatory diagram illustrating an example of a display device having a TFT substrate according to the first embodiment. As shown in Fig. 1, the display device 1 includes a display unit 2 and a backlight 6. The display device 1 may be a transmissive or semi-transmissive display device, or may be a reflective display device that does not include the backlight 6.

[0012] The display unit 2 has, in a plan view, a display area 21 that displays an image, and peripheral areas 11gl and 11gr that are located around the display area 21 and are non-display areas in which an image cannot be displayed.

[0013] The backlight 6 is provided below the display unit 2 (on the surface opposite to the surface displaying an image). The backlight 6 may be, for example, a so-called side-light type backlight having a light guide plate provided at a position corresponding to the display area 21 and a plurality of light sources arranged at one end or both ends of the light guide plate. For example, a light-emitting diode (LED) that emits light of a predetermined color is used as the light source. The backlight 6 may also be a so-called direct-type backlight having a light source (e.g., an LED) provided directly below the display area 21. Note that, although the display device 1 of this embodiment will be described using the backlight 6 provided below the display unit 2 as the light source, a front light provided above the display unit 2 may also be used.

[0014] Fig. 2 is a block diagram showing an example of a system of a display device. As shown in Fig. 2, a display area 21 has a matrix structure in which pixels SPX including a liquid crystal layer are arranged in m rows and n columns, each unit constituting one pixel on the display. In this embodiment, a row refers to a pixel row having n pixels SPX arranged in one direction. A column refers to a pixel column having m pixels SPX arranged in a direction perpendicular to the direction in which the rows are arranged. The values ​​of m and n are determined according to the display resolution in the vertical direction and the display resolution in the horizontal direction.

[0015] 2, an external signal to the driver IC 3 or driving power for driving the driver IC 3 is transmitted from a flexible printed circuit (FPC) (not shown). The first vertical driver 22A and the second vertical driver 22B (vertical driving circuits) are arranged to sandwich the display area 21.

[0016] The driver IC 3 has the functions of an interface (I / F) and a timing generator. The driver IC 3 generates a common potential (counter electrode potential) Vcom that is applied to the pixel electrodes 72 of each pixel SPX in common to each pixel, and applies the common potential Vcom to the display area 21. The driver IC 3 may be an integrated circuit integrated with the horizontal driver 23.

[0017] In the display area 21, a scanning line 24 is wired for each row of an m-row by n-column array of pixels SPX, and a signal line 25 is wired for each column. A first vertical driver 22A and a second vertical driver 22B sequentially output gate drive signals to the plurality of scanning lines 24 to select pixels SPX row by row. A horizontal driver 23 writes display data to each pixel SPX in the selected row via the signal line 25.

[0018] 3 is a circuit diagram showing an example of the configuration of a pixel of a display device. Wiring such as signal lines 25 that supply pixel signals as display data to transistors (TFTs: Thin Film Transistors) Tr of each pixel SPX shown in FIG. 3, and scanning lines 24 that drive each transistor Tr, are formed in the display area 21. Each pixel SPX includes a transistor Tr and a liquid crystal capacitance LC. In this example, the transistor Tr is configured as an n-channel MOS (Metal Oxide Semiconductor) TFT. One of the source electrode and drain electrode of the transistor Tr is connected to the signal line 25, the gate is connected to the scanning line 24, and the other of the source electrode and drain electrode is connected to one end of the liquid crystal capacitance LC. One end of the liquid crystal capacitance LC is connected to the transistor Tr, and the other end is connected to a common potential Vcom of the common electrode com.

[0019] The common potential Vcom of the common electrode com is connected to a drive electrode driver (not shown) and a voltage is supplied from the drive electrode driver. Furthermore, the pixel SPX is connected to other pixels SPX belonging to the same column in the display area 21 by the common potential Vcom of the common electrode com.

[0020] The scanning lines 24 and the signal lines 25 are arranged in areas overlapping with the black matrix 76a, which is in the same layer as the color filter 66 (see FIG. 4). Areas where the black matrix 76a is not arranged become openings 76b.

[0021] The color filter 66 (see FIG. 4) has color regions colored in three colors, for example, red (R), green (G), and blue (B), arranged periodically. The red (R), green (G), and blue (B) color regions of the color filter 66 are arranged corresponding to the openings 76b shown in FIG. 3. The pixel Pix includes three pixels SPX, and each pixel SPX is associated with a set of three color regions of R, G, and B. The pixel Pix is ​​formed by a set of pixels SPX corresponding to the three color regions. For this reason, the pixel SPX is also called a sub-pixel. The color filter 66 may include color regions of four or more colors. In this case, the pixel Pix may include four or more pixels SPX.

[0022] Fig. 4 is a cross-sectional view showing an example of a display unit. As shown in Fig. 4, the display unit 2 includes a TFT substrate SUB1, a counter substrate SUB2 disposed opposite to the surface of the TFT substrate SUB1 in a direction perpendicular to the surface of the TFT substrate SUB1, and a liquid crystal layer 54 interposed between the TFT substrate SUB1 and the counter substrate SUB2. A backlight 6 is disposed on the surface of the TFT substrate SUB1 opposite to the liquid crystal layer 54. In this specification, the direction from the TFT substrate SUB1 toward the counter substrate SUB2 is referred to as the upper side.

[0023] A large number of liquid crystals are dispersed in the liquid crystal layer 54. The liquid crystals in the liquid crystal layer 54 modulate light passing therethrough according to the state of the electric field, and are driven by liquid crystals in a transverse electric field mode such as FFS (fringe field switching) or IPS (in-plane switching).

[0024] The TFT substrate SUB1 has a substrate 71 which is a light-transmitting substrate such as glass, a first alignment film 62 laminated on the liquid crystal layer 54 side of the substrate 71, and a first polarizing plate 63 laminated on the side of the substrate 71 opposite the liquid crystal layer 54. The first alignment film 62 aligns the liquid crystal molecules in the liquid crystal layer 54 in a predetermined direction and is in direct contact with the liquid crystal layer 54. The first alignment film 62 is made of a polymer material such as polyimide, and is formed, for example, by applying a rubbing treatment to a coated polyimide. The first polarizing plate 63 has the function of converting light incident from the backlight 6 side into linearly polarized light.

[0025] The counter substrate SUB2 includes a substrate 64 which is a translucent insulating substrate such as glass, a color filter 66 formed on the liquid crystal layer 54 side of the substrate 64, a second alignment film 67 formed on the liquid crystal layer 54 side of the color filter 66, a retardation plate 68 formed on the side of the substrate 64 opposite the liquid crystal layer 54 side, and a second polarizing plate 69 formed on the side of the retardation plate 68 opposite the substrate 64 side.

[0026] The display device 1 may be provided with a cover member formed of a glass substrate or a resin substrate, a detection device such as a touch panel, and the like, as needed.

[0027] Next, the detailed configuration of the TFT substrate SUB1 will be described. Fig. 5 is a plan view schematically showing the relationship between transistors, scanning lines, and signal lines of the TFT substrate according to the first embodiment. As shown in Fig. 5, the plurality of scanning lines 24 each extend in a first direction Dx and are arranged side by side in a second direction Dy that intersects with the first direction Dx. The plurality of signal lines 25 each extend in the second direction Dy and are arranged side by side in the first direction Dx. The plurality of transistors Tr are provided near the intersections of the scanning lines 24 and the signal lines 25.

[0028] In the following description, the first direction Dx is a direction in a plane parallel to the substrate 71. The second direction Dy is a direction in a plane parallel to the substrate 71, and is a direction perpendicular to the first direction Dx. The second direction Dy may intersect the first direction Dx without being perpendicular thereto. The third direction Dz is a direction perpendicular to the first direction Dx and the second direction Dy, and is the normal direction to the main surface of the substrate 71. Furthermore, "planar view" refers to the positional relationship when viewed from a direction perpendicular to the substrate 71.

[0029] At least one of the multiple signal lines 25 is provided with a slit 25S, and the signal lines 25 are separated in the second direction Dy by the slit 25S. In other words, the length of the signal line 25 connected to one transistor Tr in the second direction Dy is shorter than the length of the display region 21 in the second direction Dy. The TFT substrate SUB1 also has a connection wiring 25B. The connection wiring 25B electrically connects one signal line 25 and the other signal line 25 adjacent to each other in the second direction Dy via the slit 25S. The one signal line 25 and the other signal line 25 adjacent to each other in the second direction Dy and separated by the slit 25S are formed in the same layer.

[0030] The positions, number, and arrangement pitch P1 of the slits 25S and the connection wirings 25B can be changed as appropriate. For example, in the example shown in Fig. 5, the slits 25S and the connection wirings 25B are provided in one signal line 25 that is located at the center in the first direction Dx among the multiple signal lines 25. This is not a limitation, and the slits 25S and the connection wirings 25B may be provided in all signal lines 25. Furthermore, it is sufficient that the slits 25S and the connection wirings 25B are provided in at least one location in one signal line 25. Alternatively, the slits 25S and the connection wirings 25B may be provided for each of the multiple pixels SPX in one signal line 25.

[0031] 6 is an enlarged plan view of region A shown in FIG. 5. FIG. 6 shows an enlarged view of two pixels SPX adjacent to each other in the first direction Dx. As shown in FIG. 6, the transistor Tr includes a semiconductor layer 90, a source electrode 25a, a drain electrode 25b, and a gate electrode 24G. The semiconductor layer 90 uses an oxide semiconductor as a semiconductor material, and for example, an oxide semiconductor layer such as zinc oxide (ZnO) or InGaO3 (ZnO) containing indium oxide, gallium oxide, and zinc oxide is used. m (m is a natural number) is used.

[0032] The semiconductor layer 90 extends in the first direction Dx along the scanning line 24. One end of the semiconductor layer 90 in the first direction Dx is connected to the source electrode 25a, and the other end is connected to the drain electrode 25b. The source electrode 25a is connected to the signal line 25 and branches off from the signal line 25 to extend in the first direction Dx. In other words, a portion of the signal line 25 functions as the source electrode 25a of the transistor Tr. In this manner, the signal line 25 is electrically connected to the semiconductor layer 90 made of an oxide semiconductor layer of the transistor Tr. The drain electrode 25b is formed in the same layer as the source electrode 25a and is electrically connected to the pixel electrode 72 via a through-hole SH1. In this embodiment, the scanning line 24 is a wiring made of a metal such as molybdenum (Mo) or aluminum (Al), and the signal line 25 is a wiring made of a metal such as aluminum.

[0033] The gate electrode 24G is connected to the scanning line 24 and branches off from the scanning line 24 to extend in the second direction Dy. The gate electrode 24G crosses a part of the semiconductor layer 90 at an intersection and functions as the gate of the transistor Tr. The gate electrode 24G and a part of the semiconductor layer 90 cross at one intersection, and the thin-film transistor Tr is a single-gate transistor having an n-channel channel region. Because the gate electrode 24G is located below the semiconductor layer 90, the structure of this thin-film transistor Tr is called a bottom-gate structure or an inverted staggered structure.

[0034] Each signal line 25 is separated by a slit 25S, and one signal line 25c and the other signal line 25d are arranged adjacent to each other in the second direction Dy. The connection wiring 25B extends along the signal line 25. One end of the connection wiring 25B in the second direction Dy is electrically connected to one signal line 25c through a contact hole CH1, and the other end is electrically connected to the other signal line 25d through a contact hole CH2. The connection wiring 25B is made of a metal material with good conductivity, such as a MAM (Mo / Al / Mo) film, which is a laminated film of molybdenum (Mo) and aluminum (Al), a TAT (Ti / Al / Ti) film, which is a laminated film of titanium (Ti) and aluminum (Al), or a Mo single layer film. The signal lines 25c, 25d, and the connection wiring 25B have contact portions in which contact holes CH1 and CH2 are formed. The contact portions are formed to be larger than the width (length in the first direction Dx) of each wiring other than the contact portions. This can prevent poor connection between the signal line 25 and the connection wiring 25B.

[0035] At positions other than the contact portions, the connection wiring 25B has the same width (length in the first direction Dx) as the signal line 25. This makes it possible to suppress variations in capacitance and resistance between the signal line 25 provided with the slit 25S and the connection wiring 25B and the signal line 25 not provided with the slit 25S and the connection wiring 25B.

[0036] The stacked structure of the signal line 25, the connection wiring 25B, and the transistor Tr will be described later with reference to FIG.

[0037] 7 is a cross-sectional view taken along the line VII-VII' in FIG. 6. FIG. 7 is a cross-sectional view schematically showing a connection portion between the drain electrode 25b and the pixel electrode 72. As shown in FIG. 7, a common electrode com, an insulating film 74a, the drain electrode 25b, an insulating film 74b, and a pixel electrode 72 are stacked in this order on a substrate 71. The pixel electrode 72 and the common electrode com are insulated by an insulating layer 74 (insulating films 74a and 74b) and face each other in a direction perpendicular to the surface of the substrate 71. The pixel electrode 72 and the common electrode com are formed of a translucent conductive material (translucent conductive oxide) such as ITO (Indium Tin Oxide). The insulating films 74a and 74b of this embodiment are made of SiN x (silicon nitride) or SiO x The insulating films 74a and 74b are inorganic insulating films of silicon oxide (SiO 2 ). The materials for forming the insulating films 74a and 74b are not limited to these. The insulating films 74a and 74b may be made of the same insulating material, or may be made of different insulating materials. Furthermore, the insulating films 74a and 74b are not limited to single-layer films, and may be made of, for example, SiN x (silicon nitride) or SiO x It may be formed of a laminated film of (silicon oxide).

[0038] A pixel electrode 72 is provided for each pixel SPX, and an opening SL is formed in each pixel electrode 72. As a result, of the electric field formed between the common electrode com and the pixel electrode 72, the electric field (fringe electric field) leaking from the opening SL of the pixel electrode 72 drives the liquid crystal.

[0039] 8 is a cross-sectional view taken along the line VIII-VIII' in FIG. 6. As shown in FIG. 8, a gate electrode 24G, an insulating film 74a, a semiconductor layer 90, a source electrode 25a, a drain electrode 25b, and an insulating film 74b are stacked in this order on a substrate 71, which is a light-transmitting insulating substrate. More specifically, the insulating film 74a is provided on the substrate 71, covering the gate electrode 24G. The semiconductor layer 90 is disposed on the gate electrode 24G via the insulating film 74a. A portion of the semiconductor layer 90 that overlaps with the gate electrode 24G is formed as a channel region.

[0040] The source electrode 25a and the drain electrode 25b are disposed on either side of the channel region of the semiconductor layer 90, and are provided on the semiconductor layer 90 so as to be in contact with the semiconductor layer 90. The signal line 25 formed continuously with the source electrode 25a is provided on the insulating film 74a. As described above, one signal line 25 is separated by the slit 25S into one signal line 25c and the other signal line 25d.

[0041] The insulating film 74b is provided to cover the source electrode 25a, the drain electrode 25b, the signal line 25, and the semiconductor layer 90. A contact hole CH1 is formed in the insulating film 74b in a region overlapping with one signal line 25c. A contact hole CH2 is formed in the insulating film 74b in a region overlapping with the other signal line 25d. Furthermore, no other conductor layer such as wiring is provided between the one signal line 25c and the other signal line 25d adjacent to each other in the second direction Dy (see FIG. 6) across the slit 25S, and the insulating film 74b is provided continuously. In other words, in the region overlapping with the slit 25S, the insulating film 74b is in contact with the insulating film 74a and is stacked on top of the insulating film 74a.

[0042] The connection wiring 25B is provided on the insulating film 74b, and one end side is electrically connected to one signal line 25c through a contact hole CH1, and the other end side is electrically connected to the other signal line 25d through a contact hole CH2.

[0043] Next, a method for manufacturing the TFT substrate SUB1 of this embodiment will be described. Figure 9 is a cross-sectional view that schematically shows a method for manufacturing the TFT substrate according to the first embodiment.

[0044] 9, the gate electrode 24G, the insulating film 74a, the semiconductor layer 90, and the signal line 25 (the source electrode 25a and the drain electrode 25b) are stacked in this order on the substrate 71 (step ST1). More specifically, a low-resistance metal film that forms the scanning line 24 is formed on the substrate 71 by sputtering, and the shape of the gate electrode 24G together with the scanning line 24 is patterned by etching.

[0045] Next, an insulating film 74a is formed on the gate electrode 24G. The insulating film 74a is formed by depositing SiN x is deposited to a predetermined thickness.

[0046] Next, a semiconductor layer 90 is formed on the insulating film 74a. The semiconductor layer 90 is made of, for example, ZnO or InGaO3 (ZnO). m The film is formed by CVD or sputtering using an oxide semiconductor material such as SiO 2 or the like, and is then patterned into a predetermined shape.

[0047] Next, a low-resistance metal film that forms the signal line 25 is formed by sputtering on the insulating film 74a, covering the semiconductor layer 90, and the shapes of the source electrode 25a and the drain electrode 25b are patterned by etching, along with the signal line 25. In the same process, a slit 25S is formed in the signal line 25, separating one signal line 25c from the other signal line 25d.

[0048] Next, an insulating film 74b is formed on the signal line 25, the source electrode 25a, and the drain electrode 25b (step ST2). The insulating film 74b is formed by, for example, depositing SiN x The insulating film 74b is formed to a predetermined thickness. Parts of the regions overlapping with the one signal line 25c and the other signal line 25d are removed by etching to form contact holes CH1 and CH2.

[0049] Next, a low-resistance metal film forming the connection wiring 25B is formed on the insulating film 74b by sputtering, and the shape of the connection wiring 25B is patterned by etching (step ST3). As a result, the connection wiring 25B is formed so as to be electrically connected to one signal line 25c through the contact hole CH1 and to the other signal line 25d through the contact hole CH2. In this way, the TFT substrate SUB1 is manufactured.

[0050] Next, with reference to Fig. 10 to Fig. 12, the effect of the configuration in which at least one signal line 25 is formed so as to be separated into multiple lines by slits 25S in the TFT substrate SUB1 of this embodiment will be described. Fig. 10 is an explanatory diagram for explaining a method for manufacturing a TFT substrate according to the first embodiment. Fig. 11 is a graph schematically showing the characteristic variation of transistors in the TFT substrate according to the first embodiment. Fig. 12 is an explanatory diagram for explaining a method for manufacturing a TFT substrate according to a comparative example. Fig. 13 is a graph schematically showing the characteristic variation of transistors in a TFT substrate according to a comparative example.

[0051] As shown in FIG. 10 , in the manufacturing process of the TFT substrate SUB1 according to the first embodiment, each of the steps described with reference to FIG. 9 is performed using a mother substrate 80. The mother substrate 80 has a plurality of planned chip formation regions 81 arranged thereon. Each of the plurality of planned chip formation regions 81 corresponds to a TFT substrate SUB1, and after the film-forming process shown in FIG. 9 , the mother substrate 80 is divided into each planned chip formation region 81, thereby forming a plurality of TFT substrates SUB1 from one mother substrate 80. Note that FIG. 10 is a schematic illustration for ease of viewing. In FIG. 10 , four planned chip formation regions 81 are arranged on the mother substrate 80, but this is not limiting, and five or more planned chip formation regions 81 may be arranged on one mother substrate 80.

[0052] 9, process variations occur in the central portion 80C, intermediate portion 80M, and peripheral portion 80E of the mother substrate 80. The process variations are caused by, for example, the plasma distribution in the CVD apparatus. For example, the plasma density may be high in the central portion 80C of the mother substrate 80, and decrease toward the peripheral portion 80E in that order.

[0053] 10 shows an enlarged view of one planned region 81 for forming individual pieces (TFT substrate SUB1) on the mother substrate 80. The process variations described above also occur within one planned region 81 for forming individual pieces. As an example, in the planned region 81 for forming individual pieces shown enlarged in FIG. 10, the plasma density increases in the order of region L1 (left side region) on one end side in the direction in which the signal lines 25 extend, region M1 in the middle, and region R1 (right side region) on the other end side.

[0054] 12, the TFT substrate SUB10 of the comparative example has a configuration in which the signal lines 25 are formed continuously from one end to the other end of the display region 21 without forming slits 25S. Similarly, in the mother substrate 80A of the comparative example, process variations occur in the central portion 80AC, the intermediate portion 80AM, and the peripheral portion 80AE. Similarly, in one planned region 81A for forming individual pieces (TFT substrate SUB10), the plasma density increases in the order of region L2 (left side region) on one end side in the extension direction of the signal lines 25, region M2 in the intermediate portion, and region R2 (right side region) on the other end side.

[0055] In this embodiment, as described above, at least one signal line 25 is separated into multiple lines by slits 25S. Therefore, the length of the signal line 25 connected to the semiconductor layer 90 of one transistor Tr is shorter than in the comparative example in which the slits 25S are not formed and the signal line 25 is continuously formed from one end to the other end of the display region 21.

[0056] 9, it is possible to suppress a shift in the oxidation degree of the semiconductor layer 90 of the transistor Tr via the signal line 25. For example, in a plurality of semiconductor layers 90 arranged along one signal line 25, it is possible to suppress a variation in the oxidation degree of the semiconductor layer 90 between a region L1 (left region) on one end side and a region R1 (right region) on the other end side.

[0057] More specifically, process variations may cause charge distribution in the signal line 25. In this case, in the comparative example, the longer the signal line 25 connected to the semiconductor layer 90 made of an oxide semiconductor, the more pronounced the variation in the oxidation degree of the semiconductor layer 90 becomes. On the other hand, in the present embodiment, the signal line 25 is separated by the slit 25S, so the length of the signal line 25 connected to the semiconductor layer 90 made of an oxide semiconductor can be shortened. Therefore, the distribution of charge in the signal line 25 connected to the semiconductor layer 90 is smaller than in the signal line 25 of the comparative example. As a result, in the present embodiment, the variation in the oxidation degree of the semiconductor layer 90 via the signal line 25 is suppressed.

[0058] Fig. 11 shows the VI characteristics of the transistors Tr in the one end region (left region) L1, the middle region M1, and the other end region (right region) R1 of the TFT substrate SUB1 of this embodiment shown in Fig. 10. Fig. 13 shows the VI characteristics of the transistors Tr in the one end region (left region) L2, the middle region M2, and the other end region (right region) R2 of the TFT substrate SUB10 of the comparative example shown in Fig. 12. In both Figs. 11 and 13, the horizontal axis represents the gate voltage and the vertical axis represents the drain current. Note that both Figs. 11 and 13 are graphs that merely schematically show the VI characteristics of the transistors Tr.

[0059] As shown in FIG. 11, in this embodiment, the variation in the degree of oxidation of the semiconductor layer 90 can be suppressed in the region L1 (left side region) on one end side, the region M1 in the middle, and the region R1 (right side region) on the other end side, thereby reducing the variation σ1 in the threshold voltage Vth of the transistor Tr.

[0060] 13, in the comparative example, the variation in the degree of oxidation of the semiconductor layer 90 via the signal line 25 increases in the region L2 (left side region) on one end side, the region M2 in the middle, and the region R2 (right side region) on the other end side, thereby increasing the variation σ2 in the threshold voltage Vth of the transistor Tr. The variation σ1 in this embodiment is 1.0 V or less, for example, about 0.1 V, while the variation σ2 in the comparative example is 1.0 V or more, for example, about 10 V.

[0061] As described above, in this embodiment, at least one signal line 25 of the TFT substrate SUB1 is separated into multiple lines by the slits 25S. This reduces the variation in the degree of oxidation of the semiconductor layer 90 via the signal line 25, which is dependent on the process variations for forming the semiconductor layer 90 made of an oxide semiconductor, the signal line 25, and the insulating film 74b shown in FIG. 9 . As a result, it has been demonstrated that it is possible to reduce the variation in the characteristics of the transistor Tr using the semiconductor layer 90 made of an oxide semiconductor. Note that the number, arrangement pattern, and arrangement pitch P1 of the slits 25S and the connecting wirings 25B can be appropriately changed depending on the process variations (e.g., plasma distribution in a CVD apparatus), the time constant of the signal line 25, etc.

[0062] (Variation) Fig. 14 is a plan view schematically showing the relationship between transistors, scanning lines, and signal lines in a TFT substrate according to a modification of Embodiment 1. As shown in Fig. 14, in the TFT substrate SUB1A (display device 1A) according to the modification, a plurality of connection wirings 25B, 25Ba are provided for each of a plurality of pixels SPX along the extending direction of the signal lines 25 (second direction Dy).

[0063] More specifically, the multiple connection wirings 25B, 25Ba are arranged side by side in the second direction Dy, overlapping one signal line 25. The connection wiring 25B is provided in a region overlapping with the slit 25S of the signal line 25. The connection wiring 25Ba is provided overlapping with a region of the signal line 25 where the slit 25S is not provided.

[0064] Fig. 15 is a cross-sectional view taken along the line XV-XV' in Fig. 14. As shown in Fig. 15, in the portion of the signal line 25 where the slit 25S is provided, similarly to the first embodiment described above, the connection wiring 25B is provided on the insulating film 74b, and one end side is electrically connected to one signal line 25c through a contact hole CH1, and the other end side is electrically connected to the other signal line 25d through a contact hole CH2.

[0065] In the portion of the signal line 25 where the slit 25S is not provided, the connection wiring 25Ba is provided on the insulating film 74b, and one end side is electrically connected to one of the signal lines 25c through the contact hole CH1, and the other end side is electrically connected to the same one of the signal lines 25c through the contact hole CH2. In other words, the connection wiring 25Ba is connected in parallel to the one of the signal lines 25c. This allows the TFT substrate SUB1A of the modified example to suppress the resistance value of the signal line 25.

[0066] For example, the connection wiring 25B (slit 25S) can be provided in one pixel SPX for every 15 pixels SPX aligned in the second direction Dy, and the connection wiring 25Ba can be provided in the other 14 pixels SPX for every 15 pixels SPX aligned in the second direction Dy. However, this is not limitative, and the number and arrangement pattern of the connection wirings 25B and 25Ba can be changed as appropriate depending on the above-mentioned process variations (for example, plasma distribution in a CVD apparatus), the time constant of the signal line 25, etc.

[0067] In the first embodiment and the modified example, the TFT substrates SUB1 and SUB1A are used in a display device 1 that uses liquid crystal elements as display elements, but the present invention is not limited to this. The TFT substrates SUB1 and SUB1A may be used in, for example, an organic EL display panel (OLED: Organic Light Emitting Diode), an inorganic EL display panel (micro LED, mini LED), or an electrophoretic display panel (EPD: Electrophoretic Display) that uses electrophoretic elements as display elements. The TFT substrates SUB1 and SUB1A may also be used in electronic devices other than the display device 1.

[0068] (Second embodiment) 16 is a plan view showing an example of a detection device having a TFT substrate according to the second embodiment. In the following description, the same components as those described in the above embodiments are denoted by the same reference numerals, and redundant description will be omitted.

[0069] In the second embodiment, a configuration will be described in which the TFT substrate SUB1B is employed in a detection device 100. The detection device 100 is an optical sensor having a PIN-type photodiode 130 as a sensor element. The detection device 100 is configured as a fingerprint sensor that can detect information such as a fingerprint based on light from a detection object such as a finger. Alternatively, the detection device 100 may be configured as a biosensor that detects, for example, blood vessel images, pulse waves, pulse rates, blood oxygen levels, etc. in a finger or palm.

[0070] As shown in FIG. 16, the detection device 100 includes a TFT substrate SUB1B (substrate 171), a sensor unit 110, a scanning line driving circuit 115, a signal line selection circuit 116, a detection circuit 148, a control circuit 102, and a power supply circuit 103.

[0071] A control substrate 501 is electrically connected to the TFT substrate SUB1B (substrate 171) via a wiring substrate 510. The wiring substrate 510 is, for example, a flexible printed circuit board or a rigid substrate. A detection circuit 148 is provided on the wiring substrate 510. A control circuit 102 and a power supply circuit 103 are provided on the control substrate 501. The control circuit 102 is, for example, an FPGA (Field Programmable Gate Array). The control circuit 102 supplies control signals to the sensor unit 110, the scanning line driving circuit 115, and the signal line selection circuit 116 to control the detection operation of the sensor unit 110. The power supply circuit 103 supplies voltage signals such as a power supply potential SVS and a reference potential VR1 (see FIG. 17 ) to the sensor unit 110, the scanning line driving circuit 115, and the signal line selection circuit 116.

[0072] The TFT substrate SUB1B has a detection area AA and a peripheral area GA. The detection area AA is an area where a plurality of photodiodes 130 of the sensor unit 110 are provided. The peripheral area GA is an area between the periphery of the detection area AA and the outer edge of the substrate 171, where a plurality of photodiodes 130 are not provided.

[0073] The scanning line driving circuit 115 and the signal line selection circuit 116 are provided in the peripheral area GA. Specifically, the scanning line driving circuit 115 is provided in a region of the peripheral area GA extending along the second direction Dy. The signal line selection circuit 116 is provided in a region of the peripheral area GA extending along the first direction Dx, and is provided between the sensor unit 110 and the detection circuit 148.

[0074] Each of the plurality of detection elements 135 of the sensor unit 110 is an optical sensor having a photodiode 130 as a sensor element. The photodiode 130 is a photoelectric conversion element that outputs an electrical signal according to the light irradiated thereon. More specifically, the photodiode 130 is a PIN (Positive Intrinsic Negative) photodiode. Alternatively, the photodiode 130 may be an OPD (Organic Photodiode) using an organic semiconductor. The plurality of detection elements 135 (photodiodes 130) are arranged in a matrix in the detection area AA.

[0075] The photodiodes 130 included in the multiple detection elements 135 perform detection in accordance with gate drive signals supplied from the scanning line drive circuit 115. The multiple photodiodes 130 output electrical signals corresponding to the light irradiated thereon as detection signals Vdet to the signal line selection circuit 116. The detection device 100 detects information related to the object to be detected based on the detection signals Vdet from the multiple photodiodes 130.

[0076] 17 is a circuit diagram showing a detection element of a TFT substrate according to the second embodiment. As shown in FIG. 17, the detection element 135 includes a photodiode 130, a capacitance element Ca, and a transistor TrS. The transistor TrS is provided corresponding to the photodiode 130. The transistor TrS is formed of a thin film transistor, and in this example, is formed of an n-channel MOS TFT. The gate of the transistor TrS is connected to the scanning line GLS. The source of the transistor TrS is connected to the output signal line SLS. The drain of the transistor TrS is connected to the anode of the photodiode 130 and the capacitance element Ca.

[0077] A power supply potential SVS is supplied to the cathode of the photodiode 130 from the power supply circuit 103. Furthermore, a reference potential VR1, which is the initial potential of the capacitance element Ca, is supplied from the power supply circuit 103 to the capacitance element Ca.

[0078] When light is irradiated onto the detection element 135, a current corresponding to the amount of light flows through the photodiode 130, causing charge to accumulate in the capacitance element Ca. When the transistor TrS is turned on, a current corresponding to the charge accumulated in the capacitance element Ca flows through the output signal line SLS. The output signal line SLS is connected to the detection circuit 148 via the signal line selection circuit 116. This allows the detection device 100 to detect a signal corresponding to the amount of light irradiated onto the photodiode 130 for each detection element 135.

[0079] 17 shows one detection element 1353, the scanning line GLS and the output signal line SLS are connected to a plurality of detection elements 135. Specifically, the scanning line GLS extends in a first direction Dx (see FIG. 16) and is connected to a plurality of detection elements 135 arranged in the first direction Dx. Furthermore, the output signal line SLS extends in a second direction Dy and is connected to a plurality of detection elements 135 arranged in the second direction Dy.

[0080] Although not shown, in the TFT substrate SUB1B of this embodiment, as in the first embodiment, at least one output signal line SLS is separated in the second direction Dy via a slit, and the output signal line SLS separated in the second direction Dy is electrically connected via a connection wiring 125B formed in a different layer.

[0081] Fig. 18 is a cross-sectional view schematically showing a TFT substrate according to the second embodiment. As shown in Fig. 8, the transistor TrS is configured by laminating a gate electrode 124G, an insulating film 174a, a semiconductor layer 190, a source electrode 125a, a drain electrode 125b, and an insulating film 174b in this order on a substrate 171, which is a light-transmitting insulating substrate. The semiconductor layer 190 uses an oxide semiconductor as a semiconductor material. The laminated structure of the transistor TrS is the same as that of the transistor Tr described above in Fig. 8, and therefore a repeated description will be omitted.

[0082] The photodiode 130 is disposed on the insulating film 174b. More specifically, the lower electrode 132, the photodiode 130, and the upper electrode 131 are stacked in this order on the insulating film 174b.

[0083] The lower electrode 132 is provided on the insulating film 174b and extends from a region overlapping with the photodiode 130 toward the transistor TrS. The lower electrode 132 is electrically connected to the drain electrode 125b via a contact hole CH12. The lower electrode 132 is the anode of the photodiode 130 and is an electrode for reading out the detection signal Vdet. The lower electrode 132 is provided in the same layer as the connection wiring 125B and is made of the same material as the connection wiring 125B, such as a metal material such as a MAM (Mo / Al / Mo) film, a TAT (Ti / Al / Ti) film, or a Mo single layer film. Alternatively, the lower electrode 132 may be a laminated film in which a plurality of these metal materials are laminated. The lower electrode 132 may also be made of a light-transmitting conductive material such as ITO.

[0084] The photodiode 130 includes an i-type semiconductor layer, an n-type semiconductor layer, and a p-type semiconductor layer as semiconductor layers. The i-type semiconductor layer, the n-type semiconductor layer, and the p-type semiconductor layer are formed of, for example, amorphous silicon (a-Si). Although not shown in the figure, the p-type semiconductor layer, the i-type semiconductor layer, and the n-type semiconductor layer are stacked in this order in the direction perpendicular to the surface of the substrate 171.

[0085] The n-type semiconductor layer is formed by doping impurities into a-Si to form an n+ region. The p-type semiconductor layer is formed by doping impurities into a-Si to form a p+ region. The i-type semiconductor layer is, for example, an undoped intrinsic semiconductor and has lower conductivity than the n-type and p-type semiconductor layers.

[0086] The upper electrode 131 is a cathode of the photodiode 130 and is an electrode for supplying a power supply potential SVS to the photoelectric conversion layer. The upper electrode 131 is a light-transmitting conductive layer such as ITO, and a plurality of upper electrodes 131 are provided for each photodiode 130.

[0087] Insulating films 175 and 176 are provided to cover the insulating film 174b and the lower electrode 132 extending from the photodiode 130. The insulating film 175 is, for example, an inorganic insulating film, and the insulating film 176 is, for example, an organic insulating film. The insulating films 175 and 176 cover the periphery of the upper electrode 131, and have openings provided in positions overlapping with the upper electrode 131. The power supply wiring 133 is connected to the upper electrode 131 in a region overlapping with the openings in the insulating films 175 and 176. An insulating layer 177 is provided on the insulating film 176 to cover the upper electrode 131 and the power supply wiring 133. An insulating layer 178, which is a planarizing layer, is provided on the insulating layer 177.

[0088] As described above, the detection device 100 having the TFT substrate SUB1B is configured. Note that the configuration of the detection device 100 is merely an example and can be modified as appropriate. For example, the lower electrode 132 of the photodiode 130 may be provided in a layer different from that of the connection wiring 125B.

[0089] Although preferred embodiments of the present invention have been described above, the present invention is not limited to such embodiments. The contents disclosed in the embodiments are merely examples, and various modifications are possible without departing from the spirit of the present invention. Appropriate modifications made without departing from the spirit of the present invention naturally fall within the technical scope of the present invention. At least one of various omissions, substitutions, and modifications of components can be made without departing from the spirit of each of the above-described embodiments and modifications. [Explanation of symbols]

[0090] 1, 1A display device 2 Display section 3 Driver IC 6 Backlight 11gr, 11gl surrounding area 21 Display area 22A 1st vertical driver 22B 2nd vertical driver 24, GLS scan line 24G, 124G gate electrode 25, 25c, 25d, SLS signal line 25a, 125a Source electrode 25b, 125b Drain electrode 25S slit 25B, 25Ba, 125B connection wiring 71, 171 board 72 pixel electrode 74a, 74b, 174a, 174b insulating film 80, 80A motherboard 81, 81A Individual formation area 90, 190 Semiconductor layer 100 Detection device 130 Photodiode 135 Detector element Pix, SPX pixel SUB1, SUB1A, SUB1B TFT substrates SUB2 opposing substrate Tr, TrS thin film transistor

Claims

1. A substrate; a plurality of transistors provided on the substrate, each including an oxide semiconductor layer; a plurality of scanning lines electrically connected to the gates of the plurality of transistors and extending in a first direction; a plurality of signal lines electrically connected to the oxide semiconductor layers of the plurality of transistors and extending in a second direction intersecting the first direction; an insulating film covering the signal lines and the oxide semiconductor layer; a connection wiring provided on the insulating film, At least one of the signal lines is separated in the second direction by a slit, the slit is not formed in another signal line adjacent to the at least one signal line, The connection wiring electrically connects one signal line and the other signal line adjacent to each other in the second direction via the slit. TFT substrate.

2. having a plurality of connection wires; The plurality of connection wirings are arranged side by side in the second direction, overlapping one of the signal lines, and are provided so as to overlap a region of at least one of the signal lines that overlaps with the slit and a region of the signal line where the slit is not provided. The TFT substrate according to claim 1 .

3. The connection wiring has the same width as the signal line. The TFT substrate according to claim 1 or 2.

4. No conductor layer is provided between the one signal line and the other signal line adjacent to each other in the second direction via the slit, and the insulating film is provided continuously. The TFT substrate according to claim 1 .

5. a step of laminating a plurality of scanning lines, an oxide semiconductor layer, and a plurality of signal lines in this order on a substrate, and forming a slit in at least one of the signal lines to separate the signal lines in an extending direction of the signal lines; forming an insulating film that covers the oxide semiconductor layer and the plurality of signal lines, and forming contact holes in the insulating film in regions that overlap with one signal line and the other signal line that are adjacent to each other with the slit interposed therebetween; forming a connection wiring on the insulating film and electrically connecting the one signal line and the other signal line through the contact hole, the slit is not formed in another signal line adjacent to the at least one signal line. A method for manufacturing a TFT substrate.

6. In the step of forming the connection wiring on the insulating film, The plurality of connection wirings are arranged side by side in the extending direction of one of the signal lines, overlapping one of the signal lines, and are provided so as to overlap a region of at least one of the signal lines that overlaps with the slit and a region of the signal line where the slit is not provided. The method for manufacturing a TFT substrate according to claim 5 .

7. The connection wiring is formed to have the same width as the signal line. The method for manufacturing a TFT substrate according to claim 5 or 6.

8. No conductor layer is provided between the one signal line and the other signal line adjacent to each other across the slit, and the insulating film is provided continuously. The method for manufacturing a TFT substrate according to any one of claims 5 to 7.

Images