Image sensing device and method of operation thereof

Abstract

To provide an image sensing device capable of reducing noise generation by setting an offset voltage for A / D (analog-to-digital) conversion on the basis of a readout pixel signal, and to provide an operation method of the same.SOLUTION: An image sensing device is provided with: a pixel array that includes unit pixels each transmitting and storing electric charges in response to a transmission signal and reading out a pixel signal corresponding to the stored electric charges in response to a selection signal; a signal converter that compares the pixel signal and a ramp signal on the basis of a switch signal to generate a distance information signal; and a signal controller that generates the switch signal in a section where the pixel signal is read out to initialize the signal converter.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to semiconductor design technology, and more particularly to an image sensing device and method of operation thereof. [Background technology]

[0002] An image sensing device is a device that captures images using the properties of semiconductors that react to light. Image sensing devices can be broadly divided into image sensing devices that use a CCD (Charge Coupled Device) and image sensing devices that use a CMOS (Complementary Metal Oxide Semiconductor). In recent years, image sensing devices that use CMOS have become more popular due to their advantage of being able to directly implement analog and digital control circuits on a single integrated circuit (IC). Summary of the Invention [Problem to be solved by the invention]

[0003] SUMMARY OF THE INVENTION An embodiment of the present invention provides an image sensing device and an operating method thereof that can reduce noise generation by setting an offset voltage for analog to digital (A / D) conversion based on a read pixel signal. [Means for solving the problem]

[0004] An image sensing device according to an embodiment of the present invention may include a pixel array including unit pixels that transfer and accumulate charges in response to a transfer signal and read out pixel signals corresponding to the accumulated charges in response to a selection signal; a signal converter that compares the pixel signal and a ramp signal based on a switch signal to generate a distance information signal; and a signal controller that generates the switch signal during a section in which the pixel signal is read out to initialize the signal converter.

[0005] According to another embodiment of the present invention, a method for operating an image sensing device may include the steps of: reading out first and second pixel signals corresponding to first and second charges accumulated in a unit pixel, respectively, in response to a selection signal; setting an offset voltage between the read-out first and second pixel signals and a ramp signal in response to a switch signal; resetting the first and second pixel signals in response to a transfer signal; and generating a distance information signal corresponding to a voltage change difference between the reset first and second pixel signals in response to the ramp signal. [Effects of the Invention]

[0006] The image sensing device according to an embodiment of the present invention can set an offset voltage for A / D (analog to digital) conversion based on a read pixel signal and perform A / D conversion while resetting the pixel signal. While setting the offset voltage and performing A / D conversion, a transistor included in a unit pixel, i.e., a driving transistor, can maintain the same state. Therefore, noise caused by a change in the threshold voltage of the transistor of the unit pixel, such as fixed pattern noise, can be eliminated, thereby improving the signal-to-noise ratio of a distance information signal generated from the image sensing device. [Brief explanation of the drawings]

[0007] [Figure 1] 1 is a block diagram illustrating an image sensing device according to an embodiment of the present invention. [Figure 2] 2 is a circuit diagram showing a unit pixel included in the pixel array shown in FIG. 1; [Figure 3] 2 is a block diagram showing the signal converter shown in FIG. 1. FIG. [Figure 4] 2 is a timing diagram illustrating the operation of the image sensing device shown in FIG. 1. FIG. [Figure 5]4 is a flowchart illustrating an operation of an image sensing device according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0008] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily carry out the technical concept of the present invention.

[0009] Throughout this specification, when a part is described as being "connected" to another part, this includes not only when the part is "directly connected" to another part, but also when the part is "electrically connected" to another part via another element therebetween. Furthermore, when a part is described as "including" or "comprising" a certain component, this does not mean that the part can further include or comprise other components, unless otherwise specified to the contrary. Furthermore, throughout this specification, even if some components are described as singular, it will be understood that the present invention is not limited to this, and that the component may consist of a plurality of components.

[0010] FIG. 1 shows a block diagram of an image sensing device according to an embodiment of the present invention.

[0011] 1, the image sensing device 100 can generate a distance information signal DOUT representing the depth of an object 200 using a time of flight (TOF) method. For example, the image sensing device 100 can generate the distance information signal DOUT by detecting a phase difference between a first optical signal MS output to the object 200 and a second optical signal RS reflected from the object 200. The image sensing device 100 can include an optical transmitter 110, an optical receiver 120, a signal controller 130, a pixel array 140, and a signal converter 150.

[0012] The optical transmitter 110 may output a first optical signal MS to the object 200. At this time, the first optical signal MS may be a periodic signal that toggles periodically.

[0013] The optical receiver 120 can receive a second optical signal RS reflected from the object 200. The optical receiver 120 can remove noise, such as ambient light, from the second optical signal RS and provide a third optical signal RS′ corresponding to the first optical signal MS to the pixel array 140.

[0014] The signal controller 130 may generate control signals MIXA / B, ROWs, SW, and VRAMP for controlling the pixel array 140 and the signal converter 150. As shown in FIG. 1 , the signal controller 130 may include a phase signal generator 132, a control signal generator 134, and a ramp signal generator 136.

[0015] The phase signal generator 132 may generate first and second phase signals MIXA and MIXB having different phases. For example, the first and second phase signals MIXA and MIXB may have a phase difference of 180 degrees, or other phase differences may be used. The first and second phase signals MIXA and MIXB may have the same period as the first optical signal MS, and one of the first and second phase signals MIXA and MIXB may have the same phase as the first optical signal MS, while the other may have a phase difference of 180 degrees.

[0016] The control signal generator 134 may generate a plurality of row signals ROWs for controlling each row of the pixel array 140. For example, the control signal generator 134 may generate a first row signal for controlling pixels arranged in a first row of the pixel array 140, and an nth row signal for controlling pixels arranged in an nth row of the pixel array 140 (where “n” is a natural number greater than 2). The control signal generator 134 may also generate a switch signal SW for initializing the signal converter 150.

[0017] The ramp signal generating unit 136 can generate a ramp signal VRAMP and transmit it to the signal converter 150. The ramp signal VRAMP can include a signal whose voltage level rises at a predetermined slope between a low voltage and a high voltage.

[0018] The pixel array 140 can generate a plurality of pixel signals VPXs based on the third optical signal RS', the first and second phase signals MIXA and MIXB, and a plurality of row signals ROWs. The pixel array 140 can include at least one unit pixel 142 for measuring the distance to the object 200. For example, the unit pixel can be selected based on the plurality of row signals ROWs and can generate first and second pixel signals VPX_A and VPX_B based on the first and second phase signals MIXA and MIXB and the third optical signal RS'. The configuration of such a unit pixel will be described in more detail with reference to FIG. 2.

[0019] The signal converter 150 can generate a distance information signal DOUT representing the distance to the subject 200 based on the multiple pixel signals VPXs. For example, the signal converter 150 can perform A / D (analog to digital) conversion on the first and second pixel signals VPX_A and VPX_B, respectively, and perform an operation on the A / D converted signals to generate the distance information signal DOUT.

[0020] Figure 2 shows a circuit diagram of a unit pixel included in the pixel array 140 shown in Figure 1. As shown in Figure 2, one unit pixel may include a pair of a first pixel TAPA and a second pixel TAPB.

[0021] The first pixel TAPA may generate a first pixel signal VPX_A based on a reset signal RX, a transfer signal TX, a selection signal SX, and a first phase signal MIXA. The reset signal RX, the transfer signal TX, and the selection signal SX may be signals included in the plurality of row signals ROWs. As shown in FIG. 2, the first pixel TAPA may include a first sensing circuit P1, a first reset circuit RT1, a first transfer circuit TT1, a first charge storage circuit C1, a first drive circuit DT1, and a first selection circuit ST1.

[0022] The first sensing circuit P1 may be connected between the first node N1 and the low voltage end. The first sensing circuit P1 may generate a first charge corresponding to the third optical signal RS' in response to the first phase signal MIXA. For example, the first sensing circuit P1 may include a photodiode. The photodiode may receive the third optical signal RS', convert it into a first digital signal associated with the first charge, and provide the converted first digital signal to the first node N1.

[0023] The first reset circuit RT1 may be connected between the high voltage terminal and the first node N1. The first reset circuit RT1 may reset the first sensing circuit P1 and the first charge storage circuit C1 in response to a reset signal RX. For example, the first reset circuit RT1 may include an NMOS transistor.

[0024] The first transfer circuit TT1 may be connected between the first node N1 and the first floating diffusion node FD1. The first transfer circuit TT1 may reset the first charge storage circuit C1 in response to a transfer signal TX and transfer a first charge generated from the first sensing circuit P1 to the first charge storage circuit C1. According to an embodiment of the present invention, the first transfer circuit TT1 may reset the first charge storage circuit C1 in response to the transfer signal TX during a readout period of the first pixel TAPA. For example, the first transfer circuit TT1 may include an NMOS transistor.

[0025] The first charge storage circuit C1 may be connected between the first floating diffusion node FD1 and the low voltage end. As described above, the first charge storage circuit C1 may be reset by the first transfer circuit TT1 during the readout period of the first pixel TAPA. For example, the first charge storage circuit C1 may include a parasitic capacitor and / or a capacitor added between the low voltage end and the first floating diffusion node FD1.

[0026] The first driver circuit DT1 can be connected between the high voltage terminal and the first select circuit ST1. The first driver circuit DT1 can drive the first column line COL1 with a high voltage supplied via the high voltage terminal based on the voltage applied to the first floating diffusion node FD1. For example, the first driver circuit DT1 can include an NMOS transistor.

[0027] The first selection circuit ST1 may be connected between the first driving circuit DT1 and the first column line COL1. The first selection circuit ST1 may selectively connect the first driving circuit DT1 and the first column line COL1 in response to a selection signal SX. For example, the first selection circuit ST1 may include an NMOS transistor.

[0028] The second pixel TAPB can generate a second pixel signal VPX_B based on the reset signal RX, the transfer signal TX, the selection signal SX, and the second phase signal MIXB. As shown in FIG. 2, the second pixel TAPB can include a second sensing circuit P2, a second reset circuit RT2, a second transfer circuit TT2, a second charge storage circuit C2, a second drive circuit DT2, and a second selection circuit ST2.

[0029] The second sensing circuit P2 may be connected between the second node N2 and the low voltage end. The second sensing circuit P2 may generate a second charge corresponding to the third optical signal RS' in response to the second phase signal MIXB. For example, the second sensing circuit P2 may include a photodiode. The photodiode may receive the third optical signal RS', convert it into a second digital signal associated with the second charge, and provide the converted second digital signal to the second node N2.

[0030] The second reset circuit RT2 may be connected between the high voltage terminal and the second node N2. The second reset circuit RT2 may reset the second sensing circuit P2 and the second charge storage circuit C2 in response to a reset signal RX. For example, the second reset circuit RT2 may include an NMOS transistor.

[0031] The second transfer circuit TT2 may be connected between the second node N2 and the second floating diffusion node FD2. The second transfer circuit TT2 may reset the second charge storage circuit C2 in response to a transfer signal TX and transfer the second charge generated from the second sensing circuit P2 to the second charge storage circuit C2. According to an embodiment of the present invention, the second transfer circuit TT1 may reset the second charge storage circuit C2 in response to the transfer signal TX during a readout period of the second pixel TAPB. For example, the second transfer circuit TT2 may include an NMOS transistor.

[0032] The second charge storage circuit C2 may be connected between the second floating diffusion node FD2 and the low voltage terminal. As described above, the second charge storage circuit C2 may be reset by the second transfer circuit TT2 during the readout period of the second pixel TAPB. For example, the second charge storage circuit C2 may include a parasitic capacitor.

[0033] The second driver circuit DT2 can be connected between the high voltage terminal and the second select circuit ST2. The second driver circuit DT2 can drive the second column line COL2 with a high voltage supplied via the high voltage terminal based on the voltage applied to the second floating diffusion node FD2. For example, the second driver circuit DT2 can include an NMOS transistor.

[0034] The second selection circuit ST2 may be connected between the second driving circuit DT2 and the second column line COL2. The second selection circuit ST2 may selectively connect the first driving circuit DT2 and the second column line COL2 in response to a selection signal SX. For example, the second selection circuit ST2 may include an NMOS transistor.

[0035] FIG. 3 is a block diagram illustrating an example of the signal converter 150 shown in FIG.

[0036] The signal converter 150 can generate a first count signal CNT1 and a second count signal CNT2 corresponding to the voltage level difference between the first pixel signal VPX_A and the second pixel signal VPX_B and the ramp signal VRAMP. The signal converter 150 can include the same configuration for processing the first pixel signal VPX_A and the second pixel signal VPX_B, and Fig. 3 representatively describes only the configuration for processing one of the first pixel signal VPX_A and the second pixel signal VPX_B.

[0037] 3, the signal converter 150 may include first and second input units C3 and C4, first and second switching units SW1 and SW2, a comparison unit 310, and a counting unit 320. Although not shown in FIG. 3, the signal converter 150 may further include a configuration, such as a logic operation unit, that performs an operation on the first count signal CNT1 and the second count signal CNT2 and outputs the difference between the count values ​​as the distance information signal DOUT.

[0038] The first input unit C3 can receive the first pixel signal VPX_A (or the second pixel signal VPX_B) and generate the input signal VIN_A or VIN_B. For example, the first input unit C3 can include a capacitor that samples the first pixel signal VPX_A (or VPX_B) and generates the input signal VIN_A or VIN_B.

[0039] The second input C4 can receive the ramp signal VRAMP to generate the reference signal VREF. For example, the second input C4 can include a capacitor that samples the ramp signal VRAMP to generate the reference signal VREF.

[0040] The comparator 310 may compare the input signal VIN_A or VIN_B with the reference signal VREF and output a comparison signal VOUTP_A or VOUTP_B. The comparator 310 may maintain the comparison signal VOUTP_A or VOUTP_B at a logic high or low level until the voltage level of the reference signal VREF becomes the same as that of the input signal VIN_A or VIN_B.

[0041] The first and second switching units SW1 and SW2 may be connected between the input node and the output node of the comparing unit 310. In response to a switch signal SW, the first and second switching units SW1 and SW2 may selectively connect the input node and the output node of the comparing unit 310. When the switch signal SW transitions, the first and second switching units SW1 and SW2 are turned on, thereby connecting the input node and the output node of the comparing unit 310.

[0042] The counting unit 320 may count the clock signal CLK in response to the comparison signal VOUTP_A or VOUTP_B and output the count signal CNT1 or CNT2. The counting unit 320 may output the count signal CNT1 or CNT2 having a count value corresponding to an interval during which the logic level of the comparison signal VOUTP_A or VOUTP_B is maintained.

[0043] FIG. 4 shows a timing diagram for explaining the operation of the image sensing device 100 shown in FIG.

[0044] 4, the first and second pixels TAPA and TAPB may perform a reset operation during a reset period RESET in response to a reset signal RX and a transfer signal TX. That is, when the reset signal RX is activated, the first sensing circuit P1 of the first pixel TAPA and the second sensing circuit P2 of the second pixel TAPB may be reset. Also, in response to the activation of the reset signal RX and the transfer signal TX, the first charge storage circuit C1 of the first pixel TAPA and the second charge storage circuit C2 of the second pixel TAPB may be reset.

[0045] Then, during the exposure period (EXPOSURE), the first and second pixels TAPA and TAPB can generate, transfer, and accumulate first and second charges based on the third light signal RS', the transfer signal TX, and the first and second phase signals MIXA and MIXB. For example, the first sensing circuit P1 can generate a first charge based on the third light signal RS' and the first phase signal MIXA. If the first transfer circuit TT1 of the first pixel TAPA transfers the first charge in response to the transfer signal TX, the first charge accumulation circuit C1 can accumulate the first charge. Similarly, the second sensing circuit P2 can generate a second charge based on the third light signal RS' and the second phase signal MIXB. If the second transfer circuit TT2 of the second pixel TAPB transfers the second charge in response to the transfer signal TX, the second charge accumulation circuit C2 can accumulate the second charge. At this time, the first phase signal MIXA and the second phase signal MIXB may have a phase difference of 180 degrees.

[0046] During the readout period READOUT of the first and second pixels TAPA and TATB, the reset signal RX and the select signal SX may be activated to a logic high level, and the first and second pixels TAPA and TATB may read out first and second pixel signals VPX_A and VPX_B corresponding to the first and second charges stored in the first and second charge storage circuits C1 and C2 in response to the select signal SX.

[0047] For example, in the first pixel TAPA, the first selection circuit ST1 may electrically connect the first driving circuit DT1 to the first column line COL1 in response to activation of the selection signal SX. The first driving circuit DT1 may read out the first pixel signal VPX_A by driving the first column line COL1 with a high voltage in response to the voltage applied to the first floating diffusion node FD1.

[0048] Similarly, in the second pixel TAPB, the second selection circuit ST2 can electrically connect the second driving circuit DT2 to the second column line COL2 in response to activation of the selection signal SX. The second driving circuit DT2 can read out the second pixel signal VPX_B by driving the second column line COL2 with a high voltage in response to the voltage applied to the second floating diffusion node FD2.

[0049] According to an embodiment of the present invention, the switch signal SW may transition between a logic low level and a logic high level at the beginning of the read period READOUT. The control signal generator 134 of the signal controller 130 activates the selection signal SX at the read period READOUT, and when the selection signal SX is activated, the switch signal SW may transition between a logic low level and a logic high level.

[0050] The signal converter 150 may be initialized in response to a transition of the switch signal SW. That is, the first and second switching units SW1 and SW2 may be turned on in response to a transition of the switch signal SW, thereby connecting the input node and the output node of the comparator 310. As a result, an offset voltage between the readout first and second pixel signals VPX_A and VPX_B and the ramp signal VRAMP may be stored in the first and second input units C3 and C4. Therefore, the initialization operation of the signal converter 150 may include an auto-zeroing operation that cancels out the input offset voltage of the comparator 310.

[0051] After the switch signal SW transitions, the control signal generator 134 of the signal controller 130 may activate the transfer signal TX. If the transfer signal TX is activated while the reset signal RX is at a logic high level during the readout period READOUT, the first and second pixel signals VPX_A and VPX_B may be reset. That is, the first and second reset circuits RT1 and RT2 and the first and second transfer circuits TT1 and TT2 may initialize the first and second charge storage circuits C1 and C2 in response to the activated reset signal RX and transfer signal TX. Therefore, the first and second pixel signals VPX_A and VPX_B, i.e., the input signals VIN_A and VIN_B, may increase by the reset voltage changes ΔVPX_A and ΔVPX_B.

[0052] After the transfer signal TX is activated, the ramp signal generator 136 of the signal controller 130 may generate a ramp signal VRAMP that gradually rises from a low voltage to a high voltage. The voltage level of the reference signal VREF may also rise in proportion to the ramp signal VRAMP. Therefore, the comparator 310 may compare the input signals VIN_A and VIN_B with the reference signal VREF, and maintain the comparison signals VOUTP_A and VOUTP_B at a logic high or logic low level until the voltage level of the reference signal VREF becomes the same as that of the input signals VIN_A and VIN_B.

[0053] That is, the counting unit 320 counts the clock signal CLK from the time when the reference signal VREF ramps to the time when the logic levels of the comparison signals VOUTP_A and VOUTP_B change, and generates first and second count signals CNT1 and CNT2 corresponding to the voltage changes ΔVPX_A and ΔVPX_B, respectively. The signal converter 150 operates on the first and second count signals CNT1 and CNT2, and outputs a distance information signal DOUT corresponding to the difference between the first and second charges generated in the first and second pixels TAPA and TATB.

[0054] FIG. 5 is a flowchart illustrating the operation of the image sensing device according to an embodiment of the present invention.

[0055] In step S510, the unit pixels of the pixel array 140 may read out first and second pixel signals VPX_A and VPX_B in response to a selection signal SX. During a readout period READOUT, the control signal generator 134 of the signal controller 130 may activate the selection signal SX to a logic high level. When the selection signal SX is activated, the first and second pixels TAPA and TATB may read out first and second pixel signals VPX_A and VPX_B corresponding to the first and second charges stored in the first and second charge storage circuits C1 and C2.

[0056] In step S520, the signal converter 150 may set an offset voltage between the readout first and second pixel signals VPX_A and VPX_B and the ramp signal VRAMP. After the selection signal SX is activated to a logic high level in the readout period READOUT, the control signal generator 134 may transition the switch signal SW between a logic low level and a logic high level. In response to the transition of the switch signal SW, the switching units SW1 and SW2 of the signal converter 150 are turned on, and the offset voltage between the readout first and second pixel signals VPX_A and VPX_B and the ramp signal VRAMP may be stored in the first and second input units C3 and C4.

[0057] In step S530, the unit pixels of the pixel array 140 may reset the first and second pixel signals VPX_A and VPX_B in response to the selection signal TX. After transitioning the switch signal SW, the control signal generator 134 may activate the transfer signal TX to a logic high level. When the transfer signal TX is activated, the first and second pixels TAPA and TATB may initialize the first and second charge storage circuits C1 and C2, and the first and second pixel signals VPX_A and VPX_B may be reset.

[0058] In step S540, the signal converter 150 generates a distance information signal DOUT corresponding to the difference between voltage changes ΔVPX_A and ΔVPX_B of the reset first and second pixel signals VPX_A and VPX_B in response to the ramp signal VRAMP. When the transfer signal TX is activated, the ramp signal generator 136 of the signal controller 130 gradually increases the ramp signal VRAMP from a low voltage to a high voltage.

[0059] The signal converter 150 can compare the rising ramp signal VRAMP with the reset first pixel signal VPX_A to generate a first count signal CNT1 corresponding to the voltage change ΔVPX_A. The signal converter 150 can also compare the rising ramp signal VRAMP with the reset second pixel signal VPX_B to generate a second count signal CNT2 corresponding to the voltage change ΔVPX_B. The signal converter 150 can perform an operation on the first count signal CNT1 and the second count signal CNT2 to generate a distance information signal DOUT corresponding to the difference between the voltage changes ΔVPX_A and ΔVPX_B.

[0060] Although the technical concept of the present invention has been specifically described by the above preferred embodiments, it should be noted that the above-described embodiments are for illustrative purposes only and are not intended to limit the scope of the present invention. Furthermore, those skilled in the art will understand that various embodiments can be implemented by various substitutions, modifications, and alterations within the scope of the technical concept of the present invention. [Explanation of symbols]

[0061] 100 Image sensing device 200 subjects 110 Light Transmitter 120 Optical Receiver 130 Traffic light controller 132 Phase signal generation section 134 Control signal generation unit 136 Ramp signal generator 140 pixel array 150 Signal Converter 310 Comparison Section 320 Counting Department

Claims

1. a pixel array including unit pixels that transfer and store charges in response to a transfer signal, and that read out pixel signals including a first pixel signal and a second pixel signal corresponding to the stored charges in response to a selection signal provided to the unit pixels; a signal converter that compares the pixel signal and the ramp signal based on a switch signal to generate a distance information signal; a signal controller that generates the switch signal during a temporary period in which the pixel signal is read out to initialize the signal converter; Equipped with the distance information signal is generated by comparing the first pixel signal and the second pixel signal with the ramp signal; The signal controller generates the selection signal that is activated during the temporary period for reading out the pixel signal, and when the selection signal is activated, transitions the switch signal between a first logic level and a second logic level.

2. The signal converter comprises: a first input section that receives the pixel signal and generates an input signal; a second input for receiving the ramp signal and generating a reference signal; a comparison unit that compares the input signal with the reference signal and outputs a comparison signal; a switching unit for selectively connecting the input node and the output node of the comparison unit in response to the switch signal; a counting unit that counts clock signals in response to the comparison signal; The image sensing device of claim 1 .

3. 3. The image sensing device of claim 2, wherein the switching unit is turned on in response to a transition of the switch signal to connect the input node and the output node of the comparator.

4. 2. The image sensing device of claim 1, wherein the signal controller generates the transfer signal that is activated when the switch signal transitions, and the unit pixel resets the pixel signal in response to the activated transfer signal.

5. The unit pixel is a charge storage circuit that stores the charge; a reset circuit that resets the charge storage circuit in response to a reset signal; a transfer circuit that transfers the charge to the charge storage circuit in response to the transfer signal; a selection circuit that generates the pixel signal corresponding to the charge stored in the charge storage circuit in response to the selection signal; The image sensing device according to claim 4 , comprising:

6. The image sensing device of claim 5 , wherein the signal controller generates the reset signal, which is activated simultaneously with the select signal, during a period in which the pixel signal is read out.

7. 7. The image sensing device of claim 6, wherein the reset circuit and the transfer circuit initialize the charge storage circuit in response to the activated reset signal and the activated transfer signal, respectively.

8. The image sensing device of claim 4 , wherein the signal controller generates the ramp signal that gradually rises from a low voltage to a high voltage when the transfer signal is activated.

9. The unit pixel is a first pixel that generates a first charge in response to a light signal and a first phase signal, and generates a first pixel signal corresponding to the first charge in response to the selection signal; a second pixel that generates a second charge in response to the optical signal and a second phase signal, and generates a second pixel signal corresponding to the second charge in response to the selection signal; 10. The image sensing device of claim 1, comprising:

10. The signal converter comprises: a first signal conversion unit that generates a first count signal corresponding to a voltage level difference between the first pixel signal and the ramp signal; a second signal conversion unit that generates a second count signal corresponding to a voltage level difference between the second pixel signal and the ramp signal; a logic operation unit that performs an operation on the first count signal and the second count signal and outputs a difference between the count values ​​as the distance information signal; The image sensing device of claim 9 , comprising:

11. The image sensing device of claim 9 , wherein the first and second phase signals have a phase difference of 180 degrees.

12. reading out first and second pixel signals corresponding to the first and second charges stored in the unit pixel in response to a selection signal; setting an offset voltage between the readout first and second pixel signals and a ramp signal in response to a switch signal; resetting the first and second pixel signals in response to a transfer signal; generating a distance information signal corresponding to a voltage change difference between the reset first and second pixel signals in response to the ramp signal; A method of operating an image sensing device, comprising:

13. 13. The method of claim 12, wherein the selection signal is activated during a period in which the first and second pixel signals are read out, and when the selection signal is activated, the switch signal transitions between a first logic level and a second logic level.

14. The method of claim 13 , wherein the transfer signal is activated when the switch signal transitions.

15. 15. The method of claim 14, wherein the ramp signal gradually rises from a low voltage to a high voltage when the transfer signal is activated.

16. The step of generating the distance information signal in response to the ramp signal includes: comparing the ramp signal with the reset first pixel signal to generate a first count signal corresponding to a voltage change of the reset first pixel signal; comparing the ramp signal with the reset second pixel signal to generate a second count signal corresponding to a voltage change of the reset second pixel signal; calculating the first count signal and the second count signal to generate the distance information signal; 13. A method of operating an image sensing device according to claim 12, comprising:

Images