Multilayer photonic devices with metastructure layers

Abstract

The aim is to improve the performance of photonic devices. A multilayer photonic device is described that includes an input region configured to receive an input signal, a multilayer stack optically coupled to the input region to receive the input signal, and an output region optically coupled to the multilayer stack to output an output signal. The multilayer stack may include a first metastructure dispersion region disposed in a first patterned layer of the multilayer stack and a second metastructure dispersion region disposed in a second patterned layer of the multilayer stack and optically coupled to the first metastructure dispersion region. The first metastructure dispersion region and the second metastructure dispersion region may together configure the multilayer stack to generate an output signal in response to the input signal.

Description

[Technical Field]

[0001] (CROSS-REFERENCE TO RELATED APPLICATIONS) This application claims the benefit of U.S. Patent Application No. 17 / 540,088, filed December 1, 2021, the contents of which are incorporated herein by reference.

[0002] FIELD OF THE INVENTION The present disclosure relates generally to photonic devices, and particularly, but not exclusively, to photonic integrated circuits including multilayer photonic devices. [Background technology]

[0003] Silicon-on-insulator (SOI) technology enables the fabrication of photonic devices using technology compatible with complementary metal oxide semiconductor (CMOS) processing systems. In this way, integrated circuits can be designed and fabricated to include both electronic and photonic components. Photonic integrated circuits can be designed to convert optical fiber signals, typically employed to transmit information over long distances, directly onto the chip to electronic signals, or vice versa. Therefore, SOI devices are limited by the space and manufacturability constraints imposed by semiconductor fabrication systems. Therefore, there is a need for SOI circuit components to implement optical processes, such as combining, routing, multiplexing, demultiplexing, interleaving, and / or deinterleaving, directly onto the chip, while also reducing the footprint of the SOI components. [Brief explanation of the drawings]

[0004] Non-limiting and non-exhaustive embodiments of the present invention are described with reference to the following figures, in which like reference numerals refer to like parts throughout the various views unless otherwise specified. Not every instance of an element is necessarily labeled, so as to avoid cluttering the figures where appropriate. The figures are not necessarily to scale, emphasis instead being placed upon illustrating the principles described. [Figure 1A] FIG. 1 is a functional block diagram illustrating a system for optical communication between two optical communication devices via optical signals, according to an embodiment of the present disclosure. [Figure 1B] 1B illustrates an example of the optical signal shown in FIG. 1A with individual channels comprising multiple channels of the optical signal arranged by wavelength, according to one embodiment of the present disclosure. [Figure 1C] 1C illustrates exemplary channels, characterized by distinct wavelengths, contained in the optical signal shown in FIG. 1B, according to one embodiment of the present disclosure. [Figure 2A] 1A-1C are schematic diagrams illustrating exemplary multilayer photonic devices including a multilayer stack of metastructure layers including non-uniformly distributed materials that together define a material interface pattern, according to embodiments of the present disclosure. [Figure 2B] 2B is a schematic diagram illustrating an example of the multilayer photonic device of FIG. 2A including a multilayer stack of meta-structure layers, according to an embodiment of the present disclosure. [Figure 2C] 2B including coupling to the interface device of FIG. 1 according to an embodiment of the present disclosure. [Figure 2D] 2B is a schematic diagram illustrating an example of the multilayer photonic device of FIG. 2A including a multilayer stack of metastructure layers including an input region on two patterned layers and an output region including two output portions, according to an embodiment of the present disclosure. [Figure 2E] 2D including a coupling to the interface device of FIG. 1 including a ridge waveguide and a rib waveguide, according to an embodiment of the present disclosure. FIG. [Figure 2F]FIG. 2B is a schematic diagram illustrating an example of the multilayer photonic device of FIG. 2A including a multilayer stack of meta-structure layers configured to apply multiplexing transformation, according to an embodiment of the present disclosure. [Figure 2G] FIG. 2F is another schematic diagram illustrating the example multiplexed waveguide coupler device of FIG. 2F including coupling to two input ridge waveguides and one output rib waveguide, in accordance with an embodiment of the present disclosure. [Figure 2H] FIG. 2B is a schematic diagram illustrating an example of the multilayer photonic device of FIG. 2A including a multilayer stack of metastructure layers configured to redirect input signals between patterned layers and multiplex or demultiplex input signals, in accordance with an embodiment of the present disclosure. [Figure 2I] FIG. 2H is another schematic diagram illustrating the example multi-layer photonic device of FIG. 2H including coupling to three ridge waveguides on two layers of a photonic integrated circuit in accordance with an embodiment of the present disclosure. [Figure 3A] FIG. 1 is a schematic diagram illustrating exemplary layers of a multilayer photonic device, including an input region, an output region, and a metastructure dispersive region, according to an embodiment of the present disclosure. [Figure 3B] FIG. 2 is a schematic diagram illustrating an exemplary multilayer stack of a multilayer photonic device including a metastructure patterned layer, according to an embodiment of the present disclosure. [Figure 3C] FIG. 1 is a schematic diagram illustrating an exemplary multilayer stack of a multilayer photonic device coupled with an input region in two metastructure patterned layers, according to an embodiment of the present disclosure. [Figure 3D] 1A-1C are schematic diagrams illustrating interfaces of an exemplary multilayer stack of a multilayer photonic device that together define a material interface pattern of a metastructure dispersive region, according to embodiments of the present disclosure. [Figure 4A] 2A-3D show an exemplary patterned layer of a multilayer stack as described with reference to FIGS. 2A-3D, including a plurality of features non-uniformly arranged to define a material interface pattern, according to an embodiment of the present disclosure. [Figure 4B]FIG. 1B is a schematic diagram illustrating an exemplary multilayer photonic device for coupling a waveguide on a first layer to a waveguide on a second layer of an SOI photonic circuit, including two patterned layers having different metastructure dispersion regions that define different material interface patterns including sloped sidewalls, according to an embodiment of the present disclosure. [Figure 4C] FIG. 1B is a schematic diagram illustrating an exemplary multilayer photonic device for coupling a waveguide on a first layer to a waveguide on a second layer of an SOI photonic circuit, the device including a patterned layer having multiple metastructure dispersion regions that define different material interface patterns with sloped sidewalls, in accordance with an embodiment of the present disclosure. [Figure 5] FIG. 1 is a functional block diagram illustrating a system for generating a design of a photonic integrated circuit, according to an embodiment of the present disclosure. [Figure 6] 1 illustrates an exemplary method for generating a design of a photonic integrated circuit, according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0005] Described herein are embodiments of photonic integrated circuits that include a multi-layer stack of metastructure layers, as well as methods for producing photonic integrated circuit designs. In the following description, numerous specific details are set forth to provide a thorough understanding of the embodiments. However, those skilled in the art will recognize that the techniques described herein can be practiced without one or more of the specific details, or with other methods, components, materials, etc. In other cases, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring certain aspects.

[0006] Throughout this specification, the references to "one embodiment" or "an embodiment" mean that a particular feature, structure, or characteristic described in connection with an embodiment is included in at least one embodiment of the present invention. Thus, the appearances of the phrase "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0007] As photonic device functionality improves and manufacturing tolerances improve to allow for smaller device feature sizes, it becomes increasingly important to maximize these improvements through optimized device designs to reduce size and cost while improving device functionality, performance, and robustness. Conventional photonic devices, such as those used in optical communications, are traditionally designed using simple guess-and-check methods or manually guided grid searches, in which a small number of design parameters from a given design or building block are tuned or configured for suitability for a particular application. However, optical elements and photonic devices can have design parameters ranging from hundreds to billions or more, depending on device size and functionality. This number of parameters results in poorly defined models that are not amenable to automated (e.g., non-human) optimization algorithms.

[0008] Described herein are embodiments of photonic integrated circuits (e.g., interlayer escalators, waveguide couplers, demultiplexers, filters, or combinations thereof) that can have designs obtained through an inverse design process using first-principles simulation to enable consideration of increased design parameters compared to traditional photonic device designs. More specifically, the techniques described herein can use gradient-based optimization in combination with first-principles simulation to generate designs based on the underlying physics expected to govern the operation of the photonic integrated circuit. However, it should be understood that in other embodiments, design optimization of photonic integrated circuits without gradient-based techniques can also be used. Advantageously, the embodiments and techniques described herein are not limited to conventional techniques for designing photonic circuits. Rather, the first-principles-based methodologies described herein can yield designs that surpass state-of-the-art designs in performance, size, and / or robustness. Furthermore, rather than being limited to a small number of design parameters that make up a feature space, e.g., to provide a fully defined system, the embodiments and techniques described herein can provide scalable optimization of a nearly unlimited number of design parameters.

[0009] To further optimize the design and improve the performance of a reverse-engineered photonic integrated circuit, the photonic integrated circuit can incorporate one or more multi-layer stacks of metastructure layers. These metastructure layers can be designed to collectively apply any transformation to an input signal as part of generating an output signal, which can be applied for a variety of purposes, including, but not limited to, coupling between waveguides of different shapes, steering optical signals between layers of an SOI chip, wavelength multiplexing / demultiplexing, wavelength-selective reflectivity, TE / TM isolation, neutral density attenuation, or any other function.

[0010] In the context of this disclosure, the term "metastructured" material or layer describes a composite material that affects electromagnetic radiation that impinges on or interacts with the material's nanostructured features. In contrast to regular and periodic photonic metamaterials, the nanostructured features of a metastructured material are irregular and / or non-uniform in size and distribution, defining characteristic material interface patterns between the constituent materials. Through the inverse design techniques described herein, multilayer metastructures can be designed to apply arbitrary transformations to an input signal using multiple metastructure layers defined by distinct material interface patterns as part of generating an output signal.

[0011] Advantageously, metastructure materials, unlike optical circuits composed of discrete optical elements such as lenses or diffraction gratings, do not apply individual transformations at specific locations within a photonic device. Instead, metastructure materials can transform an input signal through complex interactions with the interfaces that make up the material interface pattern, and no single interface in the material interface pattern is individually responsible for generating any one aspect of the output signal. By including multilayer metastructure materials, the photonic devices described herein can apply transformations within a relatively smaller footprint compared to conventional SOI photonic circuit elements. Additionally, metastructure materials can combine the functions of two or more conventional SOI photonic circuit elements to apply multiple transformations to an input signal within a single photonic device. Finally, the inverse design process allows photonic devices to be optimized for transmission loss, such that the devices and methods described herein can improve the performance of photonic devices.

[0012] 1A is a functional block diagram illustrating a system 100 for optical communication between two optical communication devices 101-A and 101-B via optical signals 110, according to an embodiment of the present disclosure. Optical communication device 101-A includes a controller 105, one or more electromagnetic (EM) radiation sources 111 (e.g., light-emitting diodes, lasers, etc.), one or more sensors 113 (e.g., photodiodes, phototransistors, photoresistors, etc.), one or more interface devices 115 (e.g., fiber optic couplers, light guides, waveguides, other optical elements, etc.), one or more multi-layer devices 117, one or more optical demultiplexers 119, and one or more optical multiplexers 121.

[0013] The controller 105 includes one or more processors 107 (e.g., one or more central processing units, application specific integrated circuits, field programmable gate arrays, tensor processing units, graphics processing units, or a combination thereof) and memory 109 (e.g., volatile memory (such as dynamic RAM or static RAM), non-volatile memory (such as flash memory), other types of memory, or a combination thereof). The memory 109 may include local memory 109 embedded in one or more memory devices and / or networked memory implemented on a distributed storage network. In some embodiments, the optical communication device 101-A also includes one or more photonic integrated circuits (see, e.g., FIGS. 2A-2I, 3A-3D, or 4A and 4B), which may be formed from one or more interface devices 115, one or more multilayer devices 117, or a combination thereof.

[0014] Controller 105 is configured to coordinate operation of optical communication device 101-A. More specifically, controller 105 may include instructions (e.g., as software instructions stored in memory 109 coupled to one or more processors 107, firmware instructions stored in memory included in one or more processors 107, and / or hardware instructions corresponding to an application specific integrated circuit, a field programmable gate array, etc.) that, when executed by controller 105, cause controller 105, optical communication device 101-A, and / or system 100 to perform operations. In some embodiments, the operations include modulating electromagnetic radiation via EM source 111 to encode information in individual channels corresponding to distinct wavelengths or modes of the modulated radiation to form optical signal 110, and transmitting optical signal 110 via interface device 115. In some embodiments, operations include receiving optical signal 110 through one or more interface devices 115, converting optical signal 110 by one or more photonic integrated circuits including multilayer device 117, and converting individual channels of optical signal 110 into electronic signals using sensor 113. Sensor 113 includes CMOS-compatible circuit elements that convert light to electricity, including, but not limited to, photodiodes. A multi-channel signal may be generated using multiplexer 121, and the individual channels may be separated using demultiplexer 119 at either end of the signal transmission. In some embodiments, multilayer device 117 may multiplex or demultiplex input signals, as described in more detail with reference to FIGS. 2A-2I.

[0015] In some embodiments, optical communication devices 101-A and 101-B may be separate, individual devices (e.g., an optical transceiver or transmitter communicatively coupled to a separate optical transceiver or receiver via one or more optical fibers). However, in other embodiments, optical communication devices 101-A and 101-B may be part of a single component or device (e.g., a smartphone, a tablet, a computer, a server, an optical communication device, etc.). For example, optical communication devices 101-A and 101-B may both be components on an integrated circuit formed as part of the integrated circuit and coupled to each other via a waveguide (e.g., a silicon waveguide) adapted to carry optical signals 110 between optical communication devices 101-A and 101-B.

[0016] It should be understood that the optical communication device 101-B may include the same or similar components as the optical communication device 101-A, which have been omitted for clarity. Additionally, it should be understood that any functionality described with reference to the optical communication device 101-A is equally applicable to the optical communication device 101-B. It should be further understood that the optical communication device 101-A may be configured as an optical receiver, an optical transmitter, or an optical transceiver, and that in some embodiments, certain components shown in FIG. 1A may be omitted from the optical communication device 101-A (e.g., depending on the target functionality). For example, in one embodiment, the optical communication device 101-A is configured as an optical receiver, and one or more EM sources 111 may be omitted. Additionally, it should be noted that certain elements of the optical communication device 101-A have been omitted to avoid obscuring certain aspects of the present disclosure. For example, the optical communication device 101-A may include an amplifier circuit, a lens, a coupler, or other components to facilitate transmission, reception, encoding, or decoding of the optical signal 110.

[0017] FIG. 1B illustrates an example of the optical signal 110 shown in FIG. 1A having multiple different wavelength channels 108 (e.g., a first channel 108-1, a second channel 108-2, a third channel 108-3, and a fourth channel 108-4) of the optical signal 110 arranged by wavelength, in accordance with an embodiment of the present disclosure. Wavelength-multiplexed optical fiber signals are used to increase the density (e.g., bandwidth) of the information carried by the optical signal 110. In some embodiments, the optical communication device 101 includes a multiplexer, a demultiplexer, and / or a multilayer device 109 to process the individual channels 108. For example, a multiplexed input signal may be routed to a multilayer device 109 on an input layer that demultiplexes the input signal into separate channels 108 that are output to a higher-level hosting sensor 113 to convert the optical signal to an electronic signal. Where conventional SOI technology includes separate elements for demultiplexing and cascading, the multilayer device 109 may implement both conversions in a single device.

[0018] The multiple channels 108 are shown in ascending order of wavelength (λ) relative to the transmission (T) of the optical signal 110. For example, in the illustrated embodiment, the second channel 108-2 has a wavelength greater than the wavelength of the first channel 108-1, and the third channel 108-3 has a wavelength greater than the wavelength of the second channel 108-2. Although the multiplexed signal includes four channels, it is understood that the optical signal 110 may include more or fewer channels 108, including, but not limited to, one channel 108, two channels 108, three channels 108, four channels 108, or more channels.

[0019] In some embodiments, each channel included in the plurality of channels 108 is characterized by a distinct wavelength (e.g., a center wavelength of the respective channel) that is different from one another. In other words, the first channel 108-1 is characterized by a first center wavelength, the second channel 108-2 is characterized by a second center wavelength, the third channel 108-3 is characterized by a third center wavelength, and so on. In some embodiments, the distinct wavelengths characterizing the channels 108 are separated by predetermined increments 112 (e.g., 5 nm, 10 nm, 20 nm, 50 nm, or any other suitable increment). In some embodiments, the distinct wavelengths characterizing the channels 108 include 1270 nm, 1280 nm, 1290 nm, and 1300 nm. In some embodiments, the distinct wavelengths characterizing the channels 108 include 1271 nm, 1291 nm, 1311 nm, 1331 nm, 1511 nm, 1531 nm, 1551 nm, 1571 nm, etc. Although only four channels are shown, it should be understood that more or less than four channels may be included in the plurality of channels 108.

[0020] 1C illustrates exemplary channels 108 (e.g., a first channel 108-1, a second channel 108-2, a third channel 108-3, or a fourth channel 108-4) included in the exemplary optical signal 110 of FIG. 1B that are characterized by distinct wavelengths, in accordance with an embodiment of the present disclosure. As illustrated, the exemplary channels 108 are separated by a center wavelength (λ N) in the passband region 118. In some embodiments, the center wavelength may be defined as the midpoint of the passband region (i.e., the region defined to be between PB1 and PB2), and the channel bandwidth 116 may be defined as the width of the passband region 118. It should be appreciated that in some embodiments, the passband region 118 may include ripple, as illustrated in FIG. 1C , corresponding to variations within the passband region 118. The ripple within the passband region 118 may be + / - 2 dB or less, + / - 1 dB or less, + / - 0.5 dB or less, etc. In some embodiments, the channel bandwidth 116 may be defined by the passband region 118. In other embodiments, the channel bandwidth 116 may be defined by the passband region 118. In other embodiments, the channel bandwidth 116 may be defined by the width of the passband region 118, where the measured power exceeds a threshold (e.g., dB th ) can be defined as the wavelength range above

[0021] 2A is a schematic diagram illustrating an exemplary multilayer photonic device 200 including a multilayer stack 205 of meta-structure layers including non-uniformly distributed materials that together define a material interface pattern, according to an embodiment of the present disclosure. The exemplary multilayer photonic device 200 is an example of the multilayer device 117 of FIG. 1 and may be implemented as part of a photonic integrated circuit, as described in more detail with reference to FIG. 1. The exemplary multilayer photonic device 200 includes the multilayer stack 205, an input region 210 optically coupled to the multilayer stack 205 at one or more patterned layers 215 of the multilayer stack 205, and an output region 225 optically coupled to the multilayer stack 205 at one or more patterned layers 215.

[0022] The patterned layers 215 are optically coupled to one another via the metastructure dispersive regions 220 that together comprise the exemplary multilayer photonic device 200 to receive an input signal 230 at an input region 210 and apply a transformation 240 to the input signal 230 that converts the input signal 230 to an output signal 235 at an output region 215. As described in more detail with reference to FIG. 1A , the exemplary multilayer photonic device 200 may be optically coupled to waveguides or other optical elements at the input region 210 and output region 225, which are described in the context of FIG. 1A as interface devices 115. In this manner, the input signal 230 or the output signal 235 may be an example of the optical signal 110.

[0023] 2A-4B , where N is a non-zero integer including, but not limited to, 1, 2, 3, 4, 5, 6, or more layers, to apply a transformation 240 to the input signal 230 through the collective effect of multiple interactions between the EM radiation of the input signal 230 and the metastructure dispersive layer 220. The input region 210 where the input signal 230 is coupled to the multilayer stack 205 may be located as part of a CMOS / SOI fabrication process in one or more patterned layers 215 of the multilayer stack 205.

[0024] For example, multi-layer stack 205 may include first patterned layer 215-1 and second patterned layer 215-2, where first patterned layer 215-1 defines an upper surface 217 and second patterned layer 215-2 defines a lower surface 219, with the second patterned layer optically coupled to upper surface 217 via lower surface 219. Each respective patterned layer 215 of multi-layer mask 205 may be optically coupled to another patterned layer 215 below and / or above the respective patterned layer 215, as described in more detail with reference to Figures 3A-3D. Input region 210 and output region 225 may be optically coupled to first patterned layer 215-1 and / or second patterned layer 215-2.

[0025] While patterned layer 215 and metastructure distribution regions 220 are shown as rectangular and of the same size, it is understood that each respective patterned layer 215 and / or metastructure distribution region 220 can occupy a different footprint in terms of both shape and dimensions. For example, first patterned layer 215 and / or first metastructure distribution region 220-1 can be rectangular, while second patterned layer 215-2 and / or second metastructure distribution region 220-2 can be trapezoidal. In some embodiments, multilayer stack 205 includes N cylindrical patterned layers 215. In some embodiments, multilayer stack 205 includes multiple rectangular patterned layers 215 including metastructure distribution regions 220 defining different cross-sectional shapes and dimensions. Defining the different shapes can form part of the design process for configuring multilayer stack 205 for applying transform 240.

[0026] Transform 240 describes the overall effect of the interaction of the input signal with metastructure dispersion region 220 in three dimensions, as described in more detail with reference to FIGS. 2B-2I, 3A-3D, and 4A-4B. Transform 240 is shown as an arbitrary function f(R), where R is a feature set of design parameters that describe the mask used to fabricate exemplary multilayer photonic device 200. Features in feature set R include, but are not limited to, materials of composition, layer thicknesses, layer sizes, input region locations, output region locations, output region sizes, input region sizes, number of input and / or output regions, and / or geometric descriptions of features of metastructure dispersion region 220. The mask described by features R can be modified and / or optimized as part of an inverse design process. The inverse design process used to arrive at the configuration and arrangement of materials to define metastructure dispersion region 220, input region 210, and output region 235 of exemplary multilayer photonic device 200 is described in more detail with reference to FIGS. 5 and 6.

[0027] Illustrative examples of structures configured to implement transformations 240 between multiple layers of a photonic integrated circuit are described with reference to FIGS. 2B-2I. Transformations 240 may include, but are not limited to, inter-layer redirection of an input signal 230 between patterned layers 215, coupling between different waveguides of a photonic integrated circuit, multiplexing, demultiplexing, mode selection, rotation, polarization, or combinations thereof. Advantageously, transformations 240 may describe multiple configuration transformations such that the exemplary multilayer photonic device 200 functions, for example, as a multiplexer coupling between different waveguides. Alternatively, transformations 240 may describe gradual amplification from lower patterned layers 215 to higher patterned layers 215 co-localized within a multilayer mask 205 by demultiplexing a multiplexed input signal 230 to output individual channels 108 of an optical signal 110 to different sensors 113. In contrast, conventional SOI photonic circuits typically include individual elements for each configuration transformation. Advantageously, multilayer photonic device 200 can reduce the footprint on the substrate dedicated to applying transformation 240 by combining multiple individual transformations into a single optical element that applies transformation 240 in three dimensions.

[0028] 2B is a schematic diagram illustrating an example multilayer photonic device 245 including a multilayer stack 205 of metastructure layers 215 in accordance with an embodiment of the present disclosure. The example multilayer photonic device 245 is an implementation of the multilayer photonic device 200 and can be incorporated into the optical communication device 101-A as the multilayer device 117 of FIG. 1 . The example multilayer photonic device 245 includes an input region 210, a first patterned layer 215-1, a second patterned layer 215-2, and an output region 225. The first patterned layer 215-1 includes a first metastructure dispersive region 220-1 optically coupled to the input region 210 to receive the optical signal 110. The output region 225 is optically coupled to the second metastructure dispersive region 220-2 to output the optical signal 110 at the second patterned layer 215-2 of the multilayer stack 205.

[0029] In some embodiments, the exemplary multi-layer photonic device 245 is configured to bring the optical signal 110 from a lower layer of an SOI photonic integrated circuit dedicated to communicating the optical signal to an upper layer of the SOI photonic integrated circuit dedicated to converting the optical signal to an electronic signal. In this manner, the multi-layer mask 205 and the configured metastructure dispersing regions 220 may be configured to apply the transformation 240 to the optical signal 110 without affecting the information encoded in the optical signal 110. For example, the first metastructure dispersing region 220-1 may be configured to generate a throughput signal 250 in response to the optical signal 110, and the second metastructure dispersing region 220-2 may be configured to generate an output signal 235 in response to the throughput signal 250. When the optical signal 110 includes multiple distinct wavelength channels 108, the transformation 240 may preserve the channels 108 across the exemplary multi-layer photonic device 245, but may also filter the optical signal to select distinct channels 108, remove one or more channels 108, or attenuate one or more channels.

[0030] 2C is another schematic diagram illustrating the exemplary multilayer photonic device 245 of FIG. 2B including coupling to the interface device of FIG. 1 in accordance with an embodiment of the present disclosure. The exemplary multilayer photonic device 245 is shown integrated into a photonic integrated circuit including waveguides 255. For example, the waveguides 255 may be implementations of the interface device 115 of FIG. 1A disposed in different layers of the photonic integrated circuit components of the optical communication devices 101-A and 101-B. For example, the first waveguide 255-1 may be a ridge waveguide between the exemplary multilayer photonic device 245 and another optical component of the photonic integrated circuit, while the second waveguide 255-1 may be a ridge waveguide between the exemplary multilayer photonic device 245 and the sensor 113.

[0031] The transformation 240 in the context of the exemplary multilayer photonic device 245 may include redirecting the input signal 230 from a first direction of travel within the first waveguide 255-1 to a second direction of throughput signal 250 between the input region 210 and the output region 225. The output signal 235 may be output in a third direction, which may be aligned with the first direction of the input signal 230 or any different direction. In some embodiments, the exemplary multilayer photonic device 245 is configured to apply the transformation 240 to reflect or redirect at least a portion of the input signal or direct the throughput signal away from the first direction, such that the output signal 235 is coupled out of the output region 225 at an angle relative to the first direction in the xy plane. In this manner, the effective path length through the multilayer mask 205 may be a function of the number of patterned layers 215. For example, the output region 225 may be located on the same side of the multilayer mask 205 as the input region 210, but in a different patterned layer 215.

[0032] 2D and 2E are schematic diagrams illustrating an example multilayer photonic device 260 including a multilayer stack of metastructure layers 215, including an input region on two patterned layers and an output region including two output portions, in accordance with an embodiment of the present disclosure. The example multilayer photonic device 260 is configured to couple an optical signal, such as the optical signal 110 of FIG. 1A, between waveguides 255 of different cross sections. For example, the example multilayer photonic device 260 may include an output region 225 having a first output portion 225-1 and a second output portion 225-2, each coupled to a corresponding metastructure dispersive region 220. In the illustrated embodiment, the first output portion 225-1 is wider than the second output portion 225-2, while the input region 210 has a consistent width in both the first patterned layer 215-1 and the second patterned layer 215-2. Thus, the first metastructure dispersive region 220-1 can be configured to transform the input signal 230 from the first width 227-1 of the input region 210 to the second width 227-2 of the second output portion 225-2. In this manner, the multilayer photonic device 260 can couple the input signal 235 from the first waveguide 255-1 to the second waveguide 255-2, where the first waveguide 255-1 and the second waveguide 255-2 have different cross sections. The example shown in FIGS. 2D and 2E describes an exemplary multilayer photonic device 260 configured to apply a "ridge" to "rib" waveguide coupler transition 240. Ridge-rib coupling is useful when the optical signal 110 is transmitted over a relatively long distance in the second waveguide 255-2 or when a relatively small radius bend of the optical signal 110 is implemented in the first waveguide 255-1. The rib waveguide reduces losses caused by sidewall dimension variations that can result from the nanoscale geometry of the waveguide 255. For example, designs that approach the resolution limits of optical lithography, deposition, and etching processes can leave sidewall dimension variations.

[0033] Ridge-rib waveguide coupling at least partially improves signal loss over distance because the optical signal interacts with the material interface along only a portion of second waveguide 255-2. Additionally, metastructure dispersive region 220-1 can be configured to couple waveguides 255 without introducing additional optical modes into output signal 235 that may occur when first width 227-1 of first output portion 227-1 exceeds a given width. In an exemplary embodiment, if input signal 230 includes wavelength channel 108 at 1550 nm, first width 227-1 can be approximately 750 nm or less and second width 227-2 can be approximately 450 nm or less without introducing additional optical modes into output signal 235.

[0034] The transformation 240 can apply effects from each layer to the input signal 230, but can also include inter-layer effects that improve performance compared to conventional optical elements designed to apply similar transformations. For example, the metastructure dispersive region 220 can optically transmit and redirect portions of the input signal 230 between layers through a throughput signal 250 at one or more locations within the patterned layer 215, as described in more detail with reference to FIG. 2B . In this manner, the overall size and footprint of the exemplary multilayer photonic device 260 can be reduced compared to homogeneous optical elements such as tapered adiabatic waveguide couplers. It is understood that coupling between different waveguides 255 can represent a component of the overall transformation 240. For example, the transformation 240 can include coupling between a first waveguide 255-1 and a second waveguide 255-2, as well as multiplexing, demultiplexing, rotation, mode selection, TE-TM mode conversion, or other transformations typically applied with separate optical elements.

[0035] 2F and 2G are schematic diagrams illustrating an exemplary multilayer photonic device 265 including a multilayer stack 205 of meta-structure layers 215 configured to apply multiplexing conversion, according to embodiments of the present disclosure. In FIG. 2F, a second input signal 230-2 is coupled to the exemplary multilayer photonic device 265 at a second input region 210-2 so as to be multiplexed with the first input signal 230-1 coupled to the first patterned layer 215-1 at a first input region 210-1. Similar to the exemplary photonic device 260, the output region 225 includes a first output portion 225-1 and a second output portion 225-2, such that the multiplexed output signal 235 can be transmitted over relatively long distances with reduced loss.

[0036] As part of the transformation 240, the metastructure distribution region 220 may be configured to multiplex the first input signal 230-1 and the second input signal 230-2 across both patterned layers 215-2, as described in more detail with reference to Figures 3A-4B. The transformation 240 is applied through multiple individual interactions with nanoscale interfaces defined by features of the metastructure distribution layer 220. Thus, the multiplexing and beam-forming components of the transformation 240 may be applied collectively by the first patterned layer 215-1 and the second patterned layer 215-2 and may be distributed across the metastructure distribution region 220 rather than being localized in one or more regions of the multi-layer mask 205.

[0037] The exemplary multilayer device 265 is shown with a first input signal 230-1 coupled from a first waveguide 255-1 to a first input region 210-1, and a second input signal 230-2 coupled from a third waveguide 255-3 to a second input region 210-2. The combined effect of the interaction of the first and second input signals 230-1 and 230-2 with the metastructure dispersive region 220 of the patterned layer 215 couples the output signal 230 to a second waveguide 255-2, which is shown as a rib waveguide configured to carry the multiplexed output signal 230.

[0038] 2H and 2I are schematic diagrams illustrating an exemplary multilayer photonic device 270 including a multilayer stack 205 of meta-structure layers 215 configured to redirect input signals between patterned layers and multiplex or demultiplex input signals in accordance with an embodiment of the present disclosure. Multiplexing and demultiplexing are techniques used in optical systems to increase the information density of optical signals, as described in more detail with reference to FIGS. 1A-1C. Individual channels 108 may be multiplexed or demultiplexed by the exemplary device 270 as part of an overall conversion 240 that includes inter-layer redirection of a throughput signal 250. The exemplary device 270 includes first and second input regions 210-1 and 210-2 disposed on a first patterned layer 215-1 and an output region 225 disposed on a second patterned layer 215-2.

[0039] In exemplary device 270, first metastructure distribution region 220-1, second metastructure distribution region 220-2, or a combination thereof, may be configured to multiplex input signal 230. Similar to exemplary device 245, exemplary device 270 may include a multi-layer mask 205 that defines a volumetric interaction with input signal 230 that collectively applies a transform 240 across the volume of metastructure distribution regions 220.

[0040] In some embodiments, exemplary device 270 is configured to function as a multiplexer or demultiplexer. For example, output signal 235 from a first instance of exemplary device 270 can serve as input signal 230 to a second instance of exemplary device 270, such that a multiplexed signal is received, redirected from second patterned layer 215-2 to first patterned layer 215-1, and demultiplexed into multiple output regions 225. The output regions 225 can be coupled to different waveguides 255 such that exemplary multilayer photonic device 270 can be optically coupled to first waveguide 255-1 and third waveguide 255-3 in first patterned layer 215-1 and optically coupled to second waveguide 255-2 in second patterned layer 215-2.

[0041] 2I, the double-headed arrow is used to illustrate that the exemplary device 270 can be configured to either multiplex two input signals or demultiplex one multiplexed input signal, as well as redirect signals between layers of an SOI photonic integrated circuit. It is understood that a single exemplary device 270 may be capable of bidirectional multiplexing / demultiplexing, but it is also understood that mapping different transformations 240 onto the multilayer photonic device 270 during the reverse engineering process may result in different metastructure dispersion regions 220 that are not bidirectional.

[0042] As described in more detail with reference to FIGS. 2A-2I, designing multilayer photonic devices 200, 245, 265, and 270 can include a mapping transformation 240 between input region 210 and output region and optimization of metastructure region 220 as part of a multi-step iterative inverse design process. As a result, metastructure region 220 includes multiple features arranged according to an irregular and non-uniform distribution described by a mask. The mask, in turn, can include a binary mask or a more complex mask to describe detailed aspects of the metastructure distribution region, as described in more detail below with reference to FIGS. 3A-4D.

[0043] 3A is a schematic diagram illustrating exemplary layers of a multilayer photonic device 320, according to an embodiment of the present disclosure. FIG. 3A illustrates a cross-sectional view of the multilayer photonic device 320 along a lateral plane within the patterned layer 306 defined by a width 321 and a length 323 of the multilayer photonic device 320. As illustrated, the multilayer photonic device 320 includes an input region 324 (e.g., corresponding to the input region 210 illustrated in FIGS. 2A-2I), an output region 326 (e.g., corresponding to the output region 225 illustrated in FIGS. 2A-2I), and a metastructure dispersion region 330 disposed between the input region 324 and the output region 326.

[0044] The input region 324 and the output region 326 may correspond to a waveguide (e.g., a slab waveguide, a strip waveguide, a slot waveguide, a ridge waveguide, a rib waveguide, etc.) optically coupled to the metastructure dispersive region 330 and capable of propagating EM radiation along the path of the waveguide. The metastructure dispersive region 330 includes a non-uniform, irregular distribution of a first material 332 (e.g., silicon, silicon nitride, etc.) and a second material 334 (e.g., silicon oxide), each defining a plurality of interfaces corresponding to a change in the refractive index of the metastructure dispersive region 330, and collectively comprising the metastructure dispersive region 330 to apply at least a portion of any transformation to the input signal 230 received at the input region 324. As described in more detail with reference to FIGS. 2A-2I , the transformation applied as part of generating the output signal 235 may result from the combined effect of the patterned layers 215 of the multilayer stack 205, such that a particular aspect of the transformation cannot be attributed to one particular patterned layer 215. Instead, the metastructure distribution region 330 may participate in generating the output signal 235 together with other constituent metastructure distribution regions 220 of the multilayer stack 205. In a two-layer stack demultiplexing escalator embodiment, the first metastructure distribution region 220-1 and the second metastructure distribution region 220-1 may together constitute the multilayer stack 205 to separate the input signal 230 received at the first patterned layer 215-1 into multiple channels and direct each of the channels to one of several output regions 225 of the second patterned layer 215-2.

[0045] The metastructure dispersion region 330 of the multilayer photonic device 320 has a fixed area (e.g., defined by a width 325 and a length 327) laterally surrounded by a peripheral region 322 formed by a second material 334. It should be understood that in some embodiments, the second material 334 included in the peripheral region 322 of the multilayer photonic device 320 and proximate to the metastructure dispersion region 330 extends continuously around the metastructure dispersion region 330, except for the input region 324 and the output region 326. In some embodiments, the peripheral region 322 comprises a homogenous composition of the second material 334. In the illustrated embodiment, the metastructure dispersion region 330 includes a first side 331 and a second side 333, each having an interface with an inner boundary (i.e., the unlabeled dashed line of the peripheral region 322 disposed between the metastructure dispersion region 330 and the dash-dotted line corresponding to the outer boundary of the peripheral region 322). First side 331 and second side 333 correspond to opposite sides of metastructure distribution region 330. Input region 324 is positioned proximate first side 331 (e.g., one side of input region 324 abuts first side 331 of metastructure distribution region 330), while output region 326 is positioned proximate second side 333 (e.g., one side of output region 326 abuts second side 333 of metastructure distribution region 330).

[0046] The output region 326 is aligned with the input region 324, but may also be disposed at an angle relative to the input region 324. Similarly, one or more of the output region 326 and / or input region 324 may be disposed proximate to a side of the metastructure dispersion region 330 adjacent the first side 331 and / or the second side 333. In some embodiments, the multilayer photonic device includes multiple input regions 324 and / or multiple output regions 326. In some cases, the input regions 324 and / or output regions 326 may be separated by a distance corresponding to less than 50 μm, less than 30 μm, less than 10 μm, less than 5 μm, less than 2 μm, less than about 1.1 μm, etc. Advantageously, separating the input regions 324 and / or output regions 326 along each side of the metastructure dispersion region 330 improves isolation of the channels 108 and reduces crosstalk.

[0047] It should be noted that the first material 332 and the second material 334 of the metastructure dispersion region 330 are positioned and shaped within the metastructure dispersion region 330 such that the resulting material interface pattern is substantially proportional to the design resulting from the inverse design process, as described in more detail with reference to FIG. 6 . In some embodiments, the inverse design process includes iterative optimization of the design (e.g., gradient-based, etc.) based at least in part on a loss function that incorporates performance losses (e.g., to achieve function) and manufacturing losses (e.g., to achieve manufacturability and binarization of the first and second materials) that are collectively reduced or iteratively adjusted until a design within a target specification that is also manufacturable is obtained. Additionally and / or alternatively, other optimization techniques may be used in place of or in conjunction with gradient-based optimization. Advantageously, this enables optimization of a nearly unlimited number of design parameters to achieve function and performance within a given area that is not achievable with traditional design techniques.

[0048] The metastructure dispersion region 330 may be formed in an optical cavity having a fixed area of ​​less than 100 μm×100 μm, less than 35 μm×35 μm, etc. Accordingly, the fixed area of ​​the metastructure dispersion region 330 may be greater than 3 μm×3 μm. In some embodiments, the width 325 of the metastructure dispersion region 330 may be less than 100 μm, less than 50 μm, less than 35 μm, less than 20 μm, less than 10 μm, less than 5 μm, about 3.2 μm, etc. The length 327 of the metastructure dispersion region 330 may be less than 100 μm, less than 50 μm, less than 35 μm, less than 10 μm, about 6.4 μm, etc. As shown, the metastructure dispersion region 330 has a square area with a width 325 substantially equal to (e.g., at least 1%, 5%, or 10%) the length 327. The metastructure dispersion region 330 may have different lengths and widths (e.g., rectangular, octagonal, circular, oval, oblong, etc.). For example, the width 325 and length 327 of the metastructure dispersion region 330 may be 3.2 μm and 6.4 μm, respectively. In some embodiments, the input region 324 and the output region 326 may have a common width (e.g., parallel to the direction of the width 325) that may correspond to less than 1 μm, less than 0.5 μm, about 0.4 μm, etc. In some embodiments, the input region 324 and the output region 326 may have different widths, as described in more detail with reference to FIGS. 2D-2G.

[0049] FIG. 3B is a schematic diagram illustrating an exemplary multilayer stack 205 of a multilayer photonic device 320 including a metastructure patterned layer, according to an embodiment of the present disclosure. FIG. 3B illustrates a vertical schematic view, or stack, of various layers included in the illustrated embodiment of the multilayer photonic device 320 of FIG. 3A. However, it should be understood that the illustrated embodiment is not exhaustive, and certain features or elements may be omitted to avoid obscuring aspects of the invention. The multilayer stack 205 includes a substrate 302, a dielectric layer 304, a plurality of patterned layers 306 (e.g., as shown in the cross-sectional view of FIG. 3A), and a cladding layer 308. In some embodiments, the multilayer photonic device 320 may be a photonic integrated circuit or a silicon photonic device that is partially or otherwise compatible with CMOS fabrication techniques (e.g., photolithography, electron beam lithography, sputtering, thermal evaporation, physical and chemical vapor deposition, etc.).

[0050] In one embodiment, a silicon-on-insulator (SOI) wafer may be provided that includes sequentially stacked layers including a support substrate (e.g., a silicon substrate), a silicon oxide layer, and a silicon layer (e.g., doped silicon, undoped silicon, etc.). The support substrate of the SOI wafer may correspond to substrate 302. The silicon oxide layer of the SOI wafer may correspond to dielectric layer 304. The silicon layer of the SOI wafer may be selectively etched by lithographically creating a pattern on the SOI wafer (e.g., directly on the silicon layer), which is then transferred to the SOI wafer via a dry etching process (e.g., via a photoresist mask or any other mask) to remove portions of the silicon layer. The etched portions of the silicon layer included in the SOI wafer may then be backfilled with silicon oxide and planarized to form a patterned layer of silicon oxide, silicon nitride, and / or silicon, or other material used in SOI photonic devices. Together, the patterned depositions may collectively correspond to patterned layer 306. An oxide layer (e.g., silicon oxide, etc.) may be grown, deposited, or otherwise provided on the etched / backfilled silicon layer of the SOI wafer, which may correspond to cladding layer 308. It should be understood that during the etching process, silicon in patterned layer 306 may be selectively etched down to dielectric layer 304 to form voids, which may then be backfilled with silicon oxide, planarized, and then further encapsulated with silicon oxide to form cladding layer 308. Formation of patterned layer 306 may include several etching depths, including a full etching depth of silicon to obtain the target structure. The silicon may be 220 nm thick, and therefore the full etching depth may be at least 220 nm. In some embodiments, formation of multilayer photonic device 320 may include a two-step encapsulation process in which two silicon oxide depositions are performed, with intermediate chemical-mechanical planarization used to result in a flat surface of patterned layer 306.

[0051] The multilayer stack 205 includes a first patterned layer 306-1 and a second patterned layer 306-2 overlying the first patterned layer 306-1. The second patterned layer 306-2 may be optically coupled to the first patterned layer 306-1, as described in more detail with reference to Figures 2A-2I. In this manner, the multilayer stack 205 may transform an input signal received at the first patterned layer 306-1 and / or the second patterned layer 306-2 through interaction of the input signal with metastructure dispersive regions disposed within each respective patterned layer 306.

[0052] Different layers of the multilayer photonic device 320 can correspond to different layers of an SOI photonic circuit. Different layers of the SOI photonic circuit can be dedicated to different purposes, such as electronic layers, internal waveguide layers, output layers, etc. In an exemplary embodiment, an input signal coupled to the first patterned layer 306-1 can be steered to the second patterned layer 306-2 to be coupled out of the multilayer stack 205 at a higher layer of the multilayer photonic device 320.

[0053] In some embodiments, the patterned layer 306 is designed simultaneously as part of an inverse design process. In this manner, the design of the dispersion region 330 can be used to simulate a single response of the multilayer stack 205. With respect to the inverse design process, as described in more detail with reference to FIGS. 5 and 6 , the term “response” refers, at least in part, to the output of a single full-wave simulation of the multilayer photonic device 320, including the complex transmission coefficients between the input region 324 and the output region 326. The patterned layer 306 may include different materials, different spatial geometries, and different material interface patterns. Advantageously, the patterned layer 306 can satisfy different constraints imposed on different layers of an SOI photonic circuit or by different CMOS processes associated with different material deposition / etching operations, including, but not limited to, minimum width, spacing, solid area, void area, constituent materials, sidewall angle, erosion, and / or extension. For example, the deposition and etching operations for silicon are different from those for silicon nitride, and as a result, a patterned layer 306 comprising silicon nitride, as opposed to silicon, can be designed to be manufacturable by processes for silicon nitride.

[0054] In some embodiments, fabrication of patterned layer 306 includes a depth-controlled etch facilitated by depositing an etch-stop layer 310 over at least a portion of first patterned layer 306-1 before second patterned layer 306-2 is formed. Second patterned layer 306-2 may be formed by patterned etching of voids in an oxide material, such as silicon oxide, followed by filling of the voids. Additionally or alternatively, photoresist masking techniques may be used to deposit mesas or other tapered features defining angled and / or sloped sidewalls.

[0055] The etch stop layer 310 can be a material that is resistant to the etchant used to remove the oxide and can prevent voids from progressing into the first patterned layer 306-1 during etching. In this way, the etch stop layer 310 can maintain the fidelity of the first patterned layer 306-1 to the design describing each metastructure distribution layer 330. The thickness of the etch stop layer 310 can be controlled to maintain the performance of the multilayer stack 205. In some embodiments, the etch stop layer 310 is formed from a material that exhibits etch selectivity with respect to oxide, an example of which is silicon nitride. Alternatively, the etch stop layer 310 can be formed from a material that exhibits a refractive index between the first patterned layer 306-1 and the second patterned layer 306-2. In this way, reflections and other interface effects can be reduced by including the etch stop layer 310, where the first patterned layer 306-1 and the second patterned layer 306-2 are characterized by different refractive indices.

[0056] FIG. 3C shows a more detailed view of the patterned layer 306 (relative to FIG. 3B ) taken along a portion of the peripheral region 322 of FIG. 3A , including multiple layers of the multilayer stack 205 coupled with the input region in two metastructure patterned layers. The first patterned layer 306-1 includes a first material 332 having a refractive index of ε1 and a second material 334 having a refractive index of ε2, different from ε1. Homogeneous regions of the first material 332 and the second material 334 may form a waveguide or portion of a waveguide corresponding to the input region 324 and the output region 326. The second patterned layer 306-2 may similarly include the first material 332 and a different third material 336 having a refractive index of ε3, different from ε1 and ε2. In some embodiments, the first material 332 is silicon, the second material 334 is silicon oxide, and the third material 336 is silicon nitride. However, it is understood that different materials may be used to create the material interface pattern within metastructure dispersive region 330. Materials may be selected for compatibility with CMOS and SOI fabrication processes and to implement a given transformation within the footprint of multilayer photonic device 320.

[0057] In some embodiments, the material may be selected from III-V compounds, including, but not limited to, gallium arsenide, gallium indium arsenide, aluminum gallium nitride, aluminum nitride, aluminum phosphide, etc. By incorporating III-V materials, the multilayer photonic device 200 may form part of an optical circuit having active elements such that it may be adapted for use in optical computing, for example, as part of an optical gain circuit, a sensor circuit, or as part of a stimulated light emission source.

[0058] 3D is a schematic diagram illustrating interfaces 338 of an exemplary multilayer stack 205 of a multilayer photonic device 200 that together define a material interface pattern of a metastructure-dispersed region, according to an embodiment of the present disclosure. FIG. 3D shows a more detailed view of the patterned layer 306 along a cross-section of a metastructure-dispersed region 330. As previously described, the patterned layer 306 includes irregularly and / or non-uniformly sized and distributed first materials 332 along with second materials 334 and / or third materials 336 to define a characteristic pattern of material interfaces 338. The collective material interface pattern thus created provides a target function of the multilayer photonic device 320, as described in more detail with reference to FIGS. 4A and 4B.

[0059] FIG. 4A illustrates an exemplary patterned layer 400 of a multilayer stack 205, as described with reference to FIGS. 2A-3D , including a plurality of features 405 non-uniformly arranged to define a material interface pattern, according to an embodiment of the present disclosure. The exemplary patterned layer 400 is one possible implementation of a constituent layer of the multilayer stack 205 of the exemplary photonic device 200 illustrated in FIG. 2A and may be included in the optical communication device 101-A illustrated in FIG. 1A. More specifically, FIG. 4A illustrates a cross-sectional view within a patterned layer 215 (e.g., patterned layer 306 illustrated in FIG. 3B ) included in the exemplary photonic device 200. As illustrated, the exemplary patterned layer 400 includes a first material 332 (e.g., represented by white regions) and a second material 334 (e.g., represented by black regions). It is understood that the materials are exemplary and not limited to a particular composition. The exemplary patterned layer 400 includes a metastructure distribution region 330, which represents one possible design of the metastructure distribution region 220 described with reference to Figure 2A. In some embodiments, the metastructure distribution region 330 is optically coupled to the input region 210 and the first output portion 225-1 of the output region 225.

[0060] The metastructure dispersion region 330 includes a plurality of features 405 arranged irregularly and non-uniformly according to a design developed through an inverse design process. The inverse design process may use iterative optimization (e.g., gradient-based optimization, Markov chain Monte Carlo optimization, or other optimization techniques) combined with first-principles simulations of the fundamental physics governing photonic devices. The design may be scaled such that the exemplary patterned layer 400 transforms an input signal received at the input region 210 so that the output signal can be coupled to an output region 225 that is larger than the input region 210. The inverse design process may include manufacturing constraints that implement one or more constraints imposed by a manufacturing system using the first material 332 and the second material 334, such as a minimum feature size.

[0061] The features 405 may together define a material interface pattern formed by the first material 332 and the second material 334. The interfaces 338 defined between the first material 332 and the second material 334 may be shaped such that the radius of curvature defining any given radius of the material interface within the metastructure dispersion region 330 has a magnitude less than a threshold size that is characteristic of the fabrication system. For example, if the minimum feature size is 150 nm, the radius of curvature for any of the multiple interfaces may be less than the reciprocal of half the minimum feature size (i.e., 1 / 75 nm -1 ) may correspond to a magnitude smaller than a threshold size.

[0062] In some embodiments, features 405 may be described by a unit shape (e.g., square, circle, hexagon, octagon, or any other shape) having a width corresponding to a minimum feature size (e.g., 100 nm, 140 nm, 150 nm, 180 nm, etc.). In this manner, features 405 may be arranged within metastructure distribution region 330 such that a minimum feature shape (e.g., octagon) having a width of the minimum feature size may be used to define metastructure distribution region 330.

[0063] Advantageously, maintaining a minimum feature size and / or shape improves the inverse design process by preventing optimizations to a design that violates manufacturing constraints, also referred to as design rules. Different or additional constraints related to manufacturability, such as feature spacing, may be used. In this manner, the design rules constrain the dimensions and locations of the features 405 based at least in part on the optical resolution limits of the optical lithography process used to pattern the photoresist used during the deposition and removal of the first material 332 and the second material 334.

[0064] The overall effect of multiple interactions between the feature 405 and electromagnetic radiation received as input signal 230 at input region 210 is to couple input signal 230 to output region 225 having a width greater than the width of input region 210. As described in more detail with reference to FIGS. 2C and 2D , an exemplary application of exemplary patterned layer 400 is to couple ridge waveguide 255-1 with rib waveguide 255-2. The transformation 240 applied by metastructure dispersive region 220 includes generating a single-mode output signal that is optically confined by the shallow etched portions of rib waveguide 255-2 while also benefiting from the reduced transmission loss provided by the deeper etched portions of rib waveguide 255-2. As an illustrative example, first ray trace 410-1 and second ray trace 410-2 interact with multiple interfaces 338 defined by feature 405 that together redirect ray trace 410 in opposite directions between input region 210 and output region 225.

[0065] The exemplary patterned layers 400 are shown in isolation for ease of explanation. However, it is understood that each patterned layer 215 of the multilayer stack 205 may be optically coupled to one or more other patterned layers 215 over at least a portion of the top surface 217 or bottom surface 219. To that end, EM radiation incident on the input region 210 may couple from the first patterned layer 215-1 to the second patterned layer 215-2 and / or from the second patterned layer 215-2 to the first patterned layer 215-1 as part of applying the overall transformation 240 provided by the multilayer stack 205 to generate the output signal 235.

[0066] 4B is a schematic diagram illustrating an example multilayer photonic device 450 for coupling a waveguide 255 on a first layer to a waveguide 255 on a second layer of an SOI photonic circuit, the device including two patterned layers 215 having different metastructure dispersive regions 220 defining different material interface patterns including sloped sidewalls 425, in accordance with an embodiment of the present disclosure. The example multilayer photonic device 450 is an example of a multilayer photonic device 245 as described in more detail with reference to FIGS. 2B and 2C. The example multilayer photonic device 450 includes a plurality of features 405 disposed in a first patterned layer 215-1 of a multilayer stack 205 and a plurality of features 405 disposed in a second patterned layer 215-2. 1 , first patterned layer 215-1 is optically coupled to input region 210 to receive input signal 230, and output region 225 is optically coupled to second patterned layer 215-2 to receive output signal 235 and couple output signal 235 to waveguide 255. Exemplary multilayer photonic device 450 includes features 405 deposited with non-zero sidewall angles 415. Together, features 405 collectively configure multilayer stack 205 to redirect EM radiation from first patterned layer 215-1 to second patterned layer 215-2, or vice versa, as shown by ray trace 420-1.

[0067] An exemplary multilayer photonic device 450 is shown in cross section along a plane defined by two axes "X" and "Z" of the multilayer stack 205. The plane shown in Figure 4B is orthogonal to the plane defined by the two axes "X" and "Y" of Figure 4A. However, it will be understood that the multilayer photonic devices 400 and 450 shown in Figures 4A and 4B may illustrate different configurations of the multilayer mask 205, input region 210, and output region 225 configured to apply different transformations 240 as part of generating different output signals 235.

[0068] CMOS and SOI fabrication techniques may be used to deposit the second material 334 and / or the third material 336 in a feature 405 having sloped sidewalls 425. The feature 405 may define a sidewall angle 415 such that EM radiation incident on the sidewall 425 of the feature 405 is refracted in a direction perpendicular to the plane of the patterned layer 215, identified in FIG. 4B as the “Z” axis. As described in more detail with reference to FIG. 4A , the features 405 may be formed to collectively apply a transformation 240 in the plane of the patterned layer 215. The sidewall angle 415 may be formed on the sidewall 425 of the feature 405 such that the transformation 240 includes three or more dimensional components, identified in FIGS. 4A and 4B as “X,” “Y,” and “Z.” The axes X, Y, and Z refer to a Cartesian coordinate space corresponding to the rectilinear shape of the multi-layer mask 205. In some embodiments, the multi-layer mask 205 describes a cylinder or other geometric shape such that the transform 240 defines a component that is mapped to a geometrically appropriate coordinate space. In one example, the multi-layer mask 205 may include features 405 that define the transform 240, including a cylindrical component, such as a rotation transform.

[0069] As will be understood by those skilled in the art of optics, the sidewalls 425 may define a sidewall angle 415 to refract EM radiation in a direction perpendicular to the XY plane of the patterned layer 215, referred to as "out-of-plane." For a first feature 405-1 disposed in the first patterned layer 215-1, the first sidewall angle 415-1 is defined such that the first feature 405-1 tapers from the interface with the second patterned layer 215-2 and narrows toward the interface of the first patterned layer 215-1 with the dielectric layer 304 or substrate 302. The resulting sidewall angle 415-1 defines an angle of incidence of the EM radiation to redirect the EM radiation away from the substrate 302 and toward the second patterned layer 215-2. Conversely, second feature 405-2 may be disposed within second patterned layer 215-2 having sloped sidewalls 425 defining second sidewall angle 415 such that second feature 405-2 tapers from the interface with first patterned layer 215-1 and narrows toward the interface with cladding layer 308. The general effect of tapered sidewalls 425 is illustrated by the refraction of exemplary ray trace 430, although it should be noted that the direction, magnitude, and extent of sidewall angle 415 and exemplary ray trace 430 are intended as illustrative examples.

[0070] Because the sidewall angle 315 contributes a portion of the overall “out-of-plane” transformation, each feature 405 in the multilayer mask 205 of the exemplary multilayer photonic device 450 may define one or more different sidewall angles 415 between about 0 radians and about π / 2 radians. However, it is understood that manufacturability constraints and design parameters may provide for a sidewall angle 415 of about π / 4 radians or less, about π / 6 radians or less, about π / 8 radians or less, about π / 10 radians or less, about π / 12 radians or less, about π / 14 radians or less, about π / 16 radians or less, about π / 18 radians or less, about π / 20 radians or less, about π / 22 radians or less, about π / 24 radians or less, about π / 26 radians or less, about π / 28 radians or less, about π / 30 radians or less, about π / 32 radians or less, about π / 34 radians or less, about π / 36 radians or less, about π / 38 radians or less, about π / 40 radians or less, about π / 42 radians or less, about π / 44 radians or less, about π / 46 radians or less, about π / 48 radians or less, about π / 50 radians or less, or less. The magnitude of sidewall angle 415 may be constrained by material considerations, including, for example, the angle of total internal reflection, manufacturability limits of deposition and removal operations, etc. As such, sidewall angle 415 may, in some embodiments, be limited to values ​​specific to the design being implemented. Advantageously, the inverse design process described herein allows such constraints to be considered as part of optimizing the metastructure interface pattern.

[0071] The features 405 may be formed as linear, cylindrically symmetric, lenticular, hemispherical mesas, and / or may take on asymmetric shapes arbitrarily defined by an inverse design process, as described in more detail with reference to FIGS. 5 and 6 . In some embodiments, the features 405 may be “blob”-like, with sidewalls 425 defining two or more sidewall angles 415 as a function of position in the out-of-plane axis (“Z”). As shown in FIG. 4B , the sidewall angles 415 may be positionally dependent, such that light rays incident on the feature 405 closer to the interface between the first patterned layer 215-1 and the second patterned layer 215-2 are deflected less than light rays incident on the feature 405 closer to the peripheral region 322. In some embodiments, the features 405 define a partial convex lens profile, such that light rays incident on the feature 405 can be redirected by any angle in three dimensions.

[0072] The features 405 may be irregularly and non-uniformly distributed within the patterned layer 215 such that the component of the transformation 240 that redirects light rays out-of-plane is applied to spatially localized regions of the patterned layer 215. As described in more detail with reference to FIGS. 2H and 2I , a multilayer photonic device 270 is described that is configured to redirect and multiplex input signals 205-1 and 205-2 to generate a multiplexed output signal 210. In the context of the described multiplexing embodiment, the features 405 configured to redirect EM radiation from the first patterned layer 215-1 to the second patterned layer 215-2 may be located in the patterned layer 215 closer to the input region 210, such that multiplexing may be implemented by the features 405 located in the second patterned layer 215-2. Additionally or alternatively, features 405 configured to redirect EM radiation from the first patterned layer 215-1 to the second patterned layer 215-2 may be located in the patterned layer 215 closer to the output region 225, such that multiplexing may be implemented at least in part by features 405 located in the first patterned layer 215-1.

[0073] In some embodiments, the sidewall angle 415 is symmetric about the feature 405, such that the feature 405 may be conical, trapezoidal, or other solid of revolution. In some embodiments, the sidewall angle 415 is defined to be irregularly and non-uniformly distributed based at least on the location of the feature 405 within the patterned layer 215. In some embodiments, the second feature 405-2 is disposed in the second patterned layer 215-2 to redirect the throughput signal 250 to the output region 225. Thus, the second feature 405-2, which represents a portion of the feature 405 disposed in the second patterned layer 215-2, may be disposed closer to the output region 225 than the first feature 405-1. However, it is understood that the configuration and location of the first feature 405-1 and the second feature 405-2 may result from optimization of a loss function, taking into account manufacturing constraints imposed by the CMOS / SOI manufacturing process used to fabricate the exemplary multilayer photonic device 450. For example, constraints on sidewall angle 415 can be imposed on the maximum angle, out-of-plane radius of curvature, width, spacing, solid area, and void area of ​​the features 405 so that fabrication does not exceed erosion and / or expansion tolerances determined at least in part by the optical resolution of the fabrication system and the material properties of the deposited materials 332-336.

[0074] In some embodiments, the subset of features 405 may be arranged in the patterned layer 215 according to a locally periodic or regular pattern. For example, the subset of features 405 may be regularly spaced as part of applying the transform 240. The subset of features 405 may have a common shape, size, or orientation despite being regularly spaced, or may be of different shapes, sizes, or orientations. In an exemplary embodiment, the locally periodic or regular pattern may occupy approximately 10% of the area of ​​the first patterned layer 215-1 defined in the XY plane shown in FIG. 4A . In this manner, the subset of features 405 may represent a portion of the total number of features 405, with the remaining features 405 being irregularly and non-uniformly arranged in the patterned layer 215.

[0075] 4C is a schematic diagram illustrating an exemplary multilayer photonic device 470 for coupling a waveguide 255 on a first layer to a waveguide 255 on a second layer of an SOI photonic circuit, including two patterned layers 215 having multiple metastructure dispersion regions 475 defining different material interface patterns including sloped sidewalls 425, in accordance with an embodiment of the present disclosure. The exemplary multilayer photonic device 470 includes two patterned layers 215, each subdivided into two metastructure dispersion regions 475, with a pattern boundary 480 disposed therebetween. The patterned layers 215 thus define multiple distinct metastructure dispersion regions 475 that are coextensive in the lateral ("xy") plane.

[0076] In some embodiments, the patterned layer 215 is subdivided in the “out-of-plane” z-direction to define multiple patterns in each layer. Subdividing the patterned layer 215, such as the first patterned layer 215-1 and / or the second patterned layer 215-2 in FIG. 4B , may include defining a pattern boundary 480 in the patterned layer 215 that separates two distinct metastructure dispersion regions 475 on either side of the pattern boundary 480, similar to the etch-stop layer 310 in FIG. 3B . In this manner, an exemplary multilayer photonic device 470 may include two patterned layers 215, one or more of which are patterned multiple times. For example, an exemplary multilayer photonic device 470 may include two patterned layers 215 having three metastructure dispersion regions 475, four metastructure dispersion regions 475, five metastructure dispersion regions 475, or more metastructure dispersion regions, separated by an appropriate number of pattern boundaries 480.

[0077] In the context of designing and fabricating the exemplary multilayer photonic device 470, multiple patternings of the patterned layer 215 can be optimized for the overall performance (e.g., inter-waveguide coupling efficiency) of the exemplary multilayer photonic device 470 through control of each constituent interface pattern. During fabrication, the patterned layer 215 can be formed through multiple patterning operations corresponding to material deposition and removal, as described in more detail with reference to FIGS. 3A-3D . Similar to the fabrication process described for the multilayer stack 205, the patterning operations can include forming a first metastructure dispersion region 475 through a first patterning operation, disposing a pattern boundary 480 on the first metastructure dispersion region 475, forming a second metastructure dispersion region 475 on the pattern boundary 480, and then disposing an etch stop layer 310 on the second metastructure dispersion region 475. Advantageously, forming multiple metastructure dispersed regions 475 within a single patterned layer 215 may improve the performance of out-of-plane z-direction transformation 240, at least in part, by improving the coupling effect between patterned layers 215. As a result, forming multiple interface patterns in one or more patterned layers 215 may also reduce the area of ​​the exemplary multilayer device 470 relative to the exemplary multilayer device 450 described with reference to FIG.

[0078] FIG. 5 is a functional block diagram illustrating an example system 500 for generating a photonic integrated circuit design, according to an embodiment of the present disclosure. The example system 500 may implement an inverse design process to design and / or optimize one or more masks used in the multilayer stack 205 of FIGS. 2A-3D . More specifically, the example system 500 is a design tool that may be used to optimize structural parameters, such as the shape and arrangement of the first material 331, the second material 334, and / or the third material 336, of the metastructure dispersion region 330 of the photonic integrated circuit. The inverse design optimization may incorporate first-principles simulations, such as electromagnetic simulations or other physical models, to determine the field response of the photonic device 200 in response to the input signal 230. At each iteration, the distribution of materials in the metastructure dispersion region may converge to a solution, whereby the multilayer stack 205 applies a target transformation, examples of which are described with reference to FIGS. 2A-2I , to generate an output signal in response to the input signal.

[0079] As illustrated, system 500 includes a controller 505, a display 507, an input device 509, a communication device 511, a network 513, a remote resource 515, a bus 521, and a bus 523. Controller 505 includes a processor 531, a memory 533, local storage 535, and a photonic device simulator 539. Photonic device simulator 539 includes an operational simulation engine 541, manufacturing loss calculation logic 543, calculation logic 545, an adjoint simulation engine 547, and an optimization engine 549. It should be understood that in some embodiments, controller 505 may be a distributed system.

[0080] Controller 505 is coupled to display 507 (e.g., a light emitting diode display, a liquid crystal display, etc.) coupled to bus 521 via bus 523 for displaying information to a user of system 500 for optimizing structural parameters of multilayer stack 205 of exemplary photonic device 200. Input device 509 is coupled to bus 521 through bus 523 for communicating information and command selections to processor 531. Input device 509 may include a mouse, trackball, keyboard, stylus, or other computer peripheral to facilitate interaction between a user and controller 505. In response, controller 505 may provide verification of the interaction via display 507.

[0081] Another device that may optionally be coupled to the controller 505 is a communications device 511 for accessing remote resources 515 of the distributed system via a network 513. The communications device 511 may include any number of networking peripheral devices, such as those used to couple to an Ethernet, the Internet, a wide area network, or the like. The communications device 511 may further include mechanisms that provide connectivity between the controller 505 and the outside world. Note that any or all of the components and associated hardware of the system 500 illustrated in FIG. 5 may be used in various embodiments of the present disclosure. The remote resources 515 may be part of a distributed system and may include any number of processors, memory, and other resources for optimizing structural parameters of a photonic device.

[0082] The controller 505 orchestrates the operation of the system 500 to optimize structural parameters of a photonic device. The processor 531 (e.g., one or more central processing units, graphics processing units, and / or tensor processing units, etc.), the memory 533 (e.g., volatile memory such as DRAM and SRAM, non-volatile memory such as ROM, flash memory, etc.), the local storage 535 (e.g., magnetic memory such as a computer disk drive), and the photonic device simulator 539 are coupled to each other through a bus 523. The controller 505 includes software (e.g., instructions contained in the memory 533 coupled to the processor 531) and / or hardware logic (e.g., an application-specific integrated circuit, a field-programmable gate array, etc.) that, when executed by the controller 505, causes the controller 505 or the system 500 to perform operations. The operations may be based on instructions stored in any one or combination of the memory 533, the local storage 535, the physical device simulator 539, and the remote resources 515 accessed through the network 513.

[0083] In some embodiments, modules 541-549 of photonic device simulator 539 are used to optimize structural parameters of components of photonic integrated circuits described in embodiments herein. In some embodiments, exemplary system 500 optimizes structural parameters of components included in photonic integrated circuits (e.g., photonic devices corresponding to one or more optical deinterleavers, demultiplexers, filters, etc.) through simulations (e.g., behavioral simulations and adjoint simulations) that use, among other things, finite-difference time-domain (FDTD) techniques to model field responses (e.g., electric and magnetic fields within the photonic integrated circuit). Behavioral simulation engine 541 provides instructions for performing electromagnetic simulations of photonic devices operating in response to electromagnetic excitation sources, such as input signal 230, within a simulation environment. In particular, the behavioral simulation determines the field response of the simulation environment (and thus the photonic device described by the simulation environment) in response to the excitation sources to determine performance metrics of the physical device (e.g., based on an initial photonic device description or input design describing the structural parameters of the photonic device within the simulation environment having multiple voxels). The structural parameters may correspond, for example, to a particular design, material composition, dimensions, etc. of a physical device. Fabrication loss calculation logic 543 provides instructions for determining fabrication losses used to enforce minimum feature sizes and / or shapes to ensure manufacturability. In some embodiments, the fabrication losses are also used to enforce binarization of the design (i.e., such that the photonic device includes a first material and a second material interspersed to form multiple interfaces). Calculation logic 545 computes a loss metric based on the performance metric and the fabrication losses, as determined via a loss function that incorporates the performance losses.The adjoint simulation engine 547 is used in conjunction with the behavioral simulation engine 541 to perform adjoint simulation of the photonic device and back-propagate the loss metric through the simulation environment via a loss function to determine how changes in the structural parameters of the photonic device affect the loss metric. The optimization engine 549 is used to update the structural parameters of the photonic device to reduce the loss metric and generate a revised description of the photonic device (i.e., revise the design).

[0084] In conjunction with the multilayer stack 205, the photonic device simulator 539 incorporates optical coupling of the first patterned layer 215-1 and the second patterned layer 215-2 as part of its simulation and optimization routines. In this manner, design domains can be individually designed and optimized for overlapping volumes corresponding to layers of the multilayer stack 205. The resulting multilayer photonic device 200 can apply one or more arbitrary transformations to an input signal using multiple metastructure layers, each defined by a distinct material interface pattern, as part of generating an output signal.

[0085] In an exemplary embodiment, an algorithm for a single iteration of the design optimization process of the multilayer stack 205 includes initializing the design of each patterned layer, calculating both structures corresponding to the design, running a single full-wave simulation for all patterned layers of the multilayer stack 205 together, calculating a loss metric using the output of the simulation, running an adjoint simulation, calculating the sensitivity of the loss metric to the degrees of freedom in each patterned layer, and modifying each design of the patterned layers together.

[0086] The full-wave simulations of each patterned layer can be used together to calculate the complex transmission coefficient between input region 210 and output region 225. The simulations account for EM radiation coupled between and / or through the patterned layers of multilayer stack 205, as well as EM radiation coupled from input region 210 into multilayer stack 205 and out through output region 225.

[0087] As described in more detail with reference to FIGS. 3A-3D , the patterned layers may include different combinations of materials, such as silicon, silicon nitride, silicon oxide, or other SOI-compatible materials that transmit at least a portion of the input signal. As a result, the fabrication of each patterned layer may be constrained by a different set of design rules imposed by the corresponding fabrication process system. Such applied constraints may affect optimization by including different material properties in the physical simulation, applying different fabrication constraints, and / or applying different size, dimension, void area, or solid area constraints to each patterned layer of the multilayer stack 205. In an exemplary embodiment, different patterned layers incorporating different materials may be constrained by different fabrication system processes that impose different limits on the sidewall angle, erosion, and / or extension of the respective material interface patterns. These differences may be accounted for by one or more modules of the photonic device simulator, as described in more detail below with reference to FIG. 6 .

[0088] FIG. 6 illustrates an exemplary method for generating a design of the exemplary multilayer photonic device 200 according to an embodiment of the present disclosure. The exemplary method 600 is one possible inverse design process for generating any one of the components of a photonic integrated circuit described herein, including, but not limited to, an escalator, a coupler, a multiplexer, a demultiplexer, a mode selector, or a combination thereof. It should be understood that the exemplary method 600 is one example of an inverse design process implemented by the system 500 of FIG. 5 as a technique for iteratively optimizing the design of a multilayer stack 205 including multiple optically coupled patterned layers 306. A loss metric may be calculated from a loss function that includes performance loss and manufacturing loss. The exemplary method 600 may be encoded as computer-readable instructions stored on at least one machine-accessible storage medium (e.g., non-transitory memory) that, when executed by a machine, causes the machine to perform operations for generating a design of a multilayer photonic device. Additionally, the output of exemplary method 600 may include a photonic device including a multi-layer stack of patterned layers that together apply one or more arbitrary transformations to an input electromagnetic signal, including but not limited to an infrared optical signal.

[0089] While some of the operations described as part of exemplary method 600 are described as being performed on an individual patterned layer of a multi-layer photonic device, other operations are performed simultaneously on multiple patterned layers. Where an operation is described on an individual patterned layer, it is understood that the operation may be performed simultaneously and / or in parallel on multiple patterned layers rather than only on a single patterned layer of a multi-layer photonic device. It should further be understood that the order in which some or all of the process blocks appear in exemplary method 600 should not be considered limiting. Rather, one of ordinary skill in the art having the benefit of this disclosure will understand that some of the process blocks may be performed in various orders not illustrated, or even in parallel. As described in more detail with reference to FIG. 5 , some or all of the operations described with reference to exemplary method 600 may be performed using a distributed computing system over a network and / or on individual computing devices.

[0090] Block 610 illustrates the configuration of a simulation environment representing a received or otherwise obtained initial description of a photonic integrated circuit component (e.g., a photonic device). In some embodiments, the photonic integrated circuit component may be designed to apply one or more optional transformations after optimization (e.g., implemented as an inter-layer escalator or a waveguide coupler). The initial description may describe structural parameters of the photonic integrated circuit within the simulation environment. The simulation environment may include a plurality of voxels that collectively describe the structural parameters of the photonic device. Each of the plurality of voxels is associated with a structural value describing the structural parameter, a field value describing a field response (e.g., electric and magnetic fields in one or more orthogonal directions) to a physical stimulus (e.g., one or more excitation sources), and a source value describing the physical stimulus. Once the initial description is received, prepared, generated, or otherwise obtained, the simulation environment is configured (e.g., the number of voxels, the shape / arrangement of the voxels, and specific values ​​of the voxel's structural, field, and / or source values ​​are set based on the initial description). In some embodiments, the initial description may be a first description of a physical device, and the values ​​of the structural parameters may be random or null values ​​outside the input and output domains so as to avoid bias toward the initial (e.g., first) design. It should be understood that the initial description or input design may be relative terms. Thus, in some embodiments, the initial description may be a first description of a physical device described within the context of a simulation environment (e.g., a first input design for performing a first operational simulation).

[0091] However, in other embodiments, the term initial description may refer to an initial description (e.g., performing an operational simulation, running an adjoint simulation, and updating structural parameters). Thus, the initial description or design of a given cycle may correspond to a modified description or design (e.g., generated from a previous cycle). In some embodiments, the simulated environment includes a design domain (e.g., representing a metastructure distribution region) that includes a portion of a plurality of voxels having structural parameters that may be modified or otherwise changed as part of optimizing one or more structural parameters of a multilayer photonic device. In this manner, structural parameters of individual patterned layers of a multilayer photonic device are related to the geometric boundaries and / or material composition of a physical device based on material properties (e.g., dielectric constant, refractive index, etc.) of the simulated environment.

[0092] In one embodiment, the simulated environment includes a design region optically coupled to one or more additional design regions, one or more first communication regions, and one or more second communication regions. In some embodiments, as described in more detail with reference to FIGS. 2A-4B , the first communication region may correspond to an input region or portion (e.g., where an excitation source is coupled to one or more patterned layers 215 via input region 210), while the second communication region may correspond to multiple output regions or portions (e.g., where output signals generated in response to excitation by an input signal are coupled to output region 225 via one or more patterned layers 215). For example, multilayer stack 205 may include a first communication region on first patterned layer 215-1 and a second communication region on second patterned layer 215-2. In another embodiment, the multilayer stack 205 may include multiple first communication regions on the first patterned layer 215-1 and one second communication region on the second patterned layer 215-2, where the multilayer photonic device functions as a step-up multiplexer.

[0093] Block 615 depicts mapping one or more channels of input signal 230, each characterized by a distinct wavelength, from one or more first communication regions to one or more second communication regions to form an output signal. The distinct wavelength channels may be mapped to the second communication region by an initial description of the photonic device. For example, a loss function may be encoded as part of the instructions relating a performance metric of the photonic device to the power transfer from the input port to the individual output regions or portions for the mapped channels. The power loss across the device may form at least a portion of a performance loss function used to modify the design of multilayer stack 205 and constituent metastructure dispersion region 220. In this manner, the designs described with respect to the transforms of FIGS. 2A-2I may be physically defined and used to optimize the structure applying the transform.

[0094] Block 620 indicates performing an operational simulation of a photonic integrated circuit within a simulation environment operating in response to one or more excitation sources to determine performance metrics. More specifically, an electromagnetic simulation is performed in which the field response of the photonic integrated circuit is incrementally updated over multiple time steps to determine how the field response of the photonic device changes due to the excitation sources. Field values ​​of multiple voxels are updated in response to the excitation sources based at least in part on structural parameters of the integrated photonic circuit. Additionally, each update operation at a particular time step may also be based at least in part on a previous (e.g., immediately preceding) time step.

[0095] Thus, the operational simulation simulates interactions between constituent layers of the multilayer photonic device 200 and an electromagnetic excitation source (e.g., input signal 230) to determine a simulated output of the photonic device (e.g., at one or more of the output regions or portions). The interactions may correspond to one or more of perturbation, retransmission, attenuation, dispersion, refraction, reflection, diffraction, absorption, scattering, amplification, or interactions forming part of a full-wave simulation. In this manner, the effect of each patterned layer 215 on the input signal 230 may be simulated with respect to the interaction between the input signal 230 and the simulated structure of each metastructure dispersive region. The operational simulation simulates how the field response of the simulated design environment changes in response to the excitation source over multiple time steps (e.g., from an initial time step to a final time step with a predetermined step size) as part of an iterative gradient-based optimization technique.

[0096] In some embodiments, the simulated output may be used to determine one or more performance metrics of the photonic device. For example, an excitation source may be generated in or located proximate to one or more first communication regions when performing an operational simulation. Then, during the operational simulation, a field response in one or more second communication regions may be used to determine a simulated power transfer of the photonic device. The power metric may be a specific channel of a multi-channel signal or may describe multiple channels. Thus, as defined in block 615, a performance metric may be determined that includes determining a simulated power transfer of the excitation source from a first communication region, through multiple design regions, to a second communication region using the operational simulation.

[0097] In some embodiments, the pump source may cover the entire spectrum of the multiple output ports (e.g., the pump source spans a target frequency range of at least the bandpass region of each of the multiple channels and at least a portion of the corresponding stopband region) to determine a performance metric (i.e., simulated power transfer) associated with each of the distinct wavelength channels of the photonic integrated circuit. In some embodiments, one or more frequencies spanning the passband of a given one of the multiple channels are randomly selected to optimize the design (e.g., batch gradient descent while having the full width of each passband, including ripples within the passband, meet the target specifications). In the same or other embodiments, each of the multiple channels has a common bandwidth with a different center wavelength.

[0098] Block 625 depicts determining a loss metric based on a performance loss associated with the performance metric and a manufacturing loss associated with the minimum feature size. In some embodiments, the loss metric is determined via a loss function that includes both the performance loss and the manufacturing loss as inputs. The performance loss may correspond to a difference between the performance metric and a target performance metric of the photonic integrated circuit. In some embodiments, a minimum feature size for a design region of the simulation environment may be provided to facilitate manufacturability of a design generated by the inverse design process. The manufacturing loss is based at least in part on the minimum feature size and structural parameters of the design region. More specifically, the manufacturing loss enforces a minimum feature size of the design such that the design region does not have structural elements with a diameter less than the minimum feature size. This helps the system provide designs that meet specific manufacturability and / or yield requirements. In some embodiments, the manufacturing loss also helps enforce binarization of the design (i.e., rather than mixing first and second materials together to form a third material, the design includes regions of the first and second materials with a non-uniform arrangement). In the same or other embodiments, the minimum feature size may include a minimum feature shape.

[0099] 2A-3D , the multilayer stack 205 may include different materials in different patterned layers 215, such that each patterned layer represented by a respective design region for purposes of the exemplary method 600 may be described by a different manufacturing loss function. For example, constraints imposed on feature size, sidewall angle, erosion, and / or extension may be material-specific. In this manner, calculating a loss value for an iteration of the exemplary method 500 may include a separate calculation for each constituent patterned layer of the multilayer stack 205.

[0100] In some embodiments, the design generated by the inverse design process optimizes at least one of the materials configured within the design region. The resulting structure may be generally reproduced by feature shapes and dimensions in a material interface pattern, as described in more detail with reference to FIGS. 4A and 4B. For example, the shape and arrangement of the first and / or second materials within the design region corresponding to the first patterned layer 215-1 may be visualized using shapes and unit dimensions corresponding to the feature size and shape constraints imposed by the manufacturing system. The feature shapes may include, but are not limited to, circles, squares, hexagons, octagons, or any other shapes. In some embodiments, the feature shapes are single shapes that may be rotated, inverted, and / or overlapped with portions of another feature shape. For example, if the feature shape is an octagon, two overlapping octagons, each corresponding to the feature shape, may partially overlap each other to generate a different shape. In other embodiments, the feature shapes may be non-overlapping tiles such that the metastructure pattern is formed by multiple consecutive units of the feature shape. In some embodiments, the predetermined width of the feature shape can be between 20 nm and 200 nm. For example, the predetermined width of the feature shape can be 100 nm, 140 nm, 180 nm, etc. In some embodiments, the feature shape and the predetermined width of the feature shape correspond to the feature size constraints of the respective patterned layer 215 being simulated. For example, the first material of the metastructure dispersed region 330 (e.g., the white region) in FIG. 4A can be roughly represented by an octagon having a width of 100 nm.

[0101] In some embodiments, manufacturing loss is determined by generating a convolution kernel (e.g., circular, square, octagonal, etc.) having a width equal to the minimum feature size. The convolution kernel is then shifted through the design domain of the simulation environment to determine voxel locations (i.e., individual voxels) within the design domain that fit the convolution kernel within the design domain without extending beyond the design domain. The convolution kernel is then convolved at each of the voxel locations with a structural parameter associated with the voxel location to determine a first manufacturing value. The structural parameter is then inverted, and the convolution kernel is again convolved at each of the voxel locations with the inverted structural parameter to determine a second manufacturing value. The first and second manufacturing values ​​are then subsequently combined to determine manufacturing loss for the design domain. This process of determining manufacturing loss can address and resolve structural elements in the design domain that have a radius of curvature smaller than a threshold size (i.e., the inverse of half the minimum feature size).

[0102] Block 630 illustrates backpropagating the loss metric via the loss function through the simulation environment to determine the effect of changes in structural parameters on the loss metric (i.e., structural gradient). The loss metric is treated as an adjoint or virtual source and is incrementally backpropagated from the final time step to earlier time steps in the backward simulation to determine the structural gradient of the photonic device.

[0103] Block 635 indicates revising the design of the photonic device (e.g., generating a revised description) by updating the structural parameters to adjust the loss metric. In some embodiments, adjusting the loss metric may reduce the loss metric. However, in other embodiments, the loss metric may be adjusted or otherwise compensated for in a manner that does not necessarily reduce the loss metric. In one embodiment, adjusting the loss metric maintains manufacturability while providing a general direction within the parameterization space to ultimately obtain a design that provides improved performance while also maintaining device manufacturability and the target performance metric. In some embodiments, the revised description is generated by utilizing an optimization scheme after cycles of adjoint simulation and operation via a gradient descent algorithm, a Markov chain Monte Carlo algorithm, or other optimization technique. The iterative cycle of simulating the photonic integrated circuit, determining the loss metric, backpropagating the loss metric, and updating the structural parameters to adjust the loss metric may be performed continuously until the loss metric substantially converges such that the difference between the performance metric and the target performance metric is within a threshold range, while also accounting for manufacturability and binarization due to manufacturing losses. In some embodiments, the term "converge" may simply indicate that the difference is within a threshold range and / or is below some threshold.

[0104] Decision block 640 indicates determining whether the loss metric substantially converges such that the difference between the performance metric and the target performance metric is within a threshold range. An iterative cycle is performed to simulate a photonic integrated circuit having a pump source selected from multiple distinct wavelength channels, back-propagating the loss metric, and revising the design by updating structural parameters to reduce the loss metric until the loss metric substantially converges such that the difference between the performance metric and the target performance metric is within a threshold range. In some embodiments, structural parameters of the design domain of the integrated photonic circuit are revised as the cycle is performed to cause the design domain of the photonic integrated circuit to apply any transformations to the input signal as part of generating an output signal based on the mapping of block 615. Exemplary transformations applied by multiple interacting layers of multilayer stack 205 are described in more detail with reference to FIGS. 2A-2I.

[0105] Block 645 depicts outputting an optimized design of the photonic device in which the structural parameters of each of the constituent patterned layers have been modified. An optimized design is understood to describe not the best possible physical performance of the photonic device with respect to applying an arbitrary transformation to the input signal to generate an output signal, but rather a design in which the difference between the performance metric and the target performance metric is within a threshold range, while also satisfying the manufacturability constraints imposed by CMOS and / or SOI fabrication systems.

[0106] The processes described above are described with reference to computer software and hardware. The described techniques may constitute machine-executable instructions embodied in a tangible or non-transitory machine (e.g., computer) readable storage medium that, when executed by a machine, causes the machine to perform the described operations. Additionally, the processes may be embodied in hardware, such as an application specific integrated circuit (ASIC).

[0107] A tangible, machine-readable storage medium includes any mechanism that provides (i.e., stores) information in a non-transitory form accessible by a machine (e.g., a computer, a network device, a personal digital assistant, a manufacturing tool, any device with a set of one or more processors, etc.). For example, machine-readable storage media include recordable / non-recordable media (e.g., read only memory (ROM), random access memory (RAM), magnetic disk storage media, optical storage media, flash memory devices, etc.).

[0108] The above description of illustrated embodiments of the present invention, including what is described in the Abstract, is not intended to be exhaustive or to limit the invention to the precise form disclosed. While specific embodiments of and examples for the present invention have been described herein for illustrative purposes, those skilled in the art will recognize that various modifications are possible within the scope of the present invention.

[0109] These modifications can be made to the invention in light of the above detailed description. In general, the terms used in the following claims should not be construed to limit the invention to the specific embodiments disclosed herein. Rather, the scope of the invention should be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation.

Claims

1. 1. A multilayer photonic device comprising: an input area configured to receive an input signal; a multi-layer stack optically coupled to the input region to receive the input signal, a first metastructure dispersed region disposed in a first patterned layer of the multilayer stack; and a second metastructure dispersion region disposed in a second patterned layer of the multilayer stack and optically coupled to the first metastructure dispersion region; a multi-layer stack, the first meta-structure distribution region and the second meta-structure distribution region together configuring the multi-layer stack to generate an output signal in response to the input signal; an output region optically coupled to the multilayer stack to output the output signal; the first metastructure dispersed region includes a first plurality of features that together define a first material interface pattern, and the second metastructure dispersed region includes a second plurality of features that together define a second material interface pattern; the first plurality of features are irregularly and non-uniformly distributed within the first metastructure distribution region, and the second plurality of features are irregularly and non-uniformly distributed within the second metastructure distribution region; Multilayer photonic devices.

2. A first feature included in the first plurality of feature parts is formed from a first material and surrounded by a second material, a second feature included in the first plurality of feature parts is formed from the second material and surrounded by the first material, 10. The multilayer photonic device of claim 1, wherein a third feature in the second plurality of features is formed from the first material and is surrounded by a third material, and a fourth feature in the second plurality of features is formed from the third material and is surrounded by the first material.

3. The multilayer photonic device of claim 2 , wherein the first material is silicon oxide, the second material is silicon, and the third material is silicon nitride.

4. 10. The multilayer photonic device of claim 1, wherein said first patterned layer comprises a plurality of metastructure dispersed regions that are coextensive in the lateral plane.

5. 10. The multilayer photonic device of claim 1, wherein said multilayer stack further comprises an etch stop layer disposed between said first metastructure dispersion region and said second metastructure dispersion region.

6. the first metastructure dispersive region is optically coupled to the input region to receive the input signal propagating in a first direction; the first metastructure dispersive region is configured to generate a throughput signal propagating in a second direction in response to the input signal; the second metastructure dispersive region is optically coupled to the first metastructure dispersive region to receive the throughput signal propagating in the second direction; 10. The multilayer photonic device of claim 1, wherein said second metastructure dispersive region is configured to generate said output signal propagating in a third direction in response to said throughput signal.

7. The multilayer photonic device of claim 6 , wherein the third direction is aligned with the first direction.

8. the input signal is a first input signal, the input domain is a first input domain, the multilayer photonic device further comprising a second input region configured to receive a second input signal, the first input signal and the second input signal comprising distinct wavelength channels; 7. The multilayer photonic device of claim 6, wherein the first metastructure dispersive region is optically coupled to the first input region to receive the first input signal and to the second input region to receive the second input signal.

9. 10. The multilayer photonic device of claim 8, wherein the first metastructure dispersive region is configured to multiplex the first input signal and the second input signal to generate the throughput signal.

10. the throughput signal is a first throughput signal; the first metastructure distribution region is further configured to generate a second throughput signal in response to the second input signal, the first throughput signal being different from the second throughput signal; 10. The multilayer photonic device of claim 8, wherein the second metastructure dispersive region is configured to multiplex the first throughput signal and the second throughput signal to generate the output signal.

11. the output region comprising a first output portion and a second output portion; the first output portion is wider than the second output portion and the input area; the first metastructure dispersive region is optically coupled to the first output portion; The multilayer photonic device of claim 1 , wherein said second metastructure dispersive region is optically coupled to said second output portion.

12. the input region is optically coupled to a ridge waveguide; the first output portion is optically coupled to a deep etched portion of a rib waveguide; The multilayer photonic device of claim 11 , wherein the second output portion is optically coupled to a shallow etched portion of the rib waveguide.

13. the input signal is a first input signal, the input domain is a first input domain, the multilayer photonic device further comprising a second input region configured to receive a second input signal, the first input signal and the second input signal comprising distinct wavelength channels; the multilayer stack is optically coupled to the second input region to receive the second input signal; 12. The multilayer photonic device of claim 11, wherein the multilayer stack is configured to multiplex the first input signal and the second input signal to generate the output signal.

14. 1. A method of conducting electromagnetic radiation between layers of a multi-layer photonic device, said method comprising: receiving an input signal at an input region of the multilayer photonic device; coupling the input signal to a multi-layer stack of the multi-layer photonic device, the multi-layer stack comprising: a first metastructure dispersed region disposed in a first patterned layer of the multilayer stack; and a second metastructure dispersion region disposed in a second patterned layer of the multilayer stack and optically coupled to the first metastructure dispersion region; the first metastructure dispersed region includes a first plurality of features that together define a first material interface pattern, and the second metastructure dispersed region includes a second plurality of features that together define a second material interface pattern; the first plurality of features are irregularly and non-uniformly distributed within the first metastructure distribution region, and the second plurality of features are irregularly and non-uniformly distributed within the second metastructure distribution region; coupling the input signal to the multi-layer stack, the first metastructure distribution region and the second metastructure distribution region together configuring the multi-layer stack to generate an output signal in response to the input signal; generating the output signal; coupling the output signal to an output region of the multilayer photonic device, the output region being optically coupled to the multilayer stack to receive the output signal.

15. A first feature included in the first plurality of feature parts is formed from a first material and surrounded by a second material, a second feature included in the first plurality of feature parts is formed from the second material and surrounded by the first material, 15. The method of claim 14, wherein a third feature in the second plurality of features is formed from the first material and is surrounded by a third material, and a fourth feature in the second plurality of features is formed from the third material and is surrounded by the first material.

16. The method of claim 14 , wherein the second patterned layer overlies the first patterned layer.

17. Coupling the input signal to the multi-layer stack includes coupling the input signal to the first patterned layer, and generating the output signal includes: generating a throughput signal using the first metastructure dispersive region; coupling the throughput signal from the first meta-structure distribution region to the second meta-structure distribution region; and generating the output signal using the second metastructure dispersive region.

18. the output region comprising a first output portion and a second output portion; the first output portion is wider than the second output portion and the input area; coupling the input signal to the multi-layer stack includes coupling the input signal to the first patterned layer and the second patterned layer; coupling the output signal to the output region; coupling a first signal portion of the output signal from the first patterned layer to the first output portion; and coupling a second signal portion of the output signal from the second patterned layer to the second output portion.

19. 20. The method of claim 18, wherein the input signal and the output signal are characterized by a single optical mode.

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