Ion implantation for reducing hydrogen incorporation in amorphous silicon.

Abstract

An exemplary method of semiconductor processing may include forming a layer of amorphous silicon on a semiconductor substrate. The layer of amorphous silicon may be characterized by a first amount of hydrogen uptake. The method may include performing a beam-line ion implantation process or a plasma doping process on the layer of amorphous silicon. The method may include removing hydrogen from the layer of amorphous silicon to a second amount of hydrogen uptake that is less than the first amount of hydrogen uptake.

Description

[Technical Field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims the benefit of and priority to U.S. Provisional Application No. 63 / 054,320, filed July 21, 2020, entitled "ION IMPLANTATION FOR REDUCED HYDROGEN INCORPORATION IN AMORPHOUS SILICON," which is incorporated herein by reference in its entirety.

[0002] TECHNICAL FIELD This technology relates to semiconductor processing methods and systems, and more particularly to systems and methods for producing films with reduced hydrogen content. [Background technology]

[0003] Integrated circuits are made possible by processes that create intricately patterned layers of material on substrate surfaces. Creating patterned materials on substrates requires controlled methods for forming and removing material. As device sizes continue to decrease, film properties can have a greater impact on device performance. The materials used to form layers of material can affect the operating characteristics of the devices created. As material thickness continues to decrease, the post-deposition properties of the film can have a greater impact on device performance.

[0004] Therefore, there is a need for improved systems and methods that can be used to fabricate high quality devices and structures. These and other needs are addressed by the present technology. Summary of the Invention

[0005] An exemplary method of semiconductor processing may include forming a layer of amorphous silicon on a semiconductor substrate. The layer of amorphous silicon may be characterized by a first amount of hydrogen uptake. The method may include performing an ion implantation process on the layer of amorphous silicon. The method may include removing hydrogen from the layer of amorphous silicon to a second amount of hydrogen uptake that is less than the first amount of hydrogen uptake.

[0006] In some embodiments, the semiconductor substrate may be maintained at a temperature of about 450°C or less during the semiconductor processing method. The ion implantation process may be performed at a temperature of about 300°C or greater. The ion implantation process may be performed using helium, neon, argon, or silicon ions. The ion implantation process may be or include a beam-line ion implantation process or a plasma doping implantation process. The second hydrogen incorporation amount may be about 1 atomic % or less.

[0007] Some embodiments of the present technology may include a semiconductor processing method. The method may include forming a thin film transistor on a semiconductor substrate. The thin film transistor may include a layer of amorphous silicon characterized by a first amount of hydrogen uptake. The method may include transferring the semiconductor substrate to a beamline ion implantation chamber or a plasma doping chamber. The method may include performing a beamline ion implantation or plasma doping process on the thin film transistor. The method may include reducing the amount of hydrogen from the layer of amorphous silicon to a second amount of hydrogen uptake that is less than the first amount of hydrogen uptake.

[0008] In some embodiments, the thin-film transistor may include a multilayer stack including a layer of amorphous silicon and one or more layers of doped or undoped amorphous silicon. The multilayer stack may include at least one layer of doped amorphous silicon. The dopant of the doped amorphous silicon may include one or more of phosphorus, boron, or arsenic. The thin-film transistor may be characterized by a thickness of about 100 nm or greater. The layer of amorphous silicon may be formed at a temperature of about 500°C or less. The beam-line ion implantation process or plasma doping may be performed at a temperature of about 550°C or less. The beam-line ion implantation or plasma doping process may be performed at a temperature of about 300°C or greater. The beam-line ion implantation or plasma doping process may be performed using helium, neon, argon, or silicon ions. The second hydrogen incorporation may be about 1 atomic % or less. The hydrogen incorporation of the entire thin-film transistor may be reduced to about 1 atomic % or less.

[0009] Some embodiments of the present technology may include a semiconductor processing method. The method may include forming a thin-film transistor on a semiconductor substrate in a first semiconductor processing chamber. The thin-film transistor may include a layer of amorphous silicon characterized by a first amount of hydrogen uptake. The layer of amorphous silicon may be disposed between at least two additional material layers. The method may include transferring the semiconductor substrate from the first semiconductor processing chamber to an ion implantation chamber. The method may include performing an ion implantation process on the thin-film transistor. The ion implantation process may be or include a beam-line ion implantation process or a plasma doping implantation process. The method may include reducing an amount of hydrogen from the layer of amorphous silicon to a second amount of hydrogen uptake that is less than the first amount of hydrogen uptake.

[0010] In some embodiments, the at least two additional material layers include one or more layers of doped amorphous silicon. The dopant of the doped amorphous silicon may include phosphorus, boron, or arsenic. The layer of amorphous silicon may be formed at a temperature of about 500°C or less, and the ion implantation process may be performed at a temperature of about 300°C or more. The first hydrogen incorporation may be at least about 5 atomic % and the second hydrogen incorporation may be about 1 atomic % or less. The layer of amorphous silicon may be further characterized by a nitrogen incorporation, and the nitrogen incorporation may be reduced to about 0.5 atomic % or less.

[0011] Such technology can provide numerous benefits over conventional systems and techniques. For example, embodiments of the technology can produce films characterized by reduced hydrogen content. Furthermore, the technology can reduce hydrogen content without increasing film stress or porosity due to hydrogen outgassing. These and other embodiments, along with many of their advantages and features, are described in further detail in conjunction with the following description and accompanying drawings.

[0012] A further understanding of the nature and advantages of the disclosed technology may be realized by reference to the remaining portions of the specification and the drawings. [Brief explanation of the drawings]

[0013] [Figure 1] 1 is a schematic cross-sectional view illustrating an exemplary plasma deposition system in accordance with some embodiments of the present technique; [Figure 2] 1 is a schematic cross-sectional view illustrating an exemplary ion implantation system in accordance with some embodiments of the present technique; [Figure 3] 1A-1D illustrate operations of a semiconductor processing method in accordance with some embodiments of the present technique. DETAILED DESCRIPTION OF THE INVENTION

[0014] Some of the drawings are included as schematic views. It should be understood that the drawings are for illustrative purposes and should not be considered to scale unless specifically indicated as such. Furthermore, as schematic views, the drawings are provided to aid in understanding and may not include all aspects or information compared to actual representations and may include exaggerated material for illustrative purposes.

[0015] In the accompanying drawings, similar components and / or features may have the same reference symbol. Furthermore, various components of the same type may be distinguished by adding a letter after the reference symbol that distinguishes between the similar components. If only the first reference symbol is used in the specification, the description is applicable to any of the similar components having the same first reference symbol, regardless of the letter.

[0016] As semiconductor device sizes continue to decrease, constituent films contained within the structures can affect device performance as well as the fabrication of other materials included in the devices. For example, processes for forming silicon-containing films may use silane or other silicon-containing materials. These precursors may contain hydrogen, which may be incorporated into the film. Incorporation of hydrogen into the film can create additional problems during processing. For example, hydrogen incorporated into the film may have poor thermal stability and may result in outgassing during subsequent processing. Furthermore, hydrogen can affect film stress, which can increase the compressibility of the film and even cause film delamination. Finally, the volume of hydrogen in the plasma can affect the deposition process, increasing the grain size and crystallinity of the formed film, which can further complicate the deposition process for forming amorphous silicon films.

[0017] To reduce or compensate for hydrogen uptake, conventional techniques can modify deposition parameters or implement corrective measures. For example, if deposition is performed at high temperatures, such as above about 500°C or above about 600°C, hydrogen can be released during deposition, thereby improving the quality and properties of the film. Additionally, conventional techniques can perform an anneal following deposition. The anneal process can densify the film and allow hydrogen to be removed from the structure. While these techniques can be effective during some fabrication operations, other processes may be limited by thermal budgets.

[0018] For example, during thin film transistor formation or various other processing operations, amorphous silicon may form on or within a device. In some of these devices, the underlying material or structure may not be able to withstand the temperatures associated with high temperature deposition or annealing and may be limited to processing temperatures of about 550°C or less, about 500°C or less, about 450°C or less, about 400°C or less, or less. Prior art techniques may be limited to producing films with hydrogen incorporation of up to 10 atomic % or more. In the case of thin film transistor formation, increased hydrogen incorporation may affect transistor mobility or performance.

[0019] A correlation may exist between the hydrogen content in amorphous silicon films and device mobility. For example, hydrogen incorporation can increase the amount of silicon-hydrogen bonds within the film structure. These bonds can form boundaries between grains or crystalline interfaces. Boundaries can be sites that can scatter electrons and holes traveling through the channel region. This scattering of electrons and holes can reduce the mobility and electrical performance of the channel material. As a result, reducing hydrogen incorporation into films in thermally constrained structures can improve the performance of transistors or other films compared to conventional structures.

[0020] The present technology overcomes these problems by implementing an ion implantation process to break constituent bonds and release hydrogen from the film. By implanting ions with sufficient energy, the hydrogen bonds can be broken, allowing hydrogen to be released from the film. Furthermore, by utilizing specific ion implantation techniques or adjusting the ion dose, the effects of substrate temperature, sputtering, and material during implantation can be limited.

[0021] While the remainder of the disclosure routinely identifies specific deposition processes utilizing the disclosed technology, it will be readily understood that the systems and methods are equally applicable to other deposition and etching processes, such as those that may be performed in the described chambers or any other chamber. Accordingly, the technology should not be considered limited to use with only these specific deposition processes and chambers. The disclosure discusses one set of possible chambers that can be used to perform processes according to embodiments of the present technology, and then describes further modifications and adjustments to this system according to embodiments of the present technology.

[0022] FIG. 1 illustrates a cross-sectional view of an exemplary processing chamber 100 in accordance with some embodiments of the present technique. This diagram may provide an overview of a system that may incorporate one or more aspects of the present technique and / or be specifically configured to perform one or more operations in accordance with embodiments of the present technique. Further details of the chamber 100 or the method performed therein may be further described below. While the chamber 100 may be utilized to form a film layer in accordance with some embodiments of the present technique, it should be understood that the method may similarly be performed in any chamber in which film formation may occur. The processing chamber 100 may include a chamber body 102, a substrate support 104 disposed within the chamber body 102, and a lid assembly 106 coupled to the chamber body 102 and enclosing the substrate support 104 within a processing volume 120. A substrate 103 may be provided to the processing volume 120 through an opening 126, which may be conventionally sealed for processing using a slit valve or door. The substrate 103 may rest on a surface 105 of the substrate support during processing. The substrate support 104 may be rotatable, as indicated by arrow 145, along an axis 147 about which the axis 144 of the substrate support 104 may lie. Alternatively, the substrate support 104 may be elevated and rotated as needed during the deposition process.

[0023] The plasma profile converter 111 may be disposed within the processing chamber 100 to control plasma distribution across a substrate 103 disposed on a substrate support 104. The plasma profile converter 111 may include a first electrode 108, which may be disposed adjacent to the chamber body 102 and may separate the chamber body 102 from other components of the lid assembly 106. The first electrode 108 may be part of the lid assembly 106 or may be a separate sidewall electrode. The first electrode 108 may be an annular or ring-shaped member or may be a ring electrode. The first electrode 108 may be a continuous loop around the circumference of the processing chamber 100, surrounding the processing volume 120, or may be discontinuous at selected locations as desired. The first electrode 108 may also be a perforated electrode, such as a perforated ring or mesh electrode, or a plate electrode, such as an auxiliary gas distributor.

[0024] The one or more isolators 110 a, 110 b may be a dielectric material such as a ceramic or a metal oxide, e.g., aluminum oxide and / or aluminum nitride, and may contact the first electrode 108 and electrically and thermally isolate the first electrode 108 from the gas distributor 112 and from the chamber body 102. The gas distributor 112 may define an aperture 118 for distributing process precursors into the processing volume 120. The gas distributor 112 may be coupled to a first power source 142, such as an RF generator, an RF power supply, a DC power supply, a pulsed DC power supply, a pulsed RF power supply, or any other power supply that may be coupled to a processing chamber. In some embodiments, the first power source 142 may be an RF power supply.

[0025] The gas distributor 112 may be a conductive gas distributor or a non-conductive gas distributor. The gas distributor 112 may also be formed of conductive and non-conductive components. For example, the body of the gas distributor 112 may be conductive, and the faceplate of the gas distributor 112 may be non-conductive. The gas distributor 112 may be powered, such as by a first power source 142 as shown in FIG. 1, or the gas distributor 112 may be coupled to ground in some embodiments.

[0026] The first electrode 108 may be coupled to a first tuned circuit 128, which may control the ground path of the processing chamber 100. The first tuned circuit 128 may include a first electronic sensor 130 and a first electronic controller 134. The first electronic controller 134 may be or include a variable capacitor or other circuit element. The first tuned circuit 128 may be or include one or more inductors 132. The first tuned circuit 128 may be any circuit that allows for a variable or controllable impedance under plasma conditions present in the processing volume 120 during processing. In some embodiments, such as the one shown, the first tuned circuit 128 may include a first circuit leg and a second circuit leg coupled in parallel between ground and the first electronic sensor 130. The first circuit leg may include a first inductor 132A. The second circuit leg may include a second inductor 132B coupled in series with the first electronic controller 134. The second inductor 132B may be disposed between the first electronic controller 134 and a node connecting both the first and second circuit legs to the first electronic sensor 130. The first electronic sensor 130 may be a voltage or current sensor and may be coupled to the first electronic controller 134, which may be responsible for some closed-loop control of the plasma conditions within the process volume 120.

[0027] The second electrode 122 may be coupled to the substrate support 104. The second electrode 122 may be embedded within the substrate support 104 or coupled to a surface of the substrate support 104. The second electrode 122 may be a plate, a perforated plate, a mesh, a wire screen, or any other distributed arrangement of conductive elements. The second electrode 122 may be a tuning electrode and may be coupled to a second tuning circuit 136 by, for example, a conduit 146, a cable having a selected resistance, such as 50 Ω, disposed within the axis 144 of the substrate support 104. The second tuning circuit 136 may have a second electronic sensor 138 and a second electronic controller 140, which may be a second variable capacitor. The second electronic sensor 138 may be a voltage or current sensor and may be coupled to the second electronic controller 140 to provide further control over the plasma conditions in the process volume 120.

[0028] The third electrode 124 may be a bias electrode and / or an electrostatic chuck electrode and may be coupled to the substrate support 104. The third electrode may be coupled to a second power source 150 through a filter 148, which may be an impedance matching circuit. The second power source 150 may be DC power, pulsed DC power, RF bias power, a pulsed RF source or bias power, or a combination of these or other power sources. In some embodiments, the second power source 150 may be RF bias power.

[0029] The lid assembly 106 and substrate support 104 of FIG. 1 may be used with any processing chamber for plasma or thermal processing. During operation, the processing chamber 100 may provide real-time control of plasma conditions within the processing volume 120. A substrate 103 may be disposed on the substrate support 104, and processing gases may be flowed through the lid assembly 106 using the inlet 114 according to any desired flow scheme. The gases may exit the processing chamber 100 through the outlet 152. Power may be coupled to the gas distributor 112 to establish a plasma within the processing volume 120. The substrate may receive an electrical bias using the third electrode 124 in some embodiments.

[0030] When a current is applied to the plasma in the process volume 120, a potential difference can be established between the plasma and the first electrode 108. A potential difference can also be established between the plasma and the second electrode 122. Electronic controllers 134, 140 can then be used to adjust the flow characteristics of the ground paths represented by the two tuned circuits 128 and 136. Set points can be communicated to the first tuned circuit 128 and the second tuned circuit 136 to provide independent control of the deposition rate and the center-to-edge plasma density uniformity. In embodiments where both electronic controllers are variable capacitors, electronic sensors can adjust the variable capacitors to independently maximize the deposition rate and minimize thickness non-uniformity.

[0031] Each tuning circuit 128, 136 can have a variable impedance that can be adjusted using the respective electronic controller 134, 140. If the electronic controller 134, 140 is a variable capacitor, the capacitance range of each variable capacitor and the inductance of the first inductor 132A and the second inductor 132B can be selected to provide an impedance range. This range can depend on the frequency and voltage characteristics of the plasma and can have a minimum value for the capacitance range of each variable capacitor. Thus, when the capacitance of the first electronic controller 134 is at a minimum or maximum value, the impedance of the first tuning circuit 128 can be high, resulting in a plasma shape with minimal aerial or lateral coverage above the substrate support. As the capacitance of the first electronic controller 134 approaches a value that minimizes the impedance of the first tuning circuit 128, the aerial coverage of the plasma can grow to a maximum value, effectively covering the entire active area of ​​the substrate support 104. As the capacitance of the first electronic controller 134 deviates from the minimum impedance setting, the plasma shape may shrink from the chamber walls and the air coverage of the substrate support may decrease. The second electronic controller 140 may have a similar effect, increasing or decreasing the air coverage of the plasma above the substrate support as the capacitance of the second electronic controller 140 can be changed.

[0032] Electronic sensors 130, 138 can be used to tune the respective circuits 128, 136 in a closed loop. A current or voltage setpoint may be installed in each sensor, depending on the type of sensor used, and the sensors may be equipped with control software that determines adjustments to the respective electronic controllers 134, 140 to minimize deviations from the setpoint. As a result, the plasma shape may be selected and dynamically controlled during processing. While the above discussion is based on electronic controllers 134, 140 being variable capacitors, it should be understood that any electronic component with adjustable characteristics may be used to provide tuning circuits 128 and 136 with adjustable impedance.

[0033] FIG. 2 shows a schematic cross-sectional view of an exemplary ion implantation system 200 in accordance with some embodiments of the present technique. System 200 may be utilized to implant electrons or ions into a film layer, which can alter the film layer's properties, such as breaking bonds within the film and allowing hydrogen to escape from the forming layer on the substrate. It should be understood that system 200 is merely one example of a beam-line ion implantation chamber that may be utilized in some embodiments of the present technique. Various other chambers capable of performing ion implantation, including plasma doping chambers or other implantation systems, may be utilized in embodiments of the present technique. For example, ion implantation system 200 is merely one example of an apparatus that may be utilized. In embodiments of the present technique, conventional plasma processing equipment may be utilized, as well as patterned beams, electron beams that may be pulsed or continuous, raster scans, variable scans, and any other ion or electron implantation methods. According to certain aspects, the one or more energetic particle beams may include a cylindrical beam, multiple adjacent or overlapping cylindrical beams, or ribbon-shaped beams, including a continuous rectangular beam. The energetic particle beam(s) may be moved relative to the substrate during processing, and / or the substrate can be moved relative to the energetic particle beam(s) during processing.

[0034] The plasma processing system 200 may include a processing chamber 202, a platen 234, a source 206, and a modifying element 208. The platen 234 may be positioned within the processing chamber 202 to support a substrate 238. The platen 234 may be coupled to an actuator, which may enable the platen 234 to move or translate in one or more horizontal and / or vertical directions during a scanning motion. The scanning motion may be performed in a single horizontal plane, which may be substantially parallel to the modifying element 208. The source 206 may be configured to generate a plasma 240 within the processing chamber 202. The modifying element 208 may include a pair of insulators 212, 214, which may define a gap therebetween with a horizontal spacing G. The insulators 212, 214 may be or include various insulating or semiconductor materials. In some embodiments, the elements may alternatively be conductive materials. The modifying element may also include a directional element 213 disposed in a position relative to the insulators 212 , 214 such that the ions 201 can be directed toward the substrate 238 .

[0035] In operation, the gas source 288 may supply an ionizable gas to the process chamber 202. Examples of ionizable gases may be or include various precursors containing one or more elements or ions. For example, precursors may include any material or materials that may be ionized to create one or more ions, including helium, hydrogen, neon, argon, krypton, fluorine, carbon, boron, nitrogen, or any other element or combination of elements, alone or in combination. The source 206 may generate a plasma 240 by exciting and ionizing a gas provided to the process chamber 202. Ions 201 may be attracted from the plasma 240 across the plasma sheath 242. For example, the bias source 290 may be configured to bias the substrate 238 to attract ions 201 from the plasma 240 across the plasma sheath 242. The bias source 290 may be a DC power supply that provides a DC voltage bias signal or an RF power supply that provides an RF bias signal.

[0036] The modifying element 208 may modify the electric field within the plasma sheath 242 to control the shape of the boundary 241 between the plasma 240 and the plasma sheath 242. The modifying element 208, in some embodiments, may include insulators 212, 214 and a directional element 213. The insulators 212, 214 and the directional element 213 may be made from materials such as quartz, alumina, boron nitride, glass, silicon nitride, or various other suitable materials. Because the directional element 213 can change the electric field within the plasma sheath 242, the boundary 241 between the plasma 240 and the plasma sheath 242 may depend on the placement of the directional element 213 relative to the insulators 212, 214.

[0037] Ions following orbital path 271 may strike substrate 238 at an angle of about +θ normal to surface 251. Ions following orbital path 269 may strike substrate 438 at an angle of about −θ normal to surface 251. Thus, the range of incidence angles normal to surface 251 may be about +1° to about +65° and about −1° to about −65°, and in some embodiments may exclude 0°. For example, a first range of incidence angles normal to surface 251 may be about +5° to about +65°, and a second range of incidence angles may be about −5° to about −65°. In some embodiments, the first range of incidence angles relative to surface 251 may be about −10° to about −20°, and the second range of incidence angles relative to surface 451 may be about +10° to about +20°. Additionally, in some embodiments, ion trajectories resulting from paths 269 and 271 may intersect with each other. Depending on numerous factors, which may include the positioning of the directional element 213, the horizontal spacing between the insulators 212, 214, the vertical spacing of the insulators 212, 214 above the surface 251, the dielectric constants of the directional element 213 and the insulators 212, 214, and other plasma processing parameters, the range of the angle of incidence (θ) may be from about +89° to about −89° and may exclude 0° in some embodiments.

[0038] In general, ions provided to a film on a substrate may modify various properties of the film. The range of incident angles may be selected based on the aspect ratio of 3D features on the substrate 238. For example, the sidewalls 247 of trench 244, whose size is exaggerated for clarity of illustration, may be treated more uniformly by ions 201 than in conventional plasma processing equipment and procedures. The aspect ratio may be defined as the relationship between the pitch between sidewalls 247 and the height of sidewall 247 extending from the substrate 238, and may determine the angle at which ions 201 are provided to provide more uniform treatment to sidewall 247. For example, a first range of incident angles normal to surface 251 and adapted to impinge on sidewall 247 may be from about +60° to about +90°, and a second range of incident angles may be from about −60° to about −90°. A variety of different angles may be employed as well. In some embodiments, the angle at which ions 201 may be provided may be selected to avoid contact with material below sidewall 247, such as substrate 238 or an insulator.

[0039] 3 illustrates exemplary operations of a processing method 300 in accordance with some embodiments of the present technique. The method may be performed in a variety of processing chambers, including processing chambers 100 and / or 200 described above. Method 300 may include one or more operations prior to the initiation of the specified method operations, including front-end processing, deposition, etching, polishing, cleaning, or any other operations that may be performed prior to the described operations. The method may include multiple optional operations as illustrated in the drawings, which may or may not be specifically associated with methods in accordance with the present technique. For example, many of the operations are described to provide a broader scope of semiconductor processing, but are not critical to the present technique or may be performed by alternative methods, as further described below.

[0040] Method 300 may involve any operation that develops a semiconductor structure for a particular fabrication operation. In some embodiments, method 300 may be performed on a base structure, while in some embodiments, the method may be performed subsequent to other material formation or removal. For example, various deposition, masking, or removal operations may be performed to fabricate any transistor, memory, or other structural features on the substrate. The substrate may be positioned in a processing region of a semiconductor processing chamber or disposed on a substrate support. Operations may be performed in the same chamber in which aspects of method 300 may be performed, or one or more operations may be performed in one or more chambers on a similar platform as the chamber in which operations of method 300 may be performed, or on a different platform.

[0041] In some embodiments, method 300 may include, in operation 305, forming a layer of amorphous silicon on a substrate. The formation or deposition may be performed using various precursors, such as silane or other silicon-containing materials, and in some embodiments, the delivered silicon-containing precursor may also include hydrogen. As a result, the amorphous silicon deposition or formed layer may be characterized by a first amount of hydrogen uptake. It should be understood that the present technique may not be limited to silicon films, such as amorphous silicon. The present technique may also encompass hydrogen management in various films formed on semiconductor substrates. As a result, the amorphous silicon layer should be considered as just one example film to which the present technique may be applied.

[0042] The amorphous silicon layer may be part of various structures, including thin film transistor structures in some embodiments. For example, in some embodiments, the amorphous silicon layer may be one of multiple layers in a stack of films formed on a substrate. In some embodiments, the amorphous silicon layer may be included with or between other layers of material, such as other silicon-containing layers or layers of other materials. In some thin film transistor structures, the amorphous silicon layer may be formed between layers of doped amorphous silicon. For example, one or more layers above and / or below the amorphous silicon layer may be formed with a dopant, such as phosphorus, boron, arsenic, or other material. The dopant may form an n-type material layer, and thus the thin film transistor structure may include n-type doped amorphous silicon disposed on either side of the formed amorphous silicon layer. Each layer of the stack, including the amorphous silicon layer, may be characterized by a thickness of about 500 nm or less, and may also be characterized by a thickness of about 400 nm or less, about 350 nm or less, about 300 nm or less, about 250 nm or less, about 200 nm or less, about 150 nm or less, about 100 nm or less, about 50 nm or less, or less.

[0043] As described above, some embodiments of the present technology may involve films formed on materials or structures characterized by a thermal budget of about 550°C or less, about 500°C or less, about 450°C or less, about 400°C or less, about 350°C or less, about 300°C or less, or less. Thus, the amorphous silicon layer may be formed at or below any of these temperatures to accommodate the underlying material, and in some embodiments, one or more operations, including all operations of method 300, may be performed at or below any of these temperatures, and the substrate being processed may be maintained below or near any of these temperatures throughout processing. The process pressure during formation may be about 1 Torr or greater, and may range from about 2 Torr to about 20 Torr, in some embodiments. Films may also be formed using any silicon-containing material, such as silane or other binary silicon-hydrogen compounds, and any silicon- and hydrogen-containing precursors. As a result, the formed layer may be characterized by a first hydrogen uptake. Higher temperature deposition and annealing may not be feasible for some structures, so hydrogen incorporation may reach up to about 3 atomic % or more, about 5 atomic % or more, about 7 atomic % or more, about 10 atomic % or more, or even more, which may result in any of the problems mentioned above, including stress effects and subsequent outgassing.

[0044] Following film formation, in some embodiments, the substrate with the layer of amorphous silicon formed thereon may be transferred from the first processing chamber to a second processing chamber in optional operation 310. For example, the formation or deposition of the amorphous silicon layer may be performed in a first chamber, such as chamber 100 or any other deposition chamber in which a silicon-containing material may be deposited. Following deposition, the substrate may be moved to a second chamber for an ion implantation process. The second chamber may be included on the same platform or tool as the first chamber, although in some embodiments, the substrate may be moved between tools for the ion implantation process.

[0045] In operation 315, an ion implantation process, such as beam-line ion implantation, may be performed on one or more layers of the substrate, including the amorphous silicon layer. In addition, a plasma doping process may be performed. Although referred to as ion implantation, the process may involve ion modification, which may include releasing ions from the ion implantation process, in which ion implantation is performed to break bonds within the formed film and release material from the film. The process may include a beam-line ion implantation process, a plasma doping implantation process, or any other implantation as described above. The ion implantation process may be performed to modify the properties of the film. For example, in some embodiments, ion implantation may be performed to break silicon-hydrogen bonds within a layer of material, thereby allowing hydrogen to be removed from the film. In a multilayer stack, the ion implantation process may be tailored to penetrate one or more layers of the stack, thereby allowing hydrogen to be reduced in multiple layers, including all layers of doped and undoped material.

[0046] Ion implantation processes may be performed at low pressures, depending on the process being performed. For example, plasma doping ion implantation may be performed at chamber pressures of about 100 mTorr or less, about 10 mTorr or less, about 1 mTorr or less, or even less. Beamline ion implantation may be performed at much lower chamber pressures, such as about 0.1 mTorr or less, about 0.05 mTorr or less, about 0.01 mTorr or less, or even less. These low-pressure operations can facilitate ion penetration through the film structure. Ion implantation processes may be performed at various substrate temperatures, such as from about 25°C to about 550°C. Exemplary beamline ion implantation species may include inert materials, such as helium, neon, or argon, that do not bond with amorphous silicon. In addition, silicon species may be used and may bond with amorphous silicon without doping the material to make it n- or p-type. The energy range of ion implantation may depend on the species used. For example, for relatively light species such as helium, the energy range may be lower than for heavier species such as silicon. For light to heavy species, the implant energy range may be about 500 eV to 300 keV, and the implant dose may be about 1 e 13 ~1e 16 ions / cm 2 For example, helium dosed at an energy of about 300 keV can modify amorphous silicon up to 2 μm or more, while silicon species will modify less than 1 μm.

[0047] The temperature at which the process may be performed can affect the energy of the ions, and in some embodiments, high-temperature ion implantation may be performed, thereby promoting the breaking of silicon-hydrogen bonds. For example, in some embodiments, sufficient removal of hydrogen may be achieved at temperatures of about 200°C or higher, about 250°C or higher, about 300°C or higher, about 350°C or higher, about 400°C or higher, about 450°C or higher, or even higher, although in some embodiments, the ion implantation process may be performed at or near the thermal budget temperatures mentioned above. If plasma doping is performed, the doping bias voltage may range from about 500 eV to 10 keV or higher. Thicker films can be modified by increasing the bias voltage. As one non-existent example, bias voltages closer to 10 kV can be used to modify films characterized by thicknesses of 100 nm to 200 nm using lighter species such as helium. Plasma doping can be performed at temperatures of 5e 15 ~1e 17 ions / cm 2 The plasma doping may also be carried out at a temperature ranging from about 25°C to about 500°C.

[0048] Ion implantation may use ions made from various precursors. For example, in some embodiments, ion implantation may be performed using helium, which, as a relatively light ion, can easily penetrate structures of 100 nm or more, thereby enabling hydrogen removal deeper within the film. Helium ion implantation may be performed at higher powers, which can facilitate bond breaking within the film and enable hydrogen removal. Because helium tends to become trapped within the film when ion implantation is performed, thus facilitating helium release, ion implantation may be performed at temperatures of about 250°C or higher, about 300°C or higher, or even higher. In some embodiments, silicon ions may be used in the ion implantation process from various silicon-containing precursors. Silicon may be characterized by a heavier mass, which, in some embodiments, may facilitate bond breaking. As a result, lower temperature and higher implant energy processes may be performed using silicon. Similarly, because the film being modified may be amorphous silicon, silicon ions may not act as dopants in the film, and trapping or incorporation may not adversely affect the resulting film. Additionally, heavier ions may be used to more easily control implantation depth, thus providing improved control over implantation and modification depth. For example, the process may be controlled to affect one or more layers of a thin film transistor structure, but may be limited to minimal penetration into the underlying structure.

[0049] A certain amount of densification may occur in the film based on the removal of hydrogen through the film and the reformation of bonds. Thus, in some embodiments, the thickness of the film after the ion modification process may be about 99% or less of the thickness of the layer or film after deposition. In some embodiments, the thickness may be about 98% or less, about 97% or less, about 96% or less, about 95% or less, about 94% or less, about 93% or less, about 92% or less, about 91% or less, about 90% or less, or less than the thickness of the film after deposition, while the thickness of the layer after ion modification may remain at about 80% or more, about 85% or more, about 87% or more, about 90% or more, about 92% or more, about 95% or more, or more.

[0050] The ion implantation dose can be more controlled than other plasma-enhanced processes, so sputtering of the formed film may be limited. For example, in some embodiments, the ion dose is about 1×10 16 ions / cm 2 It may be greater than or equal to about 1 x 10 17 ions / cm 2 More than 1 × 10 18 ions / cm 2 The plasma doping implant may be characterized by a higher dose than a beam-line implant, whereby helium may be used to break bonds and facilitate the release of hydrogen from the film. When the ion implantation is performed, the amount of hydrogen in the layer may be reduced to a second hydrogen incorporation amount in operation 320, which may be less than the first hydrogen incorporation amount. The second hydrogen incorporation amount, i.e., the amount remaining in either the thin film transistor or the amorphous silicon layer, may be about 5 atomic % or less, about 3 atomic % or less, about 1 atomic % or less, about 0.5 atomic % or less, or less.

[0051] Other materials within the amorphous silicon layer or any thin film transistor layer may also be reduced or removed. For example, in some embodiments, nitrogen may be incorporated into the deposited film. Nitrogen may be present in the deposition environment or incorporated into chamber seasoning materials, thereby exposing the formed film to nitrogen incorporation. In some embodiments, an ion implantation process may also remove nitrogen from one or more layers, reducing the amount of nitrogen incorporation in the film to about 1 atomic % or less, and may reduce nitrogen incorporation to about 0.5 atomic % or less, about 0.3 atomic % or less, about 0.1 atomic % or less, or even less. By utilizing ion implantation or modification processes, hydrogen incorporation in the film may be reduced from post-deposition levels, thereby improving the electrical performance of the deposited material. Additionally, by utilizing ion implantation techniques, hydrogen removal may occur at lower temperatures, thereby accommodating structures that may be constrained by thermal budgets.

[0052] In the foregoing description, for purposes of explanation, numerous details have been set forth in order to provide an understanding of various embodiments of the present technology. However, it will be apparent to one skilled in the art that particular embodiments may be practiced without some of these details, or with additional details.

[0053] Although several embodiments have been disclosed, those skilled in the art will recognize that various modifications, alternative configurations, and equivalents may be used without departing from the spirit of the embodiments. Additionally, in order to avoid unnecessarily obscuring the technology, many well-known processes and elements have not been described. Therefore, the above description should not be considered as limiting the scope of the technology.

[0054] Where a range of values ​​is provided, unless the context clearly indicates otherwise, it is understood that each intervening value between the upper and lower limits of that range, to the smallest decimal point of the unit of the lower limit, is also specifically disclosed. Any stated or unstated intervening value within a stated range, and any narrower range between any other stated or intervening value within that stated range, are also encompassed. The upper and lower limits of those smaller ranges may independently be included or excluded from the range, and each range in which either, neither, or both limits are included in the smaller range is also encompassed within the technology, subject to any specifically excluded limits in the stated range. When a stated range includes one or both of the limits, ranges excluding either or both of those included limits are also included.

[0055] As used in this specification and the appended claims, the singular forms "a," "an," and "the" include the plural forms unless the context clearly indicates otherwise. Thus, for example, a reference to a "precursor" includes a plurality of such precursors, a reference to a "layer" includes one or more layers and equivalents thereof known to those skilled in the art, and so forth.

[0056] Additionally, the words "comprise," "comprising," "contain," "containing," "include," and "including," when used in this specification and the claims that follow, are intended to specify the presence of stated features, integers, components, or operations, but do not exclude the presence or addition of one or more other features, integers, components, operations, acts, or groups.

Claims

1. forming a layer of amorphous silicon characterized by a first amount of hydrogen uptake on a semiconductor substrate; performing an ion implantation process on the layer of amorphous silicon at a temperature of 200° C. or greater to remove hydrogen from the layer of amorphous silicon to a second hydrogen uptake level less than the first hydrogen uptake level; A semiconductor processing method comprising:

2. 10. The semiconductor processing method of claim 1, wherein said semiconductor substrate is maintained at a temperature of 450[deg.] C. or less during said semiconductor processing method.

3. 10. The semiconductor processing method of claim 1, wherein said ion implantation process is carried out at a temperature of 300[deg.] C. or greater.

4. 10. The semiconductor processing method of claim 1, wherein the ion implantation process is performed using ions of helium, neon, argon, or silicon.

5. 10. The semiconductor processing method of claim 1, wherein the ion implantation process comprises a beam-line ion implantation process or a plasma doping implantation process.

6. 2. The semiconductor processing method of claim 1, wherein said second hydrogen uptake is less than or equal to 1 atomic percent.

7. forming a thin film transistor on a semiconductor substrate, the thin film transistor comprising a layer of amorphous silicon characterized by a first amount of hydrogen uptake; transferring the semiconductor substrate to a beam-line ion implantation chamber or plasma doping chamber; performing a beamline ion implantation or plasma doping process on the thin film transistor at a temperature of 200° C. or greater to reduce an amount of hydrogen from the layer of amorphous silicon to a second hydrogen uptake amount less than the first hydrogen uptake amount; A semiconductor processing method comprising:

8. 8. The semiconductor processing method of claim 7, wherein said thin film transistor comprises a multi-layer stack including said layer of amorphous silicon and one or more layers of doped or undoped amorphous silicon.

9. 9. The semiconductor processing method of claim 8, wherein the multi-layer stack comprises at least one layer of doped amorphous silicon, the dopants of the doped amorphous silicon comprising one or more of phosphorus, boron, or arsenic.

10. 8. The semiconductor processing method of claim 7, wherein said thin film transistor is characterized by a thickness of 100 nm or greater.

11. 8. The semiconductor processing method of claim 7, wherein said layer of amorphous silicon is formed at a temperature of 500°C or less, and said beam-line ion implantation process or said plasma doping is carried out at a temperature of 550°C or less.

12. 12. The semiconductor processing method of claim 11, wherein said beam-line ion implantation or said plasma doping process is performed at a temperature of 300°C or greater.

13. 8. The semiconductor processing method of claim 7, wherein the beam-line ion implantation or the plasma doping process is performed with ions of helium, neon, argon, or silicon.

14. 8. The semiconductor processing method of claim 7, wherein the second amount of hydrogen uptake is less than or equal to 1 atomic percent.

15. 15. The semiconductor processing method of claim 14, wherein the hydrogen uptake across the thin film transistor is reduced to 1 atomic % or less.

16. forming a thin film transistor on a semiconductor substrate in a first semiconductor processing chamber, the thin film transistor comprising a layer of amorphous silicon characterized by a first amount of hydrogen uptake, the layer of amorphous silicon being disposed between at least two additional layers of material; transferring the semiconductor substrate from the first semiconductor processing chamber to an ion implantation chamber; performing an ion implantation process, including a beam-line ion implantation process or a plasma doping implantation process, on the thin film transistor at a temperature of 200° C. or greater to reduce an amount of hydrogen from the layer of amorphous silicon to a second hydrogen uptake amount that is less than the first hydrogen uptake amount; A semiconductor processing method comprising:

17. 17. The semiconductor processing method of claim 16, wherein the at least two additional layers of material comprise one or more layers of doped amorphous silicon, and wherein a dopant in the doped amorphous silicon comprises phosphorus, boron, or arsenic.

18. 17. The semiconductor processing method of claim 16, wherein said layer of amorphous silicon is formed at a temperature of 500°C or less and said ion implantation process is carried out at a temperature of 300°C or more.

19. 17. The semiconductor processing method of claim 16, wherein said first hydrogen uptake is at least 5 atomic percent and said second hydrogen uptake is less than or equal to 1 atomic percent.

20. 17. The semiconductor processing method of claim 16, wherein said layer of amorphous silicon is further characterized by nitrogen incorporation, said nitrogen incorporation being reduced to 0.5 atomic percent or less.

21. The semiconductor processing method of claim 1, wherein the ion implantation process includes a beamline ion implantation process using an ion implantation system having correction elements for directing the ion beam within the processing chamber.

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