Method of reducing particles in a physical vapor deposition (PVD) chamber

Abstract

To provide a method for reducing particle formation in a physical vapor deposition (PVD) chamber.SOLUTION: Performing a plurality of first deposition processes on a corresponding series of substrates disposed on a substrate support in a PVD chamber, the PVD chamber including a cover ring disposed around the substrate support and having a textured outer surface; A silicon nitride (SiN) layer having a first thickness is deposited on the textured outer surface during each of the plurality of first deposition processes, and performing a second deposition process on the cover ring between a subset of the plurality of first deposition processes to deposit an amorphous silicon layer having a second thickness on the underlying silicon nitride (SiN) layer.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] FIELD OF THE DISCLOSURE Embodiments of the present disclosure relate generally to substrate processing equipment, and more particularly to reducing particle formation in substrate processing equipment. [Background technology]

[0002] Sputtering, also known as physical vapor deposition (PVD), is a method for forming features in integrated circuits. Sputtering deposits a layer of material onto a substrate. A source material, such as a target, is bombarded with ions to eject material from the target. The material is then deposited on the substrate. The inventors have observed that during the deposition process, material or contaminants can deposit on chamber components. The material deposited on the chamber components can form a series of deposition layers during each successive deposition process. The deposition layers are prone to flaking, especially when the PVD chamber undergoes thermal cycles during and between processes, which can create unwanted particles and contaminants within the PVD chamber. Summary of the Invention

[0003] Accordingly, the present inventors have provided an improved PVD processing chamber and method of use for reducing unwanted particles in the chamber.

[0004]

[0009] In some embodiments, a method for reducing particle formation in a physical vapor deposition (PVD) chamber includes: performing a plurality of first deposition processes on a corresponding series of substrates disposed on a substrate support in the PVD chamber, the PVD chamber including a process kit disposed around the substrate support and having a textured outer surface, wherein a silicon nitride (SiN) layer having a first thickness is deposited on the textured outer surface during each of the plurality of first deposition processes; and performing a second deposition process on the process kit between a subset of the plurality of first deposition processes to deposit an amorphous silicon layer having a second thickness on the underlying silicon nitride (SiN) layer.

[0005] In some embodiments, a method for reducing particle formation in a physical vapor deposition (PVD) chamber includes performing a plurality of first deposition processes on a corresponding series of substrates disposed on a substrate support in the PVD chamber, the PVD chamber including a cover ring disposed around the substrate support and having a textured outer surface, wherein a silicon nitride (SiN) layer having a first thickness is deposited on the textured outer surface during each of the plurality of first deposition processes; performing a second deposition process on the cover ring between a subset of the plurality of first deposition processes to deposit an amorphous silicon layer having a second thickness on the underlying silicon nitride (SiN) layer, the second thickness being greater than the first thickness; and performing a third deposition process on the cover ring between the second subset of the plurality of first deposition processes to deposit an amorphous silicon layer having a third thickness greater than the second thickness.

[0006] In some embodiments, a method for reducing particle formation in a physical vapor deposition (PVD) chamber includes performing a first deposition process on a substrate disposed on a substrate support in the PVD chamber, the PVD chamber including a cover ring disposed around the substrate support and having a textured outer surface, wherein a silicon nitride (SiN) layer having a first thickness is deposited on the textured outer surface during the first deposition process; repeating the first deposition process on about 10 to about 20 subsequent corresponding substrates in the PVD chamber; and performing a second deposition process on the cover ring in the PVD chamber to deposit an amorphous silicon layer having a second thickness on the underlying silicon nitride (SiN) layer.

[0007] Other and further embodiments of the present disclosure are described below.

[0008] Embodiments of the present disclosure, briefly summarized above and discussed in more detail below, can be understood by reference to exemplary embodiments thereof as illustrated in the accompanying drawings, which, however, are not to be considered limiting in scope, as the present disclosure may recognize other equally effective embodiments. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a flowchart of a method for reducing particle formation in a physical vapor deposition (PVD) chamber according to at least some embodiments of the present disclosure. [Figure 2] 1 is a schematic cross-sectional view of a PVD chamber according to at least some embodiments of the present disclosure. [Figure 3] FIG. 2 is a detailed isometric view of a portion of a process kit according to some embodiments of the present disclosure. [Figure 4] FIG. 2 is a schematic side view of a portion of a process kit according to some embodiments of the present disclosure. [Figure 5]FIG. 1 is a block diagram of a multiple deposition process in accordance with at least some embodiments of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0010] To facilitate understanding, the same reference symbols have been used wherever possible to designate identical elements common to the figures. The figures are not drawn to scale and may be simplified for clarity. Elements and features of one embodiment may be beneficially incorporated in other embodiments without further elaboration.

[0011] Provided herein are embodiments of a method and apparatus for reducing particle formation in a physical vapor deposition (PVD) chamber. During a deposition process on a substrate disposed in a PVD chamber, material deposits on chamber components, such as a process kit. The material deposited on the chamber components may form a series of compressive layers during each successive deposition process. The compressive layers may be particularly susceptible to flaking when thermal cycling occurs in the PVD chamber. The methods provided herein facilitate adding a tensile layer of material on one or more compressive material layers to prevent unwanted particle generation in the PVD chamber, for example, due to flaking.

[0012] FIG. 1 shows a flowchart of a method 100 for reducing particle formation in a physical vapor deposition (PVD) chamber according to at least some embodiments of the present disclosure. At 102, the method 100 includes performing a plurality of first deposition processes in a PVD chamber, such as the process chamber 200 discussed below with respect to FIG. 2, on a corresponding series of substrates (e.g., substrates 204) disposed on a substrate support (e.g., substrate support 230) in the PVD chamber. The PVD chamber includes a process kit (e.g., process kit 250) disposed around the substrate support and having a textured outer surface. The process kit may include one or more of a cover ring (e.g., cover ring 255), a deposition ring (e.g., deposition ring 254), a lower shield (e.g., lower shield 252), or an upper shield (e.g., upper shield 251). The textured outer surface may be textured by any suitable method, for example, by additive manufacturing, such as bead blasting, arc spraying, or three-dimensional printing. In some embodiments, the textured exterior surface includes a plurality of protrusions having a spacing between them of about 0.5 millimeters to about 4.5 millimeters, hi some embodiments, the textured exterior surface includes a plurality of protrusions having a height of about 0.2 millimeters to about 1.5 millimeters.

[0013] In some embodiments, the plurality of first deposition processes includes using a process gas including nitrogen or a combination of nitrogen and argon, and supplying the process gas via a gas supply (e.g., gas supply 266). During use, in some embodiments, a silicon nitride (SiN) layer having a first thickness is deposited on the textured exterior surface of the process kit during each of the plurality of first deposition processes. In some embodiments, the first thickness is between about 100 nanometers and about 300 nanometers. In some embodiments, the SiN layer is a compressive stress layer. For example, the SiN layer may have a compressive stress of between about −2.0 GPa and about −1.0 GPa. During the plurality of first deposition processes, multiple SiN layers are deposited on the process kit. Thermal cycling in process chamber 200 between successive first deposition processes may cause the plurality of SiN layers to crack and delaminate.

[0014] At 104, method 100 includes performing a second deposition process on the process kit between subsets of the plurality of first deposition processes. In some embodiments, as shown in FIG. 4 , an amorphous silicon layer (e.g., amorphous silicon layer 404) having a second thickness is deposited on an underlying silicon nitride (SiN) layer (e.g., silicon nitride layer 402). The amorphous silicon layer can advantageously cover the SiN layer and counteract the compressive stress of the SiN layer, thereby reducing or mitigating cracking and spalling of the SiN, which can contaminate the process chamber. In some embodiments, the amorphous silicon layer is a tensile stress layer. In some embodiments, method 100 further includes pressurizing the interior volume of the PVD chamber to a pressure of about 10 mTorr to about 20 mTorr during the second deposition process, at which pressure the deposited amorphous silicon layer advantageously has a higher tensile stress. For example, the amorphous silicon layer may have a tensile stress of about 0.05 GPa to about 0.3 GPa.

[0015] In some embodiments, the subset of the plurality of first deposition processes may be based on the number of substrates processed, kilowatt-hours used, etc. For example, the subset of the plurality of first deposition processes may include processing between about 10 and about 20 substrates. In some embodiments, the subset of the plurality of first deposition processes includes processing between about 12 and about 15 substrates. In some embodiments, a second deposition process is performed every about 20 kilowatt-hours to about 60 kilowatt-hours. In some embodiments, the second thickness exceeds the combined thickness of the plurality of first deposition processes in each subset. In some embodiments, the second thickness is between about 1 micrometer and about 4 micrometers. In some embodiments, the second deposition process is performed using argon as a process gas. In some embodiments, a shutter disk is placed on the substrate support during the second deposition process instead of the substrate. The plurality of first deposition processes and the second deposition process may be repeated until the end of the life of the process kit.

[0016] Optionally, at 106, a third deposition process is performed on the process kit between second subsets of the plurality of first deposition processes to deposit an amorphous silicon layer having a third thickness greater than the second thickness. In some embodiments, the third thickness is about 3 to about 6 micrometers. In some embodiments, the second subset includes about 900 to about 1500 substrates. In some embodiments, the second subset includes about 1000 to about 1200 substrates. The third deposition process may be repeated for each second subset until the end of the life of the process kit.

[0017] FIG. 2 shows a schematic cross-sectional view of a PVD chamber (e.g., process chamber 200) in accordance with at least some embodiments of the present disclosure. However, other processing chambers may also benefit from the inventive apparatus disclosed herein. The process chamber 200 includes chamber walls 206 that enclose an interior volume having a processing volume 208 and a non-processing volume 209. The chamber walls 206 include side walls 216, a bottom wall 220, and a ceiling 224. The ceiling 224 may include a chamber lid or similar cover to seal the interior volume. The process chamber 200 can be a stand-alone chamber or part of a multi-chamber platform (not shown) having interconnected chambers connected by a substrate transfer mechanism (e.g., a substrate transfer robot) that transfers substrates 204 between the various chambers. The process chamber 200 can be a PVD chamber capable of sputter-depositing material onto the substrate 204. Non-limiting examples of materials suitable for sputter deposition include silicon nitride (SiN), silicon oxide (SiO2), amorphous Si, silicon oxycarbide (SiOC), and silicon oxynitride (SiON).

[0018] The process chamber 200 includes a substrate support 230 including a pedestal 234 for supporting a substrate 204. The pedestal 234 has a substrate support surface 238 having a plane substantially parallel to a sputtering surface 239 of a sputtering target 240 disposed in an upper portion of the process chamber 200. The substrate support surface 238 of the pedestal 234 receives and supports the substrate 204 during processing. The pedestal 234 may include an electrostatic chuck or a heater (such as a resistive heater, a heat exchanger, or other suitable heating device). During operation, the substrate 204 is introduced into the non-processing volume 209 of the process chamber 200 through a substrate entry port 242 in the sidewall 216 of the process chamber 200 and is placed on the substrate support 230 in a non-processing position during loading of the substrate 204. A support lift mechanism can raise or lower the substrate support 230, and a lift finger assembly can be used to raise or lower the substrate 204 onto the substrate support 230 while a robotic arm places the substrate 204 on the substrate support 230. The pedestal 234 can be maintained at an electrically floating potential during plasma operation or can be grounded.

[0019] The process chamber 200 may include a sealing apparatus 290 coupled to the pedestal 234 via a base plate 289, which may be coupled to the substrate support 230. The sealing apparatus 190 is configured to fluidly isolate the processing volume 208 from the non-processing volume 209 during processing of the substrate 204, such that only pumping down to process pressure and process gas supply occurs in the processing volume 208. As a result, the time required to pump down and supply gas to the processing volume 208 is reduced.

[0020] The process chamber 200 also contains a process kit 250, which includes various components that are easily removable from the process chamber 200, for example, to remove sputtering deposits from component surfaces, to replace or repair corroded components, or to adapt the process chamber 200 for other processes. The process kit 250 may be made from any suitable material, such as aluminum, stainless steel, or a ceramic material. The gas supply 266 is configured to supply one or more process gases to the process volume 208 during processing. The gas supply 266 may be coupled to gas supply channels 281 that facilitate the delivery of one or more process gases to the process volume 208. Additionally, the process chamber 200 may include a pumping plenum 280 fluidly coupled to the process volume 208. The pumping plenum 280 is coupled to a pump 285 to evacuate the process volume 208.

[0021] In some embodiments, the process kit 250 includes an upper shield 251 and a lower shield 252. The upper shield has a diameter sized to surround the sputtering surface 239 of the sputtering target 240 and the substrate support 230 (e.g., a diameter larger than the sputtering surface 239 and larger than the support surface of the substrate support 230). The upper shield may have an upper portion 257 disposed above the lower shield 252, and a lower portion 258 extending downwardly from the upper portion 257 and spaced apart from the radially inner surface of the lower shield 252 to vertically overlap at least a portion of the lower shield 252 (e.g., defining a gap between the lower portion 258 and the lower shield 252).

[0022] The bottom shield 252 includes a cylindrical portion 267, a ledge 268 extending radially inward from the bottom of the cylindrical portion 267, and a lip 269 extending upward from the radially innermost portion of the ledge 268 and surrounding the substrate support 230. While the top shield 251 and the bottom shield 252 are illustrated as separate elements, in some embodiments, the top shield 251 and the bottom shield 252 may be formed as a unitary structure. The top shield 251 and the bottom shield 252 may be formed from the same or different materials, such as, for example, an aluminum alloy, stainless steel, or ceramic. In some embodiments, the top 257 of the top shield 251 and the top of the cylindrical portion 267 mate with an annular adapter 259 to form a pumping plenum 180 and a gas delivery channel 281, both of which are fluidly coupled to the process volume 208. In some embodiments, an insulator ring 263 may be disposed between the annular adapter 259 and the backing plate 261 to electrically insulate the annular adapter 259 and the chamber wall from the backing plate 261 .

[0023] The process kit 250 may include a cover ring 255 disposed over the lip 269 and a deposition ring 254 disposed below the cover ring 255. A bottom surface of the cover ring 255 is aligned with the deposition ring 254. The cover ring 255 at least partially covers the deposition ring 254. The deposition ring 254 and the cover ring 255 cooperate to reduce the formation of sputter deposits on the peripheral wall of the substrate support 230 and the overhanging edge 253 of the substrate 204.

[0024] The process chamber 200 further includes a sealing device 190 coupled to the pedestal 134 to seal the processing volume 108 from the non-processing volume 109 when the pedestal 134 is in the processing position. The sealing device 190 is configured to selectively seal the processing volume 108 from the non-processing volume 109 when the pedestal 134 is in the processing position, allowing the processing volume 108 and the non-processing volume 109 to be fluidly coupled when the pedestal 134 is in the non-processing position, e.g., in the lower load position.

[0025] The sputtering target 240 is connected to one or both of a DC power supply 246 and an RF power supply 248. The DC power supply 246 can apply a bias voltage to the sputtering target 240 relative to the upper shield 251, which can be electrically floating during the sputtering process. The RF power supply 248 activates the sputtering gas to form a plasma of the sputtering gas, while the DC power supply 246 supplies power to the sputtering target 240, the upper shield 251, the pedestal 234, and other chamber components connected to the DC power supply 246. The formed plasma impinges on and impacts the sputtering surface 239 of the sputtering target 240, sputtering material from the sputtering surface 239 onto the substrate 204. In some embodiments, the RF energy supplied by the RF power supply 248 can have a frequency ranging from about 2 MHz to about 60 MHz, or non-limiting frequencies such as 2 MHz, 13.56 MHz, 27.12 MHz, or 60 MHz can be used. In some embodiments, multiple (ie, two or more) RF power sources may be provided to provide RF energy at multiple of the above frequencies.

[0026] In some embodiments, the process chamber 200 may include a magnetic field generator 264 disposed above the sputtering target 240 to shape a magnetic field around the sputtering target 240 to improve sputtering of the sputtering target 240. The capacitively generated plasma may be enhanced by the magnetic field generator 264, in which, for example, a permanent magnet or an electromagnetic coil may provide a magnetic field in the process chamber 200 having a rotating field with an axis of rotation perpendicular to the plane of the substrate 204. The process chamber 200 may also or alternatively include the magnetic field generator 264, which generates a magnetic field near the sputtering target 240 in the process chamber 200 to increase the ion density in a high-density plasma region adjacent to the sputtering target 240, thereby improving sputtering of the target material. In some embodiments, the sputtering target 240 is coupled to a backing plate 246 disposed between the sputtering target 240 and the magnetic field generator 264.

[0027] In some embodiments, the process chamber 200 may further include an exhaust 270. The exhaust 270 includes an exhaust port 271 that may receive a portion of the spent process gas and pass the spent gas to an exhaust conduit 272 having a throttle valve 279 to control the pressure of the gas in the process chamber 200. The exhaust conduit 272 is connected to one or more exhaust pumps 273.

[0028] The various components of the process chamber 200 may be controlled by a controller 274. The controller 274 includes program code having instruction sets for operating the components to perform the methods described herein. For example, the controller 274 may include program code including, but not limited to, a substrate positioning instruction set for operating the pedestal 234 and the substrate transfer mechanism, instructions for performing a second deposition process or a third deposition process based on the number of substrates being processed, a gas flow control instruction set for operating a gas flow control valve to set the flow rate of sputtering gas into the process chamber 200, a gas pressure control instruction set for operating to maintain the pressure in the process chamber 200, a gas energizer control instruction set for operating the RF power supply 248 to set a gas activation power level, a temperature control instruction set for controlling a temperature control system in the pedestal 234, and a process monitoring instruction set for monitoring the process in the process chamber 200.

[0029] FIG. 3 illustrates a detailed isometric view of a portion of a process kit 150 according to some embodiments of the present disclosure. An exterior surface 300 of the process kit 150 is advantageously textured to promote adhesion of deposited materials. For example, FIG. 3 illustrates an exterior surface 300 textured by additive manufacturing techniques, including a plurality of protrusions 302 extending from the exterior surface 300 and forming a plurality of valleys 306 therebetween. Additive manufacturing is generally a technique for producing three-dimensional components by laying down successive thin layers of material. The plurality of protrusions 302 may have a top surface 308 having a diameter 312 between about 0.6 millimeters and about 1.4 millimeters. The plurality of protrusions 320 may be separated by a first distance 314. In some embodiments, the first distance 314 is between about 0.5 millimeters and about 4.5 millimeters. In some embodiments, the first distance 314 may be measured from the top surface of each of the plurality of protrusions 302. In some embodiments, the plurality of protrusions 302 have a height 316 from the outer surface 300 of the process kit 250 to the top surface 308 of the plurality of protrusions 302 of between about 0.2 millimeters and about 1.5 millimeters.

[0030] FIG. 4 illustrates a schematic cross-sectional view of a process kit according to some embodiments of the present disclosure after multiple first and second deposition processes. As shown in FIG. 4, the process kit 250 includes multiple SiN layers 402, where each of the SiN layers (e.g., 402a, 402b, ... 402n) corresponds to a first deposition process. In some embodiments, the multiple SiN layers 402 include about 10 to about 20 layers. In some embodiments, the first SiN layer thickness 406 of each of the multiple SiN layers 402 is about 100 nanometers to about 300 nanometers. An amorphous silicon layer 404 is disposed on the multiple SiN layers 402. In some embodiments, the amorphous silicon layer 404 has a second thickness 410 of about 1 micrometer to about 4 micrometers.

[0031] 5 shows a block diagram of a plurality of deposition processes 500 according to some embodiments of the present disclosure. In some embodiments, the plurality of deposition processes 500 includes a plurality of subsets 502 (e.g., subsets 502a-502n). Each of the plurality of subsets 502 includes a plurality of first deposition processes 504 (e.g., first deposition processes 504a-504n), in which a SiN layer is deposited on the process kit 250. In some embodiments, the first deposition process 504n corresponds to the 10th to approximately 20th first deposition process in each of the plurality of subsets 502. After the first deposition process 504n of each subset, a second deposition process 510 including amorphous silicon deposition is performed on the process kit 250.

[0032] In some embodiments, the plurality of deposition processes 500 includes a plurality of second subsets 506 (only one is shown in FIG. 5 for clarity). Each of the plurality of second subsets 506 includes a plurality of first deposition processes 504 of the plurality of subsets. For example, second subset 506a includes a plurality of first deposition processes 504a-504n for subsets 502a-502n. A third deposition process 520 including amorphous silicon deposition may be performed on the process kit 250 after each of the plurality of second subsets 506. In some embodiments, the third deposition process 520 may be performed after processing about 900 to about 1500 substrates. Thus, the second deposition process 510 and the third deposition process 520 may be repeated until the end of the life of the process kit 250. In some embodiments, the end of the life of the process kit 250 corresponds to processing about 2000 to about 4000 substrates.

[0033] While the forgoing is directed to embodiments of the present disclosure, other and further embodiments of the present disclosure may be devised without departing from the basic scope thereof.

Claims

1. 1. A method for reducing particle formation in a physical vapor deposition (PVD) chamber, comprising: performing a plurality of first deposition processes on a corresponding series of substrates disposed on a substrate support in the PVD chamber, the PVD chamber including a process kit disposed about the substrate support and having a textured outer surface, wherein a silicon nitride layer having a thickness less than or equal to a first thickness is deposited on the textured outer surface during each of the plurality of first deposition processes; performing a second deposition process on the process kit between a subset of the plurality of first deposition processes to deposit an amorphous silicon layer having a second thickness on a last silicon nitride layer of the silicon nitride layers deposited during the plurality of first deposition processes.

2. The method of claim 1 , wherein the subset of the plurality of first deposition processes comprises processing between about 10 substrates and about 20 substrates.

3. The method of claim 1 , further comprising pressurizing the interior volume of the PVD chamber to a pressure of about 10 mTorr to about 20 mTorr during the second deposition process.

4. The method of claim 1 , wherein the first thickness is between about 100 nanometers and about 300 nanometers.

5. The method of claim 1 , wherein the second thickness is between about 1 micrometer and about 4 micrometers.

6. 10. The method of claim 1, further comprising: performing a third deposition process on the process kit between a second subset of the plurality of first deposition processes to deposit an amorphous silicon layer having a third thickness greater than the second thickness.

7. The method of claim 6 , wherein the second subset comprises from about 900 to about 1500 substrates.

8. The method of claim 6, wherein the third thickness is from about 3 to about 6 micrometers.

9. The method of claim 6, wherein the third deposition process occurs about every 250 kilowatt hours to 350 kilowatt hours.

10. 10. The method according to claim 1, wherein the silicon nitride (SiN) layer is a compressive stress layer and the amorphous silicon layer is a tensile stress layer.

11. The method of claim 1 , wherein the second deposition process comprises using argon as a process gas.

12. The method of claim 1 , wherein the plurality of first deposition processes includes using a process gas comprising nitrogen and argon.

13. The method of claim 1 , further comprising placing a shutter disk on the substrate support during the second deposition process.

14. The method of any one of claims 1 to 9, wherein the textured outer surface comprises a plurality of protrusions spaced apart from each other by about 0.5 millimeters to about 4.5 millimeters.

15. 10. The method of any one of claims 1 to 9, wherein the textured outer surface comprises a plurality of protrusions having a height of about 0.2 millimeters to about 1.5 millimeters.

16. The method of claim 1 , wherein the second thickness is greater than the first thickness.

17. 10. The method of any one of claims 1 to 9, wherein the second deposition process is performed about every 20 kilowatt hours to 60 kilowatt hours.

18. The method of any one of claims 1 to 9, wherein the process kit is a cover ring.

19. The method of claim 1 , further comprising using a controller to perform the method.

20. The method of claim 1 , wherein the plurality of first deposition processes are performed in the same chamber as the second deposition process.

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