Method for manufacturing nitride semiconductor device

Abstract

To provide a cap layer suitable for suppressing escape of nitrogen from the surface of a nitride semiconductor layer during high-temperature heat treatment.SOLUTION: A method for manufacturing a nitride semiconductor device (1) includes a step of ion-implanting a dopant into a nitride semiconductor layer (14) made of GaN, a step of forming of a cap layer (50) on at least a portion of the surface of the nitride semiconductor layer, and an annealing step of activating the dopant by heat treatment, and the cap layer includes a material having a lattice mismatch with GaN of less than 2.5% and a melting point of 1500°C or higher.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The technology disclosed in this specification relates to a method for manufacturing a nitride semiconductor device. [Background technology]

[0002] To activate dopants ion-implanted into nitride semiconductor layers made of GaN (gallium nitride), high-temperature heat treatment at temperatures above 1200°C is required. However, such high-temperature heat treatment causes nitrogen to escape from the surface of the nitride semiconductor layer, resulting in the formation of pits on the surface of the nitride semiconductor layer.

[0003] Patent Document 1 discloses a technique for forming a cap layer made of AlGaN (aluminum gallium nitride) on the surface of a nitride semiconductor layer in order to prevent nitrogen from escaping from the surface of the nitride semiconductor layer. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2015-534058 Summary of the Invention [Problem to be solved by the invention]

[0005] If the composition ratio of aluminum in the cap layer of AlGaN (aluminum gallium nitride) is decreased, the lattice mismatch with the nitride semiconductor layer made of GaN (gallium nitride) as the material becomes smaller, and the generation of cracks during high-temperature heat treatment can be suppressed. However, the melting point becomes lower and the heat resistance deteriorates. On the other hand, if the composition ratio of aluminum in the cap layer of AlGaN (aluminum gallium nitride) is increased, the melting point becomes higher and the heat resistance is improved. However, the lattice mismatch with the nitride semiconductor layer made of GaN (gallium nitride) as the material becomes larger, and cracks occur during high-temperature heat treatment. Thus, it is difficult for the cap layer made of AlGaN (aluminum gallium nitride) to achieve both suppression of crack generation and heat resistance during high-temperature heat treatment.

[0006] This specification aims to provide a cap layer suitable for suppressing the escape of nitrogen from the surface of a nitride semiconductor layer during high-temperature heat treatment.

Means for Solving the Problems

[0007] The method for manufacturing a nitride semiconductor device (1) disclosed in this specification may include a step of ion-implanting a dopant into a nitride semiconductor layer (14) made of GaN, a step of forming a cap layer (50) on at least a part of the surface of the nitride semiconductor layer, and an annealing step of activating the dopant by heat treatment. Here, the surface of the nitride semiconductor layer is the surface that would be exposed to the outside in the annealing step if the cap layer were not formed. The cap layer may be formed over the entire surface of the nitride semiconductor layer, or may be formed only on a part of the surface where the electrical characteristics may be affected by pits due to nitrogen escape. The cap layer includes a material having a lattice mismatch with GaN of less than 2.5% and a melting point of 1500 °C or higher. The cap layer used in the above manufacturing method is not particularly limited. For example, ScN, Sc x Al 1-x N (0 < x ≤ 0.36), HfN, ZrN, ZnO, ScMgAlO4, MnO, TaC, NbC, Mo, W, ZrB2, WB2, MoB2, ITO may include at least one material selected from the group consisting of.

[0008] AlN (aluminum nitride), a conventionally commonly used cap layer material, has a lattice mismatch with GaN (gallium nitride) of 2.5%. A cap layer made of AlN (aluminum nitride) has a problem of cracking during high-temperature heat treatment due to the difference in lattice constant with a nitride semiconductor layer made of GaN (gallium nitride). The material contained in the cap layer used in the above manufacturing method has a lattice mismatch with GaN (gallium nitride) of less than 2.5%, which is smaller than that of AlN (aluminum nitride). Therefore, the cap layer used in the above manufacturing method is less likely to crack than a cap layer made of AlN (aluminum nitride). Furthermore, the material contained in the cap layer used in the above manufacturing method has a melting point of 1500°C or higher. Therefore, the cap layer used in the above manufacturing method is stable even during high-temperature heat treatment and has high heat resistance. As described above, the cap layer used in the above manufacturing method can suppress the occurrence of cracks during high-temperature heat treatment and has heat resistance, and is therefore suitable for suppressing nitrogen from escaping from the surface of the nitride semiconductor layer during high-temperature heat treatment. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a schematic cross-sectional view of a main part of an embodiment of a semiconductor device; [Figure 2] 2 shows a partial manufacturing flow of a method for manufacturing the semiconductor device of FIG. [Figure 3] 2 is a schematic cross-sectional view of a main part of a manufacturing process in the manufacturing method of the semiconductor device of FIG. 1. [Figure 4] 2 is a schematic cross-sectional view of a main part of a manufacturing process in the method for manufacturing the semiconductor device of FIG. 1. [Figure 5] 2 is a schematic cross-sectional view of a main part of a manufacturing process in the method for manufacturing the semiconductor device of FIG. 1. [Figure 6] 2 is a schematic cross-sectional view of a main part of a manufacturing process in a modified example of the manufacturing method of the semiconductor device of FIG. 1. [Figure 7]2 is a schematic cross-sectional view of a main part of a manufacturing process in a modified example of the manufacturing method of the semiconductor device of FIG. 1. [Figure 8] 2 is a schematic cross-sectional view of a main part of a manufacturing process in a modified example of the manufacturing method of the semiconductor device of FIG. 1. DETAILED DESCRIPTION OF THE INVENTION

[0010] The semiconductor device and the manufacturing method thereof disclosed in this specification will be described below with reference to the drawings. In each drawing, for the purpose of clarity, common components may be denoted by only one reference symbol.

[0011] 1, the semiconductor device 1 includes a nitride semiconductor substrate 12, a nitride semiconductor layer 14, a drain electrode 32 provided to cover the lower surface of the nitride semiconductor substrate 12, a source electrode 34 provided to cover part of the upper surface of the nitride semiconductor layer 14, and a planar insulated gate 40 provided to cover part of the upper surface of the nitride semiconductor layer 14. The insulated gate 40 has a gate insulating film 42 and a gate electrode 44.

[0012] The nitride semiconductor substrate 12 is not particularly limited, but may be, for example, a semiconductor substrate made of gallium nitride (GaN). The nitride semiconductor substrate 12 contains a high concentration of n-type dopant, and also functions as the drain region 21. The n-type dopant is not particularly limited, but may be, for example, silicon. The drain region 21 is in ohmic contact with the drain electrode 32.

[0013] The nitride semiconductor layer 14 is provided so as to be in contact with the upper surface of the nitride semiconductor substrate 12. The nitride semiconductor layer 14 is a semiconductor layer made of GaN (gallium nitride). The nitride semiconductor layer 14 is formed by crystal growth from the upper surface of the nitride semiconductor substrate 12 using a crystal growth technique. The nitride semiconductor layer 14 includes an n-type drift region 22 and a p-type drift region 23. - a body region 24 of the type, and +a source region 25 of type p + A mold body contact region 26 is formed.

[0014] The drift region 22 is provided so as to be in contact with the upper surface of the drain region 21, and is disposed between the drain region 21 and the body region 24. The drift region 22 also has a JFET region 23 provided so as to be sandwiched between the body regions 24 in the surface direction of the nitride semiconductor layer 14 (the left-right direction on the page). In other words, the JFET region 23 is a part of the drift region 22 provided so as to penetrate from the upper surface of the nitride semiconductor layer 14 through the body region 24. The JFET region 23 is provided at a position exposed on the upper surface of the nitride semiconductor layer 14, and is in contact with the insulated gate 40. The drift region 22 contains an n-type dopant at a lower concentration than the drain region 21. The n-type dopant is not particularly limited, and may be, for example, silicon.

[0015] The body region 24 is provided in contact with the upper surface of the drift region 22 and is disposed adjacent to the side surface of the JFET region 23. A portion of the body region 24 is provided in a position exposed on the upper surface of the nitride semiconductor layer 14 and in contact with the insulated gate 40. The body region 24 contains a p-type dopant. The p-type dopant is not particularly limited, but may be, for example, magnesium.

[0016] The source region 25 is provided in contact with the upper surface of the body region 24 and is separated from the drift region 22 by the body region 24. The source region 25 is provided at a position exposed on the upper surface of the nitride semiconductor layer 14 and is in contact with the insulated gate 40. The source region 25 contains an n-type dopant at a higher concentration than the drift region 22. The n-type dopant is not particularly limited, but may be silicon, for example. The source region 25 is in ohmic contact with the source electrode 34.

[0017] The body contact region 26 is provided so as to be in contact with the upper surface of the body region 24. The body contact region 26 is provided at a position exposed on the upper surface of the nitride semiconductor layer 14. The body contact region 26 contains a p-type dopant at a higher concentration than the body region 24. The p-type dopant is not particularly limited, but may be, for example, magnesium. The body contact region 26 is in ohmic contact with the source electrode 34.

[0018] The insulated gate 40 is provided so as to be in contact with a portion of the upper surface of the nitride semiconductor layer 14, and has a silicon oxide gate insulating film 42 and a polysilicon gate electrode 44. The gate insulating film 42 is disposed between the nitride semiconductor layer 14 and the gate electrode 44, and is in contact with both the nitride semiconductor layer 14 and the gate electrode 44. The gate electrode 44 faces, via the gate insulating film 42, the body region 24 at a position separating the JFET region 23, which is part of the drift region 22, from the source region 25, and the JFET region 23.

[0019] Next, the operation of the semiconductor device 1 will be described. During use, a positive voltage is applied to the drain electrode 32, and the source electrode 34 is grounded. When a positive voltage higher than the gate threshold voltage is applied to the gate electrode 44, an inversion layer is formed in the body region 24, i.e., the channel region, separating the JFET region 23 and the source region 25. Electrons flow from the source region 25 into the JFET region 23 through the inversion layer formed in the channel region. The electrons that flow into the JFET region 23 flow vertically through the JFET region 23 and drift region 22 toward the drain electrode 32. This brings the drain electrode 32 and the source electrode 34 into conduction, turning the semiconductor device 1 on. When the gate electrode 44 is grounded, the inversion layer disappears, turning the semiconductor device 1 off. In this way, the semiconductor device 1 can perform a switching operation that switches the drain electrode 32 and the source electrode 34 on and off based on the voltage applied to the gate electrode 44.

[0020] (Method of manufacturing semiconductor device 1) 2 is a manufacturing flow showing a flow of some of the steps for manufacturing the semiconductor device 1. FIGS. 3 to 5 are cross-sectional views of the main part in the manufacturing process corresponding to the manufacturing flow of FIG.

[0021] First, as shown in Fig. 3, a crystal growth technique is used to grow a nitride semiconductor layer 14 from the upper surface of the nitride semiconductor substrate 12 (step S1 in Fig. 2). The nitride semiconductor layer 14 is formed by crystal growth so as to contain an n-type dopant.

[0022] 4, p-type dopants and n-type dopants are implanted into predetermined regions in the upper layer of the nitride semiconductor layer 14 using ion implantation technology to form a body region 24, a source region 25, and a body contact region 26 (Step S2 in FIG. 2). The order in which these semiconductor regions 24, 25, and 26 are formed is not particularly limited.

[0023] Next, as shown in FIG. 5, a cap layer 50 is formed on the upper surface of the nitride semiconductor layer 14 and the lower surface of the nitride semiconductor substrate 12 to prevent nitrogen from escaping during a heat treatment described later (step S3 in FIG. 2). The cap layer 50 is formed by growing crystals from the upper surface of the nitride semiconductor layer 14 and the lower surface of the nitride semiconductor substrate 12 using a crystal growth technique. The cap layer 50 may be formed only on the upper surface of the nitride semiconductor layer 14. The upper surface of the nitride semiconductor layer 14 includes a portion that becomes a channel region, and is a surface where the electrical characteristics are likely to be adversely affected if pits due to nitrogen escaping are formed. For this reason, it is sufficient that the cap layer 50 is formed on at least the upper surface of the nitride semiconductor layer 14.

[0024] The material contained in the cap layer 50 has a lattice mismatch with GaN of less than 2.5% and a melting point of 1500° C. or higher. The cap layer 50 is not particularly limited, but may be made of, for example, ScN, Sc x Al 1-xIt may contain at least one material selected from the group consisting of N(0 < x ≦ 0.36), HfN, ZrN, ZnO, ScMgAlO4, MnO, TaC, NbC, Mo, W, ZrB2, WB2, MoB2, and ITO. A layer exemplified by these materials, that is, a layer composed of a material having a lattice mismatch with GaN of less than 2.5% and a melting point of 1500 °C or higher is referred to as a high melting point lattice matching layer in this specification.

[0025] Next, a heat treatment for activating the semiconductor regions 24, 25, 26 is performed (step S4 in FIG. 2). The temperature of the heat treatment is not particularly limited, but may be, for example, 1200 °C or higher and less than 1500 °C. By such a high-temperature heat treatment, the implanted dopant, particularly magnesium which is a p-type dopant, can be favorably activated.

[0026] AlN (aluminum nitride), which is a material of a conventionally well-used cap layer, has a lattice mismatch with GaN (gallium nitride) of 2.5%. The cap layer made of AlN (aluminum nitride) has had a problem of crack generation due to the lattice constant difference with the nitride semiconductor layer of GaN (gallium nitride) in a high-temperature heat treatment. The material contained in the cap layer 50 used in the above manufacturing method is a material having a lattice mismatch with GaN (gallium nitride) of less than 2.5%, and a material having a smaller lattice mismatch with GaN (gallium nitride) than AlN (aluminum nitride). Therefore, the cap layer 50 used in the above manufacturing method is less likely to generate cracks than the cap layer made of AlN (aluminum nitride). Note that the material contained in the cap layer 50 may be ScN or Sc x Al 1-x N(0 < x ≦ 0.36). These materials are materials having a lattice mismatch with GaN (gallium nitride) of 0.1% or less. Therefore, the cap layer 50 made of these materials is significantly less likely to generate cracks in a high-temperature heat treatment.

[0027] Furthermore, the material contained in the cap layer 50 used in the above manufacturing method has a melting point of 1500°C or higher. Therefore, the cap layer 50 used in the above manufacturing method is stable even during high-temperature heat treatment and has high heat resistance. As such, the cap layer 50 used in the above manufacturing method can both suppress the occurrence of cracks during high-temperature heat treatment and have high heat resistance, and therefore can suppress the loss of nitrogen from the upper surface of the nitride semiconductor layer 14 and the lower surface of the nitride semiconductor substrate 12 during high-temperature heat treatment, and can suppress the formation of pits on the upper surface of the nitride semiconductor layer 14 and the lower surface of the nitride semiconductor substrate 12.

[0028] Next, after removing the cap layer 50, the insulated gate 40, the drain electrode 32, and the source electrode 34 are formed using a known manufacturing technique (step S5 in FIG. 2). Through these steps, the semiconductor device 1 shown in FIG. 1 can be manufactured.

[0029] The cap layer 50 can be modified as follows.

[0030] 6 is characterized by having a first cap layer 52 and a second cap layer 54. The first cap layer 52 is formed so as to be in contact with the upper surface of the nitride semiconductor layer 14 (or the lower surface of the nitride semiconductor substrate 12) and is disposed between the nitride semiconductor layer 14 (or the lower surface of the nitride semiconductor substrate 12) and the second cap layer 54. The second cap layer 54 is formed so as to be in contact with the surface of the first cap layer 52 and is disposed on the outermost surface of the cap layer 50. The second cap layer 54 is composed of the high-melting-point lattice-matched layer described above.

[0031] The material of the first cap layer 52 is AlGaN (aluminum gallium nitride). y Ga 1-yN satisfies 0 ≦ y ≦ 1. In a high-temperature heat treatment, the first cap layer 52 of AlGaN has a reaction suppressed between the upper surface of the nitride semiconductor layer 14 (or the lower surface of the nitride semiconductor substrate 12) and the above-described high melting point lattice-matched layer. Therefore, by interposing the first cap layer 52, the crystallinity of the upper surface of the nitride semiconductor layer 14 (or the lower surface of the nitride semiconductor substrate 12) can be maintained well in a high-temperature heat treatment. The material of the first cap layer 52 necessarily contains aluminum, Al y Ga 1-y N may satisfy 0 < y ≦ 1. In this case, the lattice constant difference between the first cap layer 52 and the nitride semiconductor layer 14 (or the nitride semiconductor substrate 12) can be reduced.

[0032] The cap layer 50 shown in FIG. 7 is characterized in that the first cap layer 52 shown in FIG. 6 is composed of a plurality of AlGaN layers having different compositions laminated. In this example, the first cap layer 52 is composed of two AlGaN layers having different compositions laminated. Instead of this example, the first cap layer 52 may be composed of three or more AlGaN layers having different compositions laminated. The first cap layer 52 has a lower AlGaN layer 56 and an upper AlGaN layer 58. The lower AlGaN layer 56 is formed to contact the upper surface of the nitride semiconductor layer 14 (or the lower surface of the nitride semiconductor substrate 12), and is disposed between the upper surface of the nitride semiconductor layer 14 (or the lower surface of the nitride semiconductor substrate 12) and the upper AlGaN layer 58. The upper AlGaN layer 58 is formed to contact the surface of the lower AlGaN layer 56, and is disposed between the lower AlGaN layer 56 and the second cap layer 54.

[0033] The material of the lower AlGaN layer 56 is Al ya Ga 1-ya N, where 0 ≦ ya ≦ 1. The material of the upper AlGaN layer 58 is Al yb Ga 1-ybN(0<yb≦1,yb> ya). The aluminum composition ratio of the upper AlGaN layer 58 is greater than the aluminum composition ratio of the lower AlGaN layer 56. In this way, by increasing the aluminum composition ratio in the multiple AlGaN layers constituting the first cap layer 52 with increasing distance from the upper surface of the nitride semiconductor layer 14 (or the lower surface of the nitride semiconductor substrate 12), it is possible to improve heat resistance while suppressing the difference in lattice constant between the first cap layer 52 and the nitride semiconductor layer 14 (or the nitride semiconductor substrate 12).

[0034] The cap layer 50 shown in Fig. 8 has a superlattice structure in which first cap layers 52 and second cap layers 54 are alternately repeated along the thickness direction. The thickness of each cap layer 52, 54 is not particularly limited, but may be, for example, 10 nm or less. The specific material of the first cap layer 52 constituting the superlattice structure is not particularly limited, but may be, for example, Al yc Ga 1-yc N (0.5≦yc≦1). In this way, the aluminum composition ratio of the first cap layer 52 constituting the superlattice structure is set to be relatively high. In this superlattice structure, the first cap layer 52 is disposed so as to be in contact with the upper surface of the nitride semiconductor layer 14 (or the lower surface of the nitride semiconductor substrate 12), and the second cap layer 54 is disposed on the outermost surface of the cap layer 50. The second cap layer 54 is constituted by the above-mentioned high-melting-point lattice-matched layer.

[0035] As described above, the aluminum composition ratio of the first cap layer 52 constituting the superlattice structure is relatively high. However, since the first cap layer 52 forms a superlattice structure together with the second cap layer, which is a high-melting-point lattice-matching layer, the lattice mismatch between the first cap layer 52 and the nitride semiconductor layer 14 (or the nitride semiconductor substrate 12) is alleviated across the cap layer 50. On the other hand, since the aluminum composition ratio of the first cap layer 52 constituting the superlattice structure is relatively high, the heat resistance of the entire cap layer 50 is improved.

[0036] In the above description, the technology disclosed in this specification has been described using the semiconductor device 1 including the planar insulating gate 40. However, the technology disclosed in this specification is also applicable to a semiconductor device including a trench-type insulating gate.

[0037] The above manufacturing method may further include a step of forming a carbon film on the surface of the cap layer 50 after forming the cap layer 50 and before the heat treatment for activation. When the carbon film is formed, it is possible to suppress the atmosphere gas during the heat treatment for activation from entering the cap layer 50.

[0038] Hereinafter, the features of the technology disclosed in this specification will be organized. Note that the technical elements described below are each independent technical elements, which exhibit technical utility alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing.

[0039] (Feature 1) A method for manufacturing a nitride semiconductor device, comprising: a step of ion-implanting a dopant into a nitride semiconductor layer made of GaN; a step of forming a cap layer on at least a part of the surface of the nitride semiconductor layer; an annealing step of activating the dopant by heat treatment, and the cap layer includes a material having a lattice mismatch with GaN of less than 2. , and a melting point of 1500 °C or higher.

[0040] (Feature 2) The cap layer is ScN, Sc x Al 1-x N(0 < x ≤ 0.36), HfN, ZrN, ZnO, ScMgAlO4, MnO, TaC, NbC, Mo, W, ZrB2, WB2, MoB2, ITO.

[0041] (Feature 3) The cap layer is ScN and Sc x Al 1-xThe manufacturing method according to Feature 2, comprising at least one of the materials of N (0 < x ≤ 0.36).

[0042] (Feature 4) The cap layer includes a first cap layer (52) formed on the surface of the nitride semiconductor layer, and a second cap layer (54) formed on the first cap layer, and has the material of the first cap layer is Al y Ga 1-y N (0 ≤ y ≤ 1), and the second cap layer is at least one material selected from the group consisting of ScN, Sc x Al 1-x N (0 < x ≤ 0.36), HfN, ZrN, ZnO, ScMgAlO4, MnO, TaC, NbC, Mo, W, ZrB2, WB2, MoB2, ITO, the manufacturing method according to Feature 2 or 3.

[0043] (Feature 5) The first cap layer is composed of a plurality of stacked AlGaN layers (56, 58) with different compositions, the manufacturing method according to Feature 4.

[0044] [[ID=3l]]<00002l2>(Feature 6) In the plurality of AlGaN layers constituting the first cap layer, the composition ratio of aluminum is configured to increase as it moves away from the surface of the nitride semiconductor layer, the manufacturing method according to Feature 5.

[0045] (Feature 7) The first cap layer (52) and the second cap layer (54) constitute a superlattice structure that alternates repeatedly in the thickness direction, the material of the first cap layer is Al y Ga 1-y N (0 ≤ y ≤ 1), and the second cap layer is ScN, Sc x Al 1-xThe manufacturing method according to Feature 2, comprising at least one material selected from the group consisting of N (0 < x ≦ 0.36), HfN, ZrN, ZnO, ScMgAlO4, MnO, TaC, NbC, Mo, W, ZrB2, WB2, MoB2, and ITO.

[0046] (Feature 8) The manufacturing method according to any one of Features 1 to 7, further comprising a step of forming a carbon film on the cap layer.

[0047] Although specific examples of the present invention have been described in detail above, these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above. In addition, the technical elements described in this specification or the drawings exhibit technical utility alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Also, the technology illustrated in this specification or the drawings can achieve multiple purposes simultaneously, and achieving one of those purposes itself has technical utility.

Explanation of Reference Signs

[0048] 1: Semiconductor device, 12: Nitride semiconductor substrate, 14: Nitride semiconductor layer, 21: Drain region, 22: Drift region, 23: JFET region, 25: Source region, 26: Body contact region, 32: Drain electrode, 34: Source electrode, 40: Insulated gate, 42: Gate insulating film, 44: Gate electrode, 50: Cap layer, 52: First cap layer, 54: Second cap layer, 56: Lower AlGaN layer, 58: Upper AlGaN layer

Claims

1. A method for manufacturing a nitride semiconductor device (1), comprising: A step of ion-implanting a dopant into a nitride semiconductor layer (14) made of GaN; forming a cap layer (50) on at least a portion of the surface of the nitride semiconductor layer; an annealing step of activating the dopant by heat treatment, the cap layer includes a material having a lattice mismatch with GaN of less than 2.5% and a melting point of 1500°C or higher; The method for manufacturing the semiconductor device, wherein the cap layer contains at least one of ScN and Sc x Al 1-x N (0<x≦0.36).

2. A method for manufacturing a nitride semiconductor device (1), comprising: A step of ion-implanting a dopant into a nitride semiconductor layer (14) made of GaN; forming a cap layer (50) on at least a portion of the surface of the nitride semiconductor layer; an annealing step of activating the dopant by heat treatment, the cap layer includes a material having a lattice mismatch with GaN of less than 2.5% and a melting point of 1500°C or higher; The cap layer is a first cap layer (52) formed on the surface of the nitride semiconductor layer; a second cap layer (54) formed on the first cap layer, the material of the first cap layer is Al y Ga 1-y N (0≦y≦1); the second cap layer includes at least one material selected from the group consisting of ScN, Sc x Al 1-x N (0<x≦0.36), HfN, ZrN, ZnO, ScMgAlO 4 , MnO, TaC, NbC, Mo, W, ZrB 2 , WB 2 , MoB 2 , and ITO; The first cap layer is configured by stacking a plurality of AlGaN layers (56, 58) having different compositions, The plurality of AlGaN layers constituting the first cap layer are configured so that the aluminum composition ratio increases with increasing distance from the surface of the nitride semiconductor layer.

3. A method for manufacturing a nitride semiconductor device (1), comprising: A step of ion-implanting a dopant into a nitride semiconductor layer (14) made of GaN; forming a cap layer (50) on at least a portion of the surface of the nitride semiconductor layer; an annealing step of activating the dopant by heat treatment, the cap layer includes a material having a lattice mismatch with GaN of less than 2.5% and a melting point of 1500°C or higher; The cap layer has a superlattice structure in which first cap layers (52) and second cap layers (54) are alternately repeated in the thickness direction, the material of the first cap layer is Al y Ga 1-y N (0≦y≦1); The manufacturing method, wherein the second cap layer comprises at least one material selected from the group consisting of ScN, Sc x Al 1-x N (0<x≦0.36), HfN, ZrN, ZnO, ScMgAlO 4 , MnO, TaC, NbC, Mo, W, ZrB 2 , WB 2 , MoB 2 , and ITO.

4. The manufacturing method according to claim 1 , further comprising the step of forming a carbon film on the cap layer.

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