Semiconductor Devices

Abstract

To provide a semiconductor device capable of improving a short circuit tolerance dose, and reducing a feedback capacity.SOLUTION: A semiconductor device 1 includes: an n-type SiC semiconductor layer 2 (semiconductor layer) having a first principal plane 3; a trench gate structure 10 (first trench structure) formed on the first principal plane 3; a trench source structure 11 (second trench structure) formed on the first principal plane 3 deeper than the trench gate structure 10 and having a depth ratio of 1.5 or more and 4.0 or less to depth of the trench gate structure 10; and a p-type deep well region 21 (well region) formed along the trench source structure 11 at a surface layer part of the first principal plane 3.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device. [Background technology]

[0002] Patent Document 1 discloses a semiconductor device having a gate trench and a source trench. The gate trench and the source trench are formed at the surface of an n-type semiconductor layer to approximately the same depth. A p-type body region is formed in the region between the gate trench and the source trench in the surface layer portion of the surface of the semiconductor layer.

[0003] The surface layer of the p-type body region is + A p-type source region is formed in the semiconductor layer, and a p-type breakdown voltage maintaining region (deep well region) is formed in the region along the source trench in the semiconductor layer.

[0004] A gate electrode is buried in the gate trench via a gate insulating layer, a source electrode is buried in the source trench, and a drain electrode is connected to the back surface of the semiconductor layer. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] International Publication No. 2014 / 030589A1 Summary of the Invention [Problem to be solved by the invention]

[0006] Known electrical characteristics of semiconductor devices with a MISFET structure including a gate, source, and drain include short-circuit withstand capability and feedback capacitance. Short-circuit withstand capability is the time a device can withstand a short-circuit current. The short-circuit current is the current that flows between the source and drain when switching from an on state to an off state. Feedback capacitance is the electrostatic capacitance between the gate and drain.

[0007] The higher the short-circuit resistance, the higher the reliability of the semiconductor device. Also, the smaller the feedback capacitance, the faster the switching speed of the semiconductor device. Therefore, by achieving excellent short-circuit resistance and excellent feedback capacitance, it is possible to provide a semiconductor device that can be used in a variety of situations.

[0008] However, in a semiconductor device having a structure in which the gate trench and the source trench are formed to approximately the same depth, the p-type deep well region can only be formed in a relatively shallow region in the n-type semiconductor layer.

[0009] In this structure, the depletion layer cannot be sufficiently expanded from the boundary region between the semiconductor layer and the deep well region. As a result, the depletion layer does not adequately narrow the current path of the short-circuit current, and therefore the short-circuit resistance cannot be adequately improved. Furthermore, the width of the depletion layer is too small to adequately reduce the feedback capacitance.

[0010] One embodiment provides a semiconductor device that can improve short-circuit resistance and reduce feedback capacitance. [Means for solving the problem]

[0011] One embodiment provides a semiconductor device including: a semiconductor layer of a first conductivity type having a main surface; a first trench structure formed on the main surface; a second trench structure formed deeper in the main surface than the first trench structure, the second trench structure having a ratio of its depth to the depth of the first trench structure of 1.5 or more and 4.0 or less; and a well region of a second conductivity type formed along the second trench structure in a surface layer portion of the main surface.

[0012] One embodiment provides a semiconductor device including: a semiconductor layer of a first conductivity type having a first main surface on one side and a second main surface on the other side; a trench gate structure including: a gate trench formed in the first main surface of the semiconductor layer; and a gate electrode embedded in the gate trench with a gate insulating layer interposed therebetween; a source trench formed in the first main surface of the semiconductor layer at a distance from the gate trench and deeper than the gate trench; a source electrode embedded in the source trench; and a trench source structure including: a well region of a second conductivity type formed in a region along the source trench in the semiconductor layer, wherein the ratio of the depth of the trench source structure to the depth of the trench gate structure is 1.5 or more and 4.0 or less; a body region of a second conductivity type formed in a surface portion of the first main surface of the semiconductor layer in a region between the gate trench and the source trench; a source region of a first conductivity type formed in a surface portion of the body region; and a drain electrode connected to the second main surface of the semiconductor layer.

[0013] One embodiment is a trench gate structure including a semiconductor layer of a first conductivity type having a first main surface on one side and a second main surface on the other side, a gate trench formed in the first main surface of the semiconductor layer, and a gate electrode embedded in the gate trench via a gate insulating layer, a source trench formed in the first main surface of the semiconductor layer at a distance from the gate trench and deeper than the gate trench, a source electrode embedded in the source trench, and a well region of a second conductivity type formed in a region of the semiconductor layer along the source trench, wherein the trench The present invention provides a semiconductor device including: a trench source structure in which the ratio of the depth of the trench source structure to the depth of the gate structure is 1.5 or more and 4.0 or less; a body region of a second conductivity type formed in a region between the gate trench and the source trench in a surface layer portion of the first main surface of the semiconductor layer; a source region of a first conductivity type formed in a surface layer portion of the body region; and a drain electrode connected to the second main surface of the semiconductor layer, wherein the well region is continuously formed in the semiconductor layer in regions along the sidewalls and bottom wall of the source trench, and along corners connecting the sidewalls and the bottom wall. child Rera According to this semiconductor device, the ratio of the depth of the trench source structure to the depth of the trench gate structure is 1.5 or more and 4.0 or less, which allows the depletion layer to expand from the boundary region between the semiconductor layer and the well region toward the region closer to the second main surface than the bottom wall of the gate trench.

[0014] As a result, the current path of the short-circuit current flowing between the source electrode and the drain electrode can be narrowed. Also, the depletion layer extending from the boundary region between the semiconductor layer and the well region reduces the feedback capacitance inversely. Therefore, a semiconductor device can be provided that can improve short-circuit resistance and reduce the feedback capacitance.

[0015] One embodiment includes a trench gate structure including a semiconductor layer of a first conductivity type having a first main surface on one side and a second main surface on the other side, a gate trench having a first sidewall and a first bottom wall and formed in the first main surface of the semiconductor layer, and a gate electrode embedded in the gate trench via a gate insulating layer, a trench source structure including a source trench having a second sidewall and a second bottom wall and formed at a distance from the gate trench in the first main surface of the semiconductor layer, a source electrode embedded in the source trench, and a well region of a second conductivity type formed in a region along the source trench in the semiconductor layer, and a gate insulating layer formed in a surface portion of the first main surface of the semiconductor layer in a region between the gate trench and the source trench. the well region includes a first region formed along the first wall portion of the second sidewall of the source trench and a second region formed along the second wall portion of the second sidewall of the source trench, the second region having a length greater than a length of the first region in the thickness direction of the semiconductor layer.

[0016] According to this semiconductor device, the well region includes a first region formed along a first wall portion of the second sidewall of the source trench, and a second region formed along a second wall portion of the second sidewall of the source trench.

[0017] In the thickness direction of the semiconductor layer, the length of the second region of the well region is greater than the length of the first region of the well region, which allows the depletion layer to expand from the boundary region between the semiconductor layer and the well region toward the region closer to the second main surface than the first bottom wall of the gate trench.

[0018] As a result, the current path of the short-circuit current flowing between the source electrode and the drain electrode can be narrowed. Also, the depletion layer extending from the boundary region between the semiconductor layer and the well region reduces the feedback capacitance inversely. Therefore, a semiconductor device can be provided that can improve short-circuit resistance and reduce the feedback capacitance.

[0019] The above and other objects, features and advantages of the present invention will become apparent from the following description of the embodiments with reference to the accompanying drawings. [Brief explanation of the drawings]

[0020] [Figure 1] FIG. 1 is a plan view showing a semiconductor device according to a first embodiment of the present invention. [Figure 2] FIG. 2 is a cross-sectional view taken along line II-II in FIG. [Figure 3] FIG. 3 is a cross-sectional view for explaining the operation of the semiconductor device of FIG. [Figure 4] FIG. 4 is a graph showing the current-voltage characteristics of the semiconductor device of FIG. [Figure 5] FIG. 5 is a graph showing the capacitance-voltage characteristics of the semiconductor device of FIG. [Figure 6] FIG. 6 is a cross-sectional view showing a semiconductor device according to a second embodiment of the present invention. [Figure 7] FIG. 7 is a cross-sectional view showing a semiconductor device according to a third embodiment of the present invention. [Figure 8] FIG. 8 is a cross-sectional view showing a semiconductor device according to a fourth embodiment of the present invention. [Figure 9] FIG. 9 is a cross-sectional view showing a semiconductor device according to a fifth embodiment of the present invention. [Figure 10] FIG. 10 is a plan view showing a semiconductor device according to a sixth embodiment of the present invention. [Figure 11] FIG. 11 is a plan view showing a semiconductor device according to a seventh embodiment of the present invention. [Figure 12] FIG. 12 is an enlarged view of region XII shown in FIG. 11, and is a view for explaining the structure of the first main surface of the SiC semiconductor layer. [Figure 13] FIG. 13 is a cross-sectional view taken along line XIII-XIII shown in FIG. [Figure 14] FIG. 14 is a cross-sectional view taken along line XIV-XIV shown in FIG. [Figure 15] FIG. 15 is a graph showing the relationship between the resistivity of polycide and the formation temperature. [Figure 16] FIG. 16 is a graph for explaining the sheet resistance. [Figure 17A] FIG. 17A is a cross-sectional view showing an example of a method for manufacturing the semiconductor device shown in FIG. [Figure 17B] FIG. 17B is a cross-sectional view showing a step subsequent to FIG. 17A. [Figure 17C] FIG. 17C is a cross-sectional view showing a step subsequent to FIG. 17B. [Figure 17D] FIG. 17D is a cross-sectional view showing a step subsequent to FIG. 17C. [Figure 17E] FIG. 17E is a cross-sectional view showing a step subsequent to FIG. 17D. [Figure 17F] FIG. 17F is a cross-sectional view showing a step subsequent to FIG. 17E. [Figure 17G] FIG. 17G is a cross-sectional view showing a step subsequent to FIG. 17F. [Figure 17H] FIG. 17H is a cross-sectional view showing a step subsequent to FIG. 17G. [Figure 17I] FIG. 17I is a cross-sectional view showing a step subsequent to FIG. 17H. [Figure 17J] FIG. 17J is a cross-sectional view showing a step subsequent to FIG. 17I. [Figure 17K] FIG. 17K is a cross-sectional view showing a step subsequent to FIG. 17J. [Figure 17L] FIG. 17L is a cross-sectional view showing a step subsequent to FIG. 17K. [Figure 18] FIG. 18 is a cross-sectional view of a region corresponding to FIG. 13, showing a semiconductor device according to an eighth embodiment of the present invention. [Figure 19] FIG. 19 is a cross-sectional view of a region corresponding to FIG. 13, showing a semiconductor device according to a ninth embodiment of the present invention. [Figure 20A] FIG. 20A is a cross-sectional view showing an example of a method for manufacturing the semiconductor device shown in FIG. [Figure 20B] FIG. 20B is a cross-sectional view showing a step subsequent to that shown in FIG. 20A. [Figure 20C] FIG. 20C is a cross-sectional view showing a step subsequent to FIG. 20B. [Figure 21] FIG. 21 is an enlarged view of a region corresponding to FIG. 12, showing a semiconductor device according to a tenth embodiment of the present invention. [Figure 22] FIG. 22 is a cross-sectional view taken along line XXII-XXII shown in FIG. [Figure 23] FIG. 23 is a cross-sectional view of a region corresponding to FIG. 13, illustrating the structure of a semiconductor device according to an eleventh embodiment of the present invention. [Figure 24] FIG. 24 is an enlarged view of a region corresponding to FIG. 12, and is an enlarged view for explaining the structure of a semiconductor device according to a twelfth embodiment of the present invention. [Figure 25] FIG. 25 is a cross-sectional view of a region corresponding to FIG. 13, illustrating the structure of a semiconductor device according to a thirteenth embodiment of the present invention. [Figure 26] FIG. 26 is a cross-sectional view of a region corresponding to FIG. 13, illustrating the structure of a semiconductor device according to a fourteenth embodiment of the present invention. [Figure 27] FIG. 27 is a cross-sectional view of a region corresponding to FIG. 13, illustrating the structure of a semiconductor device according to a fifteenth embodiment of the present invention. [Figure 28] FIG. 28 is a cross-sectional view of a region corresponding to FIG. 13, illustrating the structure of a semiconductor device according to a sixteenth embodiment of the present invention. [Figure 29] FIG. 29 is a cross-sectional view of a region corresponding to FIG. 13, illustrating the structure of the semiconductor device according to the seventeenth embodiment of the present invention. [Figure 30] FIG. 30 is a cross-sectional view of a region corresponding to FIG. 13, illustrating the structure of a semiconductor device according to an eighteenth embodiment of the present invention. [Figure 31] FIG. 31 is a cross-sectional view of a region corresponding to FIG. 13, illustrating the structure of a semiconductor device according to a nineteenth embodiment of the present invention. [Figure 32] FIG. 32 is a cross-sectional view of a region corresponding to FIG. 13, illustrating the structure of a semiconductor device according to a twentieth embodiment of the present invention. [Figure 33] FIG. 33 is a cross-sectional view of a region corresponding to FIG. 13, illustrating the structure of a semiconductor device according to a twenty-first embodiment of the present invention. [Figure 34] FIG. 34 is a top view showing a semiconductor device according to the twenty-second embodiment of the present invention. [Figure 35] FIG. 35 is a bottom view of the semiconductor device shown in FIG. 34, showing a first embodiment of the raised portion group. [Figure 36A] FIG. 36A is a diagram showing a second example of the raised portion group. [Figure 36B] FIG. 36B is a diagram showing a third example of the raised portion group. [Figure 36C] FIG. 36C is a diagram showing a fourth example of the raised portion group. [Figure 36D] FIG. 36D is a diagram showing a fifth example of the group of raised portions. [Figure 37] FIG. 37 is an enlarged view of region XXXVII shown in FIG. 34, with the structure above the first main surface of the SiC semiconductor layer removed. [Figure 38] 38 is a cross-sectional view taken along line XXXVIII-XXXVIII in FIG. [Figure 39] FIG. 39 is a cross-sectional view taken along line XXXIX-XXXIX in FIG. [Figure 40] FIG. 40 is an enlarged view of the region XL shown in FIG. [Figure 41A] FIG. 41A is a top view showing a semiconductor wafer used to manufacture the semiconductor device shown in FIG. [Figure 41B] FIG. 41B is a bottom view of the semiconductor wafer shown in FIG. 41A, showing the state after the grinding step and the annealing treatment. [Figure 42] FIG. 42 is a flowchart for explaining an example of the semiconductor device shown in FIG. [Figure 43A] FIG. 43A is a cross-sectional view for explaining the manufacturing method shown in FIG. [Figure 43B] FIG. 43B is a cross-sectional view for explaining a step subsequent to FIG. 43A. [Figure 43C] FIG. 43C is a cross-sectional view for explaining a step subsequent to FIG. 43B. [Figure 43D] FIG. 43D is a cross-sectional view for explaining the step subsequent to FIG. 43C. [Figure 43E] FIG. 43E is a cross-sectional view for explaining the step after FIG. 43D. [Figure 43F] FIG. 43F is a cross-sectional view for explaining the step subsequent to FIG. 43E. [Figure 43G] FIG. 43G is a cross-sectional view for explaining the step after FIG. 43F. [Figure 43H] FIG. 43H is a cross-sectional view for explaining the step after FIG. 43G. [Figure 43I] FIG. 43I is a cross-sectional view for explaining the step after FIG. 43H. [Figure 44] FIG. 44 is a bottom view corresponding to FIG. 35, showing a semiconductor device according to the twenty-third embodiment of the present invention. [Figure 45] FIG. 45 is a cross-sectional view corresponding to FIG. 39, showing a semiconductor device according to the twenty-fourth embodiment of the present invention. [Figure 46] FIG. 46 is an enlarged view of region XLVI shown in FIG. [Figure 47] FIG. 47 is a cross-sectional view corresponding to FIG. 39, showing a semiconductor device according to the 25th embodiment of the present invention. [Figure 48] FIG. 48 is an enlarged view of region XLVIII shown in FIG. [Figure 49] FIG. 49 is a top view showing a semiconductor device according to the 26th embodiment of the present invention. [Figure 50]FIG. 50 is a top view showing the semiconductor device shown in FIG. 49, with the resin layer removed. [Figure 51] FIG. 51 is an enlarged view of region LI shown in FIG. 50, and is a view for explaining the structure of the first main surface of the SiC semiconductor layer. [Figure 52] FIG. 52 is a cross-sectional view taken along the line LII-LII shown in FIG. 51, showing the first example of the gate trench and the first example of the source trench. [Figure 53] FIG. 53 is a cross-sectional view taken along the line LIII-LIII shown in FIG. 51, showing a first embodiment of the gate wiring layer. [Figure 54] FIG. 54 is an enlarged view of the region LIV shown in FIG. [Figure 55] Figure 55 is a cross-sectional view along the line LV-LV shown in Figure 50, showing a first example of the active sidewall, a first example of the outer main surface, a first example of the sidewall, a first example of the diode region, a first example of the outer deep well region, a first example of the field limit structure, and a first example of the anchor hole. [Figure 56] FIG. 56 is an enlarged view of an area LVI shown in FIG. 55, showing a first example of the active sidewall and a first example of the outer main surface. [Figure 57A] FIG. 57A is a cross-sectional view of a region corresponding to FIG. 54, showing a second embodiment of the gate trench. [Figure 57B] FIG. 57B is a cross-sectional view of a region corresponding to FIG. 54, showing a third embodiment of the gate trench. [Figure 57C] FIG. 57C is a cross-sectional view of a region corresponding to FIG. 54, showing a fourth embodiment of the gate trench. [Figure 57D] FIG. 57D is a cross-sectional view of a region corresponding to FIG. 54, showing a fifth embodiment of the gate trench. [Figure 57E] FIG. 57E is a cross-sectional view of a region corresponding to FIG. 54, showing a sixth embodiment of the gate trench. [Figure 58A]FIG. 58A is a cross-sectional view of a region corresponding to FIG. 54, showing a second example of the source trench. [Figure 58B] FIG. 58B is a cross-sectional view of a region corresponding to FIG. 54, showing a third embodiment of the source trench. [Figure 58C] FIG. 58C is a cross-sectional view of a region corresponding to FIG. 54, showing a fourth embodiment of the source trench. [Figure 58D] FIG. 58D is a cross-sectional view of a region corresponding to FIG. 54, showing a fifth embodiment of the source trench. [Figure 58E] FIG. 58E is a cross-sectional view of a region corresponding to FIG. 54, showing a sixth embodiment of the source trench. [Figure 58F] FIG. 58F is a cross-sectional view of a region corresponding to FIG. 54, showing a seventh embodiment of the source trench. [Figure 58G] FIG. 58G is a cross-sectional view of a region corresponding to FIG. 54, showing an eighth embodiment of the source trench. [Figure 58H] FIG. 58H is a cross-sectional view of a region corresponding to FIG. 54, showing a ninth embodiment of the source trench. [Figure 58I] FIG. 58I is a cross-sectional view of a region corresponding to FIG. 54, showing a tenth embodiment of the source trench. [Figure 58J] FIG. 58J is a cross-sectional view of a region corresponding to FIG. 54, showing an eleventh embodiment of the source trench. [Figure 58K] FIG. 58K is a cross-sectional view of a region corresponding to FIG. 54, showing a twelfth embodiment of the source trench. [Figure 58L] FIG. 58L is a cross-sectional view of a region corresponding to FIG. 54, showing a thirteenth embodiment of the source trench. [Figure 58M] FIG. 58M is a cross-sectional view of a region corresponding to FIG. 54, showing a fourteenth embodiment of the source trench. [Figure 58N]FIG. 58N is a cross-sectional view of a region corresponding to FIG. 54, showing a fifteenth example of the source trench. [Figure 58O] FIG. 58O is a cross-sectional view of a region corresponding to FIG. 54, showing a sixteenth embodiment of the source trench. [Figure 58P] FIG. 58P is a cross-sectional view of a region corresponding to FIG. 54, showing a seventeenth embodiment of the source trench. [Figure 58Q] FIG. 58Q is a cross-sectional view of a region corresponding to FIG. 54, showing an eighteenth embodiment of the source trench. [Figure 59A] FIG. 59A is an enlarged view of the area corresponding to FIG. 56, showing a second embodiment of the active sidewall. [Figure 59B] FIG. 59B is an enlarged view of the area corresponding to FIG. 56, showing a third embodiment of the active sidewall. [Figure 59C] FIG. 59C is an enlarged view of the area corresponding to FIG. 56, showing a fourth embodiment of the active sidewall. [Figure 60A] FIG. 60A is an enlarged view of a region corresponding to FIG. 56, showing a second embodiment of the outer main surface. [Figure 60B] FIG. 60B is an enlarged view of a region corresponding to FIG. 56, showing a third embodiment of the outer main surface. [Figure 60C] FIG. 60C is an enlarged view of a region corresponding to FIG. 56, showing a fourth embodiment of the outer main surface. [Figure 61A] FIG. 61A is an enlarged view of a region corresponding to FIG. 56, showing a second embodiment of the sidewall. [Figure 61B] FIG. 61B is an enlarged view of a region corresponding to FIG. 56, showing a third embodiment of the sidewall. [Figure 61C] FIG. 61C is an enlarged view of a region corresponding to FIG. 56, showing a fourth embodiment of the sidewall. [Figure 61D]FIG. 61D is an enlarged view of a region corresponding to FIG. 56, showing a fifth embodiment of the sidewall. [Figure 61E] FIG. 61E is an enlarged view of a region corresponding to FIG. 56, showing a sixth embodiment of the sidewall. [Figure 61F] FIG. 61F is an enlarged view of a region corresponding to FIG. 56, showing a seventh embodiment of the sidewall. [Figure 62A] FIG. 62A is a cross-sectional view of a region corresponding to FIG. 55, and is an enlarged view showing a second embodiment of the outer deep well region. [Figure 62B] FIG. 62B is a cross-sectional view of a region corresponding to FIG. 55, and is an enlarged view showing a third embodiment of the outer deep well region. [Figure 62C] FIG. 62C is a cross-sectional view of a region corresponding to FIG. 55, and is an enlarged view showing a fourth embodiment of the outer deep well region. [Figure 63A] FIG. 63A is a cross-sectional view of a region corresponding to FIG. 55, and is an enlarged view showing a second example of the field limit structure. [Figure 63B] FIG. 63B is a cross-sectional view of a region corresponding to FIG. 55, and is an enlarged view showing a third embodiment of the field limit structure. [Figure 63C] FIG. 63C is a cross-sectional view of a region corresponding to FIG. 55, and is an enlarged view showing a fourth embodiment of the field limit structure. [Figure 63D] FIG. 63D is a cross-sectional view of a region corresponding to FIG. 55, and is an enlarged view showing a fifth embodiment of the field limit structure. [Figure 64A] FIG. 64A is a cross-sectional view of a region corresponding to FIG. 55, and is an enlarged view showing a second example of the anchor hole. [Figure 64B] FIG. 64B is a cross-sectional view of a region corresponding to FIG. 55, and is an enlarged view showing a third example of the anchor hole. [Figure 64C] FIG. 64C is a cross-sectional view of a region corresponding to FIG. 55, and is an enlarged view showing a fourth example of the anchor hole. [Figure 64D]FIG. 64D is a plan view corresponding to FIG. 50, showing a fifth example of the anchor hole. [Figure 65A] FIG. 65A is an enlarged view of a region corresponding to FIG. 54, and is an enlarged view showing an example of a method for manufacturing the semiconductor device shown in FIG. [Figure 65B] FIG. 65B is an enlarged view showing a step subsequent to that of FIG. 65A. [Figure 65C] FIG. 65C is an enlarged view showing a step subsequent to that of FIG. 65B. [Figure 65D] FIG. 65D is an enlarged view showing a step subsequent to that of FIG. 65C. [Figure 65E] FIG. 65E is an enlarged view showing a step subsequent to that of FIG. 65D. [Figure 65F] FIG. 65F is an enlarged view showing a step subsequent to that of FIG. 65E. [Figure 65G] FIG. 65G is an enlarged view showing a step subsequent to that of FIG. 65F. [Figure 65H] FIG. 65H is an enlarged view showing the step after FIG. 65G. [Figure 65I] FIG. 65I is an enlarged view showing the step after FIG. 65H. [Figure 65J] FIG. 65J is an enlarged view showing a step subsequent to that of FIG. 65I. [Figure 65K] FIG. 65K is an enlarged view showing a step subsequent to that of FIG. 65J. [Figure 65L] FIG. 65L is an enlarged view showing a step subsequent to FIG. 65K. [Figure 65M] FIG. 65M is an enlarged view showing a step subsequent to FIG. 65L. [Figure 65N] FIG. 65N is an enlarged view showing a step subsequent to FIG. 65M. [Figure 65O] FIG. 65O is an enlarged view showing a step subsequent to FIG. 65N. [Figure 65P] FIG. 65P is an enlarged view showing a step subsequent to that of FIG. 65O. [Figure 65Q] FIG. 65Q is an enlarged view showing a step subsequent to FIG. 65P. [Figure 65R] FIG. 65R is an enlarged view showing a step subsequent to that of FIG. 65Q. [Figure 65S] FIG. 65S is an enlarged view showing the step after FIG. 65R. [Figure 65T] FIG. 65T is an enlarged view showing the step after FIG. 65S. [Figure 65U] FIG. 65U is an enlarged view showing the step after FIG. 65T. [Figure 65V] FIG. 65V is an enlarged view showing a step subsequent to FIG. 65U. [Figure 65W] FIG. 65W is an enlarged view showing a step subsequent to that of FIG. 65V. [Figure 65X] FIG. 65X is an enlarged view showing a step subsequent to FIG. 65W. [Figure 65Y] FIG. 65Y is an enlarged view showing a step subsequent to that of FIG. 65X. [Figure 65Z] FIG. 65Z is an enlarged view showing a step subsequent to that of FIG. 65Y. [Figure 66A] 66A is a cross-sectional view of a region corresponding to FIG. 55, showing an example of a method for manufacturing the semiconductor device shown in FIG. [Figure 66B] FIG. 66B is a cross-sectional view showing a step subsequent to that of FIG. 66A. [Figure 66C] FIG. 66C is a cross-sectional view showing a step subsequent to FIG. 66B. [Figure 66D] FIG. 66D is a cross-sectional view showing a step subsequent to FIG. 66C. [Figure 66E] FIG. 66E is a cross-sectional view showing a step subsequent to FIG. 66D. [Figure 66F] FIG. 66F is a cross-sectional view showing a step subsequent to FIG. 66E. [Figure 66G] FIG. 66G is a cross-sectional view showing a step subsequent to FIG. 66F. [Figure 66H] FIG. 66H is a cross-sectional view showing a step subsequent to FIG. 66G. [Figure 66I] FIG. 66I is a cross-sectional view showing a step subsequent to FIG. 66H. [Figure 66J] FIG. 66J is a cross-sectional view showing a step subsequent to FIG. 66I. [Figure 66K] FIG. 66K is a cross-sectional view showing a step subsequent to FIG. 66J. [Figure 66L] FIG. 66L is a cross-sectional view showing a step subsequent to FIG. 66K. [Figure 66M] FIG. 66M is a cross-sectional view showing a step subsequent to FIG. 66L. [Figure 66N] FIG. 66N is a cross-sectional view showing a step subsequent to FIG. 66M. [Figure 66O] FIG. 66O is a cross-sectional view showing a step subsequent to FIG. 66N. [Figure 66P] FIG. 66P is a cross-sectional view showing a step subsequent to that shown in FIG. 66O. [Figure 66Q] FIG. 66Q is a cross-sectional view showing a step subsequent to FIG. 66P. [Figure 66R] FIG. 66R is a cross-sectional view showing a step subsequent to FIG. 66Q. [Figure 66S] FIG. 66S is a cross-sectional view showing a step subsequent to FIG. 66R. [Figure 66T] FIG. 66T is a cross-sectional view showing a step subsequent to FIG. 66S. [Figure 66U] FIG. 66U is a cross-sectional view showing a step subsequent to FIG. 66T. [Figure 66V] FIG. 66V is a cross-sectional view showing a step subsequent to FIG. 66U. [Figure 66W] FIG. 66W is a cross-sectional view showing a step subsequent to FIG. 66V. [Figure 66X] FIG. 66X is a cross-sectional view showing a step subsequent to FIG. 66W. [Figure 66Y] FIG. 66Y is a cross-sectional view showing a step subsequent to that shown in FIG. 66X. [Figure 66Z] FIG. 66Z is a cross-sectional view showing a step subsequent to that shown in FIG. 66Y. [Figure 67] FIG. 67 is an enlarged view of a region corresponding to FIG. 51, showing a semiconductor device according to the 27th embodiment of the present invention. [Figure 68] 68 is a cross-sectional view taken along line LXVIII-LXVIII shown in FIG. 67. FIG. [Figure 69] 69 is a cross-sectional view taken along line LXIX-LXIX shown in FIG. [Figure 70] FIG. 70 is an enlarged view of the area LXX-LXX shown in FIG. [Figure 71] FIG. 71 is a graph showing the leakage current characteristics when NiSi is used as the low resistance electrode layer. [Figure 72] FIG. 72 is a graph showing the leakage current characteristics when CoSi2 is used as the low resistance electrode layer. [Figure 73] FIG. 73 is a graph showing the leakage current characteristics when TiSi2 is used as the low resistance electrode layer. [Figure 74A] 74A is an enlarged view of a region corresponding to FIG. 70, and is an enlarged view for explaining an example of a method for manufacturing the semiconductor device shown in FIG. [Figure 74B] FIG. 74B is an enlarged view showing a step subsequent to that of FIG. 74A. [Figure 74C] FIG. 74C is an enlarged view showing a step subsequent to that of FIG. 74B. [Fig. 74D] FIG. 74D is an enlarged view showing a step subsequent to that of FIG. 74C. [Figure 74E] FIG. 74E is an enlarged view showing a step subsequent to that of FIG. 74D. [Figure 74F] FIG. 74F is an enlarged view showing a step subsequent to that of FIG. 74E. [Figure 74G] FIG. 74G is an enlarged view showing a step subsequent to that of FIG. 74F. [Figure 75] FIG. 75 is an enlarged view of a region corresponding to FIG. 70, showing a semiconductor device according to the 28th embodiment of the present invention. [Figure 76A] 76A is an enlarged view of a region corresponding to FIG. 75, and is an enlarged view for explaining an example of a method for manufacturing the semiconductor device shown in FIG. [Figure 76B] FIG. 76B is an enlarged view showing a step subsequent to that of FIG. 76A. [Figure 76C] FIG. 76C is an enlarged view showing a step subsequent to that of FIG. 76B. [Figure 76D] FIG. 76D is an enlarged view showing a step subsequent to that of FIG. 76C. [Figure 76E] FIG. 76E is an enlarged view showing a step subsequent to that of FIG. 76D. [Figure 76F]FIG. 76F is an enlarged view showing a step subsequent to that of FIG. 76E. [Figure 76G] FIG. 76G is an enlarged view showing a step subsequent to that of FIG. 76F. [Figure 77] FIG. 77 is an enlarged view of a region corresponding to FIG. 70, showing a semiconductor device according to the twenty-ninth embodiment of the present invention. [Figure 78A] 78A is an enlarged view of a region corresponding to FIG. 77, and is an enlarged view for explaining an example of a method for manufacturing the semiconductor device shown in FIG. [Figure 78B] FIG. 78B is an enlarged view showing a step subsequent to that of FIG. 78A. [Figure 78C] FIG. 78C is an enlarged view showing a step subsequent to that of FIG. 78B. [Figure 78D] FIG. 78D is an enlarged view showing a step subsequent to that of FIG. 78C. [Figure 78E] FIG. 78E is an enlarged view showing a step subsequent to that of FIG. 78D. [Figure 78F] FIG. 78F is an enlarged view showing a step subsequent to that of FIG. 78E. [Figure 79] FIG. 79 is an enlarged view of a region corresponding to FIG. 70, showing a semiconductor device according to a 30th embodiment of the present invention. [Figure 80] 80 is a cross-sectional view of a region corresponding to FIG. 69, showing the semiconductor device shown in FIG. [Figure 81] FIG. 81 is a cross-sectional view of a region corresponding to FIG. 55, showing the semiconductor device shown in FIG. [Figure 82A] 82A is an enlarged view of a region corresponding to FIG. 79, and is an enlarged view for explaining an example of a method for manufacturing the semiconductor device shown in FIG. [Figure 82B] FIG. 82B is an enlarged view showing a step subsequent to that of FIG. 82A. [Figure 82C] FIG. 82C is an enlarged view showing a step subsequent to that of FIG. 82B. [Figure 83] FIG. 83 is a bottom view showing a semiconductor device according to the thirty-first embodiment of the present invention, and is a bottom view showing a first embodiment of a protrusion group. [Figure 84A] FIG. 84A is a diagram showing a second example of the raised portion group. [Figure 84B] FIG. 84B is a diagram showing a third example of the raised portion group. [Figure 84C] FIG. 84C is a diagram showing a fourth example of the raised portion group. [Figure 84D] FIG. 84D is a diagram showing a fifth example of the group of raised portions. [Figure 85] FIG. 85 is a cross-sectional view of a region corresponding to FIG. 68, showing the semiconductor device shown in FIG. [Figure 86] FIG. 86 is a cross-sectional view of a region corresponding to FIG. 69, showing the semiconductor device shown in FIG. [Figure 87] FIG. 87 is an enlarged view of area LXXXVII shown in FIG. [Figure 88] FIG. 88 is a cross-sectional view of a region corresponding to FIG. 55, showing the semiconductor device shown in FIG. [Figure 89] FIG. 89 is a bottom view corresponding to FIG. 83, showing the semiconductor device according to the 32nd embodiment of the present invention. [Figure 90] FIG. 90 is a cross-sectional view corresponding to FIG. 86, showing a semiconductor device according to the thirty-third embodiment of the present invention. [Figure 91] FIG. 91 is an enlarged view of region XCI shown in FIG. [Figure 92] FIG. 92 is a cross-sectional view corresponding to FIG. 86, showing a semiconductor device according to the thirty-fourth embodiment of the present invention. [Figure 93] FIG. 93 is an enlarged view of region XCIII shown in FIG. [Figure 94] FIG. 94 is a cross-sectional view of a region corresponding to FIG. 55, showing a semiconductor device according to the 35th embodiment of the present invention. [Figure 95] FIG. 95 is a cross-sectional view of a region corresponding to FIG. 55, showing a semiconductor device according to the 36th embodiment of the present invention. [Figure 96]FIG. 96 is a cross-sectional view of a region corresponding to FIG. 55, showing a semiconductor device according to the 37th embodiment of the present invention. [Figure 97] FIG. 97 is a cross-sectional view of a region corresponding to FIG. 55, showing a semiconductor device according to the 38th embodiment of the present invention. [Figure 98] FIG. 98 is a cross-sectional view of a region corresponding to FIG. 55, showing a semiconductor device according to the thirty-ninth embodiment of the present invention. [Figure 99] FIG. 99 is a cross-sectional view of a region corresponding to FIG. 55, showing a semiconductor device according to the fortieth embodiment of the present invention. [Figure 100] FIG. 100 is a cross-sectional view of a region corresponding to FIG. 55, showing a semiconductor device according to the forty-first embodiment of the present invention. [Figure 101] FIG. 101 is a cross-sectional view of a region corresponding to FIG. 55, showing a semiconductor device according to the 42nd embodiment of the present invention. [Figure 102] FIG. 102 is an enlarged view of a region corresponding to FIG. 51, showing a semiconductor device according to the 43rd embodiment of the present invention. [Figure 103] FIG. 103 is a cross-sectional view taken along the line CIII-CIII shown in FIG. [Figure 104] FIG. 104 is an enlarged view of a region corresponding to FIG. 51, showing a semiconductor device according to the 44th embodiment of the present invention. [Figure 105] FIG. 105 is an enlarged view of a region corresponding to FIG. 54, showing a semiconductor device according to the 45th embodiment of the present invention. [Figure 106] FIG. 106 is a perspective view showing a semiconductor package in which any one of the semiconductor devices according to the first to forty-fifth embodiments can be incorporated, with the sealing body shown in perspective. [Figure 107] FIG. 107 is a diagram showing a unit cell of a 4H—SiC single crystal applied to an embodiment of the present invention. [Figure 108] FIG. 108 is a plan view showing the silicon surface of the unit cell of the 4H—SiC single crystal shown in FIG. DETAILED DESCRIPTION OF THE INVENTION

[0021] Fig. 1 is a plan view showing a semiconductor device 1 according to a first embodiment of the present invention, and Fig. 2 is a cross-sectional view taken along line II-II in Fig. 1.

[0022] 1 and 2, semiconductor device 1 includes an n-type SiC semiconductor layer 2 containing silicon carbide (SiC) single crystal.

[0023] The SiC semiconductor layer 2 includes a first main surface 3 on one side and a second main surface 4 on the other side. In this embodiment, the SiC semiconductor layer 2 includes a SiC semiconductor substrate 5 including a SiC single crystal and a n-type SiC single crystal. - The SiC semiconductor layer 2 has a layered structure including a SiC epitaxial layer 6. The second main surface 4 of the SiC semiconductor layer 2 is formed by the SiC semiconductor substrate 5. The first main surface 3 of the SiC semiconductor layer 2 is formed by the SiC epitaxial layer 6.

[0024] A drain electrode 7 is connected to the second main surface 4 of the SiC semiconductor layer 2. The SiC semiconductor substrate 5 has an n + The SiC epitaxial layer 6 is formed as an n-type drain region. - The drain drift region is formed as a gate electrode.

[0025] The n-type impurity concentration of the SiC semiconductor substrate 5 is 1.0×10 18 cm -3 Over 1.0 x 10 21 cm -3 The n-type impurity concentration of the SiC epitaxial layer 6 may be 1.0×10 or less. 15 cm -3 Over 1.0 x 10 17 cm -3 Hereinafter, in this specification, the term "impurity concentration" refers to the peak value of the impurity concentration.

[0026] 1 and 2, a plurality of trench gate structures 10 and a plurality of trench source structures 11 are formed on a first main surface 3 of a SiC semiconductor layer 2. The trench gate structures 10 and the trench source structures 11 are alternately formed at intervals from each other along an arbitrary first direction X.

[0027] The trench gate structure 10 and the trench source structure 11 are formed in strip shapes extending along a second direction Y perpendicular to the first direction X. Preferably, the first direction X is the [11-20] direction, and the second direction Y is the [1-100] direction.

[0028] A stripe structure including a plurality of trench gate structures 10 and a plurality of trench source structures 11 is formed on the first main surface 3 of the SiC semiconductor layer 2. The distance between the trench gate structures 10 and the trench source structures 11 in the first direction X may be not less than 0.3 μm and not more than 1.0 μm.

[0029] Each trench gate structure 10 includes a gate trench 12, a gate insulating layer 13, and a gate electrode layer 14. For clarity, the gate electrode layer 14 is shown by hatching in Figure 1 .

[0030] The gate trench 12 is formed by digging down the first main surface 3 of the SiC semiconductor layer 2 toward the second main surface 4. The gate trench 12 includes a first sidewall 15 and a first bottom wall 16.

[0031] The gate insulating layer 13 is formed in the form of a film along the first sidewall 15, the first bottom wall 16, and the corners 17 connecting the first sidewall 15 and the first bottom wall 16 of the gate trench 12. The gate insulating layer 13 defines a recessed space within the gate trench 12.

[0032] The gate insulating layer 13 may contain silicon oxide. In addition to silicon oxide, the gate insulating layer 13 may contain at least one of undoped silicon, silicon nitride, aluminum oxide, aluminum nitride, and aluminum oxynitride.

[0033] The gate electrode layer 14 is embedded in the gate trench 12 with the gate insulating layer 13 sandwiched therebetween. More specifically, the gate electrode layer 14 is embedded in a concave space defined by the gate insulating layer 13.

[0034] The gate electrode layer 14 may contain conductive polysilicon. In addition to conductive polysilicon, the gate electrode layer 14 may contain at least one of titanium, nickel, copper, aluminum, silver, gold, titanium nitride, and tungsten.

[0035] Each trench source structure 11 includes a source trench 18, a barrier-forming layer 19, a source electrode layer 20, and a p - 1, the source electrode layer 20 is shown by hatching for clarity. The deep well region 21 is also referred to as a breakdown voltage holding region.

[0036] The source trench 18 is formed by digging down the first main surface 3 of the SiC semiconductor layer 2 toward the second main surface 4. The source trench 18 includes a second sidewall 22 and a second bottom wall .

[0037] The second sidewall 22 of the source trench 18 includes a first wall portion 24 and a second wall portion 25. The first wall portion 24 of the source trench 18 is located on the first main surface 3 side of the SiC semiconductor layer 2 with respect to the first bottom wall 16 of the gate trench 12. In other words, the first wall portion 24 is a portion that overlaps with the gate trench 12 in a lateral direction parallel to the first main surface 3 of the SiC semiconductor layer 2.

[0038] The second wall portion 25 of the source trench 18 is located on the second main surface 4 side of the SiC semiconductor layer 2 with respect to the second bottom wall 23 of the gate trench 12. In other words, the second wall portion 25 is a portion of the source trench 18 located in a region on the second main surface 4 side of the SiC semiconductor layer 2 with respect to the second bottom wall 23 of the gate trench 12.

[0039] In the thickness direction of the SiC semiconductor layer 2, the length of the second wall portion 25 of the source trench 18 is greater than the length of the first wall portion 24 of the source trench 18. In the thickness direction of the SiC semiconductor layer 2, the second bottom wall 23 of the source trench 18 is located in a region between the first bottom wall 16 of the gate trench 12 and the second main surface 4 of the SiC semiconductor layer 2.

[0040] In this embodiment, the second bottom wall 23 of the source trench 18 is located in the SiC epitaxial layer 6. The second bottom wall 23 of the source trench 18 may be located in the SiC semiconductor substrate 5.

[0041] The barrier-forming layer 19 is formed in the form of a film along the second sidewall 22, the second bottom wall 23, and the corner 26 connecting the second sidewall 22 and the second bottom wall 23 of the source trench 18. The barrier-forming layer 19 defines a recessed space within the source trench 18.

[0042] The barrier-forming layer 19 is made of a material different from the conductive material of the source electrode layer 20. The barrier-forming layer 19 has a potential barrier higher than the potential barrier between the source electrode layer 20 and the deep well region 21.

[0043] A conductive barrier-forming layer may be employed as barrier-forming layer 19. The conductive barrier-forming layer may include at least one of conductive polysilicon, tungsten, platinum, nickel, cobalt, or molybdenum.

[0044] An insulating barrier-forming layer may be employed as the barrier-forming layer 19. The insulating barrier-forming layer may contain at least one of undoped silicon, silicon oxide, silicon nitride, aluminum oxide, aluminum nitride, or aluminum oxynitride. FIG. 2 shows an example in which an insulating barrier-forming layer is formed as the barrier-forming layer 19.

[0045] More specifically, the barrier-forming layer 19 is silicon oxide. The barrier-forming layer 19 and the gate insulating layer 13 are preferably formed of the same material. In this case, the thickness of the barrier-forming layer 19 and the thickness of the gate insulating layer 13 are preferably the same. When the barrier-forming layer 19 and the gate insulating layer 13 are formed of silicon oxide, the barrier-forming layer 19 and the gate insulating layer 13 can be formed simultaneously by a thermal oxidation process.

[0046] The source electrode layer 20 is embedded in the recessed space of the source trench 18 with the barrier-forming layer 19 sandwiched therebetween. The source electrode layer 20 may include conductive polysilicon. The source electrode layer 20 may be n-type polysilicon doped with n-type impurities or p-type polysilicon doped with p-type impurities.

[0047] The source electrode layer 20 may contain, in addition to conductive polysilicon, at least one of titanium, nickel, copper, aluminum, silver, gold, titanium nitride, and tungsten.

[0048] The source electrode layer 20 may be formed from the same conductive material as the gate electrode layer 14. In this case, the gate electrode layer 14 and the source electrode layer 20 can be formed simultaneously. Of course, the source electrode layer 20 may be formed from a conductive material different from that of the gate electrode layer 14.

[0049] The deep well region 21 is formed in the SiC semiconductor layer 2 in a region along the source trench 18. The p-type impurity concentration of the deep well region 21 is 1.0×10 17 cm -3 Over 1.0 x 10 19 cm-3 It may be the following:

[0050] The deep well region 21 is formed in a region of the SiC semiconductor layer 2 along the second sidewall 22 of the source trench 18. The deep well region 21 is formed in a region of the SiC semiconductor layer 2 along the second bottom wall 23 of the source trench 18.

[0051] In this embodiment, the deep well region 21 is continuously formed in the SiC semiconductor layer 2 in a region along the second sidewall 22, the corner portion 26, and the second bottom wall 23 of the source trench 18. The deep well region 21 includes a first region 27 and a second region 28 in a portion along the second sidewall 22 of the source trench 18.

[0052] The first region 27 of the deep well region 21 is formed along the first wall portion 24 of the second sidewall 22 of the source trench 18. The second region 28 of the deep well region 21 is formed along the second wall portion 25 of the second sidewall 22 of the source trench 18. In the thickness direction of the SiC semiconductor layer 2, the length of the second region 28 of the deep well region 21 is greater than the length of the first region 27 of the deep well region 21.

[0053] The thickness of the deep well region 21 along the second bottom wall 23 of the source trench 18 may be equal to or greater than the thickness of the deep well region 21 along the second sidewall 22 of the source trench 18 .

[0054] The portion of the deep well region 21 along the second bottom wall 23 of the source trench 18 may be located within the SiC semiconductor substrate 5 , across the boundary region between the SiC semiconductor substrate 5 and the SiC epitaxial layer 6 .

[0055] In the portion of the SiC semiconductor layer 2 along the second bottom wall 23 of the source trench 18, the p-type impurity is implanted along the normal direction to the first main surface 3 of the SiC semiconductor layer 2. On the other hand, in the portion of the SiC semiconductor layer 2 along the second sidewall 22 of the source trench 18, the p-type impurity is implanted at an angle with respect to the first main surface 3 of the SiC semiconductor layer 2.

[0056] Therefore, in the portion of the SiC semiconductor layer 2 along the second bottom wall 23 of the source trench 18, the p-type impurity is implanted at a deeper position than in the portion along the second side wall 22 of the source trench 18. As a result, in the deep well region 21, a difference in thickness occurs between the portion along the second bottom wall 23 of the source trench 18 and the portion along the second side wall 22 of the source trench 18.

[0057] The surface layer portion of the first main surface 3 of the SiC semiconductor layer 2 contains p - A body region 30 of a type is formed in the source trench 18. The body region 30 is formed in a region between the gate trench 12 and the source trench 18. The body region 30 is formed in a strip shape extending along the second direction Y in a plan view.

[0058] The body region 30 is exposed from the first sidewall 15 of the gate trench 12 and the second sidewall 22 of the source trench 18. The body region 30 is continuous with the first region 27 of the deep well region 21.

[0059] The p-type impurity concentration of the body region 30 is 1.0×10 16 cm -3 Over 1.0 x 10 19 cm -3 The p-type impurity concentration of the body region 30 may be approximately equal to the p-type impurity concentration of the deep well region 21. The p-type impurity concentration of the body region 30 may be higher than the p-type impurity concentration of the deep well region 21.

[0060] The surface layer of the body region 30 is +A source region 31 of a type is formed in the body region 30. The source region 31 is formed in a surface layer portion of the body region 30 in a region along the first sidewall 15 of the gate trench 12. The source region 31 is exposed from the first sidewall 15 of the gate trench 12.

[0061] The source region 31 may be formed in a strip shape extending along the second direction Y in a plan view. Although not shown, the source region 31 may include a portion exposed from the second sidewall 22 of the source trench 18.

[0062] The width WS of the source region 31 may be 0.2 μm or more and 0.6 μm or less (for example, about 0.4 μm). In this embodiment, the width WS is the width of the source region 31 along the first direction X. The n-type impurity concentration of the source region 31 is 1.0×10 18 cm -3 Over 1.0 x 10 21 cm -3 It may be the following:

[0063] The surface layer of the body region 30 is + A contact region 32 is formed in the body region 30. The contact region 32 is formed in a surface portion of the body region 30 in a region along the second sidewall 22 of the source trench 18. The contact region 32 is exposed from the second sidewall 22 of the source trench 18.

[0064] The contact region 32 may be connected to the source region 31. The contact region 32 may be formed in a strip shape extending along the second direction Y in a plan view. The contact region 32 may include a portion exposed from the first sidewall 15 of the adjacent gate trench 12.

[0065] The width WC of the contact region 32 may be 0.1 μm or more and 0.4 μm or less (for example, about 0.2 μm). In this embodiment, the width WC is the width of the contact region 32 along the first direction X. The p-type impurity concentration of the contact region 32 is 1.0×10 18 cm -3 Over 1.0 x 10 21cm -3 It may be the following:

[0066] An insulating layer 40 is formed on the first main surface 3 of the SiC semiconductor layer 2. The insulating layer 40 collectively covers the plurality of trench gate structures 10. A contact hole 41 is formed in the insulating layer 40. The contact hole 41 selectively exposes the trench source structure 11, the source region 31, and the contact region 32.

[0067] A main surface source electrode 42 is formed on the insulating layer 40. The main surface source electrode 42 extends from above the insulating layer 40 into the contact hole 41. The main surface source electrode 42 is electrically connected to the source electrode layer 20, the source region 31, and the contact region 32 within the contact hole 41.

[0068] The principal surface source electrode 42 may be formed of the same conductive material as the source electrode layer 20. The principal surface source electrode 42 may be formed of a conductive material different from that of the source electrode layer 20.

[0069] In this embodiment, the source electrode layer 20 includes n-type polysilicon or p-type polysilicon, and the main surface source electrode 42 includes aluminum or a metal material containing aluminum as a main component. The main surface source electrode 42 may include at least one of conductive polysilicon, titanium, nickel, copper, aluminum, silver, gold, titanium nitride, and tungsten.

[0070] The main surface source electrode 42 may be composed of an electrode layer formed integrally with the source electrode layer 20. In this case, the source electrode layer 20 and the main surface source electrode 42 may be formed through a common process.

[0071] The dimensions of the trench gate structure 10 and the dimensions of the trench source structure 11 will be specifically described below.

[0072] The trench gate structure 10 has an aspect ratio D1 / W1, which is defined by the ratio of the depth D1 of the trench gate structure 10 to the width W1 of the trench gate structure 10.

[0073] In this embodiment, the width W1 is the width of the trench gate structure 10 along the first direction X. The aspect ratio D1 / W1 of the trench gate structure 10 is also the aspect ratio of the gate trench 12.

[0074] The aspect ratio D1 / W1 of the trench gate structure 10 may be 0.25 or more and 15.0 or less. The width W1 of the trench gate structure 10 may be 0.2 μm or more and 2.0 μm or less (for example, about 0.4 μm). The depth D1 of the trench gate structure 10 may be 0.5 μm or more and 3.0 μm or less (for example, about 1.0 μm).

[0075] The trench source structure 11 has an aspect ratio D2 / W2, which is the ratio of the depth D2 of the trench source structure 11 to the width W2 of the trench source structure 11.

[0076] The width W2 of the trench source structure 11 is the sum of the width WST of the source trench 18, the first width Wα of the deep well region 21, and the second width Wβ of the deep well region 21 (W2=WST+Wα+Wβ).

[0077] In this embodiment, the width WST is the width of the source trench 18 along the first direction X. In this embodiment, the first width Wα is the width of the deep well region 21 along the second sidewall 22 on one side of the source trench 18 along the first direction X. In this embodiment, the second width Wβ is the width of the deep well region 21 along the second sidewall 22 on the other side of the source trench 18 along the first direction X.

[0078] The aspect ratio D2 / W2 of the trench source structure 11 is greater than the aspect ratio D1 / W1 of the trench gate structure 10. The aspect ratio D2 / W2 of the trench source structure 11 may be equal to or greater than 0.5 and equal to or less than 18.0.

[0079] The ratio D2 / D1 of the depth D2 of the trench source structure 11 to the depth D1 of the trench gate structure 10 may be 1.5 or more and 4.0 or less. Increasing the depth D2 of the trench source structure 11 can also enhance the breakdown voltage retention effect of the SJ (Super Junction) structure.

[0080] The width W2 of the trench source structure 11 may be 0.6 μm or more and 2.4 μm or less (for example, about 0.8 μm). The depth D2 of the trench source structure 11 may be 1.5 μm or more and 11 μm or less (for example, about 2.5 μm). The width W2 of the trench source structure 11 may be equal to the width W1 of the trench gate structure 10. The width W2 of the trench source structure 11 may be different from the width W1 of the trench gate structure 10.

[0081] In the trench source structure 11, the source trench 18 has an aspect ratio DST / WST, which is the ratio of the depth DST of the source trench 18 to the width WST of the source trench 18.

[0082] The aspect ratio DST / WST of the source trench 18 is larger than the aspect ratio D1 / W1 of the trench gate structure 10. The aspect ratio DST / WST of the source trench 18 may be equal to or greater than 0.5 and equal to or less than 18.0.

[0083] The width WST of source trench 18 may be 0.2 μm or more and 2.0 μm or less (for example, about 0.4 μm). The width WST of source trench 18 may be equal to the width W1 of gate trench 12 (WST=W1).

[0084] When the width WST of the source trench 18 or the width W1 of the gate trench 12 varies along the depth direction, the widths WST and W1 are defined as the widths of the openings. The depth DST of the source trench 18 may be 1.0 μm or more and 10 μm or less (for example, about 2.0 μm).

[0085] The ratio of the depth DST of the source trench 18 to the depth D1 of the trench gate structure 10 (gate trench 12) is preferably equal to or greater than 2. The ratio DST / D1 of the depth DST of the source trench 18 to the depth D1 of the trench gate structure 10 may exceed 4.0. In this case, attention must be paid to the durability of the resist mask used when forming the source trench 18 by etching.

[0086] For example, when the depth D1 of the trench gate structure 10 is about 3.0 μm and the ratio DST / D1 exceeds 4, it is expected that the resist mask will approach or exceed its durability limit due to etching. If the resist mask exceeds its durability limit, undesired etching of the SiC semiconductor layer 2 will occur.

[0087] Therefore, it is preferable that the ratio DST / D1 of the depth DST of the source trench 18 to the depth D1 of the trench gate structure 10 is greater than 1.0 and not more than 4.0. If the ratio DST / D1 is in this range, the source trench 18 can be formed appropriately.

[0088] Fig. 3 is a cross-sectional view for explaining the operation of the semiconductor device 1 of Fig. 1. In Fig. 3, the same structures as those in Fig. 2 are denoted by the same reference numerals.

[0089] In the semiconductor device 1, a pn junction 45 is formed in the boundary region between the SiC semiconductor layer 2 and the deep well region 21. When the semiconductor device 1 switches from an on state to an off state, a depletion layer 46 expands from the pn junction 45 toward the SiC semiconductor layer 2. In FIG. 3, the depletion layer 46 is indicated by a two-dot chain line.

[0090] The deep well region 21 includes a first region 27 and a second region 28. The first region 27 is formed along a first wall portion 24 of the second sidewall 22 of the source trench 18. The second region 28 is formed along a second wall portion 25 of the second sidewall 22 of the source trench 18.

[0091] The depletion layer 46 from the pn junction 45 extends into a region of the SiC semiconductor layer 2 that is closer to the first main surface 3 than the first bottom wall 16 of the gate trench 12. The depletion layer 46 from the pn junction 45 extends into a region of the SiC semiconductor layer 2 that is closer to the second main surface 4 than the first bottom wall 16 of the gate trench 12.

[0092] When the semiconductor device 1 switches from an on state to an off state, the current path of the short-circuit current flowing from the drain electrode 7 to the source electrode layer 20 is narrowed by the depletion layer 46. This can delay the time until the semiconductor device 1 is destroyed.

[0093] In particular, in the semiconductor device 1, the aspect ratio D2 / W2 of the trench source structure 11 is larger than the aspect ratio D1 / W1 of the trench gate structure 10. The aspect ratio D2 / W2 of the trench source structure 11 is not less than 0.5 and not more than 18.0.

[0094] Moreover, the ratio D2 / D1 of the depth D2 of the trench source structure 11 to the depth D1 of the trench gate structure 10 is 1.5 or more and 4.0 or less. In the thickness direction of the SiC semiconductor layer 2, the length of the second region 28 of the deep well region 21 is greater than the length of the first region 27 of the deep well region 21.

[0095] Therefore, in SiC semiconductor layer 2, the proportion of the area occupied by depletion layer 46 extending into the area on the second main surface 4 side can be reliably increased compared to the proportion of the area occupied by depletion layer 46 extending into the area on the first main surface 3 side. This ensures that the current path of the short-circuit current can be narrowed in the area on the drain electrode 7 side.

[0096] The depletion layer 46 from the pn junction 45 may overlap the first bottom wall 16 of the gate trench 12. The depletion layer 46 on the second region 28 side of the deep well region 21 may overlap the first bottom wall 16 of the gate trench 12.

[0097] In this structure, the current path of the short-circuit current can be reliably narrowed in the region on the drain electrode 7 side. Of course, the depletion layer 46 on the first region 27 side of the deep well region 21 may overlap the first bottom wall 16 of the gate trench 12.

[0098] Furthermore, according to the semiconductor device 1, the area occupied by the depletion layer 46 in the SiC semiconductor layer 2 can be increased, thereby reducing the feedback capacitance Crss inversely proportionally. The feedback capacitance Crss is the electrostatic capacitance between the gate electrode layer 14 and the drain electrode 7.

[0099] As described above, the semiconductor device 1 can improve the short-circuit resistance and reduce the feedback capacitance Crss.

[0100] Furthermore, according to the semiconductor device 1, a barrier-forming layer 19 is formed in the source trench 18. The barrier-forming layer 19 has a potential barrier higher than the potential barrier between the deep well region 21 and the source electrode layer 20.

[0101] Therefore, even if the depletion layer 46 extending from the pn junction 45 between the SiC semiconductor layer 2 and the deep well region 21 comes into contact with the inner wall surface of the source trench 18, the occurrence of punch-through can be suppressed. This makes it possible to suppress the leakage current caused by punch-through.

[0102] In the absence of the barrier-forming layer 19, punch-through tends to be more pronounced at the corners 26 of the source trench 18 because the depletion layer 46 extends from the second sidewall 22 of the source trench 18 along the second bottom wall 23 of the source trench 18.

[0103] Therefore, in the semiconductor device 1, the inner wall surface of the source trench 18, including the corner portion 26, is covered with the barrier-forming layer 19. This makes it possible to effectively suppress the occurrence of punch-through in the source trench 18.

[0104] According to the semiconductor device 1, from the viewpoint of designing the short-circuit resistance and the feedback capacitance Crss, a depletion layer 46 is formed in a relatively wide region in the SiC semiconductor layer 2, but the leakage current caused by the depletion layer 46 can be appropriately suppressed by the barrier formation layer 19.

[0105] Fig. 4 is a graph showing the drain current-drain voltage characteristics of the semiconductor device 1 of Fig. 1. In Fig. 4, the vertical axis represents the drain current ID [A / cm 2 The horizontal axis represents the drain voltage VD [V]. The drain current ID is a current (short-circuit current) that flows between the drain electrode 7 and the source electrode layer 20.

[0106] 4 shows curves L1 and L2. Both curves L1 and L2 were obtained by simulation. Curves L1 and L2 show the change in drain current ID when a predetermined range of drain voltage VD is applied to the drain electrode 7. The drain voltage VD is changed in the range from 0 V to 1000 V.

[0107] A curve L1 shows the drain current-drain voltage characteristics of the semiconductor device according to the reference example. A curve L2 shows the drain current-drain voltage characteristics of the semiconductor device 1. The semiconductor device according to the reference example has a similar structure to the semiconductor device 1, except that the depth D2 of the source trench 18 is equal to the depth D1 of the gate trench 12.

[0108] Referring to the curve L1, in the semiconductor device according to the reference example, when the drain voltage VD exceeds 200 V, the drain current ID becomes 15000 A / cm 2 On the other hand, referring to the curve L2, in the semiconductor device 1, the drain current ID exceeds 15000 A / cm when the drain voltage VD is in the range of 0 V to 1000 V. 2is less than.

[0109] In the semiconductor device 1, when the drain voltage VD is in the range of 400 V or more and 1000 V or less, the drain current ID is 10000 A / cm 2 More than 15000A / cm 2 It is within the range of less than.

[0110] When the drain voltage VD is 600 V, the drain current ID of the semiconductor device 1 is reduced by about 45% compared to the drain current ID of the semiconductor device according to the reference example.

[0111] From the simulation results, it was confirmed that by forming the deep well region 21 along the source trench 18 that is deeper than the gate trench 12, the short-circuit resistance can be significantly improved.

[0112] Fig. 5 is a graph showing the feedback capacitance-drain voltage characteristics of the semiconductor device 1 of Fig. 1. In Fig. 5, the vertical axis represents the feedback capacitance Crss [F / cm 2 ], and the horizontal axis represents the drain voltage VD [V].

[0113] 5 shows curves L3 and L4. Both curves L3 and L4 were obtained by simulation. Curves L3 and L4 show the change in feedback capacitance Crss when a predetermined range of drain voltages VD is applied to the drain electrode 7. The drain voltage VD is changed in the range from 0 V to 1000 V.

[0114] A curve L3 shows the feedback capacitance-drain voltage characteristics of the semiconductor device according to the reference example. A curve L4 shows the feedback capacitance-drain voltage characteristics of the semiconductor device 1. The semiconductor device according to the reference example has a similar structure to the semiconductor device 1, except that the depth D2 of the source trench 18 is equal to the depth D1 of the gate trench 12.

[0115] With reference to curve L3, in the semiconductor device according to the reference example, the feedback capacitance Crss decreases gradually when the drain voltage VD is in the range of 1 V to 10 V. In the semiconductor device according to the reference example, the rate of decrease in the feedback capacitance Crss is about 25% when the drain voltage VD is in the range of 1 V to 10 V.

[0116] On the other hand, in the semiconductor device 1, the feedback capacitance Crss decreases sharply when the drain voltage VD is in the range of 1 V to 10 V. When the drain voltage VD is 10 V, the feedback capacitance Crss of the semiconductor device 1 is reduced by about 95% compared to the feedback capacitance Crss of the semiconductor device according to the reference example. In the semiconductor device 1, the reduction rate of the feedback capacitance Crss is between 95% and 99% in the drain voltage VD range of 1 V to 10 V.

[0117] From the simulation results, it was confirmed that the feedback capacitance Crss can be significantly reduced by forming the deep well region 21 along the source trench 18, which is deeper than the gate trench 12. In other words, it was confirmed that the switching speed can be significantly improved by reducing the feedback capacitance Crss.

[0118] 6 is a cross-sectional view showing a semiconductor device 51 according to a second embodiment of the present invention. In the following, structures corresponding to those described with respect to the semiconductor device 1 are given the same reference numerals, and descriptions thereof will be omitted.

[0119] 6 , the source region 31 is exposed from the first sidewall 15 of the gate trench 12 and the second sidewall 22 of the source trench 18. The contact region 32 is formed in the deep well region 21 in a region along the second bottom wall 23 of the source trench 18. The contact region 32 is exposed from the second bottom wall 23 of the source trench 18.

[0120] The contact region 32 may cover the entire second bottom wall 23 of the source trench. The p-type impurity concentration of the contact region 32 is higher than the p-type impurity concentration of the deep well region 21.

[0121] 6 shows an example in which the barrier-forming layer 19 is made of a conductive barrier-forming layer. The barrier-forming layer 19 is formed along the inner wall surface of the source trench 18 and selectively exposes the contact region 32 from the second bottom wall 23 of the source trench 18.

[0122] More specifically, the barrier-forming layer 19 includes a first portion 52 and a second portion 53. The first portion 52 of the barrier-forming layer 19 covers the second sidewall 22 of the source trench 18. The second portion 53 of the barrier-forming layer 19 partially covers the second bottom wall 23 of the source trench 18.

[0123] The second portion 53 of the barrier-forming layer 19 is continuous with the first portion 52 of the barrier-forming layer 19. The second portion 53 of the barrier-forming layer 19 extends from the corner 26 of the source trench 18 along the second bottom wall 23.

[0124] The second portion 53 of the barrier-forming layer 19 exposes the center of the second bottom wall 23 of the source trench 18. The second portion 53 of the barrier-forming layer 19 may be formed in an endless shape (annular shape) in plan view.

[0125] As described above, the semiconductor device 51 can achieve the same effects as those described for the semiconductor device 1. Furthermore, according to the semiconductor device 51, even if the depletion layer 46 spreads from the corner 26 of the source trench 18 along the second bottom wall 23, the barrier-forming layer 19 can increase the distance until the depletion layer 46 reaches the source electrode layer 20. This makes it possible to suppress the occurrence of punch-through near the corner 26 of the source trench 18.

[0126] 7 is a cross-sectional view showing a semiconductor device 61 according to a third embodiment of the present invention. In the following, structures corresponding to those described for the semiconductor device 51 are given the same reference numerals, and descriptions thereof will be omitted.

[0127] An exposed portion 62 that selectively exposes the second bottom wall 23 of the source trench 18 is formed in the deep well region 21. More specifically, the second region 28 of the deep well region 21 is formed along the corner 26 of the source trench 18 so as to expose the center portion of the second bottom wall 23 of the source trench 18. The second region 28 of the deep well region 21 may be formed in an endless shape (annular shape) in a plan view.

[0128] In this embodiment, no contact region 32 is formed. The contact region 32 may be formed in a region along the second sidewall 22 of the source trench 18 in the surface layer portion of the body region 30.

[0129] The source electrode layer 20 forms a heterojunction with the SiC semiconductor layer 2 at the exposed portion 62 of the deep well region 21. This forms a heterojunction diode 63 in which the source electrode layer 20 serves as an anode and the SiC semiconductor layer 2 serves as a cathode.

[0130] The source electrode layer 20 may include conductive polysilicon. Of course, as long as the heterojunction diode 63 is formed, the source electrode layer 20 may include a conductive material other than conductive polysilicon.

[0131] A body diode 64 is formed at a pn junction between the SiC semiconductor layer 2 and the body region 30. The junction barrier of the heterojunction diode 63 is smaller than the built-in potential of the body diode 64. The junction barrier of the heterojunction diode 63 may be 1.0 eV or more and 1.5 eV or less. The built-in potential of the body diode 64 may be 2.8 eV or more and 3.2 eV or less.

[0132] As described above, the semiconductor device 61 can achieve the same effects as those described for the semiconductor device 51. Furthermore, when a reverse bias voltage is applied to the semiconductor device 61, a current can be preferentially flowed into the heterojunction diode 63. This can suppress the expansion of SiC crystal defects in the SiC semiconductor layer 2. As a result, it is possible to suppress an increase in on-resistance while improving the short-circuit resistance and reducing the feedback capacitance Crss.

[0133] 8 is a cross-sectional view showing a semiconductor device 71 according to a fourth embodiment of the present invention. In the following, structures corresponding to those described for the semiconductor device 51 are given the same reference numerals, and descriptions thereof will be omitted.

[0134] The barrier-forming layer 19 has a laminated structure including a plurality of barrier-forming layers formed along the inner wall of the source trench 18. In this embodiment, the barrier-forming layer 19 has a laminated structure including an insulating barrier-forming layer 72 and a conductive barrier-forming layer 73 laminated in this order from the inner wall of the source trench 18.

[0135] The insulating barrier-forming layer 72 is formed in the form of a film along the inner wall surface of the source trench 18. The insulating barrier-forming layer 72 selectively exposes the contact region 32 from the second bottom wall 23 of the source trench 18.

[0136] More specifically, the insulating barrier-forming layer 72 includes a first portion 74 and a second portion 75. The first portion 74 covers the second sidewall 22 of the source trench 18. The second portion 75 selectively covers the second bottom wall 23 of the source trench 18.

[0137] The second portion 75 is continuous with the first portion 74. The second portion 75 extends from the corner 26 of the source trench 18 along the second bottom wall 23 so as to expose the central portion of the second bottom wall 23 of the source trench 18.

[0138] The insulating barrier-forming layer 72 may include at least one of undoped silicon, silicon oxide, silicon nitride, aluminum oxide, aluminum nitride, or aluminum oxynitride.

[0139] The conductive barrier-forming layer 73 is formed in a film shape along the insulating barrier-forming layer 72 so as to selectively expose the contact region 32 from the second bottom wall 23 of the source trench 18. The conductive barrier-forming layer 73 contains a conductive material different from the conductive material of the source electrode layer 20.

[0140] The conductive barrier-forming layer 73 may be formed of the same conductive material as the gate electrode layer 14. The conductive barrier-forming layer 73 may contain at least one of conductive polysilicon, tungsten, platinum, nickel, cobalt, or molybdenum.

[0141] As described above, the semiconductor device 71 can achieve the same effects as those described for the semiconductor device 51. Furthermore, in the semiconductor device 71, the barrier-forming layer 19 has a layered structure including an insulating barrier-forming layer 72 and a conductive barrier-forming layer 73. As a result, the two layers, the insulating barrier-forming layer 72 and the conductive barrier-forming layer 73, can suppress the occurrence of punch-through.

[0142] If the conductive material of the conductive barrier forming layer 73 is the same as that of the gate electrode layer 14, the gate electrode layer 14 and the conductive barrier forming layer 73 can be formed in the same process, thereby suppressing an increase in the number of steps.

[0143] 9 is a cross-sectional view showing a semiconductor device 81 according to a fifth embodiment of the present invention. In the following, structures corresponding to those described with respect to the semiconductor device 1 are given the same reference numerals, and descriptions thereof will be omitted.

[0144] The barrier-forming layer 19 includes a first portion 82 and a second portion 83. The first portion 82 of the barrier-forming layer 19 covers the second sidewall 22 of the source trench 18. The second portion 83 of the barrier-forming layer 19 covers the second bottom wall 23 of the source trench 18.

[0145] The first portion 82 of the barrier-forming layer 19 selectively has a sidewall contact hole 84 that exposes the SiC semiconductor layer 2 from the second sidewall 22 of the source trench 18. The first portion 82 covers the first wall portion 24 of the source trench 18 and exposes the second wall portion 25.

[0146] First portion 82 may be formed to cross the boundary region between SiC semiconductor layer 2 and body region 30. An end portion of first portion 82 on the second main surface 4 side may be formed in a region deeper than the bottom of body region 30.

[0147] In the first portion 82, the end portion on the second main surface 4 side may be formed in a region shallower than the bottom of the body region 30. In the first portion 82, the end portion on the second main surface 4 side may be formed in a region between the bottom of the body region 30 and the bottom of the contact region 32. In these cases, the source electrode layer 20 is connected to at least the body region 30 in the source trench 18.

[0148] In the first portion 82, the end portion on the second main surface 4 side may be formed in a region between the first main surface 3 of the SiC semiconductor layer 2 and the bottom of the contact region 32. The barrier-forming layer 19 may not have the first portion 82, and may have only the second portion 83. In these cases, the source electrode layer 20 is connected to the body region 30 and the contact region 32 in the source trench 18.

[0149] The second portion 83 of the barrier-forming layer 19 is formed to be spaced apart from the first portion 82 of the barrier-forming layer 19. The second portion 83 is separated from the first portion 82. The second portion 83 may cover the corner 26 of the source trench 18.

[0150] The second portion 83 may expose the corner 26 of the source trench 18. The second portion 83 may cover the corner 26 of the source trench 18 and also cover a portion of the second sidewall 22 of the source trench 18.

[0151] The source electrode layer 20 forms a Schottky junction with the SiC semiconductor layer 2 in the source trench 18. This forms a Schottky barrier diode 85 in which the source electrode layer 20 serves as an anode and the SiC semiconductor layer 2 serves as a cathode.

[0152] The source electrode layer 20 may be formed of the same conductive material as the principal surface source electrode 42. The source electrode layer 20 and the principal surface source electrode 42 may be formed of aluminum or a metal material containing aluminum as a main component.

[0153] The source electrode layer 20 and the main surface source electrode 42 may contain at least one of conductive polysilicon, titanium, nickel, copper, aluminum, silver, gold, titanium nitride, and tungsten. In this case, the gate electrode layer 14 is preferably formed of polysilicon (n-type polysilicon or p-type polysilicon).

[0154] The p-type deep well region 21 is formed in the SiC semiconductor layer 2 in a region along the second bottom wall 23 of the source trench 18. The deep well region 21 may be formed continuously in the SiC semiconductor layer 2 in a region along the second side wall 22 and the corner portion 26 of the source trench 18 so as to expose the source electrode layer 20 from the second side wall 22 of the source trench 18.

[0155] That is, the deep well region 21 covers the second bottom wall 23 of the source trench 18. The deep well region 21 also covers a corner 26 connecting the second side wall 22 and the second bottom wall 23 of the source trench 18. The deep well region 21 may expose almost the entire second side wall 22 of the source trench 18 in the SiC semiconductor layer 2.

[0156] The deep well region 21 extends from the second bottom wall 23 of the source trench 18 in a lateral direction parallel to the first main surface 3 of the SiC semiconductor layer 2. As a result, the deep well region 21 faces the body region 30 across a partial region of the SiC semiconductor layer 2 in the normal direction to the first main surface 3 of the SiC semiconductor layer 2.

[0157] More specifically, the source electrode layer 20 forms a Schottky junction with the SiC semiconductor layer 2 at a depth position between the body region 30 and the deep well region 21 in the normal direction to the first main surface 3 of the SiC semiconductor layer 2.

[0158] More specifically, the source electrode layer 20 forms a Schottky junction with the SiC semiconductor layer 2 in a region sandwiched between the body region 30 and the deep well region 21 in the SiC semiconductor layer 2 with respect to the normal direction of the first main surface 3 of the SiC semiconductor layer 2.

[0159] The width W2 of the trench source structure 11 may be equal to the width WST of the source trench 18. In other words, the first width Wα and the second width Wβ of the deep well region 21 may both be zero.

[0160] As described above, the semiconductor device 81 can achieve the same effects as those described for the semiconductor device 1. Furthermore, when a reverse bias voltage is applied to the semiconductor device 81, a current can be preferentially flowed into the Schottky barrier diode 85. This can suppress the expansion of SiC crystal defects in the SiC semiconductor layer 2. As a result, it is possible to suppress an increase in on-resistance while improving the short-circuit resistance and reducing the feedback capacitance Crss.

[0161] In this embodiment, an example has been described in which the source electrode layer 20 forms a Schottky junction with the SiC semiconductor layer 2 in the sidewall contact hole 84 of the barrier-forming layer 19. However, a configuration in which the barrier-forming layer 19 (first portion 82 and second portion 83) is not formed may also be employed.

[0162] 10 is a plan view of a semiconductor device 91 according to a sixth embodiment of the present invention. In the following, structures corresponding to those described with respect to the semiconductor device 1 will be given the same reference numerals and descriptions thereof will be omitted.

[0163] 10, in this embodiment, trench gate structures 10 are formed in a lattice pattern in a plan view. Trench source structures 11 may be formed in a region surrounded by trench gate structures 10.

[0164] The source region 31 may be formed along the periphery of the trench gate structure 10. The contact region 32 may be formed along the periphery of the trench source structure 11.

[0165] As described above, the semiconductor device 91 can also achieve the same effects as those described for the semiconductor device 1. Furthermore, the semiconductor device 91 can also increase the density of the current flowing through the SiC semiconductor layer 2.

[0166] The structure of the semiconductor device 91 can also be applied to each of the above-described embodiments. That is, a structure in which the trench gate structures 10 are formed in a lattice shape in a plan view and the trench source structures 11 are formed in the regions surrounded by the trench gate structures 10 can also be applied to each of the above-described embodiments.

[0167] Although the first to sixth embodiments of the present invention have been described, the first to sixth embodiments of the present invention can also be implemented in other forms.

[0168] In the above-described first to sixth embodiments, the barrier-forming layer 19 may selectively expose the SiC semiconductor layer 2 from the second sidewall 22 of the source trench 18. For example, the barrier-forming layer 19 may expose at least one of the contact region 32, the source region 31, and the body region 30 in the source trench 18.

[0169] In the first to sixth embodiments described above, a structure in which the barrier-forming layer 19 is omitted may be employed.

[0170] In the first to sixth embodiments described above, the gate trench 12 may be formed in a tapered shape in which the area of ​​the first bottom wall 16 is smaller than the area of ​​the opening in a cross-sectional view.

[0171] In the above-described first to sixth embodiments, the first bottom wall 16 of the gate trench 12 may be formed parallel to the first main surface 3 of the SiC semiconductor layer 2. The first bottom wall 16 of the gate trench 12 may be formed in a convex curved shape extending from the first side wall 15 toward the second main surface 4 of the SiC semiconductor layer 2.

[0172] In the first to sixth embodiments described above, the source trench 18 may be formed in a tapered shape in which the area of ​​the second bottom wall 23 is smaller than the area of ​​the opening in a cross-sectional view.

[0173] In the above-described first to sixth embodiments, the second bottom wall 23 of the source trench 18 may be formed parallel to the first main surface 3 of the SiC semiconductor layer 2. The second bottom wall 23 of the source trench 18 may be formed in a convex curved shape extending outward from the second side wall 22.

[0174] In the above-described first to sixth embodiments, a Si semiconductor layer (2) made of Si (silicon) may be used instead of the SiC semiconductor layer 2 made of SiC single crystal. That is, the Si semiconductor layer (2) may have a layered structure including a Si semiconductor substrate (5) made of Si and a Si epitaxial layer (6) made of Si.

[0175] In the first to sixth embodiments described above, a structure in which the conductivity type of each semiconductor portion is reversed may be adopted, i.e., the p-type portion may be formed as n-type, and the n-type portion may be formed as p-type.

[0176] In the first to sixth embodiments, n + Instead of the SiC semiconductor substrate 5 of the p +Alternatively, a SiC semiconductor substrate 5 of this type may be employed. With this structure, an IGBT (Insulated Gate Bipolar Transistor) can be provided instead of a MISFET.

[0177] In this case, the "source" of the MISFET is replaced with the "emitter" of the IGBT. Also, the "drain" of the MISFET is replaced with the "collector" of the IGBT. Even when an IGBT is used instead of a MISFET, the same effects as those described in the above embodiments can be achieved.

[0178] FIG. 11 is a plan view showing a semiconductor device 101 according to the seventh embodiment of the present invention.

[0179] 11, a semiconductor device 101 has a SiC (silicon carbide) semiconductor layer 102 containing SiC single crystal. The SiC semiconductor layer 102 may contain 4H—SiC single crystal.

[0180] The 4H—SiC single crystal has an off-angle tilted from the (0001) plane by an angle of 10° or less with respect to the [11-20] direction. The off-angle may be 0° or more and 4° or less. The off-angle may be greater than 0° and less than 4°. The off-angle is typically set to 2° or 4°, more specifically, in the range of 2°±0.2° or 4°±0.4°.

[0181] In this embodiment, the SiC semiconductor layer 102 is formed in the shape of a rectangular parallelepiped chip. The SiC semiconductor layer 102 has a first main surface 103 on one side, a second main surface 104 on the other side, and side surfaces 105A, 105B, 105C, and 105D connecting the first main surface 103 and the second main surface 104.

[0182] First main surface 103 and second main surface 104 are formed in a quadrangular shape in a plan view seen from the normal direction thereof (hereinafter simply referred to as "plan view"). Side surface 105A faces side surface 105C. Side surface 105B faces side surface 105D.

[0183] Side surfaces 105A to 105D each extend planarly along the normal direction of first main surface 103 and second main surface 104. The length of side surfaces 105A to 105D may each be 1 mm or more and 10 mm or less (for example, 2 mm or more and 5 mm or less).

[0184] The SiC semiconductor layer 102 has an active region 106 and an outer region 107. The active region 106 is a region in which a vertical MISFET (Metal Insulator Semiconductor Field Effect Transistor) is formed. The outer region 107 is a region outside the active region 106.

[0185] In plan view, the active region 106 is set in the center of the SiC semiconductor layer 102 at a distance from the side surfaces 105A-105D of the SiC semiconductor layer 102 to an inner region of the SiC semiconductor layer 102. In plan view, the active region 106 is set in a quadrangular shape having four sides parallel to the four side surfaces 105A-105D of the SiC semiconductor layer 102.

[0186] Outer region 107 is set in a region between side surfaces 105A to 105D of SiC semiconductor layer 102 and the periphery of active region 106. Outer region 107 is set in an endless shape (quadratic ring shape) surrounding active region 106 in plan view.

[0187] A gate pad 108, gate fingers 109, and source pad 110 are formed as first main surface electrodes on the first main surface 103 of the SiC semiconductor layer 102. In Fig. 11, the gate pad 108, gate fingers 109, and source pad 110 are indicated by hatching for clarity. The gate pad 108, gate fingers 109, and source pad 110 may contain aluminum or copper.

[0188] The gate pad 108 is formed along the side surface 105A of the SiC semiconductor layer 102 in a plan view. The gate pad 108 is formed along a central region of the side surface 105A of the SiC semiconductor layer 102 in a plan view. The gate pad 108 may be formed along a corner connecting any two of the four side surfaces 105A to 105D of the SiC semiconductor layer 102 in a plan view.

[0189] The gate pad 108 is formed in a rectangular shape in a plan view and is drawn out from the outer region 107 into the active region 106 so as to cross the boundary region between the outer region 107 and the active region 106 in a plan view.

[0190] The gate fingers 109 are formed in the outer region 107. The gate fingers 109 are drawn out from the gate pad 108 and extend in a strip shape in the outer region 107. In this embodiment, the gate fingers 109 are formed along three side surfaces 105A, 105B, and 105D of the SiC semiconductor layer 102 so as to partition the active region 106 from three directions.

[0191] The source pad 110 is formed in the active region 106 at a distance from the gate pad 108 and the gate fingers 109. The source pad 110 is formed in a concave shape in a plan view so as to cover the concave region defined by the gate pad 108 and the gate fingers 109.

[0192] A gate voltage is applied to the gate pad 108 and the gate fingers 109. The gate voltage may be 10 V or more and 50 V or less (for example, about 30 V). A source voltage is applied to the source pad 110. The source voltage may be a reference voltage (for example, a GND voltage).

[0193] Fig. 12 is an enlarged view of region XII shown in Fig. 11 and is an enlarged view for explaining the structure of first main surface 103 of SiC semiconductor layer 102. Fig. 13 is a cross-sectional view taken along line XIII-XIII shown in Fig. 12. Fig. 14 is a cross-sectional view taken along line XIV-XIV shown in Fig. 12.

[0194] 12 to 14, in this embodiment, the SiC semiconductor layer 102 is + The SiC semiconductor layer 102 has a layered structure including an n-type SiC semiconductor substrate 111 and an n-type SiC epitaxial layer 112. The SiC semiconductor substrate 111 forms the second main surface 104 of the SiC semiconductor layer 102.

[0195] The first main surface 103 of the SiC semiconductor layer 102 is formed by the SiC epitaxial layer 112. The second main surface 104 of the SiC semiconductor layer 102 may be a ground surface. The second main surface 104 of the SiC semiconductor layer 102 may have grinding marks.

[0196] The thickness of the SiC semiconductor substrate 111 may be equal to or greater than 1 μm and less than 1000 μm. The thickness of the SiC semiconductor substrate 111 may be equal to or greater than 5 μm. The thickness of the SiC semiconductor substrate 111 may be equal to or greater than 25 μm. The thickness of the SiC semiconductor substrate 111 may be equal to or greater than 50 μm. The thickness of the SiC semiconductor substrate 111 may be equal to or greater than 100 μm.

[0197] The thickness of the SiC semiconductor substrate 111 may be 700 μm or less. The thickness of the SiC semiconductor substrate 111 may be 500 μm or less. The thickness of the SiC semiconductor substrate 111 may be 400 μm or more. The thickness of the SiC semiconductor substrate 111 may be 300 μm or less.

[0198] The thickness of the SiC semiconductor substrate 111 may be 250 μm or less. The thickness of the SiC semiconductor substrate 111 may be 200 μm or less. The thickness of the SiC semiconductor substrate 111 may be 150 μm or less. The thickness of the SiC semiconductor substrate 111 may be 100 μm or less.

[0199] The thickness of the SiC semiconductor substrate 111 is preferably 150 μm or less. By reducing the thickness of the SiC semiconductor substrate 111, the resistance value can be reduced by shortening the current path.

[0200] The thickness of the SiC epitaxial layer 112 may be 1 μm or more and 100 μm or less. The thickness of the SiC epitaxial layer 112 may be 5 μm or more. The thickness of the SiC epitaxial layer 112 may be 10 μm or more.

[0201] The thickness of the SiC epitaxial layer 112 may be 50 μm or less. The thickness of the SiC epitaxial layer 112 may be 40 μm or less. The thickness of the SiC epitaxial layer 112 may be 30 μm or less.

[0202] The thickness of the SiC epitaxial layer 112 may be 20 μm or less. The thickness of the SiC epitaxial layer 112 is preferably 15 μm or less. The thickness of the SiC epitaxial layer 112 is preferably 10 μm or less.

[0203] The n-type impurity concentration of the SiC epitaxial layer 112 is equal to or lower than the n-type impurity concentration of the SiC semiconductor substrate 111. More specifically, the n-type impurity concentration of the SiC epitaxial layer 112 is lower than the n-type impurity concentration of the SiC semiconductor substrate 111.

[0204] The n-type impurity concentration of the SiC semiconductor substrate 111 is 1.0×10 18 cm -3 Over 1.0 x 10 21 cm -3 The n-type impurity concentration of the SiC epitaxial layer 112 may be 1.0×10 or less. 15 cm -3 Over 1.0 x 10 18 cm -3 In this embodiment, the SiC epitaxial layer 112 has a plurality of regions having different n-type impurity concentrations along the normal direction of the first main surface 103 of the SiC semiconductor layer 102.

[0205] More specifically, the SiC epitaxial layer 112 includes a high-concentration region 112a having a relatively high n-type impurity concentration, and a low-concentration region 112b having a lower n-type impurity concentration than the high-concentration region 112a. The high-concentration region 112a is formed in a region on the first main surface 103 side. The low-concentration region 112b is formed in a region on the SiC semiconductor substrate 111 side of the high-concentration region 112a.

[0206] The n-type impurity concentration of the high concentration region 112a is 1×10 16 cm -3 More than 1×10 18 cm -3 The n-type impurity concentration of the low concentration region 112b may be 1×10 15 cm -3 More than 1×10 16 cm -3 The thickness of the high concentration region 112a may be equal to or less than the thickness of the low concentration region 112b. More specifically, the thickness of the high concentration region 112a is less than the thickness of the low concentration region 112b.

[0207] A drain pad 113 serving as a second main surface electrode is connected to the second main surface 104 of the SiC semiconductor layer 102. The maximum voltage that can be applied between the source pad 110 and the drain pad 113 in the off state may be 1000 V or more and 10000 V or less.

[0208] The SiC semiconductor substrate 111 is formed as a drain region 114 of the MISFET. The SiC epitaxial layer 112 is formed as a drift region 115 of the MISFET.

[0209] In the active region 106, a p-type body region 116 is formed in the surface layer portion of the first main surface 103 of the SiC semiconductor layer 102. The p-type impurity concentration of the body region 116 is 1×10 17 cm -3 More than 1×10 20 cm -3 The body region 116 defines the active region 106.

[0210] In the active region 106, a plurality of gate trenches 121 are formed in a surface layer portion of the first main surface 103 of the SiC semiconductor layer 102. The plurality of gate trenches 121 are formed at intervals along an arbitrary first direction X. The plurality of gate trenches 121 are formed in strip shapes extending along a second direction Y intersecting the first direction X.

[0211] More specifically, the first direction X is a direction along the side surfaces 105B and 105D of the SiC semiconductor layer 102. The second direction Y is a direction perpendicular to the first direction X. The second direction Y is also a direction along the side surfaces 105A and 105C of the SiC semiconductor layer 102.

[0212] The gate trenches 121 are formed in a stripe pattern in plan view. In this embodiment, each gate trench 121 extends in a strip shape from the peripheral edge on one side (side surface 105B side) to the peripheral edge on the other side (side surface 105D side) of the first main surface 103 of the SiC semiconductor layer 102 in plan view.

[0213] Each gate trench 121 crosses an intermediate portion between a peripheral edge portion on one side of the first main surface 103 and a peripheral edge portion on the other side of the first main surface 103 in a plan view. One end of each gate trench 121 is located at a peripheral edge portion on one side of the first main surface 103 of the SiC semiconductor layer 102. The other end of each gate trench 121 is located at a peripheral edge portion on the other side of the first main surface 103 of the SiC semiconductor layer 102.

[0214] The first direction X may be set to the [11-20] direction ([-1-120] direction). In this case, each gate trench 121 may extend along the [11-20] direction. The first direction X may be set to the [-1100] direction ([1-100] direction) perpendicular to the [11-20] direction. In this case, each gate trench 121 may extend along the [-1100] direction ([1-100] direction).

[0215] Each gate trench 121 has a length on the order of millimeters (1 mm or longer). The length of the gate trench 121 is the length from the end of the connection portion between the gate trench 121 and the gate finger 109 to the opposite end in the cross section shown in FIG.

[0216] The length of each gate trench 121 may be 0.5 mm or more. In this embodiment, the length of each gate trench 121 is 1 mm or more and 10 mm or less (for example, 2 mm or more and 5 mm or less). The total length of one or more gate trenches 121 per unit area is 0.5 μm / μm. 2 More than 0.75μm / μm 2 It may be the following:

[0217] Each gate trench 121 integrally includes an active trench portion 121a and a contact trench portion 121b. The active trench portion 121a is a portion of the gate trench 121 formed in the active region 106. The contact trench portion 121b is a portion of the gate trench 121 drawn from the active trench portion 121a to the outer region 107.

[0218] Each gate trench 121 penetrates the body region 116 and reaches the SiC epitaxial layer 112. The bottom wall of each gate trench 121 is located within the SiC epitaxial layer 112. More specifically, the bottom wall of each gate trench 121 is located in a high concentration region 112a of the SiC epitaxial layer 112.

[0219] The depth of gate trench 121 may be 0.5 μm or more and 3 μm or less (for example, about 1 μm) in the normal direction to first main surface 103 of SiC semiconductor layer 102. The depth of gate trench 121 is preferably 0.5 μm or more and 1.0 μm or less.

[0220] The width in the first direction of the gate trench 121 may be 0.1 μm or more and 2 μm or less (for example, about 0.5 μm). The width in the first direction of the gate trench 121 is preferably 0.1 μm or more and 0.5 μm or less.

[0221] 13 and 14 , opening edge portion 124 of each gate trench 121 includes a curved portion 125 that curves inward of gate trench 121. Opening edge portion 124 of gate trench 121 is a corner that connects first main surface 103 of SiC semiconductor layer 102 and a sidewall of gate trench 121.

[0222] The electric field at the opening edge 124 of the gate trench 121 is dispersed along the curved portion 125. This makes it possible to alleviate the electric field concentration at the opening edge 124 of the gate trench 121.

[0223] In the surface layer of the body region 116, the region along the sidewall of the gate trench 121 contains n + The n-type source region 126 is formed. The n-type impurity concentration of the source region 126 is 1.0×10 18 cm -3 Over 1.0 x 10 21 cm -3 It may be the following:

[0224] A plurality of source regions 126 are formed along one sidewall and the other sidewall of the gate trench 121 in the first direction X. The plurality of source regions 126 are each formed in a strip shape extending along the second direction Y. The plurality of source regions 126 are formed in a stripe shape in a plan view.

[0225] A gate insulating layer 131 and a gate electrode layer 132 are formed in each gate trench 121. In Fig. 12, the gate insulating layer 131 and the gate electrode layer 132 are shown by hatching for clarity.

[0226] The gate insulating layer 131 may contain silicon oxide or other insulating films such as silicon nitride. The gate insulating layer 131 is formed in the form of a film along the inner wall surface of the gate trench 121 so as to define a recessed space within the gate trench 121.

[0227] The gate insulating layer 131 includes a first region 131a, a second region 131b, and a third region 131c. The first region 131a is formed along the sidewall of the gate trench 121. The second region 131b is formed along the bottom wall of the gate trench 121. The third region 131c is formed along the first main surface 103 of the SiC semiconductor layer 102.

[0228] The thickness T1 of the first region 131a is smaller than the thickness T2 of the second region 131b and the thickness T3 of the third region 131c. The ratio T2 / T1 of the thickness T2 of the second region 131b to the thickness T1 of the first region 131a may be equal to or greater than 2 and equal to or less than 5. The ratio T3 / T1 of the thickness T3 of the third region 131c to the thickness T1 of the first region 131a may be equal to or greater than 2 and equal to or less than 5.

[0229] The thickness T1 of the first region 131a may be 0.01 μm or more and 0.2 μm or less, the thickness T2 of the second region 131b may be 0.05 μm or more and 0.5 μm or less, and the thickness T3 of the third region 131c may be 0.05 μm or more and 0.5 μm or less.

[0230] By forming the first region 131a of the gate insulating layer 131 thin, it is possible to suppress an increase in carriers induced in the region near the sidewall of the gate trench 121 in the body region 116. This makes it possible to suppress an increase in channel resistance. By forming the second region 131b of the gate insulating layer 131 thick, it is possible to alleviate electric field concentration on the bottom wall of the gate trench 121.

[0231] By forming the third region 131c of the gate insulating layer 131 thick, it is possible to improve the breakdown voltage of the gate insulating layer 131 in the vicinity of the opening edge portion 124 of the gate trench 121. Furthermore, by forming the third region 131c thick, it is possible to prevent the third region 131c from being lost by an etching method.

[0232] This can prevent the first region 131a from being removed by etching due to the disappearance of the third region 131c, and as a result, the gate electrode layer 132 can be appropriately opposed to the SiC semiconductor layer 102 with the gate insulating layer 131 interposed therebetween.

[0233] The gate electrode layer 132 is embedded in the gate trench 121 with the gate insulating layer 131 sandwiched therebetween. More specifically, the gate electrode layer 132 is embedded in the gate trench 121 so as to fill a recessed space defined by the gate insulating layer 131. The gate electrode layer 132 is controlled by a gate voltage.

[0234] 13 and 14, the gate electrode layer 132 is formed in a wall shape extending along the normal direction of the first main surface 103 of the SiC semiconductor layer 102 in a cross-sectional view perpendicular to the direction in which the gate trench 121 extends.

[0235] The gate electrode layer 132 has an upper end portion located on the opening side of the gate trench 121. The upper end portion of the gate electrode layer 132 is formed in a curved shape recessed toward the bottom wall of the gate trench 121.

[0236] The cross-sectional area of ​​the gate electrode layer 132 (the cross-sectional area perpendicular to the direction in which the gate trench 121 extends) is 0.05 μm 2 More than 0.5μm 2 The cross-sectional area of ​​the gate electrode layer 132 is defined as the product of the depth of the gate electrode layer 132 and the width of the gate electrode layer 132 .

[0237] The depth of the gate electrode layer 132 is the distance from the upper end to the lower end of the gate electrode layer 132. The width of the gate electrode layer 132 is the width of the trench at the midpoint between the upper end and the lower end of the gate electrode layer 132. When the upper end is a curved surface (in this embodiment, a curved shape recessed downward), the position of the upper end of the gate electrode layer 132 is the midpoint in the depth direction on the upper surface of the gate electrode layer 132.

[0238] The gate electrode layer 132 includes p-type polysilicon doped with p-type impurities, which may include at least one of boron (B), aluminum (Al), indium (In), and gallium (Ga).

[0239] The p-type impurity concentration of the gate electrode layer 132 is equal to or higher than the p-type impurity concentration of the body region 116. More specifically, the p-type impurity concentration of the gate electrode layer 132 is higher than the p-type impurity concentration of the body region 116.

[0240] The p-type impurity concentration of the gate electrode layer 132 is 1×10 18 cm -3 More than 1×10 22 cm -3 The sheet resistance of the gate electrode layer 132 may be 10 Ω / □ or more and 500 Ω / □ or less (approximately 200 Ω / □ in this embodiment).

[0241] 14, a gate wiring layer 133 is formed in the outer region 107. The gate wiring layer 133 is electrically connected to the gate pad 108 and the gate finger 109.

[0242] The gate wiring layer 133 is formed on the first main surface 103 of the SiC semiconductor layer 102. More specifically, the gate wiring layer 133 is formed on the third region 131c of the gate insulating layer 131.

[0243] In this embodiment, the gate wiring layer 133 is formed along the gate fingers 109. The gate wiring layer 133 is formed along three side surfaces 105A, 105B, and 105D of the SiC semiconductor layer 102 so as to partition the active region 106 from three directions.

[0244] The gate wiring layer 133 is connected to the gate electrode layer 132 exposed from the contact trench portion 121b of each gate trench 121. In this embodiment, the gate wiring layer 133 is formed by an extension portion that is extended from the gate electrode layer 132 onto the first main surface 103 of the SiC semiconductor layer 102. An upper end portion of the gate wiring layer 133 is connected to an upper end portion of the gate electrode layer 132.

[0245] 13, a low resistance electrode layer 134 is formed on the gate electrode layer 132. The low resistance electrode layer 134 covers the upper end of the gate electrode layer 132 in the gate trench 121.

[0246] The low resistance electrode layer 134 includes a conductive material having a sheet resistance lower than the sheet resistance of the gate electrode layer 132. The sheet resistance of the low resistance electrode layer 134 may be 0.01 Ω / □ or more and 10 Ω / □ or less.

[0247] The current supplied into the gate trench 121 flows through the low-resistance electrode layer 134, which has a relatively low sheet resistance, and is transmitted to the entire gate electrode layer 132. This allows the entire gate electrode layer 132 (the entire active region 106) to quickly transition from the OFF state to the ON state, thereby suppressing delays in switching response.

[0248] In particular, in the case of the gate trench 121 having a length on the order of millimeters, it takes time for the current to propagate, but the delay in the switching response can be appropriately suppressed by using the low-resistance electrode layer 134. In other words, the low-resistance electrode layer 134 is formed as a current diffusion electrode layer that diffuses the current inside the gate trench 121.

[0249] Furthermore, as the cell structure becomes finer, the width, depth, cross-sectional area, etc. of the gate electrode layer 132 become smaller, which raises concerns about delays in switching response due to increased electrical resistance in the gate trench 121.

[0250] However, the low resistance electrode layer 134 allows the entire gate electrode layer 132 to transition quickly from the OFF state to the ON state, so that delays in switching response due to miniaturization can be appropriately suppressed.

[0251] The low-resistance electrode layer 134 is formed in a film shape. The low-resistance electrode layer 134 has a connection portion 134a that contacts the upper end of the gate electrode layer 132 and a non-connection portion 134b on the opposite side. The connection portion 134a and the non-connection portion 134b of the low-resistance electrode layer 134 may be formed in a curved shape following the upper end of the gate electrode layer 132. The connection portion 134a and the non-connection portion 134b of the low-resistance electrode layer 134 may take various forms.

[0252] The entire connecting portion 134a of the low-resistance electrode layer 134 may be located above the first main surface 103 of the SiC semiconductor layer 102. The entire connecting portion 134a of the low-resistance electrode layer 134 may be located below the first main surface 103 of the SiC semiconductor layer 102.

[0253] The connection portion 134a of the low-resistance electrode layer 134 may include a portion located above the first main surface 103 of the SiC semiconductor layer 102. The connection portion 134a of the low-resistance electrode layer 134 may include a portion located below the first main surface 103 of the SiC semiconductor layer 102.

[0254] For example, the central portion of the connection portion 134a of the low-resistance electrode layer 134 may be located below the first main surface 103 of the SiC semiconductor layer 102, and the peripheral portion of the connection portion 134a of the low-resistance electrode layer 134 may be located above the first main surface 103 of the SiC semiconductor layer 102.

[0255] The entire non-connected portion 134b of the low-resistance electrode layer 134 may be located above the first main surface 103 of the SiC semiconductor layer 102. The entire non-connected portion 134b of the low-resistance electrode layer 134 may be located below the first main surface 103 of the SiC semiconductor layer 102.

[0256] The non-connected portion 134b of the low-resistance electrode layer 134 may include a portion located above the first main surface 103 of the SiC semiconductor layer 102. The non-connected portion 134b of the low-resistance electrode layer 134 may include a portion located below the first main surface 103 of the SiC semiconductor layer 102.

[0257] For example, the central portion of the non-connected portion 134b of the low-resistance electrode layer 134 may be located below the first main surface 103 of the SiC semiconductor layer 102, and the peripheral portion of the non-connected portion 134b of the low-resistance electrode layer 134 may be located above the first main surface 103 of the SiC semiconductor layer 102.

[0258] The low resistance electrode layer 134 has an edge 134c that contacts the gate insulating layer 131. The edge 134c of the low resistance electrode layer 134 contacts a corner of the gate insulating layer 131 that connects the first region 131a and the second region 131b.

[0259] The edge portion 134c of the low-resistance electrode layer 134 is formed in a region closer to the first main surface 103 of the SiC semiconductor layer 102 than the bottom of the source region 126. That is, the edge portion 134c of the low-resistance electrode layer 134 is formed in a region closer to the first main surface 103 of the SiC semiconductor layer 102 than the boundary region between the body region 116 and the source region 126.

[0260] Therefore, the edge 134c of the low resistance electrode layer 134 faces the source region 126 across the gate insulating layer 131. The edge 134c of the low resistance electrode layer 134 does not face the body region 116 across the gate insulating layer 131.

[0261] This can suppress the formation of a current path in the region between the low-resistance electrode layer 134 and the body region 116 in the gate insulating layer 131. The current path can be formed by an undesired diffusion of the electrode material of the low-resistance electrode layer 134 with respect to the gate insulating layer 131.

[0262] In particular, the design of connecting the edge 134c of the low-resistance electrode layer 134 to the third region 131c (the corner of the gate insulating layer 131) of the relatively thick gate insulating layer 131 is effective in reducing the risk of forming a current path.

[0263] With respect to the normal direction of the first main surface 103 of the SiC semiconductor layer 102, the thickness TR of the low-resistance electrode layer 134 is not more than the thickness TG of the gate electrode layer 132 (TR ≦ TG). Preferably, the thickness TR of the low-resistance electrode layer 134 is less than the thickness TG of the gate electrode layer 132 (TR < TG). More specifically, preferably, the thickness TR of the low-resistance electrode layer 134 is not more than half of the thickness TG of the gate electrode layer 132 (TR ≦ TG / 2).

[0264] The ratio TR / TG of the thickness TR of the low-resistance electrode layer 134 to the thickness TG of the gate electrode layer 132 is 0.01 or more and 1 or less. The thickness TG of the gate electrode layer 132 may be 0.5 μm or more and 3 μm or less. The thickness TR of the low-resistance electrode layer 134 may be 0.01 μm or more and 3 μm or less.

[0265] Referring to FIG. 14, in this form, the low-resistance electrode layer 134 also covers the upper end portion of the gate wiring layer 133. The portion of the low-resistance electrode layer 134 covering the upper end portion of the gate wiring layer 133 is integrally formed with the portion of the low-resistance electrode layer 134 covering the upper end portion of the gate electrode layer 132. Thereby, the low-resistance electrode layer 134 covers the entire area of the gate electrode layer 132 and the entire area of the gate wiring layer 133.

[0266] Therefore, the current supplied from the gate pad 108 and the gate finger 109 to the gate wiring layer 133 flows through the low resistance electrode layer 134 having a relatively low sheet resistance, and is transmitted to the entire gate electrode layer 132 and gate wiring layer 133 .

[0267] This allows the entire gate electrode layer 132 (the entire active region 106) to be quickly transitioned from an OFF state to an ON state via the gate wiring layer 133, thereby suppressing delays in switching response.

[0268] In particular, in the case of the gate trench 121 having a length on the order of millimeters, the low resistance electrode layer 134 covering the upper end of the gate wiring layer 133 can appropriately suppress delay in switching response.

[0269] The low-resistance electrode layer 134 includes a polycide layer. The polycide layer is formed by silicidating with a metal material a portion that forms a surface layer of the gate electrode layer 132. More specifically, the polycide layer is made of a p-type polycide layer containing p-type impurities added to the gate electrode layer 132 (p-type polysilicon).

[0270] In this embodiment, the polycide layer has a resistivity of 10 μΩ·cm or more and 110 μΩ·cm or less. More specifically, the polycide layer contains at least one of TiSi, TiSi2, NiSi, CoSi, CoSi2, MoSi2, and WSi2.

[0271] When the low-resistance electrode layer 134 is formed on the p-type polysilicon, the sheet resistance in the gate trench 121 is equal to or less than the sheet resistance of the gate electrode layer 132 (p-type polysilicon) alone. The sheet resistance in the gate trench 121 is preferably equal to or less than the sheet resistance of n-type polysilicon doped with n-type impurities.

[0272] The sheet resistance in the gate trench 121 is approximated to the sheet resistance of the low resistance electrode layer 134. That is, the sheet resistance in the gate trench 121 may be 0.01 Ω / □ or more and 10 Ω / □ or less. The sheet resistance in the gate trench 121 is preferably less than 10 Ω / □.

[0273] The results of investigating the resistivity of the polycide layer are shown in Figure 15. Figure 15 is a graph showing the relationship between the resistivity of the polycide and the formation temperature. In Figure 15, the vertical axis represents the resistivity [μΩ·cm], and the horizontal axis represents the polycide formation temperature [°C].

[0274] 15, the resistivity decreases in the order of MoSi2, WSi2, NiSi, CoSi2, and TiSi2. Therefore, the priority of materials used as the polycide layer increases in the order of MoSi2, WSi2, NiSi, CoSi2, and TiSi2.

[0275] Among these species, NiSi, CoSi2 and TiSi2 are particularly suitable as the polycide layer forming the low resistance electrode layer 134 because they have relatively small resistivity and temperature dependency.

[0276] Furthermore, as a result of the inventors' testing, when TiSi2 was used as the material for the low-resistance electrode layer 134, an increase in the leakage current between the gate and source was observed when a low electric field was applied. In contrast, when CoSi2 was used, no increase in the leakage current between the gate and source was observed when a low electric field was applied. Considering that NiSi has issues with heat resistance compared to CoSi2, CoSi2 is most preferable as the polycide layer that forms the low-resistance electrode layer 134.

[0277] 12 and 13, a plurality of source trenches 141 are formed in the first main surface 103 of the SiC semiconductor layer 102 in the active region 106. Each source trench 141 is formed in a region between two gate trenches 121 adjacent to each other.

[0278] The source trenches 141 are each formed in a band shape extending along the second direction Y. The source trenches 141 are formed in a stripe shape in a plan view. The pitch between the centers of adjacent source trenches 141 in the first direction X may be 1.5 μm or more and 3 μm or less.

[0279] Each source trench 141 penetrates the body region 116 and reaches the SiC epitaxial layer 112. The bottom wall of each source trench 141 is located within the SiC epitaxial layer 112. More specifically, the bottom wall of each source trench 141 is located in a high concentration region 112a of the SiC epitaxial layer 112.

[0280] The depth of source trench 141 may be approximately equal to the depth of gate trench 121. The depth of source trench 141 may be equal to or greater than the depth of gate trench 121. The depth of source trench 141 in the normal direction to first main surface 103 of SiC semiconductor layer 102 may be equal to or greater than 0.5 μm and equal to or less than 10 μm (for example, about 1 μm).

[0281] The first direction width of source trench 141 may be approximately equal to the first direction width of gate trench 121. The first direction width of source trench 141 may be equal to or greater than the first direction width of gate trench 121. The first direction width of source trench 141 may be equal to or greater than 0.1 μm and equal to or less than 2 μm (for example, approximately 0.5 μm).

[0282] Opening edge portion 142 of each source trench 141 includes a curved portion 143 that curves inward of source trench 141. Opening edge portion 142 of source trench 141 is a corner that connects first main surface 103 of SiC semiconductor layer 102 and the sidewall of source trench 141.

[0283] The electric field at the opening edge 142 of the source trench 141 is dispersed along the curved portion 143. This allows the electric field concentration at the opening edge 142 of the source trench 141 to be alleviated.

[0284] In the SiC semiconductor layer 102, the region along the sidewall of the source trench 141 is + The p-type contact region 144 is formed with a p-type impurity concentration of 1.0×10 18 cm -3 Over 1.0 x 10 21 cm -3 The contact regions 144 may be formed on one side surface and the other side surface of one source trench 141.

[0285] The contact regions 144 are formed at intervals along the second direction Y. The contact regions 144 are formed at intervals along the first direction X from the gate trench 121.

[0286] A p-type deep well region 145 is formed in the SiC semiconductor layer 102 in a region along the inner wall of the source trench 141. The deep well region 145 is also referred to as a breakdown voltage holding region. The deep well region 145 is formed in a strip shape extending along the source trench 141. The deep well region 145 extends along the inner wall of the source trench 141.

[0287] 12 and 14, more specifically, the deep well region 145 extends along the sidewall of the source trench 141 and covers the bottom wall of the source trench 141 through the edge portion. The deep well region 145 is continuous with the body region 116 at the sidewall of the source trench 141.

[0288] The deep well region 145 has a bottom located on the second main surface 104 side of the SiC semiconductor layer 102 relative to the bottom wall of the gate trench 121. The deep well region 145 is formed in the high concentration region 112a of the SiC epitaxial layer 112.

[0289] The p-type impurity concentration of the deep well region 145 may be approximately equal to the p-type impurity concentration of the body region 116. The p-type impurity concentration of the deep well region 145 may be greater than the p-type impurity concentration of the body region 116. The p-type impurity concentration of the deep well region 145 may be less than the p-type impurity concentration of the body region 116.

[0290] The p-type impurity concentration of the deep well region 145 may be equal to or lower than the p-type impurity concentration of the contact region 144. The p-type impurity concentration of the deep well region 145 may be lower than the p-type impurity concentration of the contact region 144. The p-type impurity concentration of the deep well region 21 is 1.0×10 17 cm -3 Over 1.0 x 10 19 cm -3 It may be the following:

[0291] 12 and 14, a p-type peripheral deep well region 148 is formed in the outer region 107. The peripheral deep well region 148 is electrically connected to the deep well region 145.

[0292] The peripheral deep well region 148 has the same potential as the deep well region 145. In this embodiment, the peripheral deep well region 148 is formed integrally with the deep well region 145.

[0293] More specifically, the peripheral deep well region 148 extends in a strip shape along the periphery of the active region 106 in the outer region 107. More specifically, the peripheral deep well region 148 is formed in an endless shape (a square ring shape in this form) surrounding the active region 106.

[0294] The peripheral deep well region 148 is formed in the outer region 107 in a surface portion of the first main surface 103 of the SiC semiconductor layer 102 and in a region along the inner wall of the contact trench portion 121b of the gate trench 121. The peripheral deep well region 148 extends along the side wall of the contact trench portion 121b, passes through the edge portion, and covers the bottom wall of the contact trench portion 121b.

[0295] In plan view, the peripheral deep well region 148 overlaps the gate wiring layer 133. That is, the peripheral deep well region 148 faces the gate wiring layer 133 with the gate insulating layer 131 (third region 131c) interposed therebetween.

[0296] The peripheral deep well region 148 has a bottom located on the second main surface 104 side of the SiC semiconductor layer 102 relative to the bottom wall of the contact trench portion 121b of the gate trench 121. The peripheral deep well region 148 is formed in the high concentration region 112a of the SiC epitaxial layer 112.

[0297] The peripheral deep well region 148 includes a lead-out portion 148a that is led out from the outer region 107 to the peripheral portion of the active region 106 in a plan view. The lead-out portion 148a of the peripheral deep well region 148 covers the end of the source trench 141 that is located on the outer region 107 side in a plan view.

[0298] The leading portion 148a of the peripheral deep well region 148 covers the inner wall of the active trench portion 121a at the periphery of the active region 106. The leading portion 148a of the peripheral deep well region 148 extends along the sidewall of the active trench portion 121a and covers the bottom wall of the active trench portion 121a through the edge portion. The leading portion 148a of the peripheral deep well region 148 is continuous with the deep well region 145 in the active region 106.

[0299] The drawn-out portion 148a of the peripheral deep well region 148 has a bottom portion located on the second main surface 104 side of the SiC semiconductor layer 102 relative to the bottom wall of the active trench portion 121a of the gate trench 121. The drawn-out portion 148a of the peripheral deep well region 148 is formed in the high-concentration region 112a of the SiC epitaxial layer 112.

[0300] The p-type impurity concentration of the peripheral deep well region 148 may be approximately equal to the p-type impurity concentration of the body region 116. The p-type impurity concentration of the peripheral deep well region 148 may be greater than the p-type impurity concentration of the body region 116. The p-type impurity concentration of the peripheral deep well region 148 may be less than the p-type impurity concentration of the body region 116.

[0301] The p-type impurity concentration of the peripheral deep well region 148 may be approximately equal to the p-type impurity concentration of the deep well region 145. The p-type impurity concentration of the peripheral deep well region 148 may be greater than the p-type impurity concentration of the deep well region 145. The p-type impurity concentration of the peripheral deep well region 148 may be less than the p-type impurity concentration of the deep well region 145.

[0302] The p-type impurity concentration of the peripheral deep well region 148 may be equal to or less than the p-type impurity concentration of the contact region 144. The p-type impurity concentration of the peripheral deep well region 148 may be less than the p-type impurity concentration of the contact region 144. The p-type impurity concentration of the peripheral deep well region 148 may be less than 1.0×10 17 cm -3 Over 1.0 x 10 19 cm -3 It may be the following:

[0303] A source insulating layer 146 and a source electrode layer 147 are formed in each source trench 141. In Fig. 12, the source insulating layer 146 and the source electrode layer 147 are shown by hatching for clarity.

[0304] The source insulating layer 146 may contain silicon oxide. The source insulating layer 146 is formed in the form of a film along the inner wall surface of the source trench 141 so as to define a recessed space within the source trench 141.

[0305] The source insulating layer 146 includes a first region 146a and a second region 146b. The first region 146a is formed along the sidewall of the source trench 141. The second region 146b is formed along the bottom wall of the source trench 141. A thickness T11 of the first region 146a is smaller than a thickness T12 of the second region 146b.

[0306] The ratio T12 / T11 of the thickness T12 of the second region 146b to the thickness T11 of the first region 146a may be equal to or greater than 2 and equal to or less than 5. The thickness T11 of the first region 146a may be equal to or greater than 0.01 μm and equal to or less than 0.2 μm. The thickness T12 of the second region 146b may be equal to or greater than 0.05 μm and equal to or less than 0.5 μm.

[0307] The thickness T11 of the first region 146a may be approximately equal to the thickness T1 of the first region 131a of the gate insulating layer 131. The thickness T12 of the second region 146b may be approximately equal to the thickness T2 of the second region 131b of the gate insulating layer 131.

[0308] Source insulating layer 146 exposes opening edge 142 of source trench 141. More specifically, source insulating layer 146 exposes source region 126 and contact region 144 from opening edge 142 of source trench 141.

[0309] More specifically, first region 146a of source insulating layer 146 has an upper end portion located on the opening side of source trench 141. The upper end portion of first region 146a is formed below first main surface 103 of SiC semiconductor layer 102.

[0310] The upper end of the first region 146a exposes the sidewall of the source trench 141 on the opening side of the source trench 141. In this way, the first region 146a exposes the source region 126 and the contact region 144 from the opening edge portion 142 of the source trench 141.

[0311] The source electrode layer 147 is embedded in the source trench 141 with the source insulating layer 146 sandwiched therebetween. More specifically, the source electrode layer 147 is embedded in the source trench 141 so as to fill the recessed space defined by the source insulating layer 146. The source electrode layer 147 is controlled by a source voltage.

[0312] The source electrode layer 147 has an upper end located on the opening side of the source trench 141. The upper end of the source electrode layer 147 is formed below the first main surface 103 of the SiC semiconductor layer 102. The upper end of the source electrode layer 147 may be formed flush with the upper end of the source insulating layer 146.

[0313] The upper end of the source electrode layer 147 may protrude above the upper end of the source insulating layer 146. The upper end of the source electrode layer 147 may be located below the upper end of the source insulating layer 146. The thickness of the source electrode layer 147 may be 0.5 μm or more and 10 μm or less (for example, about 1 μm).

[0314] The source electrode layer 147 preferably contains polysilicon, which has properties similar to those of SiC, thereby reducing stress generated in the SiC semiconductor layer 102. The source electrode layer 147 preferably contains p-type polysilicon doped with p-type impurities. In this case, the source electrode layer 147 can be formed simultaneously with the gate electrode layer 132.

[0315] The p-type impurity concentration of the source electrode layer 147 is equal to or higher than the p-type impurity concentration of the body region 116. More specifically, the p-type impurity concentration of the source electrode layer 147 is higher than the p-type impurity concentration of the body region 116. The p-type impurity of the source electrode layer 147 may include at least one of boron (B), aluminum (Al), indium (In), and gallium (Ga).

[0316] The p-type impurity concentration of the source electrode layer 147 is 1×10 18 cm -3 More than 1×10 22 cm -3 The sheet resistance of the source electrode layer 147 may be 10 Ω / □ or more and 500 Ω / □ or less (approximately 200 Ω / □ in this embodiment).

[0317] The p-type impurity concentration of the source electrode layer 147 may be approximately equal to the p-type impurity concentration of the gate electrode layer 132. The sheet resistance of the source electrode layer 147 may be approximately equal to the sheet resistance of the gate electrode layer 132.

[0318] The source electrode layer 147 may contain n-type polysilicon instead of p-type polysilicon, or may contain at least one of tungsten, aluminum, copper, an aluminum alloy, or a copper alloy instead of p-type polysilicon.

[0319] As described above, the semiconductor device 101 has a trench gate structure 151 and a trench source structure 152. The trench gate structure 151 includes a gate trench 121, a gate insulating layer 131, a gate electrode layer 132, and a low-resistance electrode layer 134. The trench source structure 152 includes a source trench 141, a source insulating layer 146, and a source electrode layer 147.

[0320] 13 and 14 , an interlayer insulating layer 153 is formed on first main surface 103 of SiC semiconductor layer 102. Interlayer insulating layer 153 covers trench gate structure 151 in active region 106 and gate wiring layer 133 in outer region 107.

[0321] The interlayer insulating layer 153 may contain silicon oxide or silicon nitride. A gate contact hole 154 and a source contact hole 155 are formed in the interlayer insulating layer 153.

[0322] The gate contact hole 154 exposes the gate wiring layer 133 (low-resistance electrode layer 134) in the outer region 107. The source contact hole 155 exposes the source region 126, the contact region 144, and the trench source structure 152 in the active region 106. A gate pad 108, a gate finger 109, and a source pad 110 are formed on the interlayer insulating layer 153.

[0323] The gate finger 109 extends from above the interlayer insulating layer 153 into the gate contact hole 154. The gate finger 109 is electrically connected to the low-resistance electrode layer 134 in the gate contact hole 154. This allows an electrical signal from the gate pad 108 to be transmitted to the gate electrode layer 132 via the low-resistance electrode layer 134, which has a relatively low resistance value.

[0324] The source pad 110 extends from above the interlayer insulating layer 153 into the source contact hole 155. Within the source contact hole 155, the source pad 110 is electrically connected to the source region 126, the contact region 144, and the source electrode layer 147. The source electrode layer 147 may be formed by utilizing a portion of the source pad 110.

[0325] Fig. 16 is a graph for explaining sheet resistance. In Fig. 16, the vertical axis represents sheet resistance [Ω / □], and the horizontal axis represents items. Fig. 16 shows a first bar graph L1, a second bar graph L2, and a third bar graph L3.

[0326] The first bar graph L1 represents the sheet resistance of n-type polysilicon. The second bar graph L2 represents the sheet resistance of p-type polysilicon. The third bar graph L3 represents the sheet resistance when a low-resistance electrode layer 134 is formed on the p-type polysilicon. Here, the low-resistance electrode layer 134 contains TiSi2 (p-type titanium silicide).

[0327] Referring to the first bar graph L1, the sheet resistance of the n-type polysilicon was 10 Ω / □. Referring to the second bar graph L2, the sheet resistance of the p-type polysilicon was 200 Ω / □. Referring to the third bar graph L3, the sheet resistance when the low resistance electrode layer 134 was formed on the p-type polysilicon was 2 Ω / □.

[0328] P-type polysilicon has a work function different from that of n-type polysilicon, and simply burying p-type polysilicon in the gate trench 121 can increase the gate threshold voltage Vth by about 1V.

[0329] However, p-type polysilicon has a sheet resistance several tens of times (here, 20 times) higher than that of n-type polysilicon. Therefore, when p-type polysilicon is used as the material for gate electrode layer 132, the energy loss increases significantly as the parasitic resistance in gate trench 121 (hereinafter simply referred to as "gate resistance") increases.

[0330] In contrast, in a structure having a low-resistance electrode layer 134 on p-type polysilicon, the sheet resistance can be reduced to 1 / 100 or less compared to a structure without the low-resistance electrode layer 134. In a structure having the low-resistance electrode layer 134, the sheet resistance can be reduced to 1 / 5 or less compared to a gate electrode layer 132 including n-type polysilicon.

[0331] As described above, according to the semiconductor device 101, a trench gate structure 151 is formed in which the gate electrode layer 132 is embedded in the gate trench 121 with the gate insulating layer 131 sandwiched therebetween. In this trench gate structure 151, the gate electrode layer 132 is covered with the low-resistance electrode layer 134 in the limited space of the gate trench 121.

[0332] The gate electrode layer 132 includes p-type polysilicon, which can increase the gate threshold voltage Vth. The low-resistance electrode layer 134 includes a conductive material having a sheet resistance lower than that of p-type polysilicon.

[0333] This reduces the gate resistance, which in turn allows current to be efficiently spread along the trench gate structure 151, thereby reducing the switching delay.

[0334] In particular, the structure in which the gate electrode layer 132 is covered with the low-resistance electrode layer 134 eliminates the need to increase the p-type impurity concentration in the body region 116. Therefore, the gate threshold voltage Vth can be increased while preventing an increase in channel resistance.

[0335] Furthermore, in the semiconductor device 101, the gate wiring layer 133 is covered with the low resistance electrode layer 134 in the outer region 107. This also makes it possible to reduce the gate resistance of the gate wiring layer 133.

[0336] In particular, in a structure in which the gate electrode layer 132 and the gate wiring layer 133 are covered with the low-resistance electrode layer 134, current can be efficiently diffused along the trench gate structure 151. Therefore, switching delay can be appropriately reduced.

[0337] 17A to 17L are cross-sectional views showing an example of a method for manufacturing the semiconductor device 101 shown in Fig. 11. Fig. 17A to 17L are cross-sectional views of a portion corresponding to Fig. 12.

[0338] Referring to FIG. 17A, first, + A molded SiC semiconductor substrate 111 is prepared. Next, a SiC epitaxial layer 112 is formed on the main surface of the SiC semiconductor substrate 111. The SiC epitaxial layer 112 is formed by growing SiC from the main surface of the SiC semiconductor substrate 111 by epitaxial growth.

[0339] In this embodiment, the SiC epitaxial layer 112 having the high concentration region 112a and the low concentration region 112b is formed, whereby the SiC semiconductor layer 102 including the SiC semiconductor substrate 111 and the SiC epitaxial layer 112 is formed.

[0340] Next, a p-type body region 116 is formed in a surface layer portion of the first main surface 103 of the SiC semiconductor layer 102. The body region 116 is formed by introducing a p-type impurity into the first main surface 103 of the SiC semiconductor layer 102.

[0341] The body region 116 may be formed in a surface layer portion of the first main surface 103 of the SiC semiconductor layer 102 by ion implantation using an ion implantation mask (not shown). The body region 116 defines the active region 106.

[0342] Next, referring to FIG. 17B, n + In this case, an n-type source region 126 is formed. The source region 126 is formed by introducing n-type impurities into the surface layer portion of the body region 116. The source region 126 may be formed in the surface layer portion of the body region 116 by ion implantation using an ion implantation mask 161.

[0343] Next, referring to FIG. 17C, p + A p-type contact region 144 is formed by introducing a p-type impurity into the surface portion of the body region 116. The contact region 144 may be formed in the surface portion of the body region 116 by ion implantation using an ion implantation mask 162.

[0344] 17D, a mask 163 having a predetermined pattern is formed on first main surface 103 of SiC semiconductor layer 102. Mask 163 has a plurality of openings 164 that expose regions where gate trench 121 and source trench 141 are to be formed.

[0345] Next, unnecessary portions of the SiC semiconductor layer 102 are removed. The unnecessary portions of the SiC semiconductor layer 102 may be removed by an etching method (for example, a wet etching method) using the mask 163. This forms the gate trench 121 and the source trench 141. Thereafter, the mask 163 is removed.

[0346] Next, deep well regions 145 are formed in the SiC semiconductor layer 102 in regions along the inner walls of the source trenches 141. The deep well regions 145 may be formed in the SiC semiconductor layer 102 by ion implantation using an ion implantation mask (not shown).

[0347] In addition, in the outer region 107, a peripheral deep well region 148 is formed in a surface portion of the first main surface 103 of the SiC semiconductor layer 102 and in a region along the inner wall of the contact trench portion 121b of the gate trench 121. In this process, the peripheral deep well region 148 is formed, including a lead-out portion 148a led out from the outer region 107 to the peripheral portion of the active region 106.

[0348] The peripheral deep well region 148 may be formed in the SiC semiconductor layer 102 by ion implantation using an ion implantation mask (not shown). Part or all of the peripheral deep well region 148 may be formed simultaneously with the deep well region 145 using the process for forming the deep well region 145. Part of the peripheral deep well region 148 may be formed simultaneously with the body region 116 using the process for forming the body region 116.

[0349] 17E, the SiC semiconductor layer 102 is subjected to an annealing treatment. The annealing treatment may be a high-temperature hydrogen annealing treatment. The annealing temperature may be 1400° C. or higher.

[0350] As a result, a curved portion 125 is formed at the opening edge 124 of the gate trench 121. Also, a curved portion 143 is formed at the opening edge 142 of the source trench 141.

[0351] 17F, base insulating layer 165, which serves as a base for gate insulating layer 131 and source insulating layer 146, is formed to cover first main surface 103 of SiC semiconductor layer 102. Base insulating layer 165 may be formed by a CVD (chemical vapor deposition) method. Base insulating layer 165 may contain silicon oxide.

[0352] In this step, the base insulating layer 165 is formed so that the portions covering the sidewalls of the gate trench 121 and the sidewalls of the source trench 141 are thinner than the other portions.

[0353] The insulating base layer 165 having such a configuration is formed by adjusting predetermined conditions such as gas flow rate, gas species, gas ratio, and gas supply time in the CVD method. The insulating base layer 165 may be formed by an oxidation treatment method instead of the CVD method. The oxidation treatment method may be a thermal oxidation treatment method or a wet oxidation treatment method.

[0354] Next, referring to FIG. 17G, a base conductor layer 166 serving as a base for gate electrode layer 132, gate wiring layer 133, and source electrode layer 147 is formed on first main surface 103 of SiC semiconductor layer .

[0355] The base conductor layer 166 includes p-type polysilicon doped with p-type impurities. The base conductor layer 166 may be formed by a CVD method. The CVD method may be a low pressure CVD (LP-CVD) method.

[0356] 17H, unnecessary portions of base conductor layer 166 are removed by etching (e.g., wet etching) using a mask (not shown) having a predetermined pattern.

[0357] This mask (not shown) covers the region where gate wiring layer 133 is to be formed. Unnecessary portions of base conductor layer 166 are removed until at least the portion of base insulating layer 165 that covers first main surface 103 of SiC semiconductor layer 102 is exposed. As a result, gate electrode layer 132, gate wiring layer 133, and source electrode layer 147 are formed.

[0358] 17G to 17H are separately performed for the electrode material of the source electrode layer 147 to form the source electrode layer 147. When the source electrode layer 147 is formed by a part of the source pad 110, the source electrode layer 147 is formed when the source pad 110 is formed.

[0359] 17I, a metal material layer 167 is formed on the gate electrode layer 132. In this embodiment, the metal material layer 167 is formed on the first main surface 103 of the SiC semiconductor layer 102 so as to collectively cover the gate electrode layer 132 and the source electrode layer 147.

[0360] The metal material layer 167 includes a metal material that can be polycide-formed with p-type polysilicon, and may include at least one of Mo, W, Ni, Co, and Ti.

[0361] Next, a p-type polycide layer is formed on the surface layer of the gate electrode layer 132 and the surface layer of the gate wiring layer 133. In this embodiment, a p-type polycide layer is also formed on the surface layer of the source electrode layer 147.

[0362] The p-type polycide layer is formed by polycide-forming the surface portions of the gate electrode layer 132, the gate wiring layer 133, and the source electrode layer 147 through heat treatment of the metal material layer 167. The heat treatment of the metal material layer 167 may be performed by RTA (Rapid Thermal Annealing).

[0363] This forms a p-type polycide containing at least one of TiSi, TiSi2, NiSi, CoSi, CoSi2, MoSi2, and WSi2 depending on the metal material of the metal material layer 167. The low resistance electrode layer 134 is formed by this p-type polycide layer.

[0364] 17J, the unreacted portion of the metal material layer 167 that has not bonded to the p-type polysilicon is removed. The unreacted portion of the metal material layer 167 may be removed by an etching method (for example, a wet etching method).

[0365] When the low-resistance electrode layer 134 (p-type polycide) contains at least one of TiSi and CoSi, after the unreacted portion of the metal material layer 167 is removed, the low-resistance electrode layer 134 may be subjected to a heat treatment as needed.

[0366] The heat treatment for the low resistance electrode layer 134 may be an RTA method, which reforms TiSi to TiSi2 and CoSi to CoSi2, thereby achieving a low resistance.

[0367] 17K, an interlayer insulating layer 153 is formed on the first main surface 103 of the SiC semiconductor layer 102. The interlayer insulating layer 153 is formed on the first main surface 103 of the SiC semiconductor layer 102 so as to cover the trench gate structure 151 and the gate wiring layer 133. The interlayer insulating layer 153 includes silicon oxide or silicon nitride. The interlayer insulating layer 153 may be formed by a CVD method.

[0368] Next, a mask 168 having a predetermined pattern is formed on the interlayer insulating layer 153. The mask 168 has a plurality of openings 169 that expose regions where the gate contact holes 154 and the source contact holes 155 are to be formed.

[0369] Next, unnecessary portions of the interlayer insulating layer 153 are removed. The unnecessary portions of the interlayer insulating layer 153 may be removed by an etching method (e.g., dry etching method) using the mask 168. As a result, the gate contact hole 154 and the source contact hole 155 are formed.

[0370] 17L, gate pad 108, gate fingers 109, and source pad 110 are formed on interlayer insulating layer 153. Gate pad 108, gate fingers 109, and source pad 110 are formed using a mask (not shown) having a predetermined pattern. In addition, drain pad 113 is formed on second main surface 104 of SiC semiconductor layer 102. Through the steps including those described above, semiconductor device 101 is manufactured.

[0371] 18 is a cross-sectional view of a region corresponding to FIG. 13, showing a semiconductor device 171 according to an eighth embodiment of the present invention. In the following, structures corresponding to those described for the semiconductor device 101 are given the same reference numerals and will not be described again.

[0372] 18, in a semiconductor device 171, a gate insulating layer 131 includes a bulging portion 172 that bulges toward the inside of the gate trench 121 at an opening edge portion 124 of the gate trench 121. The bulging portion 172 is formed at a corner portion that connects the first region 131a and the third region 131c of the gate insulating layer 131.

[0373] The bulging portion 172 curves and protrudes inward of the gate trench 121. The bulging portion 172 narrows the opening of the gate trench 121 at an opening edge portion 124 of the gate trench 121.

[0374] The upper end of the gate electrode layer 132 has a constricted portion that is recessed along the bulging portion 172 of the gate insulating layer 131. The low-resistance electrode layer 134 covers the constricted portion (upper end) of the gate electrode layer 132. In this embodiment, the edge 134c of the low-resistance electrode layer 134 is in contact with the bulging portion 172 of the gate insulating layer 131.

[0375] The bulging portion 172 of the gate insulating layer 131 is formed in the process of Figure 17F described above by setting predetermined conditions for the CVD method (gas flow rate, gas type, gas ratio, gas supply time, etc.) taking into consideration the shape of the bulging portion 172 of the gate insulating layer 131.

[0376] As described above, according to the semiconductor device 171, the edge portion 134c of the low-resistance electrode layer 134 is in contact with the bulging portion 172 of the gate insulating layer 131. This makes it possible to appropriately suppress the formation of a current path in the region between the low-resistance electrode layer 134 and the SiC semiconductor layer 102.

[0377] Furthermore, according to the semiconductor device 171, in addition to the opening edge 124 of the gate trench 121 having the curved portion 125, a bulging portion 172 is formed at the opening edge 124 of the gate trench 121. This makes it possible to further improve the dielectric strength of the gate insulating layer 131 at the opening edge 124 of the gate trench 121.

[0378] 19 is a cross-sectional view of a region corresponding to FIG. 13, showing a semiconductor device 181 according to a ninth embodiment of the present invention. In the following, structures corresponding to those described for the semiconductor device 101 are given the same reference numerals and will not be described again.

[0379] 19, in a semiconductor device 181, an opening edge portion 124 of a gate trench 121 has an inclined portion 182 that slopes downward from a first main surface 103 of a SiC semiconductor layer 102 toward a sidewall of the gate trench 121.

[0380] The inclined portion 182 of the gate trench 121 allows the electric field to be dispersed along the inclined portion 182, thereby reducing the concentration of the electric field on the opening edge portion 124 of the gate trench 121.

[0381] The gate insulating layer 131 includes a bulging portion 183 that bulges into the gate trench 121 at the inclined portion 182 of the gate trench 121. The bulging portion 183 is formed at a corner that connects the first region 131a and the third region 131c of the gate insulating layer 131.

[0382] The bulging portion 183 curves and protrudes inward of the gate trench 121. The bulging portion 183 narrows the opening of the gate trench 121 at an opening edge portion 124 of the gate trench 121.

[0383] The upper end of the gate electrode layer 132 has a constricted portion that is recessed along the bulging portion 183 of the gate insulating layer 131. The low-resistance electrode layer 134 covers the constricted portion (upper end) of the gate electrode layer 132. In this embodiment, the edge 134c of the low-resistance electrode layer 134 is in contact with the bulging portion 183 of the gate insulating layer 131.

[0384] Opening edge 142 of source trench 141 has inclined portion 184 that slopes downward from first main surface 103 of SiC semiconductor layer 102 toward the side wall of source trench 141. Inclined portion 184 of source trench 141 allows the electric field to be dispersed along inclined portion 184, thereby mitigating electric field concentration at opening edge 142 of source trench 141.

[0385] 20A to 20C are cross-sectional views showing an example of a method for manufacturing the semiconductor device 181 shown in FIG.

[0386] First, referring to FIG. 20A, SiC semiconductor layer 102 having gate trench 121 and source trench 141 formed in first main surface 103 through the steps of FIGS. 17A to 17D is prepared.

[0387] 20B, first main surface 103 of SiC semiconductor layer 102 is subjected to a thermal oxidation treatment to form sacrificial oxide film 185. In this step, oxidation begins uniformly from both first main surface 103 of SiC semiconductor layer 102 and the sidewall of gate trench 121.

[0388] The oxide film growing from the first main surface 103 of the SiC semiconductor layer 102 and the oxide film growing from the sidewall of the gate trench 121 are integrated at the opening edge 124 of the gate trench 121.

[0389] The integration of these oxide films accelerates oxidation at the opening edge 124 of the gate trench 121. Then, a slope 182 is formed below the integrated oxide film at the opening edge 124 of the gate trench 121.

[0390] The oxide film growing from the first main surface 103 of the SiC semiconductor layer 102 and the oxide film growing from the sidewall of the source trench 141 are integrated at the opening edge 142 of the source trench 141 .

[0391] The integration of these oxide films accelerates oxidation at the opening edge 142 of the source trench 141. Then, a slope 184 is formed below the integrated oxide film at the opening edge 142 of the source trench 141.

[0392] Next, referring to Fig. 20C, the sacrificial oxide film 185 is removed. The sacrificial oxide film 185 may be removed by etching (for example, wet etching). Thereafter, the steps of Fig. 17F to Fig. 17L are performed in order.

[0393] 17F, the bulging portion 183 of the gate insulating layer 131 is formed by setting predetermined conditions for the CVD method (gas flow rate, gas type, gas ratio, gas supply time, etc.) in consideration of the shape of the bulging portion 183 of the gate insulating layer 131. Through the steps including those described above, the semiconductor device 181 is manufactured.

[0394] As described above, according to the semiconductor device 181, the edge portion 134c of the low-resistance electrode layer 134 is in contact with the bulging portion 183 of the gate insulating layer 131. This makes it possible to appropriately suppress the formation of a current path in the region between the low-resistance electrode layer 134 and the SiC semiconductor layer 102.

[0395] Furthermore, according to the semiconductor device 181, in addition to the opening edge 124 of the gate trench 121 having the inclined portion 182, a bulging portion 183 is formed at the opening edge 124 of the gate trench 121. This makes it possible to further improve the dielectric strength of the gate insulating layer 131 at the opening edge 124 of the gate trench 121.

[0396] In the present embodiment, an example has been described in which the gate insulating layer 131 having the bulging portion 183 is formed in the semiconductor device 181. However, the gate insulating layer 131 without the bulging portion 183 may be formed in the semiconductor device 181.

[0397] Fig. 21 is an enlarged view of a region corresponding to Fig. 12, showing a semiconductor device 191 according to a tenth embodiment of the present invention. Fig. 22 is a cross-sectional view taken along line XXII-XXII shown in Fig. 21. In the following, structures corresponding to those described for the semiconductor device 101 will be given the same reference numerals and will not be described again.

[0398] 21 and 22, in semiconductor device 191, outer gate trench 192 is formed in first main surface 103 of SiC semiconductor layer 102 in outer region 107. Outer gate trench 192 extends in outer region 107 in a strip shape.

[0399] The outer gate trench 192 is formed in a region directly below the gate finger 109 on the first main surface 103 of the SiC semiconductor layer 102. The outer gate trench 192 extends along the gate finger 109.

[0400] More specifically, the outer gate trench 192 is formed along three side surfaces 105A, 105B, and 105D of the SiC semiconductor layer 102 so as to partition the active region 106 from three directions. The outer gate trench 192 may be formed in an endless shape (for example, a rectangular ring shape) surrounding the active region 106.

[0401] The outer gate trench 192 communicates with the contact trench portion 121b of each gate trench 121. As a result, the outer gate trench 192 and the gate trench 121 are formed by a single trench.

[0402] A gate wiring layer 133 is buried in the outer gate trench 192. The gate wiring layer 133 is connected to the gate electrode layer 132 at the communicating portion between the outer gate trench 192 and the contact trench portion 121b.

[0403] In this embodiment, the low-resistance electrode layer 134 covers the upper end of the gate wiring layer 133 in the outer gate trench 192. Therefore, the low-resistance electrode layer 134 covering the gate electrode layer 132 and the low-resistance electrode layer 134 covering the gate wiring layer 133 are both located within a single trench.

[0404] In this embodiment, the peripheral deep well region 148 covers the inner wall of the outer gate trench 192 in the outer region 107. The peripheral deep well region 148 extends along the sidewall of the outer gate trench 192 and covers the bottom wall of the outer gate trench 192 through the edge portion.

[0405] That is, the peripheral deep well region 148, in the portion along the inner wall of the outer gate trench 192, faces the gate wiring layer 133 with the gate insulating layer 131 interposed therebetween. Also, the peripheral deep well region 148, in the portion along the inner wall of the gate trench 121, faces the gate electrode layer 132 with the gate insulating layer 131 interposed therebetween.

[0406] As described above, the semiconductor device 191 can also achieve the same effects as those described for the semiconductor device 101. Furthermore, according to the semiconductor device 191, it is not necessary to extend the gate wiring layer 133 onto the first main surface 103 of the SiC semiconductor layer 102.

[0407] This makes it possible to prevent the gate wiring layer 133 from facing the SiC semiconductor layer 102 across the gate insulating layer 131 at the opening edge portions of the gate trench 121 and the outer gate trench 192. As a result, it is possible to prevent electric field concentration at the opening edge portions of the gate trench 121.

[0408] 23 is a cross-sectional view of a region corresponding to FIG. 13, illustrating the structure of a semiconductor device 201 according to an eleventh embodiment of the present invention. In the following, structures corresponding to those described for the semiconductor device 101 are denoted by the same reference numerals, and descriptions thereof will be omitted.

[0409] 23 , in semiconductor device 201, each source trench 141 is formed deeper than gate trench 121. Therefore, the bottom wall of each source trench 141 is located on the second main surface 104 side of SiC semiconductor layer 102 relative to the bottom of gate trench 121. More specifically, the bottom wall of each source trench 141 is located in high concentration region 112a of SiC epitaxial layer 112.

[0410] The ratio of the depth of the source trench 141 to the depth of the gate trench 121 may be 1.5 or more. The ratio of the depth of the source trench 141 to the depth of the gate trench 121 is preferably 2 or more.

[0411] The depth of the gate trench 121 may be 0.5 μm or more and 3 μm or less (for example, about 1 μm). The depth of the source trench 141 may be 0.75 μm or more and 10 μm or less (for example, about 2 μm).

[0412] As in the semiconductor device 101, the deep well region 145 extends along the inner wall of the source trench 141 and has a bottom located on the second main surface 104 side of the SiC semiconductor layer 102 with respect to the bottom wall of the gate trench 121. The deep well region 145 is formed in the high concentration region 112a of the SiC epitaxial layer 112.

[0413] As described above, the semiconductor device 201 can also achieve the same effects as those described for the semiconductor device 101.

[0414] 24 is a plan view of a region corresponding to FIG. 12, and is a plan view for explaining the structure of a semiconductor device 211 according to a twelfth embodiment of the present invention. In the following, structures corresponding to those described for the semiconductor device 101 are given the same reference numerals, and descriptions thereof will be omitted.

[0415] Referring to Figure 24, in this embodiment, the gate trenches 121 are formed in a lattice shape that integrally includes a plurality of gate trenches 121 extending along the first direction X in a plan view and a plurality of gate trenches 121 extending along the second direction Y.

[0416] A plurality of cell regions 212 are partitioned in a matrix pattern on the first main surface 103 of the SiC semiconductor layer 102 by gate trenches 121. Each cell region 212 is formed in a quadrangular shape in a plan view. A source trench 141 is formed in each of the plurality of cell regions 212. The source trench 141 may be formed in a quadrangular shape in a plan view.

[0417] The cross-sectional view taken along line XIII-XIII in Fig. 24 is substantially the same as the cross-sectional view shown in Fig. 13. The cross-sectional view taken along line XIV-XIV in Fig. 24 is substantially the same as the cross-sectional view shown in Fig. 14.

[0418] As described above, the semiconductor device 211 can also achieve the same effects as those described for the semiconductor device 101. The gate trench 121 having a structure formed in a lattice shape instead of a stripe shape can also be applied to other forms.

[0419] 25 is a cross-sectional view of a region corresponding to FIG. 13, and is a plan view for explaining the structure of a semiconductor device 221 according to a thirteenth embodiment of the present invention. In the following, structures corresponding to those described for the semiconductor device 101 are given the same reference numerals, and descriptions thereof will be omitted.

[0420] Referring to FIG. 25, in a semiconductor device 221, a SiC semiconductor layer 102 has an n + Instead of the SiC semiconductor substrate 111, + The SiC semiconductor substrate 222 includes a p + The SiC semiconductor substrate 222 is formed as a collector region of an IGBT (Insulated Gate Bipolar Transistor).

[0421] The description of the semiconductor device 101 applies mutatis mutandis to the description of the semiconductor device 221, with the "source" of the MISFET being read as the "emitter" of the IGBT, and the "drain" of the MISFET being read as the "collector" of the IGBT.

[0422] That is, the source pad 110 and the source region 126 are respectively referred to as the emitter pad (110) and the emitter region (126), and the drain pad 113 and the drain region 114 are respectively referred to as the collector electrode layer (113) and the collector region (114).

[0423] As described above, the semiconductor device 221 can also achieve the same effects as those described for the semiconductor device 101.

[0424] 26 is a cross-sectional view of a region corresponding to FIG. 13, illustrating the structure of a semiconductor device 231 according to a fourteenth embodiment of the present invention. In the following, structures corresponding to those described for the semiconductor device 101 are denoted by the same reference numerals, and descriptions thereof will be omitted.

[0425] 26, contact region 144 is formed in deep well region 145 in a region along the bottom wall of source trench 141. Contact region 144 is exposed from the bottom wall of source trench 141.

[0426] The source insulating layer 146 is formed along the inner wall surface of the source trench 141 so as to selectively expose the contact region 144 from the bottom wall of the source trench 141 .

[0427] More specifically, the source insulating layer 146 includes a first portion 232 and a second portion 233. The first portion 232 covers the sidewall of the source trench 141. The second portion 233 partially covers the bottom wall of the source trench 141.

[0428] The second portion 233 is continuous with the first portion 232. The second portion 233 extends from a corner of the source trench 141 along the bottom wall so as to expose a central portion of the bottom wall of the source trench 141. The second portion 233 may be formed in an endless shape (annular shape) in a plan view.

[0429] As described above, the semiconductor device 231 can achieve the same effects as those described for the semiconductor device 101. Furthermore, the semiconductor device 231 forms a pn junction in the boundary region between the SiC semiconductor layer 102 and the deep well region 145.

[0430] Even if a depletion layer spreads from this pn junction along the bottom wall from the corner of the source trench 141, the source insulating layer 146 can increase the distance until the depletion layer reaches the source electrode layer 147. This makes it possible to suppress the occurrence of punch-through near the corner of the source trench 141.

[0431] 27 is a cross-sectional view of a region corresponding to FIG. 13, illustrating the structure of a semiconductor device 241 according to a fifteenth embodiment of the present invention. In the following, structures corresponding to those described for the semiconductor device 101 are denoted by the same reference numerals, and descriptions thereof will be omitted.

[0432] 27, deep well region 145 has formed therein exposed portion 242 that selectively exposes the bottom wall of source trench 141. Exposed portion 242 exposes the center portion of the bottom wall of source trench 141.

[0433] In this embodiment, the source insulating layer 146 includes a first portion 243 and a second portion 244. The first portion 243 covers the sidewall of the source trench 141. The second portion 244 partially covers the bottom wall of the source trench 141.

[0434] The second portion 244 is continuous with the first portion 243. The second portion 244 extends from a corner of the source trench 141 along the bottom wall so as to expose the center of the bottom wall of the source trench 141. The second portion 244 may be formed in an endless shape (annular shape) in a plan view.

[0435] The source electrode layer 147 forms a heterojunction with the SiC semiconductor layer 102 in the exposed portion 242 of the deep well region 145. This forms a heterojunction diode 245 in which the source electrode layer 147 serves as an anode and the SiC semiconductor layer 102 serves as a cathode. The source electrode layer 147 may contain a conductive material other than polysilicon as long as the heterojunction diode 245 is formed.

[0436] A body diode 246 is formed at the pn junction between the SiC semiconductor layer 102 and the body region 116. The junction barrier of the heterojunction diode 245 is smaller than the built-in potential of the body diode 246.

[0437] The junction barrier of the heterojunction diode 245 may be 1.0 eV or more and 1.5 eV or less, and the built-in potential of the body diode 246 may be 2.8 eV or more and 3.2 eV or less.

[0438] As described above, the semiconductor device 241 can achieve the same effects as those described for the semiconductor device 101. Furthermore, when a reverse bias voltage is applied to the semiconductor device 241, a current can be preferentially made to flow into the heterojunction diode 245.

[0439] This makes it possible to suppress the expansion of crystal defects in SiC in the SiC semiconductor layer 102. As a result, it is possible to suppress an increase in on-resistance while improving the short-circuit resistance and reducing the feedback capacitance Crss.

[0440] 28 is a cross-sectional view of a region corresponding to FIG. 13, illustrating the structure of a semiconductor device 251 according to the sixteenth embodiment of the present invention. In the following, structures corresponding to those described for the semiconductor device 101 are denoted by the same reference numerals, and descriptions thereof will be omitted.

[0441] 28, contact region 144 is formed in deep well region 145 in a region along the bottom wall of source trench 141. Contact region 144 is exposed from the bottom wall of source trench 141.

[0442] The source insulating layer 146 has a layered structure including a plurality of barrier-forming layers formed along the inner wall of the source trench 141. In this embodiment, the source insulating layer 146 has a layered structure including an insulating barrier-forming layer 252 and a conductive barrier-forming layer 253 that are layered in this order from the inner wall of the source trench 141.

[0443] The insulating barrier-forming layer 252 may include at least one of undoped silicon, silicon oxide, silicon nitride, aluminum oxide, aluminum nitride, or aluminum oxynitride.

[0444] The insulating barrier forming layer 252 is formed in the form of a film along the inner wall surface of the source trench 141 so as to selectively expose the contact region 144 from the bottom wall of the source trench 141 .

[0445] More specifically, the insulating barrier-forming layer 252 includes a first portion 254 and a second portion 255. The first portion 254 covers the sidewall of the source trench 141. The second portion 255 selectively covers the bottom wall of the source trench 141.

[0446] The second portion 255 is continuous with the first portion 254. The second portion 255 extends from the corner of the source trench 141 along the bottom wall so as to expose the center of the bottom wall of the source trench 141.

[0447] The conductive barrier-forming layer 253 may include at least one of conductive polysilicon, tungsten, platinum, nickel, cobalt, or molybdenum. The conductive barrier-forming layer 253 includes a conductive material that is different from the conductive material of the source electrode layer 147.

[0448] The conductive barrier-forming layer 253 is formed in the form of a film along the insulating barrier-forming layer 252 so as to selectively expose the contact region 144 from the bottom wall of the source trench 141 .

[0449] The source insulating layer 146 may include, instead of the conductive barrier-forming layer 253, an insulating barrier-forming layer made of an insulating material different from that of the insulating barrier-forming layer 252. The source insulating layer 146 may include, instead of the conductive barrier-forming layer 253, an insulating barrier-forming layer made of the same insulating material as that of the insulating barrier-forming layer 252.

[0450] As described above, the semiconductor device 251 can achieve the same effects as those described for the semiconductor device 101. Furthermore, in the semiconductor device 251, the source insulating layer 146 has a layered structure including the insulating barrier-forming layer 252 and the conductive barrier-forming layer 253. As a result, the two layers, the insulating barrier-forming layer 252 and the conductive barrier-forming layer 253, can suppress the occurrence of punch-through.

[0451] 29 is a cross-sectional view of a region corresponding to FIG. 13, illustrating the structure of a semiconductor device 261 according to the seventeenth embodiment of the present invention. In the following, structures corresponding to those described for the semiconductor device 101 are denoted by the same reference numerals, and descriptions thereof will be omitted.

[0452] 29, contact region 144 is formed in deep well region 145 in a region along the bottom wall of source trench 141. Contact region 144 is exposed from the bottom wall of source trench 141.

[0453] The source insulating layer 146 includes a first portion 262 and a second portion 263. The first portion 262 covers the sidewall of the source trench 141. The second portion 263 covers the bottom wall of the source trench 141.

[0454] The first portion 262 selectively has a sidewall contact hole 264 that exposes the SiC semiconductor layer 102 from the sidewall of the source trench 141. The first portion 262 may be formed to cross the boundary region between the SiC semiconductor layer 102 and the body region 116.

[0455] A lower end of the first portion 262 (an end on the bottom wall side of the source trench 141) may be located closer to the bottom wall side of the source trench 141 than the bottom of the body region 116. In this case, the source electrode layer 147 is electrically connected to the drift region 115 in the source trench 141.

[0456] The lower end of the first portion 262 may be located on the first major surface 103 side with respect to the bottom of the body region 116. The lower end of the first portion 262 may be formed in a region between the bottom of the body region 116 and the bottom of the source region 126. In these cases, the source electrode layer 147 is connected to at least the body region 116 in the source trench 141.

[0457] A lower end of the first portion 262 may be formed in a region between the first main surface 103 of the SiC semiconductor layer 102 and the bottom of the source region 126. The source insulating layer 146 may not have the first portion 262, but may have only the second portion 263. In these cases, the source electrode layer 147 is connected to the body region 116 and the contact region 144 within the source trench 141.

[0458] The second portion 263 of the source insulating layer 146 is formed at a distance from the first portion 262 of the source insulating layer 146. In other words, the second portion 263 is separated from the first portion 262. The second portion 263 may cover the corners of the source trench 141.

[0459] The second portion 263 may expose the corners of the source trench 141. The second portion 263 may cover the corners of the source trench 141 and also cover part of the sidewalls of the source trench 141.

[0460] The source electrode layer 147 forms a Schottky junction with the SiC semiconductor layer 102 (drift region 115) in the source trench 141. This forms a Schottky barrier diode 265 in which the source electrode layer 147 serves as an anode and the SiC semiconductor layer 102 serves as a cathode.

[0461] The p-type deep well region 145 is formed in the SiC semiconductor layer 102 in a region along the bottom wall of the source trench 141. In this embodiment, the deep well region 145 is formed in the high concentration region 112a of the SiC epitaxial layer 112. The entire area of ​​the deep well region 145 is formed in the high concentration region 112a.

[0462] The deep well region 145 may be formed continuously in the SiC semiconductor layer 102 in a region along the sidewall and corner of the source trench 141 so as to expose the source electrode layer 147 from the sidewall of the source trench 141 .

[0463] The deep well region 145 covers the bottom wall of the source trench 141. The deep well region 145 covers the corners connecting the side walls and bottom walls of the source trench 141. The deep well region 145 may expose almost the entire side wall of the source trench 141 in the SiC semiconductor layer 102.

[0464] The deep well region 145 extends from the bottom wall of the source trench 141 in a lateral direction parallel to the first main surface 103 of the SiC semiconductor layer 102. As a result, the deep well region 145 faces the body region 116 with a partial region of the SiC semiconductor layer 102 (drift region 115) sandwiched therebetween, in the normal direction to the first main surface 103 of the SiC semiconductor layer 102.

[0465] More specifically, the source electrode layer 147 forms a Schottky junction with the SiC semiconductor layer 102 (drift region 115) at a depth position between the body region 116 and the deep well region 145 in the normal direction to the first main surface 103 of the SiC semiconductor layer 102.

[0466] More specifically, the source electrode layer 147 forms a Schottky junction with the SiC semiconductor layer 102 (drift region 115) in a region of the SiC semiconductor layer 102 sandwiched between the body region 116 and the deep well region 145 in the normal direction of the first main surface 103 of the SiC semiconductor layer 102.

[0467] The source electrode layer 147 may have a laminated structure including a plurality of electrode layers. The source electrode layer 147 may include a first electrode layer and a second electrode layer laminated in this order from the SiC semiconductor layer 102 side.

[0468] The first electrode layer may be a barrier electrode layer including a Ti (titanium) film and / or a TiN (titanium nitride) film. The first electrode layer may have a laminated structure in which a Ti (titanium) film and a TiN (titanium nitride) film are laminated in this order from the SiC semiconductor layer 102 side. The first electrode layer may have a single-layer structure made of a Ti (titanium) film or a TiN (titanium nitride) film. The second electrode layer may contain aluminum or tungsten.

[0469] As described above, the semiconductor device 261 can achieve the same effects as those described for the semiconductor device 101. Furthermore, when a reverse bias voltage is applied to the semiconductor device 261, a current can be preferentially made to flow into the Schottky barrier diode 265.

[0470] This makes it possible to suppress the expansion of crystal defects in SiC in the SiC semiconductor layer 102. As a result, it is possible to suppress an increase in on-resistance while improving short-circuit resistance and reducing feedback capacitance Crss.

[0471] In this embodiment, an example has been described in which the source electrode layer 147 forms a Schottky junction with the SiC semiconductor layer 102 in the sidewall contact hole 264 of the source insulating layer 146. However, a configuration in which the source insulating layer 146 (the first portion 262 and the second portion 263) is not formed may also be employed.

[0472] 30 is a cross-sectional view of a region corresponding to FIG. 13, illustrating the structure of a semiconductor device 271 according to the eighteenth embodiment of the present invention. In the following, structures corresponding to those described for the semiconductor device 201 are denoted by the same reference numerals, and descriptions thereof will be omitted.

[0473] 30 , contact region 144 is formed in deep well region 145 in a region along the bottom wall of source trench 141. Contact region 144 is exposed from the bottom wall of source trench 141. Source insulating layer 146 is formed along the inner wall surface of source trench 141 so as to selectively expose contact region 144 from the bottom wall of source trench 141.

[0474] More specifically, the source insulating layer 146 includes a first portion 272 and a second portion 273. The first portion 272 covers the sidewall of the source trench 141. The second portion 273 partially covers the bottom wall of the source trench 141.

[0475] The second portion 273 is continuous with the first portion 272. The second portion 273 extends from a corner of the source trench 141 along the bottom wall so as to expose a central portion of the bottom wall of the source trench 141. The second portion 273 may be formed in an endless shape (annular shape) in a plan view.

[0476] As described above, the semiconductor device 271 can achieve the same effects as those described for the semiconductor device 201. Furthermore, the semiconductor device 271 forms a pn junction in the boundary region between the SiC semiconductor layer 102 and the deep well region 145.

[0477] Even if a depletion layer spreads from this pn junction along the bottom wall from the corner of the source trench 141, the source insulating layer 146 can increase the distance until the depletion layer reaches the source electrode layer 147. This makes it possible to suppress the occurrence of punch-through near the corner of the source trench 141.

[0478] 31 is a cross-sectional view of a region corresponding to FIG. 13, illustrating the structure of a semiconductor device 281 according to a nineteenth embodiment of the present invention. In the following, structures corresponding to those described for the semiconductor device 201 are denoted by the same reference numerals, and descriptions thereof will be omitted.

[0479] 31, an exposed portion 282 that selectively exposes the bottom wall of source trench 141 is formed in deep well region 145. Exposed portion 282 exposes the center portion of the bottom wall of source trench 141.

[0480] In this embodiment, the source insulating layer 146 includes a first portion 283 and a second portion 284. The first portion 283 covers the sidewall of the source trench 141. The second portion 284 partially covers the bottom wall of the source trench 141.

[0481] The second portion 284 is continuous with the first portion 283. The second portion 284 extends from a corner of the source trench 141 along the bottom wall so as to expose a central portion of the bottom wall of the source trench 141. The second portion 284 may be formed in an endless shape (annular shape) in a plan view.

[0482] The source electrode layer 147 forms a heterojunction with the SiC semiconductor layer 102 in the exposed portion 282 of the deep well region 145. This forms a heterojunction diode 285 in which the source electrode layer 147 serves as an anode and the SiC semiconductor layer 102 serves as a cathode. The source electrode layer 147 may contain a conductive material other than polysilicon as long as the heterojunction diode 285 is formed.

[0483] A body diode 286 is formed at the pn junction between the SiC semiconductor layer 102 and the body region 116. The junction barrier of the heterojunction diode 285 is smaller than the built-in potential of the body diode 286.

[0484] The junction barrier of the heterojunction diode 285 may be 1.0 eV or more and 1.5 eV or less, and the built-in potential of the body diode 286 may be 2.8 eV or more and 3.2 eV or less.

[0485] As described above, the semiconductor device 281 can achieve the same effects as those described for the semiconductor device 201. Furthermore, when a reverse bias voltage is applied to the semiconductor device 281, a current can be preferentially made to flow into the heterojunction diode 285.

[0486] This makes it possible to suppress the expansion of crystal defects in SiC in the SiC semiconductor layer 102. As a result, it is possible to suppress an increase in on-resistance while improving the short-circuit resistance and reducing the feedback capacitance Crss.

[0487] 32 is a cross-sectional view of a region corresponding to FIG. 13, illustrating the structure of a semiconductor device 291 according to a twentieth embodiment of the present invention. In the following, structures corresponding to those described for the semiconductor device 201 are denoted by the same reference numerals, and descriptions thereof will be omitted.

[0488] 32, contact region 144 is formed in deep well region 145 in a region along the bottom wall of source trench 141. Contact region 144 is exposed from the bottom wall of source trench 141.

[0489] The source insulating layer 146 has a layered structure including a plurality of barrier-forming layers formed along the inner wall of the source trench 141. In this embodiment, the source insulating layer 146 has a layered structure including an insulating barrier-forming layer 292 and a conductive barrier-forming layer 293 that are layered in this order from the inner wall of the source trench 141.

[0490] The insulating barrier-forming layer 292 may include at least one of undoped silicon, silicon oxide, silicon nitride, aluminum oxide, aluminum nitride, or aluminum oxynitride.

[0491] The insulating barrier forming layer 292 is formed in the form of a film along the inner wall surface of the source trench 141 so as to selectively expose the contact region 144 from the bottom wall of the source trench 141 .

[0492] More specifically, the insulating barrier-forming layer 292 includes a first portion 294 and a second portion 295. The first portion 294 covers the sidewall of the source trench 141. The second portion 295 selectively covers the bottom wall of the source trench 141.

[0493] The second portion 295 is continuous with the first portion 294. The second portion 295 extends from the corner of the source trench 141 along the bottom wall so as to expose the center of the bottom wall of the source trench 141.

[0494] The conductive barrier-forming layer 293 may comprise at least one of conductive polysilicon, tungsten, platinum, nickel, cobalt, or molybdenum. The conductive barrier-forming layer 293 comprises a conductive material that is different from the conductive material of the source electrode layer 147.

[0495] The conductive barrier-forming layer 293 is formed in a film shape along the insulating barrier-forming layer 292 so as to selectively expose the contact region 144 from the bottom wall of the source trench 141 .

[0496] As described above, the semiconductor device 291 can achieve the same effects as those described for the semiconductor device 201. Furthermore, in the semiconductor device 291, the source insulating layer 146 has a layered structure including an insulating barrier-forming layer 292 and a conductive barrier-forming layer 293. As a result, the two layers, the insulating barrier-forming layer 292 and the conductive barrier-forming layer 293, can suppress the occurrence of punch-through.

[0497] 33 is a cross-sectional view of a region corresponding to FIG. 13, illustrating the structure of a semiconductor device 301 according to the twenty-first embodiment of the present invention. In the following, structures corresponding to those described for the semiconductor device 201 are denoted by the same reference numerals, and descriptions thereof will be omitted.

[0498] 33, contact region 144 is formed in deep well region 145 in a region along the bottom wall of source trench 141. Contact region 144 is exposed from the bottom wall of source trench 141.

[0499] The source insulating layer 146 includes a first portion 302 and a second portion 303. The first portion 302 covers the sidewall of the source trench 141. The second portion 303 covers the bottom wall of the source trench 141.

[0500] The first portion 302 selectively has a sidewall contact hole 304 that exposes the SiC semiconductor layer 102 from the sidewall of the source trench 141. The first portion 302 may be formed to cross a boundary region between the SiC semiconductor layer 102 and the body region 116.

[0501] A lower end of the first portion 302 (an end on the source trench 141 side) may be located closer to the bottom wall of the source trench 141 than the bottom of the body region 116. In this case, the source electrode layer 147 is electrically connected to the drift region 115 in the source trench 141.

[0502] The lower end of first portion 302 may be located on the first main surface 103 side of the bottom of body region 116. The lower end of first portion 302 may be formed in a region between the bottom of body region 116 and the bottom of source region 126. In these cases, source electrode layer 147 is connected to at least body region 116 in source trench 141.

[0503] A lower end of the first portion 302 may be formed in a region between the first main surface 103 of the SiC semiconductor layer 102 and the bottom of the source region 126. The source insulating layer 146 may not have the first portion 302, but may have only the second portion 303. In these cases, the source electrode layer 147 is connected to the body region 116 and the contact region 144 within the source trench 141.

[0504] The second portion 303 of the source insulating layer 146 is formed at a distance from the first portion 302 of the source insulating layer 146. In other words, the second portion 303 is separated from the first portion 302. The second portion 303 may cover the corners of the source trench 141.

[0505] The second portion 303 may expose the corners of the source trench 141. The second portion 303 may cover the corners of the source trench 141 and also cover a portion of the sidewall of the source trench 141.

[0506] The source electrode layer 147 forms a Schottky junction with the SiC semiconductor layer 102 (drift region 115) in the source trench 141. This forms a Schottky barrier diode 305 in which the source electrode layer 147 serves as an anode and the SiC semiconductor layer 102 serves as a cathode.

[0507] The p-type deep well region 145 is formed in the SiC semiconductor layer 102 in a region along the bottom wall of the source trench 141. In this embodiment, the deep well region 145 is formed in the high concentration region 112a of the SiC epitaxial layer 112. The entire area of ​​the deep well region 145 is formed in the high concentration region 112a.

[0508] The deep well region 145 may be formed continuously in the SiC semiconductor layer 102 in a region along the sidewall and corner of the source trench 141 so as to expose the source electrode layer 147 from the sidewall of the source trench 141 .

[0509] The deep well region 145 covers the bottom wall of the source trench 141. The deep well region 145 covers the corners connecting the side walls and bottom walls of the source trench 141. The deep well region 145 may expose almost the entire side wall of the source trench 141 in the SiC semiconductor layer 102.

[0510] The deep well region 145 extends from the bottom wall of the source trench 141 in a lateral direction parallel to the first main surface 103 of the SiC semiconductor layer 102. As a result, the deep well region 145 faces the body region 116 with a partial region of the SiC semiconductor layer 102 (drift region 115) sandwiched therebetween, in the normal direction to the first main surface 103 of the SiC semiconductor layer 102.

[0511] The deep well region 145 extends from the bottom wall of the source trench 141 in a lateral direction parallel to the first main surface 103 of the SiC semiconductor layer 102. As a result, the deep well region 145 faces the body region 116 with a partial region of the SiC semiconductor layer 102 (drift region 115) sandwiched therebetween, in the normal direction to the first main surface 103 of the SiC semiconductor layer 102.

[0512] More specifically, the source electrode layer 147 forms a Schottky junction with the SiC semiconductor layer 102 (drift region 115) at a depth position between the body region 116 and the deep well region 145 in the normal direction to the first main surface 103 of the SiC semiconductor layer 102.

[0513] More specifically, the source electrode layer 147 forms a Schottky junction with the SiC semiconductor layer 102 (drift region 115) in a region of the SiC semiconductor layer 102 sandwiched between the body region 116 and the deep well region 145 in the normal direction of the first main surface 103 of the SiC semiconductor layer 102.

[0514] The source electrode layer 147 may have a laminated structure including a plurality of electrode layers. The source electrode layer 147 may include a first electrode layer and a second electrode layer laminated in this order from the SiC semiconductor layer 102 side.

[0515] The first electrode layer may be a barrier electrode layer including a Ti (titanium) film and / or a TiN (titanium nitride) film. The first electrode layer may have a laminated structure in which a Ti (titanium) film and a TiN (titanium nitride) film are laminated in this order from the SiC semiconductor layer 102 side. The first electrode layer may have a single-layer structure made of a Ti (titanium) film or a TiN (titanium nitride) film. The second electrode layer may contain aluminum or tungsten.

[0516] As described above, the semiconductor device 301 can achieve the same effects as those described for the semiconductor device 201. Furthermore, when a reverse bias voltage is applied to the semiconductor device 301, a current can be preferentially made to flow into the Schottky barrier diode 305.

[0517] This makes it possible to suppress the expansion of crystal defects in SiC in the SiC semiconductor layer 102. As a result, it is possible to suppress an increase in on-resistance while improving short-circuit resistance and reducing feedback capacitance Crss.

[0518] In this embodiment, an example has been described in which the source electrode layer 147 forms a Schottky junction with the SiC semiconductor layer 102 in the sidewall contact hole 264 of the source insulating layer 146. However, a configuration in which the source insulating layer 146 (first portion 302 and second portion 303) is not formed may also be employed.

[0519] Although the seventh to twenty-first embodiments of the present invention have been described, the seventh to twenty-first embodiments of the present invention can also be implemented in other forms.

[0520] In the seventh to twenty-first embodiments described above, examples have been described in which the SiC epitaxial layer 112 having the high-concentration region 112a and the low-concentration region 112b is formed by epitaxial growth. However, the SiC epitaxial layer 112 can also be formed by the following process.

[0521] First, an SiC epitaxial layer 112 having a relatively low n-type impurity concentration is formed by epitaxial growth. Next, an n-type impurity is introduced into the surface layer of the SiC epitaxial layer 112 by ion implantation. This results in the formation of an SiC epitaxial layer 112 having a high-concentration region 112a and a low-concentration region 112b.

[0522] In the seventh to twenty-first embodiments described above, examples have been described in which the SiC semiconductor layer 102 has a layered structure including the SiC semiconductor substrate 111 and the SiC epitaxial layer 112. However, the SiC semiconductor layer 102 may have a single-layer structure made of the SiC semiconductor substrate 111. The SiC semiconductor layer 102 may have a single-layer structure made of the SiC epitaxial layer 112.

[0523] In the seventh to twenty-first embodiments described above, a structure in which the conductivity type of each semiconductor portion is reversed may be adopted, that is, the p-type portion may be made n-type, and the n-type portion may be made p-type.

[0524] In the seventh to twenty-first embodiments described above, examples have been described in which the gate electrode layer 132 and the gate wiring layer 133 include p-type polysilicon doped with p-type impurities. However, when an increase in the gate threshold voltage Vth is not important, the gate electrode layer 132 and the gate wiring layer 133 may include n-type polysilicon doped with n-type impurities instead of p-type polysilicon.

[0525] The low-resistance electrode layer 134 may be formed by silicidating a surface portion of the gate electrode layer 132 (n-type polysilicon) with a metal material. That is, the low-resistance electrode layer 134 may include n-type polycide. With such a structure, it is possible to reduce the gate resistance.

[0526] In the seventh to twenty-first embodiments described above, the structure of the semiconductor device 221 may be adopted. That is, in the seventh to twenty-first embodiments described above, + Instead of the SiC semiconductor substrate 111, +Alternatively, a type SiC semiconductor substrate 222 may be employed. In this case, in the descriptions of the seventh to thirteenth embodiments, "source" should be read as "emitter" and "drain" should be read as "collector."

[0527] Fig. 34 is a top view showing a semiconductor device 311 according to the 22nd embodiment of the present invention. Fig. 35 is a bottom view of the semiconductor device 311 shown in Fig. 34. In the following, structures corresponding to those described for the semiconductor device 101 will be described with the same reference numerals.

[0528] 34, a semiconductor device 311 has a SiC semiconductor layer 102 including a SiC (silicon carbide) single crystal. The SiC semiconductor layer 102 may include a 4H—SiC single crystal.

[0529] The 4H—SiC single crystal has an off-angle tilted from the

[0001] plane by an angle of 10° or less with respect to the [11-20] direction. The off-angle may be 0° or more and 4° or less. The off-angle may be greater than 0° and less than 4°. The off-angle is typically set to 2° or 4°, more specifically, in the range of 2°±0.2° or 4°±0.4°.

[0530] In this embodiment, the SiC semiconductor layer 102 is formed in the shape of a rectangular parallelepiped chip. The SiC semiconductor layer 102 has a first main surface 103 on one side, a second main surface 104 on the other side, and side surfaces 105A, 105B, 105C, and 105D connecting the first main surface 103 and the second main surface 104. The first main surface 103 and the second main surface 104 are formed in a quadrangular shape (rectangular in this embodiment) in a plan view seen from the normal direction thereof (hereinafter simply referred to as "plan view").

[0531] Side surface 105A faces side surface 105C. Side surface 105B faces side surface 105D. The four side surfaces 105A to 105D each extend in a plane along the normal direction to first main surface 103 and second main surface 104. The length of each of side surfaces 105A to 105D may be 1 mm or more and 10 mm or less (for example, 2 mm or more and 5 mm or less).

[0532] The SiC semiconductor layer 102 has an active region 106 and an outer region 107. The active region 106 is a region in which a vertical MISFET is formed. The outer region 107 is a region outside the active region 106.

[0533] In plan view, the active region 106 is set in the center of the SiC semiconductor layer 102, spaced apart from the side surfaces 105A-105D of the SiC semiconductor layer 102. In plan view, the active region 106 is set in a quadrangular shape (rectangular in this embodiment) having four sides parallel to the four side surfaces 105A-105D of the SiC semiconductor layer 102.

[0534] Outer region 107 is set in a region between side surfaces 105A to 105D of SiC semiconductor layer 102 and the periphery of active region 106. Outer region 107 is set in an endless shape (quadratic ring shape) surrounding active region 106 in plan view.

[0535] A gate pad 108, gate fingers 109, and a source pad 110 are formed on the first main surface 103 of the SiC semiconductor layer 102. The gate pad 108, gate fingers 109, and source pad 110 may contain aluminum and / or copper.

[0536] The gate pad 108 is formed along the side surface 105A of the SiC semiconductor layer 102 in a plan view. The gate pad 108 is formed along a central region of the side surface 105A of the SiC semiconductor layer 102 in a plan view. The gate pad 108 may be formed along a corner connecting any two of the four side surfaces 105A to 105D of the SiC semiconductor layer 102 in a plan view.

[0537] The gate pad 108 is formed in a rectangular shape in a plan view and is drawn out from the outer region 107 into the active region 106 so as to cross the boundary region between the outer region 107 and the active region 106 in a plan view.

[0538] The gate fingers 109 include outer gate fingers 109A and inner gate fingers 109B. The outer gate fingers 109A extend from the gate pad 108 to the outer region 107. The outer gate fingers 109A extend in a strip shape in the outer region 107.

[0539] In this embodiment, the outer gate fingers 109A are formed along three side surfaces 105A, 105B, and 105D of the SiC semiconductor layer 102 so as to partition the active region 106 from three directions.

[0540] The inner gate finger 109B is drawn out from the gate pad 108 to the active region 106. The inner gate finger 109B extends in a strip shape in the active region 106. The inner gate finger 109B extends from the side surface 105A toward the side surface 105C.

[0541] The source pad 110 is formed in the active region 106 at a distance from the gate pad 108 and the gate fingers 109. The source pad 110 is formed in a C-shape (an inverted C-shape in FIG. 34) in plan view so as to cover the C-shaped region (an inverted C-shape in FIG. 34) defined by the gate pad 108 and the gate fingers 109.

[0542] A gate voltage is applied to the gate pad 108 and the gate fingers 109. The gate voltage may be 10 V or more and 50 V or less (for example, about 30 V). A source voltage is applied to the source pad 110. The source voltage may be a reference voltage (for example, a GND voltage).

[0543] A resin layer 312 is formed on the first main surface 103 of the SiC semiconductor layer 102 (more specifically, on the interlayer insulating layer 153). For clarity, the resin layer 312 is shown by hatching in Figure 34. The resin layer 312 covers the gate pad 108, the gate fingers 109, and the source pad 110.

[0544] The resin layer 312 may contain a negative or positive photosensitive resin. In this embodiment, the resin layer 312 contains polybenzoxazole, which is an example of a positive photosensitive resin. The resin layer 312 may also contain polyimide, which is an example of a negative photosensitive resin.

[0545] The peripheral portion of resin layer 312 is formed at a distance inward from side surfaces 105A-105D of SiC semiconductor layer 102. As a result, the peripheral portion of resin layer 312 exposes first main surface 103 of SiC semiconductor layer 102. More specifically, the peripheral portion of resin layer 312 exposes interlayer insulating layer 153.

[0546] A gate pad opening 313 and a source pad opening 314 are formed in the resin layer 312. The gate pad opening 313 exposes the gate pad 108. The source pad opening 314 exposes the source pad 110.

[0547] 35 and the enlarged view of FIG. 35, a group of raised portions 316 including a plurality of raised portions 315 is formed on second main surface 104 of SiC semiconductor layer 102. The plurality of raised portions 315 are portions that are raised on second main surface 104 of SiC semiconductor layer 102 along the normal direction to second main surface 104 of SiC semiconductor layer 102.

[0548] The multiple protrusions 315 are formed at intervals from one another along an arbitrary first direction X and a second direction Y intersecting the first direction X. The first direction X is one of the plane directions of the first main surface 103 of the SiC semiconductor layer 102.

[0549] In this embodiment, the first direction X is set to a direction parallel to the side surfaces 105B and 105D of the SiC semiconductor layer 102. More specifically, the second direction Y is a direction perpendicular to the first direction X. That is, in this embodiment, the second direction Y is set to a direction parallel to the side surfaces 105A and 105C of the SiC semiconductor layer 102.

[0550] The group of raised portions 316 has first portions 317 in which some of the plurality of raised portions 315 overlap in the first direction X when viewed in the first direction X.

[0551] Furthermore, the raised portion group 316 has a second portion 318 in which some of the plurality of raised portions 315 are formed apart from the first portion 317 and overlap with the first direction X when viewed in the first direction.

[0552] The plurality of raised portions 315 are continuously formed along the first direction X. More specifically, the plurality of raised portions 315 have a scattered pattern in which they are scattered at intervals along the first direction X and the second direction Y.

[0553] The plurality of raised portions 315 are formed continuously along the first direction X while maintaining this scattered pattern. In this embodiment, the plurality of raised portions 315 are formed from the periphery of the SiC semiconductor layer 102 on one side surface 105A side to the periphery of the other side surface 105C side in plan view.

[0554] The distances between the plurality of ridges 315 spaced apart in the first direction X in the ridge group 316 may be different from each other. The distances between the plurality of ridges 315 spaced apart in the second direction Y in the ridge group 316 may be different from each other.

[0555] The plurality of protrusions 315 may be formed with non-uniform shapes, sizes, and thicknesses. The thickness of protrusion 315 is the distance from the base to the top (tip) of protrusion 315 in the normal direction to second main surface 104 of SiC semiconductor layer 102.

[0556] The plurality of ridges 315 may each have a size greater than 0 μm and less than or equal to 10 μm. Each ridge 315 may have a thickness of less than or equal to 500 nm (for example, greater than or equal to 1 nm and less than or equal to 250 nm).

[0557] The group of raised portions 316 is formed on the second main surface 104 of the SiC semiconductor layer 102 in an area narrower than the width of the side surfaces 105A to 105D (side surfaces 105A and 105C in this embodiment) of the SiC semiconductor layer 102.

[0558] The group of protrusions 316 is formed in a range of 1 / 1000 to 1 / 5 of the width of the side surfaces 105A to 105D (side surfaces 105A and 105C in this embodiment) of the SiC semiconductor layer 102, for example.

[0559] The group of raised portions 316 may be formed in a range of 1 / 200 to 1 / 10 of the width of the side surfaces 105A to 105D (side surfaces 105A and 105C in this embodiment) of the SiC semiconductor layer .

[0560] The ridge group 316 may be formed in a range of 10 μm to 200 μm in the second direction Y. The ridge group 316 may be formed in a range of 50 μm to 150 μm in the second direction Y. The ridge group 316 may be formed in a range of 80 μm to 120 μm in the second direction Y.

[0561] The raised portion group 316 has a layout in which the plurality of raised portions 315 overlap in the first direction X when viewed from the first direction X. As a result, the raised portion group 316 forms a raised portion group region 319 extending in a band shape along the first direction X by a collective pattern of the plurality of raised portions 315 continuously scattered along the first direction X.

[0562] In other words, the protuberance group region 319 includes a plurality of protuberances 315 (protuberance group 316) formed in a strip-shaped region extending along the first direction X on the second main surface 104 of the SiC semiconductor layer 102.

[0563] On the second main surface 104 of the SiC semiconductor layer 102, a plurality of protrusion groups 316 (protrusion group regions 319) having such a configuration are formed at intervals along the second direction Y.

[0564] That is, the scattered pattern of the plurality of raised portions 315 is formed intermittently when viewed in the second direction Y. The distance between the plurality of raised portion groups 316 may be 1% or more and 25% or less of the range in which the raised portion groups 316 are formed.

[0565] In the second direction Y, the distance between adjacent raised portion groups 316 may be 100 μm or less. The distance between the raised portion groups 316 may be 5 μm or more and 50 μm or less. The distance between the raised portion groups 316 may be 20 μm or less.

[0566] The first direction X may be set to the [11-20] direction, and the second direction Y may be set to the [1-100] direction. That is, the ridge group 316 may form a strip-shaped ridge group region 319 extending substantially parallel to or parallel to the [11-20] direction, and a plurality of ridge group regions 319 may be formed at intervals along the [1-100] direction.

[0567] The first direction X may be set to the [1-100] direction, and the second direction Y may be set to the [11-20] direction. That is, the ridge group 316 may form a band-shaped ridge group region 319 extending substantially parallel to or parallel to the [1-100] direction, and a plurality of ridge group regions 319 may be formed at intervals along the [11-20] direction.

[0568] In the region between adjacent raised portion groups 316 in the second direction Y on the second main surface 104 of the SiC semiconductor layer 102, a space 320 not having a dotted pattern made up of a plurality of raised portions 315 is defined.

[0569] The spaces 320 are partitioned into strips extending parallel to the first direction X by adjacent raised portion groups 316 (raised portion group regions 319). As a result, a stripe pattern is formed on the second main surface 104 of the SiC semiconductor layer 102, in which the raised portion groups 316 and the spaces 320 are alternately formed along the second direction Y.

[0570] A plurality of grooves 321 are formed in the second main surface 104 of the SiC semiconductor layer 102. The grooves 321 are indicated by lines in FIG. 35 and the enlarged view of FIG. 35. The grooves 321 are formed in the ridge groups 316 and the spaces 320.

[0571] The plurality of grooves 321 include grinding marks resulting from grinding of the second wafer main surface 333 of the SiC semiconductor wafer 331, which will be described later. Therefore, the direction in which the grooves 321 extend varies depending on the position at which the SiC semiconductor layer 102 is cut out from the SiC semiconductor wafer 331.

[0572] The grooves 321 may extend substantially parallel to or parallel to each of the ridge groups 316. The grooves 321 may include portions that intersect with the ridge groups 316. The grooves 321 may extend along a direction that intersects with or is perpendicular to each of the ridge groups 316. The grooves 321 may extend linearly or arcuately.

[0573] Some of the plurality of ridges 315 included in each ridge group 316 are formed at intervals along the grooves 321. In other words, each ridge group 316 includes a third portion 322 in which some of the plurality of ridges 315 are formed at intervals along the grooves 321 in a plan view.

[0574] Each of the groups of protrusions 316 is formed by, for example, an annealing process. The plurality of protrusions 315 may be laser processing marks formed by a laser annealing process.

[0575] The plurality of protrusions 315 (third portion 322 of protrusion group 316) along groove 321 may be formed by an annealing treatment method for the irregularities defined by groove 321 on second main surface 104 of SiC semiconductor layer 102 (second wafer main surface 333 of SiC semiconductor wafer 331).

[0576] As shown in FIGS. 36A to 36D, each of the protrusion groups 316 can take various forms by adjusting the annealing treatment conditions (here, the laser annealing treatment conditions).

[0577] FIG. 36A is a diagram showing a second example of each raised portion group 316. As shown in FIG.

[0578] 36A, the raised portion group 316 may include a convexly curved raised portion 315 that extends along the first direction X in a plan view and protrudes along the second direction Y (toward the side surface 105B in FIG. 36A). The raised portion 315 may be formed by a plurality of raised portions 315 that overlap each other.

[0579] The distance between the two furthest points on the raised portions 315 may be 1 μm or more and 200 μm or less (approximately 50 μm in this embodiment). The distance between adjacent raised portions 315 in the first direction X is set to a value equal to or greater than 10% of the size of the raised portions 315. The raised portions 315 are formed by shifting adjacent laser irradiation positions in the first direction X.

[0580] FIG. 36B is a diagram showing a third example of the group of raised portions 316. In FIG.

[0581] 36B, the raised portion group 316 may include a concavely curved raised portion 315 that extends along the second direction Y in a plan view and is recessed along the first direction X. The raised portion 315 may be formed by a plurality of raised portions 315 that overlap each other.

[0582] The distance between the two furthest points on each raised portion 315 may be 1 μm or more and 200 μm or less (approximately 50 μm in this embodiment). The raised portions 315 are formed by overlapping adjacent laser irradiation positions by 50% or more and 70% or less.

[0583] FIG. 36C is a diagram showing a fourth embodiment of the group of raised portions 316. In FIG.

[0584] 36C , the raised portion group 316 may include linear raised portions 315 that extend along the second direction Y in a plan view and are recessed along the first direction X. The raised portions 315 may have protrusions that protrude along the first direction X. The raised portions 315 may be formed by a plurality of raised portions 315 that overlap each other.

[0585] The distance between the two furthest points on the raised portion 315 may be 1 μm or more and 200 μm or less (approximately 50 μm in this embodiment). The raised portions 315 are formed by overlapping adjacent laser irradiation positions by 70% or more and 90% or less.

[0586] FIG. 36D is a diagram showing a fifth example of the group of raised portions 316. In FIG.

[0587] As shown in FIG. 36D, the ridge group 316 may have a layout in which a ridge row including a plurality of ridges 315 spaced apart along the second direction Y is formed at intervals along the first direction X.

[0588] The distance between the two furthest points on the raised portion 315 may be 1 μm or more and 200 μm or less (approximately 5 μm in this embodiment). The raised portions 315 are formed by overlapping adjacent laser irradiation positions in a range of 90% or more and less than 100%.

[0589] Fig. 37 is an enlarged view of region XXXVII shown in Fig. 34, with the structure above first main surface 103 of SiC semiconductor layer 102 removed. Fig. 38 is a cross-sectional view taken along line XXXVIII-XXXVIII in Fig. 37. Fig. 39 is a cross-sectional view taken along line XXXIX-XXXIX in Fig. 37. Fig. 40 is an enlarged view of region XL shown in Fig. 39.

[0590] 37 to 39, semiconductor device 311 has the same planar structure and cross-sectional structure as semiconductor device 101, except that a group of raised portions 316 is formed on second main surface 104 of SiC semiconductor layer 102.

[0591] 40 , the raised portion group 316 (plurality of raised portions 315) and the grooves 321 are formed in the SiC semiconductor substrate 111. A modified layer 323, in which part of the SiC of the SiC semiconductor layer 102 (SiC semiconductor substrate 111) is modified to have different properties, is formed in a surface layer portion of the second main surface 104 of the SiC semiconductor layer 102. The modified layer 323 is formed by annealing the second main surface 104 of the SiC semiconductor layer 102.

[0592] The modified layer 323 includes Si atoms and C atoms. More specifically, the modified layer 323 has a carbon density that is lower than the carbon density of the region outside the modified layer 323 in the SiC semiconductor layer 102 (SiC semiconductor substrate 111).

[0593] The modified layer 323 has a silicon density higher than a carbon density. That is, the modified layer 323 includes a Si modified layer in which SiC in the SiC semiconductor layer 102 (SiC semiconductor substrate 111) is modified to Si. The Si modified layer may be a Si amorphous layer.

[0594] The modified layer 323 may include lattice defects resulting from the modification of SiC. That is, the modified layer 323 may include a lattice defect region having defect levels introduced due to the modification of SiC.

[0595] In this embodiment, the modified layer 323 is formed in a region along the raised portion groups 316 in the surface layer portion of the second main surface 104 of the SiC semiconductor layer 102. As a result, the plurality of raised portions 315 in each raised portion group 316 are formed by the modified layer 323.

[0596] In this embodiment, the modified layer 323 further extends from the protrusion group 316 toward the spaces 320. That is, the annealing treatment performed on the second main surface 104 of the SiC semiconductor layer 102 also extends to the spaces 320.

[0597] The thickness of the modified layer 323 along the ridge group 316 is greater than or equal to the thickness of the modified layer 323 along the space 320 due to the presence of the ridge 315. More specifically, the thickness of the modified layer 323 along the ridge group 316 is greater than the thickness of the modified layer 323 along the space 320.

[0598] The modified layer 323 may have a thickness of 1 nm or more and 1000 nm or less. The modified layer 323 may have a thickness Ta of 50 nm or more and 1000 nm or less in a region where the raised portion 315 is formed. The modified layer 323 may have a thickness Tb of 1 nm or more and 300 nm or less in a region outside the raised portion 315.

[0599] The thickness Ta may be 50 nm or more and 100 nm or less. The thickness Ta may be 100 nm or more and 150 nm or less. The thickness Ta may be 150 nm or more and 200 nm or less. The thickness Ta may be 200 nm or more and 250 nm or less.

[0600] The thickness Ta may be 250 nm or more and 300 nm or less. The thickness Ta may be 300 nm or more and 350 nm or less. The thickness Ta may be 350 nm or more and 400 nm or less. The thickness Ta may be 400 nm or more and 450 nm or less. The thickness Ta may be 450 nm or more and 500 nm or less.

[0601] The thickness Ta may be 500 nm or more and 600 nm or less. The thickness Ta may be 600 nm or more and 700 nm or less. The thickness Ta may be 700 nm or more and 800 nm or less. The thickness Ta may be 800 nm or more and 900 nm or less. The thickness Ta may be 900 nm or more and 1000 nm or less.

[0602] The thickness Tb may be 1 nm or more and 10 nm or less. The thickness Tb may be 10 nm or more and 50 nm or less. The thickness Tb may be 50 nm or more and 100 nm or less.

[0603] The thickness Tb may be 100 nm or more and 150 nm or less. The thickness Tb may be 150 nm or more and 200 nm or less. The thickness Tb may be 200 nm or more and 250 nm or less. The thickness Tb may be 250 nm or more and 300 nm or less.

[0604] The thickness Tb may be ½ or less, ⅓ or less, ¼ or less, ⅕ or less, ⅙ or less, ⅙ or less, ⅛ or less, ⅚ or less, ⅞ ...

[0605] The resistance value of the second main surface 104 of the SiC semiconductor layer 102 when the group of ridges 316 is not present on the second main surface 104 is greater than the resistance value of the second main surface 104 when the group of ridges 316 is present on the second main surface 104 of the SiC semiconductor layer 102.

[0606] That is, the plurality of ridge groups 316 have an electrical resistance value equal to or less than the resistance value of the SiC single crystal alone. More specifically, the plurality of ridge groups 316 have a resistance value less than the resistance value of the SiC single crystal alone.

[0607] Furthermore, the plurality of ridge groups 316 have a resistance value equal to or less than the resistance value of the spaces 320. More specifically, the plurality of ridge groups 316 have a resistance value less than the resistance value of the spaces 320.

[0608] The resistance value of the ridge group 316 is reduced by the modified layer 323. That is, the resistance value of the ridge group 316 is equal to or less than the resistance value of the SiC single crystal due to the modified layer 323 modifying the properties of the SiC. The resistance value of the space 320 is also reduced by the modified layer 323.

[0609] In this embodiment, the drain pad 113 is directly connected to the second main surface 104 of the SiC semiconductor layer 102. The drain pad 113 covers the protrusion groups 316 on the second main surface 104 of the SiC semiconductor layer 102. The drain pad 113 covers the plurality of protrusion groups 316 collectively.

[0610] The drain pad 113 is formed in the shape of a film following the outer surface of the protuberance group 316 (the outer surfaces of the plurality of protuberances 315) and the inner surface of the groove 321. As a result, a protuberance 113a protruding in a direction away from the second main surface 104 is formed in the portion of the outer surface of the drain pad 113 that covers the protuberance group 316 (the plurality of protuberances 315). In addition, a recess 113b recessed toward the second main surface 104 is formed in the portion of the outer surface of the drain pad 113 that covers the groove 321.

[0611] The drain pad 113 forms an ohmic contact with the second main surface 104 of the SiC semiconductor layer 102. More specifically, the drain pad 113 forms an ohmic contact with the protrusion group 316.

[0612] More specifically, the drain pad 113 forms ohmic contact with the plurality of protrusion groups 316. In this embodiment, the drain pad 113 also forms ohmic contact with the spaces 320.

[0613] Drain pad 113 has a layered structure including multiple electrode layers stacked on second main surface 104 of SiC semiconductor layer 102. In this embodiment, drain pad 113 has a four-layer structure including a Ti layer 324, a Ni layer 325, an Au layer 326, and an Ag layer 327 stacked in this order on second main surface 104 of SiC semiconductor layer 102.

[0614] The Ti layer 324, the Ni layer 325, the Au layer 326, and the Ag layer 327 are formed in the form of films conforming to the outer surfaces of the protrusion group 316 (the outer surfaces of the plurality of protrusions 315) and the inner surfaces of the grooves 321. The protrusions 113a and the recesses 113b of the drain pad 113 are formed on the outer surface of the Ag layer 327.

[0615] The Ti layer 324 is directly connected to the second main surface 104 of the SiC semiconductor layer 102. The Ti layer 324 collectively covers the plurality of protrusion groups 316, and forms ohmic contact with the second main surface 104 of the SiC semiconductor layer 102. In this form, the Ti layer 324 also forms ohmic contact with the space 320.

[0616] The Ni layer 325 covers almost the entire area or the entire area of ​​the Ti layer 324. The Au layer 326 covers almost the entire area or the entire area of ​​the Ni layer 325. The Ag layer 327 covers almost the entire area or the entire area of ​​the Au layer 326.

[0617] The thickness of the Ti layer 324 may be 0.01 μm or more and 5 μm or less (for example, about 0.07 μm), and the thickness of the Ni layer 325 may be 0.1 μm or more and 40 μm or less (for example, about 1.2 μm).

[0618] The thickness of the Au layer 326 may be 0.1 μm or more and 40 μm or less (for example, about 0.07 μm). The thickness of the Ag layer 327 may be 0.1 μm or more and 40 μm or less (for example, about 0.3 μm). Of course, the drain pad 113 may have a single-layer structure made up of the Ti layer 324, the Ni layer 325, the Au layer 326, or the Ag layer 327.

[0619] The drain pad 113 forms an ohmic contact with the second main surface 104 of the SiC semiconductor layer 102 without a silicide layer mainly containing silicide therebetween. The drain pad 113 forms an ohmic contact with each of the protrusion groups 316 without a silicide layer mainly containing silicide therebetween.

[0620] The drain pad 113 forms an ohmic contact with the second main surface 104 of the SiC semiconductor layer 102 without a carbon layer mainly composed of carbon therebetween. The drain pad 113 forms an ohmic contact with each of the protrusion groups 316 without a carbon layer mainly composed of carbon therebetween.

[0621] The drain pad 113 does not include a region in which a material containing silicide as a main component is formed in a layer shape, nor does the drain pad 113 include a region in which a material containing carbon as a main component is formed in a layer shape.

[0622] Fig. 41A is a top view showing SiC semiconductor wafer 331 used in manufacturing semiconductor device 311 shown in Fig. 34. Fig. 41B is a bottom view of SiC semiconductor wafer 331 shown in Fig. 41A, showing the state after second wafer main surface 333 of SiC semiconductor wafer 331 has been subjected to a grinding process and an annealing process.

[0623] 41A and 41B, SiC semiconductor wafer 331 is made of a plate-like SiC single crystal formed into a disk shape. SiC semiconductor wafer 331 serves as a base for SiC semiconductor substrate 111.

[0624] The SiC semiconductor wafer 331 has a first wafer main surface 332 on one side, a second wafer main surface 333 on the other side, and a wafer side surface 334 connecting the first wafer main surface 332 and the second wafer main surface 333.

[0625] The SiC semiconductor wafer 331 may include a 4H—SiC single crystal. The first wafer main surface 332 of the SiC semiconductor wafer 331 has an off-axis angle inclined at an angle of 10° or less from the (0001) plane to the [11-20] direction.

[0626] The off-angle may be 0° or greater and 4° or less. The off-angle may be greater than 0° and less than 4°. The off-angle is typically set to 2° or 4°, more specifically, in the range of 2°±0.2° or 4°±0.4°.

[0627] One or more (one in this embodiment) orientation flats 335 indicating the crystal orientation are formed on the wafer side surface 334 of the SiC semiconductor wafer 331. The orientation flat 335 is a notch formed on the periphery of the SiC semiconductor wafer 331. In this embodiment, the orientation flat 335 extends linearly along the [11-20] direction.

[0628] The first wafer main surface 332 is an element formation surface on which MISFETs are formed. A plurality of device formation regions 336 corresponding to the semiconductor devices 311 are defined on the first wafer main surface 332.

[0629] In this embodiment, the device formation regions 336 are arranged in a matrix along the [11-20] direction ([-1-120] direction) and the [-1100] direction ([1-100] direction).

[0630] The grid-like areas that divide the device formation regions 336 are dicing lines 337. The semiconductor devices 311 are cut out by cutting the SiC semiconductor wafer 331 along the peripheries of the device formation regions 336 (dicing lines 337).

[0631] Referring to Figure 41B, after the grinding process and annealing process have been performed on second wafer main surface 333 of SiC semiconductor wafer 331, a plurality of groups of raised portions 316 and a plurality of grinding marks 338 have been formed on second wafer main surface 333 of SiC semiconductor wafer 331.

[0632] The plurality of ridge groups 316 are formed substantially parallel to the orientation flat 335 or in parallel stripes. The plurality of ridge groups 316 may also be formed in stripes that intersect or are perpendicular to the orientation flat 335.

[0633] The plurality of grinding marks 338 each extend in an arc shape from the center toward the periphery of the SiC semiconductor wafer 331. The plurality of grinding marks 338 generally include grinding marks 338 that intersect with the [11-20] direction and the [1-100] direction.

[0634] Furthermore, the plurality of grinding marks 338 include grinding marks 338 that extend substantially parallel to or parallel to the [11-20] direction or the [1-100] direction in a portion where a tangent to the arc is along the [11-20] direction or the [1-100] direction. Grooves 321 formed in second main surface 104 of SiC semiconductor layer 102 may be formed by part of grinding marks 338.

[0635] Fig. 42 is a flowchart illustrating an example of a method for manufacturing semiconductor device 311 shown in Fig. 34. Figs. 43A to 43I are cross-sectional views illustrating a method for manufacturing semiconductor device 311 shown in Fig. 34.

[0636] In the method for manufacturing the semiconductor device 311, a processing step of the second wafer main surface 333 is performed prior to the process of forming the drain pad 113 (see FIG. 17L) in the method for manufacturing the semiconductor device 101. The processing step of the second wafer main surface 333 may be performed after the process of forming the gate pad 108, the gate fingers 109, and the source pad 110.

[0637] 43A, first, the steps of FIGS. 17A to 17L are performed to prepare a SiC semiconductor wafer 331 having a MISFET fabricated on a first wafer main surface 332. A second wafer main surface 333 of SiC semiconductor wafer 331 is in an unprocessed state.

[0638] 43B, second wafer main surface 333 of SiC semiconductor wafer 331 is ground (step S1 in FIG. 42). In this step, second wafer main surface 333 of SiC semiconductor wafer 331 is ground using abrasive grains having a grit size of 500 or greater.

[0639] The grit size of the abrasive grains is preferably equal to or greater than 1000 and equal to or less than 5000. As a result, a plurality of grinding marks 338 are formed on second wafer main surface 333 of SiC semiconductor wafer 331 (see also FIG. 41B). As a result, second wafer main surface 333 of SiC semiconductor wafer 331 is flattened, and at the same time, SiC semiconductor wafer 331 is thinned.

[0640] Next, referring to FIG. 43C, a metal layer 341 is formed on the second wafer main surface 333 of the SiC semiconductor wafer 331 (step S2 in FIG. 42). In this embodiment, the metal layer 341 is made of a Ni layer. The Ni layer may be formed by a sputtering method. The thickness of the Ni layer may be 100 Å or more and 1000 Å or less.

[0641] Next, referring to Fig. 43D, an annealing process is performed on second wafer main surface 333 of SiC semiconductor wafer 331 (step S3 in Fig. 42). In this step, a laser annealing process is performed as an example of the annealing process.

[0642] In the laser annealing method, a pulsed laser beam having a laser diameter φ of 50 μm or more and 200 μm (for example, about 100 μm) is used. The pulsed laser beam is a UV laser beam having a wavelength in the ultraviolet region. The energy of the pulsed laser beam is 1.0 J / cm 2 More than 4.0J / cm 2 Less than (for example, 3.0 J / cm 2 degree).

[0643] The pulsed laser light is applied to the second wafer main surface 333 of the SiC semiconductor wafer 331 through the metal layer 341. In this embodiment, the pulsed laser light is applied to the second wafer main surface 333 of the SiC semiconductor wafer 331 while the irradiation position is moved along the orientation flat 335.

[0644] In the region of the second wafer main surface 333 of the SiC semiconductor wafer 331 into which the pulsed laser light is applied, one or more protrusions 315 are formed on the second wafer main surface 333 of the SiC semiconductor wafer 331 .

[0645] Furthermore, in the region of the second wafer main surface 333 of the SiC semiconductor wafer 331 where the pulsed laser light is applied, a modified layer 323 is formed in which the SiC of the SiC semiconductor wafer 331 is modified to have other properties. More specifically, the SiC of the SiC semiconductor wafer 331 is modified to Si by heating, causing C atoms to desorb and / or sublimate from the SiC.

[0646] This forms a modified layer 323 including a Si modified layer. The modified layer 323 may include a silicon amorphous layer. The modified layer 323 may include C atoms. One or more protrusions 315 formed on the second wafer main surface 333 may be formed by this modified layer 323.

[0647] Then, pulsed laser light is continuously applied in a direction along orientation flat 335, and a plurality of raised portions 315 are formed along orientation flat 335. As a result, one raised portion group 316 including a plurality of raised portions 315 and extending along the [11-20] direction is formed on second wafer main surface 333 of SiC semiconductor wafer 331.

[0648] When one raised portion group 316 is formed, the irradiation position of the pulsed laser beam is moved in the [1-100] direction. Then, the pulsed laser beam is again irradiated onto second wafer main surface 333 of SiC semiconductor wafer 331 while the irradiation position is moved along orientation flat 335.

[0649] As a result, another group of protrusions 316 extending substantially parallel to or parallel to one group of protrusions 316 is formed on the second wafer main surface 333 of the SiC semiconductor wafer 331.

[0650] In the laser annealing method, these steps are repeated until a plurality of raised portions 316 are formed over almost the entire area or the entire area of ​​second wafer main surface 333 of SiC semiconductor wafer 331 (see also FIG. 41B).

[0651] In this form, the metal layer 341 that has undergone laser annealing processing has a layered structure including a carbon layer 342, a NiSi (nickel silicide) layer 343, and a Ni layer 344, which are layered in this order from the second wafer main surface 333 side of the SiC semiconductor wafer 331.

[0652] That is, the laser annealing process includes a process of silicidating the metal layer 341 by reacting it with the SiC semiconductor wafer 331. More specifically, the laser annealing process includes a process of forming the NiSi layer 343.

[0653] In the laser annealing method, in addition to the NiSi layer 343, a carbon layer 342 containing C atoms is formed as a by-product in the metal layer 341. The carbon layer 342 is formed by the precipitation of C atoms that constituted SiC.

[0654] The carbon layer 342 and the NiSi layer 343 in the metal layer 341 can be the starting point for peeling. In other words, although the metal layer 341 can be used as the drain pad 113 as it is, the metal layer 341 has the problem of poor connection and an increase in resistance due to the poor connection. Therefore, it is preferable to form a metal layer different from the metal layer 341 as the drain pad 113.

[0655] The temperature applied to the metal layer 341 during the formation of the NiSi layer 343 is equal to or higher than the melting points of the gate pad 108, the gate fingers 109, and the source pad 110 (for example, 1000° C. or higher).

[0656] The laser annealing method can locally increase the temperature of second wafer main surface 333 of SiC semiconductor wafer 331, thereby eliminating the need to heat gate pad 108, gate fingers 109, and source pad 110. Therefore, melting of gate pad 108, gate fingers 109, and source pad 110 can be appropriately suppressed.

[0657] 43E, a step of removing metal layer 341 is performed. The step of removing metal layer 341 is performed until second wafer main surface 333 of SiC semiconductor wafer 331 is exposed.

[0658] In this step, first, the NiSi layer 343 and the Ni layer 344 in the metal layer 341 are removed (Step S4 in FIG. 42). The NiSi layer 343 and the Ni layer 344 may be removed by wet etching.

[0659] Next, referring to Fig. 43F, the carbon layer 342 in the metal layer 341 is removed (step S5 in Fig. 42). The carbon layer 342 may be removed by dry etching.

[0660] 43G, residues of NiSi layer 343 and Ni layer 344 attached to second wafer main surface 333 of SiC semiconductor wafer 331 are removed (step S6 in FIG. 42). NiSi layer 343 and Ni layer 344 may be removed by wet etching.

[0661] 43H, residue of carbon layer 342 attached to second wafer main surface 333 of SiC semiconductor wafer 331 is removed (step S7 in FIG. 42). Carbon layer 342 may be removed by dry etching.

[0662] Next, the native oxide film is removed from the second wafer main surface 333 of the SiC semiconductor wafer 331 (Step S8 in FIG. 42). The native oxide film may be removed by wet etching.

[0663] Thus, in this embodiment, the step of removing the Ni-containing layer (NiSi layer 343 and Ni layer 344) and the step of removing the carbon-containing layer (carbon layer 342) are repeated twice.

[0664] This makes it possible to properly remove metal layer 341. Furthermore, after the step of removing metal layer 341, second wafer main surface 333 of SiC semiconductor wafer 331, the resistance value of which has been reduced by the laser annealing treatment, is properly exposed.

[0665] Next, referring to FIG. 43I, drain pad 113 is formed on second wafer main surface 333 of SiC semiconductor wafer 331 (Step S9 in FIG. 42).

[0666] This step includes forming a Ti layer 324, a Ni layer 325, an Au layer 326, and an Ag layer 327 in this order on the second wafer main surface 333 of the SiC semiconductor wafer 331. The Ti layer 324, the Ni layer 325, the Au layer 326, and the Ag layer 327 may all be formed by sputtering.

[0667] In the drain pad 113, the Ti layer 324 is directly connected to the second wafer main surface 333 of the SiC semiconductor wafer 331. The Ti layer 324 collectively covers the plurality of protrusion groups 316, and forms ohmic contact with the plurality of protrusion groups 316 and with the plurality of spaces 320.

[0668] Next, the SiC semiconductor wafer 331 is cut along the peripheries (dicing lines 337) of the plurality of device formation regions 336. As a result, a plurality of semiconductor devices 311 are cut out from the SiC semiconductor wafer 331. Through the steps including those described above, the semiconductor device 311 is manufactured.

[0669] As described above, semiconductor device 311 can achieve the same effects as those described for semiconductor device 101. Furthermore, semiconductor device 311 can increase the connection area of ​​drain pad 113 with respect to second main surface 104 of SiC semiconductor layer 102 by ridge group 316, thereby improving electrical characteristics.

[0670] More specifically, the drain pad 113 forms an ohmic contact with the protrusion group 316. This makes it possible to obtain good ohmic characteristics between the SiC semiconductor layer 102 and the drain pad 113, thereby improving the electrical characteristics.

[0671] Furthermore, according to the semiconductor device 311, the drain pad 113 is directly connected to the second main surface 104 of the SiC semiconductor layer 102. More specifically, the drain pad 113 forms ohmic contact with the protrusion group 316 without a carbon layer therebetween. The drain pad 113 also forms ohmic contact with the protrusion group 316 without a silicide layer therebetween.

[0672] The carbon layer and the silicide layer are likely to become the starting point of peeling. Therefore, by using a structure in which the drain pad 113 is directly connected to the second main surface 104 of the SiC semiconductor layer 102, poor connection and an increase in resistance due to poor connection can be appropriately suppressed.

[0673] Fig. 44 is a bottom view corresponding to Fig. 35, showing a semiconductor device 351 according to the twenty-third embodiment of the present invention. In the following, structures corresponding to those described with respect to the semiconductor device 311 are given the same reference numerals, and descriptions thereof will be omitted.

[0674] Referring to FIG. 44, a semiconductor device 351 has a plurality of protrusion groups 316 including a first protrusion group 316A and a second protrusion group 316B.

[0675] The first raised portion group 316A includes a plurality of first raised portions 315A formed on the second main surface 104 of the SiC semiconductor layer 102. The plurality of first raised portions 315A are portions that are raised on the second main surface 104 of the SiC semiconductor layer 102 in the normal direction to the second main surface 104 of the SiC semiconductor layer 102.

[0676] The multiple first raised portions 315A are formed at intervals from one another along a first direction X and a second direction Y that intersects with the first direction X. Some of the multiple first raised portions 315A have first portions 317A that overlap with the first direction X when viewed from the first direction X.

[0677] In addition, the first raised portion 315A has a second portion 318A in which some of the multiple first raised portions 315A are formed spaced apart from the first portion 317A and overlap with the first direction X when viewed in the first direction.

[0678] The plurality of first raised portions 315A are continuously formed along the first direction X. More specifically, the plurality of first raised portions 315A have a scattered pattern in which they are scattered at intervals along the first direction X and the second direction Y.

[0679] The plurality of first raised portions 315A are continuously formed along the first direction X while maintaining this scattered pattern. In this embodiment, the scattered pattern of the plurality of first raised portions 315A is formed from the periphery of one side surface 105A of the SiC semiconductor layer 102 to the periphery of the other side surface 105C in plan view.

[0680] The first raised portion group 316A has a layout in which the plurality of raised portions 315 overlap in the first direction X when viewed from the first direction X. As a result, the first raised portion group 316A forms a first raised portion group region 319A extending in a band shape along the first direction X by a collective pattern of the plurality of raised portions 315 continuously scattered along the first direction X.

[0681] In other words, the first protrusion group region 319A includes a plurality of first protrusions 315A (first protrusion group 316A) formed in a strip-shaped region extending along the first direction X on the second main surface 104 of the SiC semiconductor layer 102.

[0682] The second raised portion group 316B includes a plurality of second raised portions 315B formed on the second main surface 104 of the SiC semiconductor layer 102. The plurality of second raised portions 315B are portions that rise on the second main surface 104 of the SiC semiconductor layer 102 in the normal direction to the second main surface 104 of the SiC semiconductor layer 102.

[0683] The multiple second raised portions 315B are formed at intervals from one another along the first direction X and a second direction Y that intersects with the first direction X. The second raised portion group 316B has first portions 317B where some of the multiple second raised portions 315B overlap in the second direction Y when viewed from the second direction Y.

[0684] In addition, the second raised portion group 316B has a second portion 318B in which some of the multiple second raised portions 315B are formed at a distance from the first portion 317B and overlap with the second direction Y when viewed in the second direction.

[0685] The plurality of second raised portions 315B are continuously formed along the second direction Y. More specifically, the plurality of second raised portions 315B have a scattered pattern in which they are scattered at intervals along the first direction X and the second direction Y.

[0686] The plurality of second raised portions 315B are continuously formed along the second direction Y while maintaining this scattered pattern. In this embodiment, the scattered pattern of the plurality of second raised portions 315B is formed from the periphery of the SiC semiconductor layer 102 on one side surface 105B side to the periphery of the other side surface 105D side in plan view.

[0687] The second raised portion group 316B has a layout in which the multiple second raised portions 315B overlap in the second direction Y when viewed from the second direction Y. As a result, the second raised portion group 316B forms a second raised portion group region 319B extending in a band shape along the second direction Y by a collective pattern of the multiple second raised portions 315B continuously scattered along the second direction Y.

[0688] In other words, the second ridge group region 319B includes a plurality of second ridges 315B (second ridge group 316B) formed in a strip-shaped region extending along the second direction Y on the second main surface 104 of the SiC semiconductor layer 102.

[0689] The second protrusion group 316B (second protrusion group region 319B) crosses the first protrusion group 316A (first protrusion group region 319A). As a result, an intersection region 352 where the first protrusion group 316A (first protrusion group region 319A) and the second protrusion group 316B (second protrusion group region 319B) intersect with each other is formed on the second main surface 104 of the SiC semiconductor layer 102.

[0690] In this embodiment, a plurality of first raised portion groups 316A are formed at intervals along the second direction Y on the second main surface 104 of the SiC semiconductor layer 102. That is, the scattered pattern of the plurality of first raised portions 315A is formed discontinuously in the second direction Y.

[0691] In this embodiment, the second raised portion group 316B is formed at intervals along the first direction X on the second main surface 104 of the SiC semiconductor layer 102. That is, the scattered pattern of the second raised portions 315B is formed discontinuously in the first direction X.

[0692] Therefore, in this embodiment, the intersection regions 352 are formed in a matrix array spaced apart from one another along the first direction X and the second direction Y. Furthermore, the first ridge group 316A and the second ridge group 316B define spaces 320. The spaces 320 are formed in a matrix array spaced apart from one another along the first direction X and the second direction Y.

[0693] The first ridges 315A and the second ridges 315B may overlap each other in the intersection region 352. The thicknesses of the first ridges 315A and the second ridges 315B formed in the intersection region 352 may be greater than the thicknesses of the first ridges 315A and the second ridges 315B formed in regions outside the intersection region 352.

[0694] Furthermore, the number of the first ridges 315A and the second ridges 315B formed in the intersection region 352 may be greater than the number of the first ridges 315A and the second ridges 315B formed in the region outside the intersection region 352.

[0695] The first direction X may be set to the [11-20] direction, and the second direction Y may be set to the [1-100] direction. In other words, the first ridge group 316A (first ridge group region 319A) may be formed substantially parallel to or parallel to the [11-20] direction, and the second ridge group 316B (second ridge group region 319B) may be formed substantially parallel to or parallel to the [1-100] direction.

[0696] The first direction X may be set to the [1-100] direction, and the second direction Y may be set to the [11-20] direction. In other words, the first ridge group 316A (first ridge group region 319A) may be formed substantially parallel to or parallel to the [1-100] direction, and the second ridge group 316B (second ridge group region 319B) may be formed substantially parallel to or parallel to the [11-20] direction.

[0697] The first raised portion 315A and the first raised portion group 316A correspond to the raised portion 315 and the raised portion group 316 according to the 22nd embodiment. The description of the raised portion 315 and the raised portion group 316 according to the 22nd embodiment applies mutatis mutandis to the description of the first raised portion 315A and the first raised portion group 316A, and other specific descriptions of the first raised portion 315A and the first raised portion group 316A will be omitted.

[0698] The second raised portion 315B and the second raised portion group 316B correspond to the raised portion 315 and the raised portion group 316 according to the 22nd embodiment. The description of the raised portion 315 and the raised portion group 316 according to the 22nd embodiment applies mutatis mutandis to other descriptions of the second raised portion 315B and the second raised portion group 316B, and other specific descriptions of the second raised portion 315B and the second raised portion group 316B will be omitted.

[0699] In this embodiment, the drain pad 113 covers the first protrusion group 316A and the second protrusion group 316B on the second main surface 104 of the SiC semiconductor layer 102. In this embodiment, the drain pad 113 collectively covers the plurality of first protrusion groups 316A and the plurality of second protrusion groups 316B.

[0700] The drain pad 113 is formed in the form of a film conforming to the outer surfaces of the first ridge group 316A (outer surfaces of the first ridges 315A), the outer surfaces of the second ridge group 316B (outer surfaces of the second ridges 315B), and the inner surfaces of the grooves 321.

[0701] As a result, although not shown, raised portions 113a are formed in portions covering the first raised portion group 316A (first raised portion 315A) and the second raised portion group 316B (second raised portion 315B) on the outer surface of the drain pad 113. In addition, recesses 113b are formed in portions covering the grooves 321 on the outer surface of the drain pad 113.

[0702] The drain pad 113 forms an ohmic contact with the second main surface 104 of the SiC semiconductor layer 102. More specifically, the drain pad 113 forms an ohmic contact with the first protrusion group 316A and the second protrusion group 316B.

[0703] More specifically, the drain pad 113 forms ohmic contact with the plurality of first ridge groups 316A and the plurality of second ridge groups 316B. In this embodiment, the drain pad 113 also forms ohmic contact with the space 320.

[0704] The portion of the drain pad 113 covering the first ridge group 316A and the second ridge group 316B engages with the uneven portion defined by the plurality of first ridge groups 316A, the plurality of second ridge groups 316B and the plurality of grooves 321.

[0705] That is, the contact area of ​​drain pad 113 with second main surface 104 of SiC semiconductor layer 102 is increased by first ridge group 316A, second ridge group 316B, and grooves 321. This increases the adhesion of drain pad 113 with second main surface 104 of SiC semiconductor layer 102.

[0706] The semiconductor device 351 having such a structure is manufactured by carrying out the following steps in the above-mentioned laser annealing step (step S3 in FIG. 42).

[0707] First, a laser annealing process is used to form a plurality of first ridge groups 316A along a direction substantially parallel or parallel to the orientation flat 335. Next, a laser annealing process is used to form a plurality of second ridge groups 316B along a direction intersecting (orthogonal to) the orientation flat 335.

[0708] In this step, a plurality of first raised portion groups 316A may be formed in a direction intersecting (orthogonal to) the orientation flat 335, and a plurality of second raised portion groups 316B may be formed substantially parallel to or parallel to the orientation flat 335. Thereafter, through steps S4 to S9 in FIG. 42, the semiconductor device 351 is manufactured.

[0709] The first ridge group 316A and the second ridge group 316B may be formed in any order. Thus, the first ridge group 316A may be formed after the second ridge group 316B. The first ridge group 316A and the second ridge group 316B may be formed alternately.

[0710] As described above, the semiconductor device 351 can also achieve the same effects as those described for the semiconductor device 311.

[0711] Fig. 45 is a cross-sectional view corresponding to Fig. 39, showing a semiconductor device 361 according to the twenty-fourth embodiment of the present invention. Fig. 46 is an enlarged view of region XLVI shown in Fig. 45. In the following, structures corresponding to those described with respect to semiconductor device 311 are given the same reference numerals, and descriptions thereof will be omitted.

[0712] In semiconductor device 361, drain pad 113 has a three-layer structure including Ni layer 325, Au layer 326, and Ag layer 327 stacked in this order on second main surface 104 of SiC semiconductor layer 102. That is, drain pad 113 is formed by omitting the step of forming Ti layer 324 in step S9 of FIG.

[0713] The Ni layer 325 is directly connected to the second main surface 104 of the SiC semiconductor layer 102. The Ni layer 325 covers the plurality of protrusion groups 316 collectively.

[0714] The Ni layer 325 forms ohmic contact with the ridges 316 and with the spaces 320. The Au layer 326 covers almost the entire area or the entirety of the Ni layer 325. The Ag layer 327 covers almost the entire area or the entirety of the Au layer 326.

[0715] As described above, the semiconductor device 361 can also achieve the same effects as those described for the semiconductor device 311. In the semiconductor device 361, the drain pad 113 may have a single-layer structure made of the Ni layer 325.

[0716] Fig. 47 is a cross-sectional view corresponding to Fig. 39, showing a semiconductor device 371 according to the twenty-fifth embodiment of the present invention. Fig. 48 is an enlarged view of region XLVIII shown in Fig. 47. In the following, structures corresponding to those described with respect to the semiconductor device 311 are given the same reference numerals, and descriptions thereof will be omitted.

[0717] In the semiconductor device 371, the drain pad 113 includes a metal layer 341, an Au layer 326, and an Ag layer 327. In this embodiment, the metal layer 341 has a layered structure including a carbon layer 342, a NiSi layer 343, and a Ni layer 344, which are layered in this order from the second main surface 104 side of the SiC semiconductor layer 102.

[0718] Metal layer 341 is connected to second main surface 104 of SiC semiconductor layer 102. Metal layer 341 covers a plurality of protrusion groups 316 collectively.

[0719] The metal layer 341 forms ohmic contact with the ridges 316 and with the spaces 320. The Au layer 326 covers almost the entire area or the entire region of the metal layer 341. The Ag layer 327 covers almost the entire area or the entire region of the Au layer 326.

[0720] 42. The semiconductor device 371 is formed by omitting the step of removing the metal layer 341 (see steps S4 to S8 shown in FIG. 42). In the semiconductor device 371, the Au layer 326 and the Ag layer 327 are formed on the metal layer 341 in step S9 in FIG.

[0721] As described above, in the semiconductor device 371, the drain pad 113 includes the carbon layer 342 and the NiSi layer 343. Although the connection strength of the drain pad 113 cannot be increased as much as in the semiconductor device 311, the semiconductor device 371 can achieve substantially the same effects as those described for the semiconductor device 311. In the semiconductor device 371, the drain pad 113 may be formed of only the metal layer 341.

[0722] Although the twenty-second to twenty-fifth embodiments of the present invention have been described above, the twenty-second to twenty-fifth embodiments of the present invention can also be implemented in other forms.

[0723] In the above-described twenty-second to twenty-fifth embodiments, examples have been described in which the SiC semiconductor layer 102 has a layered structure including the SiC semiconductor substrate 111 and the SiC epitaxial layer 112.

[0724] However, the SiC semiconductor layer 102 may have a single-layer structure made of the SiC semiconductor substrate 111. The SiC semiconductor layer 102 may have a single-layer structure made of the SiC epitaxial layer 112.

[0725] In the above-described twenty-second to twenty-fifth embodiments, examples have been described in which the SiC epitaxial layer 112 having the high-concentration region 112a and the low-concentration region 112b is formed by epitaxial growth. However, the SiC epitaxial layer 112 can also be formed by the following process.

[0726] First, an SiC epitaxial layer 112 having a relatively low n-type impurity concentration is formed by epitaxial growth. Next, an n-type impurity is introduced into the surface layer of the SiC epitaxial layer 112 by ion implantation. This results in the formation of an SiC epitaxial layer 112 having a high-concentration region 112a and a low-concentration region 112b.

[0727] In the above-described twenty-second to twenty-fifth embodiments, examples have been described in which the gate electrode layer 132 and the gate wiring layer 133 include p-type polysilicon doped with p-type impurities. However, when an increase in the gate threshold voltage Vth is not important, the gate electrode layer 132 and the gate wiring layer 133 may include n-type polysilicon doped with n-type impurities instead of p-type polysilicon.

[0728] That is, the low-resistance electrode layer 134 may include n-type polycide. The low-resistance electrode layer 134 may be formed by silicidating a portion of the gate electrode layer 132 (n-type polysilicon) that forms a surface layer with a metal material. In this case, it is possible to reduce the gate resistance.

[0729] In the above-described 22nd to 25th embodiments, a structure in which the conductivity type of each semiconductor portion is reversed may be adopted, that is, the p-type portion may be made n-type, and the n-type portion may be made p-type.

[0730] In the above-described 22nd to 25th embodiments, n + Instead of the SiC semiconductor substrate 111, + Alternatively, a SiC semiconductor substrate (111) of this type may be employed. In this case, in the explanations of the 22nd to 25th embodiments, "source" should be read as "emitter" and "drain" should be read as "collector."

[0731] Fig. 49 is a top view showing a semiconductor device 401 according to the 26th embodiment of the present invention. Fig. 50 is a top view showing the semiconductor device 401 shown in Fig. 49, with the resin layer 416 removed.

[0732] 49 and 50, a semiconductor device 401 has a SiC semiconductor layer 402 including a SiC (silicon carbide) single crystal. The SiC semiconductor layer 402 may include a 4H—SiC single crystal.

[0733] The 4H—SiC single crystal has an off-angle tilted from the

[0001] plane by an angle of 10° or less with respect to the [11-20] direction. The off-angle may be 0° or more and 4° or less. The off-angle may be greater than 0° and less than 4°. The off-angle is typically set to 2° or 4°, more specifically, in the range of 2°±0.2° or 4°±0.4°.

[0734] In this embodiment, the SiC semiconductor layer 402 is formed in the shape of a rectangular parallelepiped chip. The SiC semiconductor layer 402 has a first main surface 403 on one side, a second main surface 404 on the other side, and side surfaces 405A, 405B, 405C, and 405D connecting the first main surface 403 and the second main surface 404. The first main surface 403 and the second main surface 404 are formed in a quadrangular shape (rectangular in this embodiment) in a plan view seen from the normal direction thereof (hereinafter simply referred to as "plan view").

[0735] Side surface 405A faces side surface 405C. Side surface 405B faces side surface 405D. Side surfaces 405A to 405D each extend in a plane along the normal direction of first main surface 403 and second main surface 404. The length of side surfaces 405A to 405D may each be 1 mm or more and 10 mm or less (for example, 2 mm or more and 5 mm or less).

[0736] The SiC semiconductor layer 402 has an active region 406 and an outer region 407. The active region 406 is a region in which a vertical MISFET is formed. The outer region 407 is a region outside the active region 406.

[0737] In plan view, active region 406 is set in the center of SiC semiconductor layer 402 at a distance inward from side surfaces 405A to 405D of SiC semiconductor layer 402. Active region 406 is set in a quadrangular shape (rectangular in this embodiment) having four sides parallel to side surfaces 405A to 405D of SiC semiconductor layer 402 in plan view.

[0738] Outer region 407 is set in a region between side surfaces 405A to 405D of SiC semiconductor layer 402 and the periphery of active region 406. Outer region 407 is set in an endless shape (quadratic ring shape) surrounding active region 406 in plan view.

[0739] A main surface gate electrode 408 and a main surface source electrode 409 are formed on the first main surface 403 of the SiC semiconductor layer 402 .

[0740] The main surface gate electrode 408 includes a gate pad 410 and gate fingers 411. The gate pad 410 and gate fingers 411 are disposed in the active region 406 in this embodiment.

[0741] The gate pad 410 is formed, in plan view, along the side surface 405A of the SiC semiconductor layer 402. The gate pad 410 is formed, in plan view, along the central region of the side surface 405A of the SiC semiconductor layer 402.

[0742] Gate pad 410 may be formed, in plan view, along a corner connecting any two of side surfaces 405A to 405D of SiC semiconductor layer 402. Gate pad 410 is formed in a quadrangular shape in plan view.

[0743] The gate fingers 411 include an outer gate finger 411A and an inner gate finger 411B.

[0744] The outer gate fingers 411A are drawn out from the gate pad 410 and extend in a strip shape along the periphery of the active region 406. In this embodiment, the outer gate fingers 411A are formed along three side surfaces 405A, 405B, and 405D of the SiC semiconductor layer 402 so as to partition the inner region of the active region 406 from three directions.

[0745] The outer gate finger 411A has a pair of open ends 412A, 412B. The pair of open ends 412A, 412B of the outer gate finger 411A are formed in a region facing the gate pad 410, with an inner region of the active region 406 in between. In this embodiment, the pair of open ends 412A, 412B of the outer gate finger 411A are formed along the side surface 405C of the SiC semiconductor layer 402.

[0746] The inner gate finger 411B is drawn out from the gate pad 410 to an inner region of the active region 406. The inner gate finger 411B extends in a strip shape in the inner region of the active region 406. The inner gate finger 411B extends from the side surface 405A toward the side surface 405C.

[0747] In this embodiment, the main surface source electrode 409 includes a source pad 413 , a source lead-out wiring 414 and a source connection portion 415 .

[0748] The source pad 413 is formed in the active region 406 at a distance from the gate pad 410 and the gate fingers 411. The source pad 413 is formed in a C-shape (an inverted C-shape in FIGS. 49 and 50) in plan view so as to cover the C-shaped region (an inverted C-shape in FIGS. 49 and 50) defined by the gate pad 410 and the gate fingers 411.

[0749] The source lead-out wiring 414 is formed in the outer region 407. The source lead-out wiring 414 extends in a strip shape along the active region 406. In this embodiment, the source lead-out wiring 414 is formed in an endless shape (a square loop) surrounding the active region 406 in a plan view. The source lead-out wiring 414 is electrically connected to the SiC semiconductor layer 402 in the outer region 407.

[0750] The source connection portion 415 connects the source pad 413 and the source lead-out line 414. The source connection portion 415 is provided in a region between a pair of open ends 412A, 412B of the outer gate finger 411A. The source connection portion 415 extends from the source pad 413 across the boundary region between the active region 406 and the outer region 407 and is connected to the source lead-out line 414.

[0751] The MISFET formed in the active region 406 includes an npn-type parasitic bipolar transistor due to its structure. When an avalanche current generated in the outer region 407 flows into the active region 406, the parasitic bipolar transistor turns on. In this case, there is a possibility that the control of the MISFET becomes unstable due to, for example, latch-up.

[0752] Therefore, in the semiconductor device 401, the structure of the main surface source electrode 409 is utilized to form an avalanche current absorption structure that absorbs the avalanche current generated in the region outside the active region 406.

[0753] More specifically, the avalanche current generated in the outer region 407 is absorbed by the source lead-out wiring 414. As a result, the avalanche current reaches the source pad 413 via the source connection part 415. If a conductor for external connection (e.g., a bonding wire) is connected to the source pad 413, the avalanche current is extracted by this conductor.

[0754] This makes it possible to prevent the parasitic bipolar transistor from turning on due to an undesired current generated in the outer region 407. This makes it possible to prevent latch-up, thereby improving the stability of control of the MISFET.

[0755] A gate voltage is applied to the gate pad 410 and the gate fingers 411. The gate voltage may be 10 V or more and 50 V or less (for example, about 30 V). A source voltage is applied to the source pad 413. The source voltage may be a reference voltage (for example, a GND voltage).

[0756] A resin layer 416 is formed on the first main surface 403 of the SiC semiconductor layer 402 (more specifically, on an interlayer insulating layer 491, which will be described later). For clarity, the resin layer 416 is shown by hatching in Figure 49. The resin layer 416 covers the gate pad 410, the gate fingers 411, and the source pad 413.

[0757] The resin layer 416 may contain a negative or positive photosensitive resin. In this embodiment, the resin layer 416 contains polybenzoxazole, which is an example of a positive photosensitive resin. The resin layer 416 may also contain polyimide, which is an example of a negative photosensitive resin.

[0758] A gate pad opening 417 and a source pad opening 418 are formed in the resin layer 416. The gate pad opening 417 exposes the gate pad 410. The source pad opening 418 exposes the source pad 413.

[0759] Peripheral edge portion 419 of resin layer 416 is formed at a distance inward from side surfaces 405A to 405D of SiC semiconductor layer 402. This allows resin layer 416 to expose the peripheral edge portion of SiC semiconductor layer 402 (more specifically, interlayer insulating layer 491, which will be described later).

[0760] Peripheral edge 419 of resin layer 416 is a portion where dicing streets are formed when semiconductor device 401 is cut out from one SiC semiconductor wafer. By exposing the peripheral edge of SiC semiconductor layer 402 from resin layer 416, it is no longer necessary to physically cut resin layer 416.

[0761] Therefore, semiconductor devices 401 can be smoothly cut out from one SiC semiconductor wafer. Side surfaces 405A to 405D of SiC semiconductor layer 402 may be cut surfaces (ground surfaces). Side surfaces 405A to 405D of SiC semiconductor layer 402 may have grinding marks.

[0762] Fig. 51 is an enlarged view of region LI shown in Fig. 50 and is a diagram for explaining the structure of first main surface 403 of SiC semiconductor layer 402. Fig. 52 is a cross-sectional view taken along line LII-LII shown in Fig. 51 and showing a first embodiment of gate trench 431 and a first embodiment of source trench 441. Fig. 53 is a cross-sectional view taken along line LIII-LIII shown in Fig. 51 and showing a first embodiment of gate wiring layer 436. Fig. 54 is an enlarged view of region LIV shown in Fig. 52.

[0763] Fig. 55 is a cross-sectional view taken along the line LV-LV shown in Fig. 50, illustrating a first example of the active sidewall 464, a first example of the outer main surface 462, a first example of the sidewall 482, a first example of the diode region 471, a first example of the outer deep well region 472, a first example of the field limit structure 473, and a first example of the anchor hole 495. Fig. 56 is an enlarged view of region LVI shown in Fig. 55, illustrating the first example of the active sidewall 464 and the first example of the outer main surface 462.

[0764] 51 to 55, in this embodiment, SiC semiconductor layer 402 is + The SiC semiconductor layer 402 has a layered structure including an n-type SiC semiconductor substrate 421 and an n-type SiC epitaxial layer 422. The SiC semiconductor substrate 421 forms the second main surface 404 of the SiC semiconductor layer 402.

[0765] The first main surface 403 of the SiC semiconductor layer 402 is formed by the SiC epitaxial layer 422. The second main surface 404 of the SiC semiconductor layer 402 may be a ground surface. The second main surface 404 of the SiC semiconductor layer 402 may have grinding marks.

[0766] The thickness of the SiC semiconductor substrate 421 may be equal to or greater than 1 μm and less than 1000 μm. The thickness of the SiC semiconductor substrate 421 may be equal to or greater than 5 μm. The thickness of the SiC semiconductor substrate 421 may be equal to or greater than 25 μm. The thickness of the SiC semiconductor substrate 421 may be equal to or greater than 50 μm. The thickness of the SiC semiconductor substrate 421 may be equal to or greater than 100 μm.

[0767] The thickness of the SiC semiconductor substrate 421 may be 700 μm or less. The thickness of the SiC semiconductor substrate 421 may be 500 μm or less. The thickness of the SiC semiconductor substrate 421 may be 400 μm or more. The thickness of the SiC semiconductor substrate 421 may be 300 μm or less.

[0768] The thickness of the SiC semiconductor substrate 421 may be 250 μm or less. The thickness of the SiC semiconductor substrate 421 may be 200 μm or less. The thickness of the SiC semiconductor substrate 421 may be 150 μm or less. The thickness of the SiC semiconductor substrate 421 may be 100 μm or less.

[0769] The thickness of the SiC semiconductor substrate 421 is preferably 150 μm or less. By reducing the thickness of the SiC semiconductor substrate 421, the resistance value can be reduced by shortening the current path.

[0770] The thickness of the SiC epitaxial layer 422 may be 1 μm or more and 100 μm or less. The thickness of the SiC epitaxial layer 422 may be 5 μm or more. The thickness of the SiC epitaxial layer 422 may be 10 μm or more.

[0771] The thickness of the SiC epitaxial layer 422 may be 50 μm or less. The thickness of the SiC epitaxial layer 422 may be 40 μm or less. The thickness of the SiC epitaxial layer 422 may be 30 μm or less.

[0772] The thickness of the SiC epitaxial layer 422 may be 20 μm or less. The thickness of the SiC epitaxial layer 422 is preferably 15 μm or less. The thickness of the SiC epitaxial layer 422 is preferably 10 μm or less.

[0773] The n-type impurity concentration of the SiC epitaxial layer 422 is equal to or lower than the n-type impurity concentration of the SiC semiconductor substrate 421. The n-type impurity concentration of the SiC epitaxial layer 6 is 1.0×10 15 cm -3 Over 1.0 x 10 18 cm -3 It may be the following:

[0774] In this embodiment, the SiC epitaxial layer 422 has a plurality of regions having different n-type impurity concentrations along the normal direction of the first main surface 403 of the SiC semiconductor layer 402. More specifically, the SiC epitaxial layer 422 includes a high-concentration region 422a having a relatively high n-type impurity concentration, and a low-concentration region 422b having a lower n-type impurity concentration than the high-concentration region 422a.

[0775] The high concentration region 422a is formed in a region on the first main surface 403 side. The low concentration region 422b is formed in a region on the second main surface 404 side of the SiC semiconductor layer 402 with respect to the high concentration region 422a.

[0776] The n-type impurity concentration of the high concentration region 422a is 1×10 16 cm -3 More than 1×10 18 cm -3 The n-type impurity concentration of the low concentration region 422b may be 1×10 15 cm -3 More than 1×10 16 cm -3 It may be the following:

[0777] The thickness of the high-concentration region 422a is equal to or less than the thickness of the low-concentration region 422b. More specifically, the thickness of the high-concentration region 422a is less than the thickness of the low-concentration region 422b. In other words, the thickness of the high-concentration region 422a is less than half the total thickness of the SiC epitaxial layer 422.

[0778] A drain pad 423 serving as a second main surface electrode is connected to the second main surface 404 of the SiC semiconductor layer 402. The maximum voltage that can be applied between the source pad 413 and the drain pad 423 in the off state may be 1000 V or more and 10000 V or less.

[0779] Drain pad 423 may include at least one of a Ti layer, a Ni layer, an Au layer, and an Ag layer, and may have a four-layer structure including a Ti layer, a Ni layer, an Au layer, and an Ag layer stacked in this order on second main surface 404 of SiC semiconductor layer 402.

[0780] The SiC semiconductor substrate 421 is formed as a drain region 424 of the MISFET. The SiC epitaxial layer 422 is formed as a drift region 425 of the MISFET.

[0781] In the active region 406, a p-type body region 426 is formed in a surface layer portion of the first main surface 403 of the SiC semiconductor layer 402. The body region 426 defines the active region 406.

[0782] That is, in this embodiment, the body region 426 is formed over the entire region where the active region 406 is formed on the first main surface 403 of the SiC semiconductor layer 402. The p-type impurity concentration of the body region 426 is 1×10 17 cm -3 More than 1×10 20 cm -3 It may be the following:

[0783] In the active region 406, a plurality of gate trenches 431 are formed in a surface layer portion of the first main surface 403 of the SiC semiconductor layer 402. The plurality of gate trenches 431 are formed at intervals along an arbitrary first direction X. The plurality of gate trenches 431 are formed in strip shapes extending along a second direction Y intersecting the first direction X.

[0784] More specifically, the first direction X is a direction along the side surfaces 405B and 405D of the SiC semiconductor layer 402. The second direction Y is a direction perpendicular to the first direction X. The second direction Y is also a direction along the side surfaces 405A and 405C of the SiC semiconductor layer 402.

[0785] The gate trenches 431 are formed in a stripe pattern in a plan view. In this embodiment, each gate trench 431 extends in a strip shape from the peripheral edge on one side (side surface 405B side) of the active region 406 to the peripheral edge on the other side (side surface 405D side).

[0786] Each gate trench 431 crosses the middle portion between one peripheral edge and the other peripheral edge of the active region 406. One end of each gate trench 431 is located at one peripheral edge of the active region 406. The other end of each gate trench 431 is located at the other peripheral edge of the active region 406.

[0787] The first direction X may be set to the [11-20] direction ([-1-120] direction). In this case, each gate trench 431 may extend along the [11-20] direction. The first direction X may be set to the [-1100] direction ([1-100] direction) perpendicular to the [11-20] direction. In this case, each gate trench 431 may extend along the [-1100] direction ([1-100] direction).

[0788] Each gate trench 431 has a length on the order of millimeters. That is, the length of the gate trench 431 is the length from the end of the gate trench 431 and the gate finger 411 on the connection side to the opposite end in the cross section shown in FIG.

[0789] The length of each gate trench 431 may be 0.5 mm or more. In this embodiment, the length of each gate trench 431 is 1 mm or more and 10 mm or less (e.g., 2 mm or more and 5 mm or less). The total length of one or more gate trenches 431 per unit area is 0.5 μm / μm. 2 More than 0.75μm / μm 2 It may be the following:

[0790] Each gate trench 431 integrally includes an active trench portion 431a and a contact trench portion 431b. The active trench portion 431a is a portion of the active region 406 that is along the channel region of the MISFET.

[0791] The contact trench portion 431b is a portion of the gate trench 431 that is mainly intended to make contact with the gate finger 411. The contact trench portion 431b is drawn out from the active trench portion 431a to the periphery of the active region 406. The contact trench portion 431b is formed in a region directly below the gate finger 411. The amount of drawing of the contact trench portion 431b is optional.

[0792] Each gate trench 431 penetrates the body region 426 and reaches the SiC epitaxial layer 422. The bottom wall of each gate trench 431 is located within the SiC epitaxial layer 422.

[0793] More specifically, the bottom wall of each gate trench 431 is located in a high concentration region 422a of the SiC epitaxial layer 422. The bottom wall of the gate trench 431 may be formed parallel to the first main surface 403 of the SiC semiconductor layer 402.

[0794] The sidewall of the gate trench 431 may extend along the normal direction of the first main surface 403 of the SiC semiconductor layer 402. In other words, the sidewall of the gate trench 431 may be formed substantially perpendicular to the first main surface 403 of the SiC semiconductor layer 402.

[0795] The depth of gate trench 431 may be 0.5 μm or more and 3 μm or less (for example, about 1 μm) in the normal direction to first main surface 403 of SiC semiconductor layer 402. The depth of gate trench 431 is preferably 0.5 μm or more and 1.0 μm or less.

[0796] The width in the first direction of the gate trench 431 may be 0.1 μm or more and 2 μm or less (for example, about 0.5 μm). The width in the first direction of the gate trench 431 is preferably 0.1 μm or more and 0.5 μm or less.

[0797] 54 , opening edge portion 432 of each gate trench 431 includes an inclined portion 433 that slopes downward from first main surface 403 of SiC semiconductor layer 402 toward the inside of gate trench 431. Opening edge portion 432 of gate trench 431 is a corner that connects first main surface 403 of SiC semiconductor layer 402 and a sidewall of gate trench 431.

[0798] In this embodiment, the inclined portion 433 is formed in a concave curved shape directed toward the inside of the SiC semiconductor layer 402. The inclined portion 433 may be formed in a convex curved shape directed toward the inside of the gate trench 431.

[0799] The electric field at the opening edge 432 of the gate trench 431 is dispersed along the inclined portion 433. This makes it possible to alleviate the electric field concentration at the opening edge 432 of the gate trench 431.

[0800] A gate insulating layer 434 and a gate electrode layer 435 are formed in each gate trench 431. In FIG. 51, the gate insulating layer 434 and the gate electrode layer 435 are shown by hatching for clarity.

[0801] The gate insulating layer 434 includes silicon oxide. The gate insulating layer 434 may include other insulating films such as silicon nitride. The gate insulating layer 434 is formed in the form of a film along the inner wall surface of the gate trench 431 so as to define a recessed space within the gate trench 431.

[0802] The gate insulating layer 434 includes a first region 434a, a second region 434b, and a third region 434c. The first region 434a is formed along the sidewall of the gate trench 431. The second region 434b is formed along the bottom wall of the gate trench 431. The third region 434c is formed along the first main surface 403 of the SiC semiconductor layer 402.

[0803] The thickness T1 of the first region 434a is smaller than the thickness T2 of the second region 434b and the thickness T3 of the third region 434c. The ratio T2 / T1 of the thickness T2 of the second region 434b to the thickness T1 of the first region 434a may be greater than or equal to 2 and less than or equal to 5. The ratio T3 / T1 of the thickness T3 of the third region 434c to the thickness T1 of the first region 434a may be greater than or equal to 2 and less than or equal to 5.

[0804] The thickness T1 of the first region 434a may be 0.01 μm or more and 0.2 μm or less, the thickness T2 of the second region 434b may be 0.05 μm or more and 0.5 μm or less, and the thickness T3 of the third region 434c may be 0.05 μm or more and 0.5 μm or less.

[0805] By forming the first region 434a of the gate insulating layer 434 thin, it is possible to suppress an increase in carriers induced in the region near the sidewall of the gate trench 431 in the body region 426. This makes it possible to suppress an increase in channel resistance. By forming the second region 434b of the gate insulating layer 434 thick, it is possible to alleviate electric field concentration on the bottom wall of the gate trench 431.

[0806] By forming the third region 434c of the gate insulating layer 434 thick, it is possible to improve the breakdown voltage of the gate insulating layer 434 in the vicinity of the opening edge portion 432 of the gate trench 431. Furthermore, by forming the third region 434c thick, it is possible to prevent the third region 434c from being lost by an etching method.

[0807] This can prevent the first region 434a from being removed by etching due to the disappearance of the third region 434c. As a result, the gate electrode layer 435 can be appropriately opposed to the SiC semiconductor layer 402 (body region 426) with the gate insulating layer 434 interposed therebetween.

[0808] The gate insulating layer 434 further includes a bulging portion 434d that bulges toward the inside of the gate trench 431 at the opening edge portion 432 of the gate trench 431. The bulging portion 434d is formed at a corner portion that connects the first region 434a and the third region 434c of the gate insulating layer 434.

[0809] The bulging portion 434d protrudes in a curved shape toward the inside of the gate trench 431. The bulging portion 434d narrows the opening of the gate trench 431 at an opening edge portion 432 of the gate trench 431.

[0810] The bulging portion 434d improves the dielectric strength of the gate insulating layer 434 at the opening edge portion 432. Of course, the gate insulating layer 434 may be formed without the bulging portion 434d. The gate insulating layer 434 may be formed to have a uniform thickness.

[0811] The gate electrode layer 435 is embedded in the gate trench 431 with the gate insulating layer 434 sandwiched therebetween. More specifically, the gate electrode layer 435 is embedded in the gate trench 431 so as to fill a recessed space defined by the gate insulating layer 434. The gate electrode layer 435 is controlled by a gate voltage.

[0812] The gate electrode layer 435 is formed in a wall shape extending along the normal direction of the first main surface 403 of the SiC semiconductor layer 402 in a cross-sectional view orthogonal to the extension direction of the gate trench 431. The gate electrode layer 435 has an upper end portion located on the opening side of the gate trench 431.

[0813] The upper end of the gate electrode layer 435 is formed in a curved shape recessed toward the bottom wall of the gate trench 431. The upper end of the gate electrode layer 435 has a constricted portion that is constricted along the bulging portion 434d of the gate insulating layer 434.

[0814] The cross-sectional area of ​​the gate electrode layer 435 (the cross-sectional area perpendicular to the direction in which the gate trench 431 extends) is 0.05 μm 2 More than 0.5μm 2 The cross-sectional area of ​​the gate electrode layer 435 is defined as the product of the depth of the gate electrode layer 435 and the width of the gate electrode layer 435.

[0815] The depth of the gate electrode layer 435 is the distance from the upper end to the lower end of the gate electrode layer 435. The width of the gate electrode layer 435 is the width of the trench at the midpoint between the upper end and the lower end of the gate electrode layer 435. When the upper end is a curved surface (in this embodiment, a curved shape recessed downward), the position of the upper end of the gate electrode layer 435 is the midpoint in the depth direction on the upper surface of the gate electrode layer 435.

[0816] The gate electrode layer 435 may include conductive polysilicon. The gate electrode layer 435 may include n-type polysilicon or p-type polysilicon, as examples of conductive polysilicon. The gate electrode layer 435 may include at least one of tungsten, aluminum, copper, an aluminum alloy, or a copper alloy, instead of conductive polysilicon.

[0817] 51 and 53, a gate wiring layer 436 is formed in the active region 406. The gate wiring layer 436 is electrically connected to the gate pad 410 and the gate finger 411. In FIG. 53, the gate wiring layer 436 is shown by hatching for clarity.

[0818] The gate wiring layer 436 is formed on the first main surface 403 of the SiC semiconductor layer 402. More specifically, the gate wiring layer 436 is formed on the third region 434c of the gate insulating layer 434.

[0819] In this embodiment, the gate wiring layer 436 is formed along the gate fingers 411. More specifically, the gate wiring layer 436 is formed along three side surfaces 405A, 405B, and 405D of the SiC semiconductor layer 402 so as to partition the inner region of the active region 406 from three directions.

[0820] The gate wiring layer 436 is connected to the gate electrode layer 435 exposed from the contact trench portion 431b of each gate trench 431. In this embodiment, the gate wiring layer 436 is formed by an extension portion that is extended from the gate electrode layer 435 onto the first main surface 403 of the SiC semiconductor layer 402. An upper end portion of the gate wiring layer 436 is connected to an upper end portion of the gate electrode layer 435.

[0821] 51, 52, and 54, a plurality of source trenches (trench) 441 are formed in first main surface 403 of SiC semiconductor layer 402 in active region 406. Each source trench 441 is formed in a region between two gate trenches 431 adjacent to each other.

[0822] The source trenches 441 are each formed in a strip shape extending along the second direction Y. The source trenches 441 are formed in a stripe shape in a plan view. The pitch between the centers of adjacent source trenches 441 in the first direction X may be 1.5 μm or more and 3 μm or less.

[0823] Each source trench 441 penetrates the body region 426 and reaches the SiC epitaxial layer 422. The bottom wall of each source trench 441 is located within the SiC epitaxial layer 422. More specifically, the bottom wall of each source trench 441 is located in a high concentration region 422a.

[0824] In this embodiment, the depth of the source trench 441 is equal to or greater than the depth of the gate trench 431. More specifically, the depth of the source trench 441 is greater than the depth of the gate trench 431. The bottom wall of the source trench 441 is located closer to the second main surface 404 of the SiC semiconductor layer 402 than the bottom wall of the gate trench 431.

[0825] The bottom wall of the source trench 441 is located in a region between the bottom wall of the gate trench 431 and the low-concentration region 422b. The bottom wall of the source trench 441 may be formed parallel to the first main surface 403 of the SiC semiconductor layer 402.

[0826] The sidewalls of the source trench 441 may extend along the normal direction of the first main surface 403 of the SiC semiconductor layer 402. In other words, the sidewalls of the source trench 441 may be formed substantially perpendicular to the first main surface 403 of the SiC semiconductor layer 402.

[0827] The depth of source trench 441 may be 0.5 μm or more and 10 μm or less (for example, about 2 μm) in the normal direction to first main surface 403 of SiC semiconductor layer 402. The ratio of the depth of source trench 441 to the depth of gate trench 431 may be 1.5 or more. The ratio of the depth of source trench 441 to the depth of gate trench 431 is preferably 2 or more.

[0828] The first direction width of source trench 441 may be approximately equal to the first direction width of gate trench 431. The first direction width of source trench 441 may be equal to or greater than the first direction width of gate trench 431. The first direction width of source trench 441 may be equal to or greater than 0.1 μm and equal to or less than 2 μm (for example, approximately 0.5 μm).

[0829] A source insulating layer (insulating layer) 442 and a source electrode layer (insulating layer) 443 are formed in each source trench 441. In FIG. 51, the source insulating layer 442 and the source electrode layer 443 are shown by hatching for clarity.

[0830] The source insulating layer 442 may contain silicon oxide. The source insulating layer 442 is formed in the form of a film along the inner wall surface of the source trench 441 so as to define a recessed space within the source trench 441.

[0831] The source insulating layer 442 includes a first region 442a and a second region 442b. The first region 442a is formed along the sidewall of the source trench 441. The second region 442b is formed along the bottom wall of the source trench 441. A thickness T11 of the first region 442a is smaller than a thickness T12 of the second region 442b.

[0832] The ratio T12 / T11 of the thickness T12 of the second region 442b to the thickness T11 of the first region 442a may be equal to or greater than 2 and equal to or less than 5. The thickness T11 of the first region 442a may be equal to or greater than 0.01 μm and equal to or less than 0.2 μm. The thickness T12 of the second region 442b may be equal to or greater than 0.05 μm and equal to or less than 0.5 μm.

[0833] The thickness T11 of the first region 442a may be approximately equal to the thickness T1 of the first region 434a of the gate insulating layer 434. The thickness T12 of the second region 442b may be approximately equal to the thickness T2 of the second region 434b of the gate insulating layer 434. Of course, the source insulating layer 442 may be formed to have a uniform thickness.

[0834] The source electrode layer 443 is embedded in the source trench 441 with the source insulating layer 442 sandwiched therebetween. More specifically, the source electrode layer 443 is embedded in the source trench 441 so as to fill the recessed space defined by the source insulating layer 442. The source electrode layer 443 is controlled by a source voltage.

[0835] The source electrode layer 443 has an upper end located on the opening side of the source trench 441. The upper end of the source electrode layer 443 is formed below the first main surface 403 of the SiC semiconductor layer 402. The upper end of the source electrode layer 443 may be located above the first main surface 403 of the SiC semiconductor layer 402.

[0836] The upper end of the source electrode layer 443 is formed in a curved shape recessed toward the bottom wall of the source trench 441. The upper end of the source electrode layer 443 may be formed parallel to the first main surface 403 of the SiC semiconductor layer 402.

[0837] The upper end of the source electrode layer 443 may protrude higher than the upper end of the source insulating layer 442. The upper end of the source electrode layer 443 may be located lower than the upper end of the source insulating layer 442. The thickness of the source electrode layer 443 may be 0.5 μm or more and 10 μm or less (for example, about 1 μm).

[0838] The source electrode layer 443 preferably cont...

Claims

1. A SiC semiconductor layer having a main surface on which a gate trench is formed; a gate insulating layer formed along an inner wall of the gate trench; a gate electrode layer including polysilicon doped with impurities and embedded in the gate trench with the gate insulating layer interposed therebetween; a low resistance electrode layer covering the gate electrode layer, the low resistance electrode layer including a conductive material having a sheet resistance lower than that of the gate electrode layer.

2. A SiC semiconductor device as described in claim 1, wherein the low resistance electrode layer includes a polycide layer in which the polysilicon is silicided with a metal material.

3. The SiC semiconductor device of claim 2, wherein the polycide layer contains at least one of TiSi, TiSi 2 , NiSi, CoSi, CoSi 2 , MoSi 2 or WSi 2 .

4. A SiC semiconductor device described in any one of claims 1 to 3, wherein the low resistance electrode layer is formed in the form of a film.

5. A SiC semiconductor device described in any one of claims 1 to 4, wherein the thickness of the low resistance electrode layer is less than or equal to the thickness of the gate electrode layer.

6. The gate insulating layer includes a first region formed along a side wall of the gate trench and a second region formed along a bottom wall of the gate trench; 6. The SiC semiconductor device according to claim 1, wherein the thickness of the second region of the gate insulating layer is equal to or greater than the thickness of the first region of the gate insulating layer.

7. A SiC semiconductor device as described in Claim 6, wherein the gate insulation layer has a third region covering the main surface of the SiC semiconductor layer, and the thickness of the third region of the gate insulation layer is greater than or equal to the thickness of the first region of the gate insulation layer.

8. A SiC semiconductor device described in any one of claims 1 to 7, wherein the gate trench has a curved portion that curves toward the inside of the gate trench at an opening edge portion that connects the main surface of the SiC semiconductor layer and the side wall of the gate trench.

9. A SiC semiconductor device described in any one of claims 1 to 7, wherein the gate trench has an inclined portion that slopes downward from the main surface of the SiC semiconductor layer toward the side wall of the gate trench at an opening edge portion that connects the main surface of the SiC semiconductor layer and the side wall of the gate trench.

10. The gate insulating layer includes a bulge portion that bulges toward the inside of the gate trench at an opening edge portion of the gate trench, 10. The SiC semiconductor device according to claim 1, wherein the low resistance electrode layer is in contact with the bulging portion of the gate insulating layer.

11. A SiC semiconductor device as described in Claim 10, wherein the bulging portion of the gate insulating layer protrudes in a curved manner toward the inside of the gate trench.

12. The SiC semiconductor layer further includes a source region, a body region, and a drain region formed in this order from the main surface of the SiC semiconductor layer toward a thickness direction along a sidewall of the gate trench, 12. The SiC semiconductor device according to claim 1, wherein the low resistance electrode layer faces the source region with the gate insulating layer interposed therebetween.

13. A SiC semiconductor device described in any one of claims 1 to 12, further comprising an emitter region, a body region, and a collector region formed in this order from the main surface of the SiC semiconductor layer in the thickness direction along the side wall of the gate trench, and the low resistance electrode layer faces the emitter region across the gate insulation layer.

14. A SiC semiconductor device described in any one of claims 1 to 13, wherein the polysilicon is p-type polysilicon doped with p-type impurities.

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