Read clock start and stop for synchronous memory

Abstract

The memory includes a read clock circuit and a mode register. The read clock circuit has an output for providing a hybrid read clock signal in response to a clock signal and a read clock mode signal. The mode register provides the read clock mode signal in response to a read clock mode, and the read clock circuit provides the hybrid read clock signal as a free running clock signal that toggles continuously when the read clock mode is a first mode, and as a strobe signal that is active only in response to the memory receiving a read command when the read clock mode is a second mode.

Description

[Background technology]

[0001] Modern dynamic random-access memory (DRAM) provides high memory bandwidth by increasing the speed of data transmission on the bus connecting the DRAM to one or more data processors, such as a graphics processing unit (GPU) or central processing unit (CPU). DRAM is typically inexpensive and dense, allowing for large amounts of DRAM to be integrated per device. Most DRAM chips sold today conform to various double data rate (DDR) DRAM standards promoted by the Joint Electron Devices Engineering Council (JEDEC). Typically, several DDR DRAM chips are combined on a single printed circuit board to form a memory module that is not only relatively fast but also offers scalability.

[0002] DDR DRAM is synchronous because it operates according to a free-running clock signal that synchronizes the issuance of commands from the host processor to the memory and, therefore, the exchange of data between the host processor and the memory. DDR DRAM can use the clock signal to synchronize commands and generate read data strobe signals. For example, DDR DRAM receives write data using a center-aligned data strobe signal known as "DQS" provided by the host processor, and the memory captures data on both the rising and falling edges of the DQS. Similarly, DDR DRAM provides read data synchronously with the edge-aligned DQS signal provided by the DDR DRAM. During a read cycle, the host processor internally delays the DQS signal to align it with the center portion of the DQ signal, typically by an amount determined at startup by performing data eye training. Some DDR DRAMs, such as Graphics DDR, Version 6 (GDDR6) DRAMs, receive both a main clock signal and a separate write clock signal, and programmably generate a read data strobe signal.

[0003] However, while these enhancements have improved the speed of DDR memory used for main memory in computer systems, further improvements are needed. [Brief explanation of the drawings]

[0004] [Figure 1] FIG. 1 is a block diagram illustrating a data processing system according to some embodiments. [Figure 2] 2 is a block diagram of the GDDR DRAM of FIG. 1 according to some embodiments. [Figure 3] 3 is a table showing mode register settings for receive clock modes of the memory of FIG. 2. [Figure 4]3 is a flowchart useful for understanding the operation of the memory of FIG. 2, according to some embodiments. [Figure 5] 3 is a timing diagram illustrating characteristics of the receive clock timing of the memory of FIG. 2 according to some embodiments. [Figure 6] 3 is a timing diagram illustrating further characteristics of the receive clock timing of the memory of FIG. 2 according to some embodiments. [Figure 7] 3 is a timing diagram illustrating further characteristics of the receive clock timing of the memory of FIG. 2 according to some embodiments. DETAILED DESCRIPTION OF THE INVENTION

[0005] In the following description, the use of the same reference numerals in different figures indicates similar or identical items. Unless otherwise stated, the word "coupled" and its related verb forms include both direct and indirect electrical connections by means well known in the art, and unless otherwise stated, any description of a direct connection also refers to alternative embodiments using a suitable form of indirect electrical connection.

[0006] The memory includes a read clock circuit and a mode register. The read clock circuit has an output for providing a hybrid read clock signal in response to a clock signal and a read clock mode signal. The mode register provides the read clock mode signal in response to the read clock mode, and the read clock circuit provides the hybrid read clock signal as a free-running clock signal that toggles continuously when the read clock mode is a first mode, and as a strobe signal that is active only in response to the memory receiving a read command when the read clock mode is a second mode.

[0007] The device includes an output clock circuit and a mode register. The output clock circuit has an output for providing an external hybrid clock signal in response to a clock signal and a clock mode signal. The mode register provides the clock mode signal in response to a hybrid clock mode, and the output clock circuit provides the external hybrid clock signal as a free-running clock signal that toggles continuously when the hybrid clock mode is in a first mode, and as a strobe signal that is active only in response to a device providing external data when the hybrid clock mode is in a second mode.

[0008] A method for operating a memory includes storing a read clock mode in a mode register. A read clock mode signal is provided in response to the read clock mode. A hybrid read clock signal is provided in response to the clock signal and the read clock mode signal, and providing the hybrid read clock signal includes providing the hybrid read clock signal as a free-running clock signal that toggles continuously when the read clock mode is a first mode, and as a strobe signal that is active only in response to the memory receiving a read command when the read clock mode is a second mode.

[0009] According to various embodiments disclosed herein, a memory provides the ability to start and stop a read clock (RCK) that the memory provides to a memory controller based on a command provided to the memory. Further, this behavior can be programmably enabled and disabled based on the value of one or more bits in a mode register.

[0010] 1 is a block diagram illustrating a data processing system 100, according to some embodiments. Data processing system 100 generally includes data processors in the form of a graphics processing unit (GPU) 110, a host central processing unit (CPU) 120, double data rate (DDR) memory 130, and graphics DDR (GDDR) memory 140.

[0011] GPU 110 is a discrete graphics processor with very high performance for optimized graphics processing, rendering, and display, but requires high memory bandwidth to perform these tasks. GPU 110 generally includes a set of command processors 111, graphics single instruction multiple data (SIMD) cores 112, a set of caches 113, a memory controller 114, a DDR physical interface circuit (PHY) 115, and a GDDR PHY 116.

[0012] Command processor 111 is used to interpret high-level graphics instructions, such as those specified in the OpenGL programming language. Command processor 111 has a bidirectional connection to memory controller 114 for receiving high-level graphics instructions, a bidirectional connection to cache 113, and a bidirectional connection to graphics SIMD core 112. In response to receiving the high-level instructions, command processor 111 issues SIMD instructions for rendering, geometry processing, shading, and rasterizing data, such as frame data, using cache 113 as temporary storage. In response to the graphics instructions, graphics SIMD core 112 executes low-level instructions on large data sets in a massively parallel manner. Command processor 111 and cache 113 are used for temporary storage of input data and output (e.g., rendered and rasterized) data. Cache 113 also has a bidirectional connection to graphics SIMD core 112 and a bidirectional connection to memory controller 114.

[0013] Memory controller 114 has a first upstream port connected to command processor 111, a second upstream port connected to cache 113, a first downstream bidirectional port, and a second downstream bidirectional port. As used herein, an “upstream” port is the side of the circuitry toward the data processor and away from the memory, and a “downstream” port is the side of the circuitry away from the data processor and toward the memory. Memory controller 114 controls the timing and ordering of data transfers to and from DDR memory 130 and GDDR memory 140. DDR and GDDR memories support asymmetric access, i.e., accesses to open pages in memory are faster than accesses to closed pages. Memory controller 114 stores memory access commands and processes them out of order for efficiency while observing certain quality of service objectives, for example, by prioritizing accesses to open pages and deprioritizing frequent bus turnarounds from writes to reads and vice versa.

[0014] DDR PHY 115 has an upstream port connected to a first downstream port of memory controller 114 and a downstream port bidirectionally connected to DDR memory 130. DDR PHY 115 meets all specified timing parameters of an implemented version of DDR memory 130, such as DDR version 5 (DDR5), and performs training operations at the direction of memory controller 114. Similarly, GDDR PHY 116 has an upstream port connected to a second downstream port of memory controller 114 and a downstream port bidirectionally connected to GDDR memory 200. GDDR PHY 116 meets all specified timing parameters of an implemented version of GDDR memory 140, such as GDDR version 7 (GDDR7), and performs training operations at the direction of memory controller 114.

[0015] The inventors have discovered that the read clock (RCK) that a memory, for example, GDDR memory 200, provides to GDDR PHY 116 can be programmed to operate in certain new and advantageous ways. According to some embodiments, the memory has a "read-only" mode. In read-only mode, the memory provides a read command on the RCK signal, begins toggling the RCK signal during a read preamble period before data transmission of the read command, and continues toggling until at least the end of the read postamble period following the read command. The read-only mode provides the ability to reduce power consumption during workloads where read operations are or may be infrequent.

[0016] GDDR memory 200 also has an "always-run" mode. In the always-run mode, GDDR memory 200 provides a RCK signal continuously as long as a write clock (WCK) is received from the host, e.g., the memory controller or memory PHY of a host processor chip. The always-run mode provides the ability for the host processor PHY to remain locked, avoiding the need for resynchronization during the preamble period.

[0017] According to some embodiments, the memory further has a disable mode in which the memory does not provide any read clock signal.

[0018] Figure 2 is a block diagram of the GDDR memory 200 of Figure 1, according to some embodiments. The GDDR memory 200 generally includes a control circuit 210, an address path 220, a memory array and page buffer 230, a data read path 240, a set of bond pads 250, and a data write path.

[0019] The control circuit 210 includes a command decoder 211, a mode register 212, and an RCK logic and state machine 213. The command decoder 211 decodes commands received from command and address pins (not shown in FIG. 2) into one of several supported commands defined by the memory's command truth table. One type of command decoded by the command decoder 211 is a mode register set (MRS) command. The MRS command causes the command decoder to provide a setting to the indicated mode register whose address input contains the setting. The MRS command has long been known in the context of DRAM and differs between different GDDR DRAM versions. The mode register 212 stores the programmed setting and, in some cases, outputs information about the GDDR DRAM. The RCK logic and state machine 213 has a first input connected to the output of the command decoder 211, a second input connected to a specific output of the mode register 212, and an output. As will be further described, the RCK logic and state machine 213 processes the read clock flag. The read clock flag indicates on the fly the read clock behavior after the read postamble period, i.e., during the "interamble" period. The read clock flag can be encoded in a command signal, a separate signal, or in any other known manner.

[0020] The address path 220 receives multi-bit address signals and includes an input buffer 221 and address latch 222 for each address signal, a set of row decoders 223, and a set of column decoders 224. The input buffer 221 receives and buffers the corresponding multi-bit address signal, and provides a multi-bit buffered address signal in response. The address latch 222 has an input connected to the output of the input buffer 221, an output, and a clock input that receives a signal labeled "WCK." The address latch 222 latches the bits of the buffered address on a clock edge, e.g., a rising edge, and serves as both a write clock during write commands and a main clock used to capture commands. The row decoder 223 has an input connected to the output of the address latch 222 and an output. The column decoder 224 has an input connected to the output of the address latch 222 and an output.

[0021] The memory arrays and page buffers 230 are organized into sets of individually addressable memory arrays known as banks. For example, GDDR memory 200 may have a total of 16 banks. Each bank can have only one "open" page at a time, and the open page has its contents loaded into the corresponding page buffer for faster read and write access. Row decoder 223 selects the row within the bank accessed during the activate command, and the contents of the indicated row are loaded into the page buffer, ready for read and write access. Column decoder 224 selects a column of the row according to the column address.

[0022] The data read path 240 includes a read queue 241, a read latch 242, an output buffer 243, a delay locked loop (DLL) 244, and

[0023]

number

[0024]

number

[0025] Write data path 260 includes an input buffer 261, a write latch 262, and a write queue 263. Input buffer 261 has an input connected to the set of bond pads 250 labeled "DQ" and an output. Write latch 262 has an input connected to the output of input buffer 261 and an output. Write queue 263 has an input connected to the output of write latch 262 and an output connected to the memory array and page buffer 230.

[0026] In operation, GDDR memory 200 allows for simultaneous operations on memory banks, and in one embodiment, GDDR memory 200 is compatible with any of the double data rate (DDR) standards published by the Joint Electron Device Engineering Council (JEDEC), such as the emerging Graphics DDR, version 7 (GDDR7) standard. To access data, a memory access agent, such as GPU 110, activates a row in a memory bank by issuing an activate (ACT) command. In response to the ACT command, data from memory cells along the selected row is stored in the corresponding page buffer. In DRAM, data reads are destructive to the contents of the memory cells, but a copy of the data is stored in the page buffer. After memory controller 114 finishes accessing the data in a selected row of the bank, it closes the row by issuing a precharge (PRE) command (or a write or read command with automatic precharge, or a precharge all command). The PRE command causes the data in page buffer 124 to be rewritten to that row in the selected bank, allowing another row to then be activated. These operations are conventional for DDR memories and are described in various JEDEC standard documents and will not be described further.

[0027] However, according to various embodiments disclosed herein, GDDR memory 200 includes a modified set of mode registers 212, compared to existing standards such as GDDR6, that adds a mode register field that can be used to define the behavior of the RCK signal that memory 200 provides along with the accessed data during a read cycle. In addition, memory 200 will transmit RCK (and optionally

[0028]

number

[0029] Figure 3 shows a table 300 illustrating mode register settings for the receive clock mode of the memory of Figure 2. Table 300 shows the values ​​of different bits or bit fields of a 12-bit mode register, the 12 bits corresponding to the address signals into which the mode register is loaded. Table 300 has six columns, including an OP Code (operation code) column that corresponds to a particular bit in the mode register, a Function column that identifies the function defined by the corresponding bits, an OP Code Value column that specifies different values ​​of the OP Code, and a Description column that identifies the meaning of different OP Code values.

[0030] Mode register bits [1:0] are labeled "RCKMODE" and identify the selected RCK mode. A value of 00b (binary) identifies a disabled mode in which RCK is not provided by memory 200. This mode is the default mode.

[0031] A value of 01b indicates read-only mode. As explained further below, in read-only mode, RCK is provided during one or more read cycles, with each read cycle including both a preamble and a postamble. When read-only mode is selected, interamble behavior is enforced when consecutive reads are greater than a minimum interval amount, i.e., at least t CCD +1 RCK cycle, where t CCDis the minimum inter-command delay. Generally, during read data mode, RCK starts a preamble period before the transfer of data in a read cycle and ends the preamble period after the read cycle. In particular, it starts toggling concurrently with data transfer for a read command (RD), a read with auto-precharge command (RDA), and a read training (RDTR) command. It stops on a clear condition. In some embodiments, the clear condition includes receipt of a write command (write command (WR), auto-precharge command (WRA), write training (WRTR) command), receipt of an all-banks idle indicator, entry into a power-down state, or receipt of an explicit stop command known as "RCKSTOP."

[0032] A value of 10b indicates an always running mode, in which the RCK runs continuously as long as the WCK used to generate the RCK is received by memory 200.

[0033] The value 11b is reserved (RSVD) but allows the definition of new modes that provide an RCK signal to be added in the future using this mode register structure.

[0034] Mode register bit [2] defines the receive clock type (RCKTYPE). A value of 0b indicates that the GDDR memory 200 provides the RCK signal as a single-ended signal, i.e.

[0035]

number

[0036]

number

[0037] Mode register bits [4:3] define the length of the static preamble period. To allow the memory controller to lock onto the preamble, each preamble period has a static period, a slow period, and a fast period. During the static period, the read clock signal is driven in its inactive state, i.e., RCK is driven low, and

[0038]

number

[0039] Mode register bit [5] is undefined and reserved for future use (RFU).

[0040] Mode register bits [7:6] define the length of the fast preamble period. A value of 00b indicates a fast preamble period of 0 clock cycles, i.e., no fast preamble period. Values ​​of 01b, 10b, and 11b define static periods of 2, 4, and 6 cycles, respectively.

[0041] Mode register bit [8] is undefined and is RFU.

[0042] Mode register bits [10:9] define the length of the slow preamble period. A value of 00b indicates a slow preamble period of 0 clock cycles, i.e., no slow preamble period. Values ​​of 01b, 10b, and 11b define static periods of 1, 2, and 3 cycles. Note that while the fast and slow preamble periods are independently programmable, if OP code bits [7:6] and [10:9] have the same value, the fast and slow preambles are the same length of time.

[0043] Mode register bit

[11] is undefined and is RFU.

[0044] It will be apparent that these mode register encodings are just one possible way of encoding these values, and that other encodings are possible. For example, instead of using a dedicated mode register, these bits could be distributed among multiple mode registers, e.g., in otherwise unused or reserved bit positions. Furthermore, the selection of available values ​​for the static preamble, slow preamble, and fast preamble is somewhat arbitrary and may vary in different embodiments.

[0045] Figure 4 shows a flowchart 400 useful for understanding the operation of memory 200 of Figure 2, according to some embodiments. Flowchart 400 governs RCK start and stop behavior and interamble behavior when RCKMODE is set to read-only. Flowchart 400 defines a flag known as the RCKON flag.

[0046] Flow begins at action box 410 when a first command is received. Decision box 420 determines whether the command is a read command (such as a read command (RD), a read command with auto precharge (RDA), or a read training (RDTR) command), and if so, determines the state of the RCKON flag. If the command is not a read command, or if it is a read command and the RCKON flag is clear, flow proceeds to action box 430. In action box 430, RCK stops toggling after the read postamble period.

[0047] If the command is a read command and the RCKON state variable is set to 1, flow proceeds to action box 440. In action box 440, memory 200 continues to toggle the RCK signal after the postamble period of the read command. From this point on, the state of RCKON becomes don't care. Flow proceeds to decision box 450 to determine whether a clear condition has been received. In some embodiments, the clear condition includes one or more of: receipt by memory 200 of an explicit read clock stop command; receipt by memory 200 of a write command (e.g., a write command (WR), a write with auto-precharge command (WRA), or a write read training (WRTR) command); receipt by memory 200 of a mode register set command; detection by memory 200 of an all-banks idle state; and detection of a powered-down state of memory 200. If a clear condition has not been received, flow proceeds to decision box 450. If a clear condition has been received, flow proceeds to action box 460. In action box 460 , the state variable RCKON is cleared to 0, RCK stops toggling after the read postamble, and flow returns to decision box 420 .

[0048] 5 shows a timing diagram 500 illustrating receive clock timing characteristics of memory 200 of FIG. 2 in accordance with some embodiments. In timing diagram 500, the horizontal axis represents time in picoseconds (ps) and the vertical axis represents the amplitude of various signals in volts. Shown along the vertical axis are three signals or signal groups of interest: a command signal, an RCK signal, and a data signal. Dashed lines indicate low-to-high and high-to-low transitions of the RCK signal, corresponding to various points in time.

[0049] In the example shown in timing diagram 500, mode register 300 is programmed with RCKMODE=Read Only, RCKTYPE=Single-Ended, RCKPRE_Static=4, RCKPRE_LS=1, and RCKPRE_HS=2. Timing diagram 500 illustrates the issuance of a read command, labeled "RD," on the second RCK transition with the RCKON attribute set to 1. Due to read latency, memory 200 does not provide read data until the 25th clock cycle. Therefore, prior to this RCK cycle, memory 200 provides the preamble defined in table 300.

[0050] In this example, the burst length is 16, and the memory 200 stores t CCDMIN+1 can accept other commands in CCDMIN+7 It is necessary to define the interamble behavior, as seen here, by continuously toggling RCK after the last data transmission of the first cycle, followed by a low period of the slow preamble of the second ready cycle, followed by a fast toggling of the preamble of the fast portion.

[0051] 6 is a timing diagram 600 illustrating further characteristics of the receive clock timing of memory 200 of FIG. 2, according to some embodiments. In timing diagram 600, the horizontal axis represents time in picoseconds (ps) and the vertical axis represents the amplitude of various signals in volts. Along the vertical axis, the command signal, the RCK signal, and the data signal are shown. Dashed lines indicate low-to-high and high-to-low transitions of the RCK signal, denoted "t1" through "t 68 " corresponds to the point in time specified.

[0052] In the example shown in timing diagram 600, mode register 300 is programmed with RCKMODE=Read Only, RCKTYPE=Single-Ended, RCKPRE_Static=4, RCKPRE_LS=1, and RCKPRE_HS=2. Timing diagram 600 illustrates the issuance of a read command RD at t2 where RCKON=0, and RCKON has not previously been set from a previous clear condition. In this case, the RD command causes memory 200 to issue a preamble defined in the mode register, perform a read burst cycle with RCK toggling, and follow the read burst cycle with a postamble. In this case, the postamble includes a trailing static portion of two clock cycles to terminate the postamble period. Thus, when RCKMODE=Read Only, the host processor uses RCK and

number

[0053] 7 is a timing diagram 700 illustrating further characteristics of the receive clock timing of memory 200 of FIG. 2, according to some embodiments. In timing diagram 700, the horizontal axis represents time in picoseconds (ps) and the vertical axis represents the amplitude of various signals in volts. Along the vertical axis, the command signal, the RCK signal, and the data signal are shown. Dashed lines indicate low-to-high and high-to-low transitions of the RCK signal, corresponding to various points in time.

[0054] In timing diagram 700, memory 200 receives a RD command with the RCKON attribute set to 1 at a time prior to the time shown in timing diagram 700. Memory 200 provides a preamble for the RCK signal in response to the RD command. However, after the data transfer is complete, memory 200 continues to toggle the RCK signal, which forms an extended interamble period in the example timing diagram 700. As shown in FIG. 7, memory 200 receives a WR command (WR, WRA, or WRTR) before a subsequent read command is received. In this case, RCK logic and state machine 213 decodes the write command and stops toggling the RCK signal after the write command latency period.

[0055] By providing the ability to start and stop RCK toggling, memory 200 provides a read clock signal that is a hybrid of a strobe and a clock signal. Memory 200 also provides a mechanism for the memory to suppress continuous RCK output after a clear condition. This capability allows a DLL in the memory controller to remain locked during a streak of read commands but stop toggling, saving power in response to a clear condition. The memory controller reorders commands to improve memory bus utilization efficiency, grouping commands of the same type to reduce the frequency of bus turnaround from read to write and from write to read. For example, bus utilization efficiency is particularly important for discrete GPUs, which users often configure to push the performance limits. This capability offers several advantages.

[0056] First, it allows memory controllers to operate more efficiently by simplifying designs that would otherwise be required due to interamble complexity. In particular, interamble calculations can be simplified or eliminated.

[0057] Second, it preserves the signal integrity of the signal that toggles when RCK is not used. For example, this mechanism allows users to avoid continuously generating RCK in response to receiving a write command. Therefore, the write cycle is more robust and there is less signal interference and crosstalk, providing more timing margin for capturing data in memory.

[0058] Third, by suppressing the switching of the RCK signal during streaks of write accesses, it saves switching power of high speed signal switching of external signals typically driven on a printed circuit board when not needed.

[0059] Fourth, the host processor can set the RCKON flag used in memory in a variety of ways, providing flexibility in implementation. For example, the host processor can issue a mode register set command to program an unused or vendor-specific RCKON bit in the mode register. It can issue an explicit RCKON command or include the RCKON attribute in the RD command encoding. It can also activate a new dedicated signal line.

[0060] The memories described herein, or portions thereof, may be embodied in one or more integrated circuits, any of which may be described or represented by a computer-accessible data structure in the form of a database or other data structure that may be read by a program and used directly or indirectly to fabricate an integrated circuit. For example, the data structure may be a behavioral or register-transfer level (RTL) description of the hardware functionality in a high-level design language (HDL) such as Verilog or VHDL. The description may be read by a synthesis tool that can synthesize the description to generate a netlist that includes a list of gates from a synthesis library. The netlist includes a set of gates that also represent the functionality of the hardware comprising the integrated circuit. The netlist may then be placed and routed to generate a data set that describes the geometric shapes to be applied to a mask. The mask may then be used in various semiconductor manufacturing processes to fabricate the integrated circuit. Alternatively, the database on the computer-accessible storage medium may be a netlist (with or without a synthesis library) or a data set, or Graphic Data System (GDS) II data, if desired.

[0061] While specific embodiments have been described, various modifications to these embodiments will be apparent to those skilled in the art. For example, a host processor can use various techniques to set the read clock on an attribute (RCKON), such as an explicit command, an unused bit in the command encoding, a mode register setting, etc. While RCK programming has been described in the context of GDDR memory, other types of circuits, integrated or discrete, can use a clock signal with the hybrid behavior described for the RCK signal. The RCK signal can also be used in other types of memory, including DDR and high-bandwidth memory (HBM) memories. Furthermore, various levels of granularity of preamble and postamble behavior can also be supported. The bits defining the supported RCK modes can be defined in a dedicated mode register or can be set in various bit positions in different mode registers. These bit positions may be previously unused and reserved for future use, or may be dedicated for customer-specific use.

[0062] Therefore, it is intended that the appended claims cover all modifications of the disclosed embodiments that fall within the scope of the disclosed embodiments.

Claims

1. A memory, a read clock circuit having an output for providing a hybrid read clock signal in response to the clock signal and the read clock mode signal; a mode register that provides the read clock mode signal in response to a read clock mode; The read clock circuit providing the hybrid read clock signal as a continuously toggling free-running clock signal when the read clock mode is a first mode; providing the hybrid read clock signal as a strobe signal that is active only in response to the memory receiving a read command and that stops toggling after a postamble period when the read clock mode is in a second mode; Memory.

2. the read clock circuit, when the read clock mode is the first mode, provides the hybrid read clock signal as a free-running clock signal that toggles continuously in response to the input clock signal as long as the memory receives the input clock signal. The memory of claim 1.

3. The read clock circuit a read clock state machine having a first input for receiving a read command signal, a second input for receiving the read clock mode signal, and an output for providing a drive enable signal; a read clock driver circuit having an input for receiving the drive enable signal and an output for providing the hybrid read clock signal in response to the input clock signal when the drive enable signal is active; The memory of claim 2.

4. when the read clock mode is the second mode, the read clock circuit stops toggling the hybrid read clock signal after a postamble period if no further read commands are received; The memory of claim 1.

5. When the read clock mode is the second mode, the read clock circuit stopping toggling of the hybrid read clock signal after the postamble period if no further read commands are received when a read clock flag is in a first state; if the read clock flag is in a second state, continuing to toggle the hybrid read clock signal after the postamble period until the memory receives a clear condition; The memory of claim 4.

6. The clearing condition is: receiving an explicit read clock stop command from the memory; receiving a write command at the memory; receiving a mode register set command at the memory; detecting an all-bank idle state of the memory; detecting a power-off state of the memory; including one or more of The memory of claim 5.

7. 1. An apparatus comprising: an output clock circuit having an output for providing an external hybrid clock signal in response to the clock signal and the clock mode signal; a mode register that provides the clock mode signal in response to a hybrid clock mode; The output clock circuit providing the external hybrid clock signal as a continuously toggling free-running clock signal when the hybrid clock mode is in a first mode; providing the external hybrid clock signal as a strobe signal that is active only in response to the device providing external data and that stops toggling after a postamble period when the hybrid clock mode is in a second mode; Device.

8. the output clock circuit, when the hybrid clock mode is in the first mode, provides the external hybrid clock signal as a free-running clock signal that toggles continuously in response to the input clock signal for as long as the device receives the input clock signal.

8. The apparatus of claim 7.

9. the device comprises an integrated circuit memory; the external hybrid clock signal is a read clock signal provided to a host processor; 8. The apparatus of claim 7.

10. the device comprises a memory controller; the external hybrid clock signal is a write clock signal provided to the memory; 8. The apparatus of claim 7.

11. 1. A method for operating a memory, comprising: storing the read clock mode in a mode register; providing a read clock mode signal in response to the read clock mode; providing a hybrid read clock signal in response to a clock signal and the read clock mode signal; providing the hybrid read clock signal comprises: providing the hybrid read clock signal as a continuously toggling free-running clock signal when the read clock mode is a first mode; providing the hybrid read clock signal as a strobe signal that becomes active only in response to the memory receiving a read command and stops toggling after a postamble period when the read clock mode is in a second mode. method.

12. providing the hybrid read clock signal as the free-running clock signal that toggles continuously in response to an input clock signal for as long as the memory receives the input clock signal. The method of claim 11.

13. stopping toggling of the hybrid read clock signal after a postamble period if no further read commands are received. The method of claim 11.

14. stopping toggling of the hybrid read clock signal after the postamble period if no further read commands are received when the read clock mode is the second mode and a read clock flag is in a first state; if the read clock flag is in a second state, continuing toggling the hybrid read clock signal after the postamble period until a clear condition is received.

14. The method of claim 13.

15. The clearing condition is: receiving an explicit read clock stop command from the memory; receiving a write command at the memory; receiving a mode register set command at the memory; detecting an all-bank idle state of the memory; detecting a power-off state of the memory; including one or more of 15. The method of claim 14.

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