Liquid crystal display device

Abstract

To improve an opening ratio of a semiconductor device.SOLUTION: A semiconductor device includes a driving circuit part and a display part (also referred as a pixel part) over the same substrate. The driving circuit part includes: a driving circuit channel etching type thin film transistor of which a source electrode and a drain electrode are constructed by a metal, and a channel layer is constructed by semiconductor oxide; and driving circuit wiring constructed by a metal. The display part includes: a pixel channel protection type thin film transistor in which a source electrode layer and a drain electrode layer are constructed by a conductor oxidation, and the semiconductor layer is constructed by a semiconductor oxidation; and display wiring that is constructed by the conductor oxidation.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device including an oxide semiconductor and a manufacturing method thereof.

[0002] In this specification, a semiconductor device is a device that can function by utilizing semiconductor characteristics. This refers to a general category of semiconductor devices, including electro-optical devices such as display devices, semiconductor circuits, and electronic devices. be. [Background technology]

[0003] Light-transmitting metal oxides are used in semiconductor devices. For example, indium oxide Conductive metal oxides such as ITO (indium tin oxide) (hereinafter referred to as oxide conductors) are used in liquid crystal displays. It is used as a transparent electrode material required for display devices such as displays.

[0004] In addition, metal oxides with optical transparency are attracting attention as materials that exhibit semiconductor properties. For example, In-Ga-Zn-O oxides are required for display devices such as liquid crystal displays. It is expected that this technology will be applied to semiconductor materials that are used in thin film transistors (TFTs). It is expected to be applied to the channel layer of a thin-film transistor (FT).

[0005] TFTs that use metal oxides with semiconducting properties (hereinafter referred to as oxide semiconductors) can be used at low temperatures. Therefore, it is possible to manufacture alumina used in display devices. There is growing expectation that it will be a material that replaces or surpasses rufus silicon.

[0006] In addition, both the oxide conductor and the oxide semiconductor have light-transmitting properties. By configuring a TFT with this, a TFT having light-transmitting properties can be fabricated (for example, For example, see Non-Patent Document 1.

[0007] Furthermore, TFTs using oxide semiconductors have high field-effect mobility. It is also possible to configure a driving circuit for a display device or the like using the above (see, for example, Non-Patent Document 2). .). [Prior art documents] [Non-patent literature]

[0008] [Non-Patent Document 1] Tetsuo Nozawa, "Transparent Circuits," Nikkei Electronics, August 27, 2007 (No. 959), pp. 39-52 [Non-patent document 2] T.Osada, and 8 others, SID '09 DIGEST, pp.184-187(2009) Summary of the Invention [Problem to be solved by the invention]

[0009] An object of one embodiment of the present invention is to reduce manufacturing costs of a semiconductor device.

[0010] An object of one embodiment of the present invention is to improve the aperture ratio of a semiconductor device.

[0011] An object of one embodiment of the present invention is to increase the resolution of an image displayed on a display portion of a semiconductor device. do.

[0012] An object of one embodiment of the present invention is to provide a semiconductor device that can be driven at high speed. [Means for solving the problem]

[0013] One embodiment of the present invention is a display device having a driver circuit portion and a display portion (also referred to as a pixel portion) over the same substrate. The driver circuit portion includes a source electrode (also referred to as a source electrode layer) and a drain electrode (also referred to as a drain electrode layer). The layer is made of metal and the channel layer is made of oxide semiconductor. The driving circuit includes a thin film transistor and a wiring for the driving circuit made of metal. The display portion has a source electrode layer and a drain electrode layer made of an oxide conductor and a semiconductor. The pixel thin film transistor is made of an oxide semiconductor layer, and the pixel thin film transistor is made of an oxide conductor layer. The semiconductor device has a display wiring configured as above.

[0014] As a thin film transistor for pixels and a thin film transistor for driving circuits, Staggered thin-film transistors are used. The thin-film transistors for pixels have a channel formed in the semiconductor layer. A channel-protected (channel-stop) thin-film transistor with a channel protection layer on the region On the other hand, the thin film transistor for the driver circuit has a source electrode layer and a drain electrode layer. A channel-etched thin-film transistor having an oxide insulating film in contact with the semiconductor layer exposed between the gate electrodes. It is a star.

[0015] In addition, Non-Patent Document 1 does not include a specific process for manufacturing a TFT and other elements constituting a semiconductor device. The structure of the capacitors (for example, capacitor elements) is not disclosed. There is also no description of fabricating a TFT having light-transmitting properties.

[0016] The semiconductor device according to one embodiment of the present invention includes a driver circuit TFT and a driver circuit TFT on the same substrate. A display section having a path section and a pixel TFT is manufactured. Costs can be reduced.

[0017] In the semiconductor device of one embodiment of the present invention, the source electrode and the drain electrode are formed of an oxide. A pixel TFT made of a conductor and having a semiconductor layer made of an oxide semiconductor. and wiring for the display portion made of an oxide conductor. The area where the pixel TFT and the display wiring are formed can be used as the opening. Therefore, the aperture ratio of the semiconductor device can be improved.

[0018] In the semiconductor device of one embodiment of the present invention, the source electrode and the drain electrode are formed of an oxide. A pixel TFT made of a conductor and having a semiconductor layer made of an oxide semiconductor. and wiring for the display portion made of an oxide conductor. Therefore, the pixel size can be designed without being limited by the size of the pixel TFT. Therefore, the resolution of an image displayed on a display portion of the semiconductor device can be increased.

[0019] In addition, in the semiconductor device of one embodiment of the present invention, a source electrode and a drain electrode of gold are provided in the driver circuit portion. A TFT for a driving circuit, the channel layer of which is made of a metal and an oxide semiconductor. and wiring for a driving circuit made of metal. The driving circuit is composed of TFTs that exhibit high field effect mobility and low resistance wiring. Therefore, the semiconductor device can be a semiconductor device capable of high-speed operation.

[0020] The oxide semiconductor used in this specification is InMO3(ZnO) m (m>0) A thin film is formed on the oxide semiconductor layer, and a thin film transistor is fabricated using the thin film as an oxide semiconductor layer. M is one or more metal elements selected from Ga, Fe, Ni, Mn, and Co. It indicates a metal element. For example, M can be Ga, Ga and Ni, or Ga and Ni. In some cases, the oxide semiconductor may contain other metal elements than Ga, such as Fe. In addition to the metal elements contained as M, Fe, Ni and other transition metals are included as impurity elements. In this specification, the term "In" refers to a transition metal or an oxide thereof. MO3(ZnO) m In the oxide semiconductor layer with a structure represented by (m>0), M is Ga The oxide semiconductor with a structure containing In-Ga-Zn-O is called an In-Ga-Zn-O oxide semiconductor, and its thin film is called an I It is also called n-Ga-Zn-O based non-single crystal film.

[0021] In addition to the above, metal oxides that can be used for the oxide semiconductor layer include In-Sn-Zn-O In-Al-Zn-O system, Sn-Ga-Zn-O system, Al-Ga-Zn-O system, Sn -Al-Zn-O series, In-Zn-O series, Sn-Zn-O series, Al-Zn-O series, In- O-based, Sn-O-based, and Zn-O-based metal oxides can be used. The oxide semiconductor layer made of the material may contain silicon oxide.

[0022] Under an inert gas atmosphere of nitrogen or rare gas (argon, helium, etc.), or under reduced pressure When the heat treatment is performed, the oxide semiconductor layer becomes oxygen-deficient by the heat treatment and has low resistance. , that is, N-type (N - and then forming an oxide insulating film in contact with the oxide semiconductor layer. By performing this, the oxide semiconductor layer is made into an oxygen-excess state, and the resistance is increased, that is, the oxide semiconductor layer is made into an I-type. This allows us to obtain thin film transistors with good electrical characteristics and high reliability. Therefore, it is possible to manufacture and provide a semiconductor device that can achieve this.

[0023] Dehydration or dehydrogenation is carried out using an inert gas such as nitrogen or a noble gas (argon, helium, etc.). In an atmosphere or under reduced pressure, at 350°C or higher, preferably at 400°C or higher but lower than the strain point of the substrate By performing the heat treatment, impurities such as moisture contained in the oxide semiconductor layer can be reduced.

[0024] In the dehydration or dehydrogenation, the oxide semiconductor layer after the dehydration or dehydrogenation is heated. Thermal Desorption Spectroscopy (Thermal Desorption Spectroscopy) Even when measurements were taken up to 450°C using TDS, two peaks for water appeared at least around 300°C. The heat treatment conditions should be such that no single peak is detected. Thin film transistors using oxide semiconductor layers that have been subjected to thermal decomposition are measured up to 450°C using TDS. Even when the temperature was measured, the water peak that appears around 300°C was not detected.

[0025] Then, the temperature is lowered from the heating temperature T at which the oxide semiconductor layer is dehydrated or dehydrogenated. When dehydrating or dehydrogenating, the water or hydrogen is removed from the atmosphere using the same furnace as that used for dehydration or dehydrogenation. It is important to prevent the re-incorporation of hydrogen into the oxide semiconductor layer. Low resistance, i.e. N-type (N - After that, the oxide semiconductor layer is made high-resistive and becomes I-type. When a thin film transistor is fabricated using this, the threshold voltage of the thin film transistor becomes positive. This allows realization of a so-called normally-off switching element. The gate voltage of the transistor is set to a positive threshold voltage as close as possible to 0V. This is desirable for semiconductor devices (display devices). In the case of a MOSFET, current flows between the source and drain electrodes even when the gate voltage is 0V. In an active matrix display device, the circuit The electrical characteristics of the thin film transistors that make up the display are important, and these electrical characteristics determine the performance of the display device. In particular, the threshold voltage (Vth) is an important electrical characteristic of thin film transistors. Even if the field effect mobility is high, the threshold voltage is high or the threshold voltage is negative. If the threshold voltage is high, it is difficult to control the circuit. In the case of a thin film transistor with a large absolute value of The switching function cannot be performed and there is a risk of it becoming a load. In the case of a transistor, a channel is formed only when a positive voltage is applied to the gate. A transistor that allows drain current to flow is desirable. If the driving voltage is not high, a channel will not form. A transistor in which a channel is formed and drain current flows even under negative voltage conditions. The transistor is not suitable as a thin film transistor for use in circuits.

[0026] In addition, the gas atmosphere when the temperature is lowered from the heating temperature T is the same as the gas atmosphere heated up to the heating temperature T. For example, the same gas atmosphere as that used for dehydration or dehydrogenation may be used. The furnace is kept free from exposure to the atmosphere and is filled with high-purity oxygen gas or N2O gas, ultra-dry air, and Cooling is carried out by filling the tank with water (dew point of -40°C or less, preferably -60°C or less).

[0027] The moisture content in the film is reduced by heat treatment for dehydration or dehydrogenation, and then the film containing moisture is Cool slowly (or cool) in an atmosphere that is free from dew (dew point is -40°C or less, preferably -60°C or less). By using the oxide semiconductor film, the electrical characteristics of the thin film transistor can be improved and mass production can be achieved. This will realize thin-film transistors that are both reliable and high-performance.

[0028] In this specification, under an inert gas atmosphere of nitrogen or a rare gas (argon, helium, etc.), Alternatively, heat treatment under reduced pressure is referred to as heat treatment for dehydration or dehydrogenation. The term "dehydrogenation" refers only to the process of desorption of hydrogen as H2 by this heat treatment. For convenience, this term is used to refer to dehydration or dehydrogenation, including the elimination of H, OH, etc. Let's say.

[0029] Under an inert gas atmosphere of nitrogen or rare gas (argon, helium, etc.), or under reduced pressure When the heat treatment is performed, the oxide semiconductor layer becomes oxygen-deficient by the heat treatment and has low resistance. , that is, N-type (N - As a result, the area overlapping with the drain electrode layer becomes oxygen deficient. The high-resistivity drain region (also called HRD region) is formed as a type.

[0030] Specifically, the carrier concentration in the high-resistance drain region is 1×10 17 / cm 3 Within the above range and the carrier concentration in the channel formation region is at least 1×10 17 / cm 3 (less than) The carrier concentration in this specification is determined by Hall effect measurement at room temperature. This refers to the carrier concentration value measured.

[0031] Then, at least a part of the dehydrated or dehydrogenated oxide semiconductor layer is brought into an oxygen-excess state. By this, the resistance is increased, that is, the I-type is formed, and a channel forming region is formed. The treatment for bringing part of the dehydrogenated oxide semiconductor layer into an oxygen-excess state includes dehydration or forming an oxide insulating film in contact with the oxide semiconductor layer by sputtering or by oxidation; Heat treatment after forming the insulating film, or heat treatment in an atmosphere containing oxygen, or in an inert gas atmosphere After heating in an oxygen atmosphere, the process is cooled in an ultra-dry air (dew point below -40°C, preferably This is preferably done by cooling to a temperature of -60°C or below.

[0032] In addition, at least a part of the dehydrated or dehydrogenated oxide semiconductor layer (a part overlapping with the gate electrode layer) is The high-resistance region is formed by selectively creating an oxygen-excess state in the channel formation region. The oxide semiconductor layer may be in contact with the dehydrated or dehydrogenated oxide semiconductor layer. The source electrode layer and the drain electrode layer are formed from metal electrodes such as Ti. The exposed area that does not overlap with the drain electrode layer is selectively made into an oxygen-excess state to form a channel forming area. When the oxygen-excess state is selectively created, the second layer overlapping the source electrode layer can be formed. A first high-resistance drain region and a second high-resistance drain region overlapping the drain electrode layer are formed. The region between the first high-resistance drain region and the second high-resistance drain region has a channel shape. That is, the channel formation region is self-aligned between the source electrode layer and the drain electrode layer. It is formed synthetically.

[0033] This allows the fabrication of a semiconductor device having a thin film transistor with good electrical characteristics and high reliability. and can be provided.

[0034] Note that the oxide semiconductor layer overlapping with the drain electrode layer (and the source electrode layer) has a high resistance. By forming a drain region, it is possible to improve reliability when forming a drive circuit. Specifically, by forming a high-resistance drain region, the high-resistance drain can be The structure is such that the conductivity can be changed stepwise from the drain region to the channel formation region. Therefore, the drain electrode layer is connected to a wiring that supplies a high power supply potential VDD. When the transistor is operated with a high resistance, even if a high electric field is applied between the gate electrode layer and the drain electrode layer, The drain region acts as a buffer, preventing the application of a localized high electric field, improving the transistor's breakdown voltage It is possible to have a configuration in which

[0035] In addition, a high-resistance drain electrode layer (and a source electrode layer) is formed in the oxide semiconductor layer overlapping the drain electrode layer (and the source electrode layer). By forming a drain region, leakage in the channel formation region when forming a drive circuit is reduced. Specifically, by forming a high-resistance drain region, the drain current can be reduced. The drain electrode layer and the source electrode layer are connected as a path for the leakage current of the transistor. Drain electrode layer, high-resistance drain region on the drain electrode layer side, channel formation region, source electrode The high-resistance drain region on the layer side and the source electrode layer are in this order. The leakage current that flows from the low-resistance N-type region on the drain electrode layer side to the channel formation region is The transistor is concentrated near the interface between the gate insulating layer and the channel formation region, which has high resistance when turned off. The back channel portion (the surface of the channel forming region away from the gate electrode layer) can be It is possible to reduce leakage current in some areas.

[0036] Also, a first high-resistance drain region overlapping the source electrode layer and a second high-resistance drain region overlapping the drain electrode layer. The high-resistance drain region is formed by a part of the gate electrode layer and the gate insulating layer, depending on the width of the gate electrode layer. The drain electrode layer overlaps the drain electrode layer via an edge layer, and the electric field strength near the edge of the drain electrode layer is more effectively reduced. This can be done.

[0037] One embodiment of the configuration of the invention disclosed in this specification is a semiconductor device having a first thin film transistor over the same substrate. a pixel portion including a first thin film transistor and a driver circuit including a second thin film transistor, a gate electrode layer on the substrate; a gate insulating layer on the gate electrode layer; and an oxide layer on the gate insulating layer. a semiconductor layer, a first oxide insulating layer in contact with a part of the oxide semiconductor layer, and a first oxide insulating layer and a source electrode layer and a drain electrode layer on the oxide semiconductor layer, and a pixel electrode layer on the first oxide insulating layer. a gate electrode layer of the first thin film transistor, a gate insulating layer, an oxide semiconductor layer, and a The dielectric layer, the source electrode layer, the drain electrode layer, the first oxide insulating layer, and the pixel electrode layer are light-transmitting. a source electrode layer and a drain electrode layer of the second thin film transistor formed of a second oxide insulating film; The first thin film transistor is covered with a layer made of a material different from that of the source electrode layer and the drain electrode layer of the second thin film transistor. a conductive material having a lower resistance than the source electrode layer and the drain electrode layer of the first thin film transistor; This is a semiconductor device.

[0038] One embodiment of the structure of the invention disclosed in this specification is a first gate electrode layer and a second gate electrode layer forming a gate insulating layer on the first gate electrode layer and the second gate electrode layer; a first oxide semiconductor layer overlapping the first gate electrode layer on the insulating layer; and a second gate electrode layer. a second oxide semiconductor layer overlapping the first oxide semiconductor layer and the second oxide semiconductor layer; After the first oxide semiconductor layer and the second oxide semiconductor layer were dehydrated or dehydrogenated, the first oxide semiconductor layer and the second oxide semiconductor layer were The second oxide semiconductor layer is then formed on the second oxide semiconductor layer. a second source electrode layer and a second drain electrode layer, the second source electrode layer being in contact with a part of the second oxide semiconductor layer; a first oxide insulating layer and a first oxide semiconductor layer in a region overlapping with the first gate electrode layer; a first oxide semiconductor layer and a first oxide insulating layer; a first oxide insulating layer, a first source electrode layer, and a first drain electrode layer; forming a protective insulating layer on the first drain electrode layer and the second oxide insulating layer; a pixel electrode layer electrically connected to the first drain electrode layer or the first source electrode layer; The present invention relates to a method for manufacturing a semiconductor device in which a conductive layer overlapping with an oxide semiconductor layer is formed.

[0039] In the above structure, the oxide semiconductor layer of the second thin film transistor is a source electrode layer or a drain electrode layer. The second thin film transistor may have a region where the film thickness is thinner than the region where the second thin film transistor overlaps with the drain electrode layer. The oxide semiconductor layer of the transistor has a larger thickness than the region overlapping with the source electrode layer or the drain electrode layer. The thin channel forming region is provided with a conductive layer on the channel forming region via a second oxide insulating layer. The structure may have an electrically conductive layer.

[0040] The first oxide insulating layer and the second oxide insulating layer can be formed in the same process, and therefore have the same light-transmitting property. An insulating material having such a property can be used.

[0041] The source electrode layer and the drain electrode layer of the second thin film transistor are made of Al, Cr, Cu. a film mainly composed of an element selected from the group consisting of Ta, Ti, Mo, and W, or an alloy film thereof; It is preferable to use a metal conductive film made of a laminated film in which the above are combined.

[0042] On the other hand, the source electrode layer, the drain electrode layer, and the pixel electrode layer of the first thin film transistor are Indium oxide, indium oxide tin oxide alloy, indium oxide zinc oxide alloy, or acid It is preferable to use a transparent conductive film such as zinc oxide.

[0043] In the above configuration, a capacitance section is further provided on the same substrate, and the capacitance section includes capacitance wiring and the capacitance wiring. The capacitor wiring and the capacitor electrode may be light-transmitting.

[0044] The oxide semiconductor layer of the second thin film transistor may be a source electrode layer or a drain electrode layer. A structure with an overlapping high-resistivity drain region is also possible.

[0045] The ordinal numbers such as 1st and 2nd are used for convenience and do not indicate the order of processes or stacking. Furthermore, the specific names used in this specification are not intended to identify the invention. This does not indicate

[0046] In addition to liquid crystal display devices, display devices having a driving circuit include light-emitting devices using light-emitting elements. display devices, and display devices that use electrophoretic display elements and are also called electronic paper. .

[0047] In a light-emitting display device using a light-emitting element, a plurality of thin film transistors are provided in a pixel portion, and a pixel In the element part, the gate electrode of a thin film transistor and the source wiring (s The point where the source wiring layer or drain wiring (also called drain wiring layer) is connected. In addition, in a driving circuit of a light emitting display device using a light emitting element, a thin film transistor The gate electrode of the thin film transistor is connected to the source wiring or drain wiring of the thin film transistor. It has a part that allows you to do this. [Effects of the Invention]

[0048] A thin film transistor having stable electrical characteristics can be manufactured and provided. It is possible to provide a semiconductor device having a thin film transistor with good electrical characteristics and high reliability. Cut. [Brief explanation of the drawings]

[0049] [Figure 1] 1A to 1C illustrate a semiconductor device. [Figure 2] 1A to 1C illustrate a method for manufacturing a semiconductor device. [Figure 3] 1A to 1C illustrate a method for manufacturing a semiconductor device. [Figure 4] 1A to 1C illustrate a method for manufacturing a semiconductor device. [Figure 5] 1A to 1C illustrate a method for manufacturing a semiconductor device. [Figure 6] 1A to 1C illustrate a method for manufacturing a semiconductor device. [Figure 7] 1A to 1C illustrate a semiconductor device. [Figure 8] 1A to 1C illustrate a semiconductor device. [Figure 9] 1A to 1C illustrate a semiconductor device. [Figure 10] 1A to 1C illustrate a semiconductor device. [Figure 11] 1A to 1C illustrate a semiconductor device. [Figure 12] 1A and 1B are diagrams illustrating pixel equivalent circuits of a semiconductor device. [Figure 13] 1A to 1C illustrate a semiconductor device. [Figure 14] FIG. 1 is a block diagram illustrating a semiconductor device. [Figure 15] 1A and 1B are a circuit diagram and a timing chart of a signal line driver circuit; [Figure 16] FIG. 1 is a circuit diagram showing a configuration of a shift register. [Figure 17] 3A and 3B are a circuit diagram and a timing chart illustrating the operation of a shift register. [Figure 18] 1A to 1C illustrate a semiconductor device. [Figure 19] 1A to 1C illustrate a semiconductor device. [Figure 20] FIG. 1 is an external view showing an example of an electronic book. [Figure 21] FIG. 1 is an external view showing an example of a television device and a digital photo frame. [Figure 22] FIG. 1 is an external view showing an example of a gaming machine. [Figure 23] FIG. 1 is an external view showing an example of a portable computer and a mobile phone. [Figure 24] 1A to 1C illustrate a semiconductor device. [Figure 25] 1A to 1C illustrate a semiconductor device. [Figure 26] 1A to 1C illustrate a semiconductor device. [Figure 27] FIG. 1 is a circuit diagram of a semiconductor device. [Figure 28] 1A to 1C illustrate a semiconductor device. [Figure 29] 1A to 1C illustrate a semiconductor device. [Figure 30] FIG. 1 is a circuit diagram of a semiconductor device. [Figure 31] 1A to 1C illustrate a semiconductor device. [Figure 32] 1A to 1C illustrate a semiconductor device. [Figure 33] 1A to 1C illustrate a semiconductor device. [Figure 34] 1A to 1C illustrate a semiconductor device. [Figure 35] 1A to 1C illustrate a semiconductor device. [Figure 36] 1A to 1C illustrate a semiconductor device. [Figure 37] 1A to 1C illustrate a semiconductor device. [Figure 38] 1A to 1C illustrate a semiconductor device. [Figure 39] 1A to 1C illustrate a method for manufacturing a semiconductor device. [Figure 40] 1A to 1C illustrate a method for manufacturing a semiconductor device. DETAILED DESCRIPTION OF THE INVENTION

[0050] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description. Those skilled in the art will recognize that various changes in form and details may be made without departing from the spirit and scope of the present invention. Therefore, the present invention should be interpreted as being limited to the following description of the embodiments. In the configuration described below, parts that have the same parts or similar functions are not included. The same reference numerals are used in common between different drawings for corresponding parts, and repeated explanations thereof will be omitted.

[0051] (Embodiment 1) One embodiment of a semiconductor device and a manufacturing method thereof will be described with reference to FIGS.

[0052] Figures 1(A1) to 1(C) show two thin-film transistors with different structures fabricated on the same substrate. 1A to 1C show an example of a cross-sectional structure of a thin film transistor 410. This is one of the bottom gate structures called channel etch type, and the thin film transistor 420 is This is one of the bottom gate structures called channel protection type (also called channel stop type). The thin film transistor 410 and the thin film transistor 420 are inverted staggered thin film transistors. It is also called.

[0053] FIG. 1(A1) is a plan view of a channel-etched thin film transistor 410 arranged in a driving circuit. 1(A1) and FIG. 1(B) is a cross-sectional view taken along line C1-C2 in FIG. 1(A1). (C) is a cross-sectional view taken along line C3-C4 in FIG. 1(A1).

[0054] The thin film transistor 410 disposed in the driving circuit is a channel-etch type thin film transistor. A gate electrode layer 411 and a first gate insulating layer 40 are formed on a substrate 400 having an insulating surface. 2a, the second gate insulating layer 402b, at least the channel forming region 413, the first high resistance an oxide semiconductor layer having a drain region 414a and a second high-resistance drain region 414b; , a source electrode layer 415a, and a drain electrode layer 415b. An oxide insulating layer 416 is provided to cover the region 410 and to be in contact with the channel formation region 413 .

[0055] The first high-resistance drain region 414a is formed in a self-aligned manner in contact with the lower surface of the source electrode layer 415a. A second high-resistance drain region is formed in contact with the lower surface of the drain electrode layer 415b. The channel forming region 413 is formed in a self-aligned manner by an oxide insulating film. The first high-resistance drain region 414a and the second high-resistance drain region 414b are in contact with the edge layer 416 and have a reduced thickness. The second high-resistance drain region 414b is a region (I-type region) having a higher resistance than the first high-resistance drain region 414a.

[0056] The thin film transistor 410 has a source electrode layer 415a and a The drain electrode layer 415b is preferably made of a metal material.

[0057] In addition, in a liquid crystal display device, when a pixel portion and a driver circuit are formed on the same substrate, In this case, logic gates such as inverter circuits, NAND circuits, NOR circuits, and latch circuits are used. thin-film transistors that make up the circuit, as well as analog components such as sense amplifiers, constant voltage generators, and VCOs. The thin film transistors that make up the gate circuits have only positive polarity between the source and drain electrodes. Therefore, the second high-resistance drain region 41, which is required to have a high breakdown voltage, The width of the first high-resistance drain region 414b may be designed to be wider than the width of the first high-resistance drain region 414a. The first high-resistance drain region 414a and the second high-resistance drain region 414b form a gate electrode. The overlapping width of the layer may be increased.

[0058] The thin film transistor 410 disposed in the driving circuit is a thin film transistor with a single gate structure. Although the explanation has been given using a transistor, a multi-gate transistor having multiple channel forming regions may be used as needed. A thin film transistor having the same structure can also be formed.

[0059] A conductive layer 417 is provided above the channel forming region 413. By electrically connecting the gate electrode layer 411 and the conductive layer 412 to each other and setting them at the same potential, the gate electrode layer 411 and the conductive layer 412 are electrically connected to each other and set at the same potential. A gate voltage can be applied from above and below to the oxide semiconductor layer disposed between the gate electrodes 17. In addition, the gate electrode layer 411 and the conductive layer 417 are set to different potentials, for example, fixed potentials, GND, and 0V. In this case, the electrical properties of the TFT, such as the threshold voltage, can be controlled. That is, the gate electrode layer 411 functions as a first gate electrode layer, and the conductive layer 417 functions as a second gate electrode layer. By making the thin film transistor 410 function as a gate electrode layer of the thin film transistor 410, It can be used as a register.

[0060] In addition, a protective insulating layer 403 and a planarizing insulating layer 404 are provided between the conductive layer 417 and the oxide insulating layer 416. 04 and stacked together.

[0061] The protective insulating layer 403 is formed on the first gate insulating layer 402 provided below the protective insulating layer 403. It is preferable that the insulating film is in contact with the insulating film that serves as the base. , hydrogen ions, oxygen ions, OH - It blocks the intrusion of impurities such as The first gate insulating layer 402a or the underlying insulating film in contact with the protective insulating layer 403 is then formed of nitride. A silicon dioxide film is effective.

[0062] FIG. 1A2 is a plan view of a channel protection type thin film transistor 420 disposed in a pixel. 1(A2) and FIG. 1(B) is a cross-sectional view taken along line D1-D2 in FIG. 1(A2). (C) is a cross-sectional view taken along line D3-D4 in FIG. 1(A2).

[0063] The thin film transistor 420 disposed in the pixel is a channel protection type thin film transistor, A gate electrode layer 421, a first gate insulating layer 402a, a second gate insulating layer 402b, a gate insulating layer 402c, a gate insulating layer 402d, a gate insulating layer 402e, a gate insulating layer 402f, a gate insulating layer 402g, a gate insulating layer 402h ...i, a gate insulating layer 4 The second gate insulating layer 402b, the oxide semiconductor layer 422 including the channel formation region, and the channel The oxide insulating layer 426 serving as a protective layer, the source electrode layer 425a, and the drain electrode layer Also, the thin film transistor 420 is covered with an oxide insulating layer 426, a source electrode 425b, and a gate insulating layer 426. A protective insulating layer 403 and a planarizing insulating layer 404 are formed in contact with the electrode layer 425a and the drain electrode layer 425b. The drain electrode layer 425b is stacked on the planarization insulating layer 404. A pixel electrode layer 427 is provided in contact with the thin film transistor 420. are.

[0064] After the formation of the oxide semiconductor film, heat treatment (dehydration) is performed to reduce impurities such as moisture. Heat treatment for dehydration or dehydrogenation) is carried out. After the oxide semiconductor layer is heated and cooled, an oxide insulating film is formed in contact with the oxide semiconductor layer. Reducing the carrier concentration in the dielectric layer improves the electrical characteristics and reliability of the thin film transistor 420. This leads to improved reliability.

[0065] The channel formation region of the thin film transistor 420 disposed in the pixel is formed by the oxide semiconductor layer 422. The oxide insulating layer 426 is in contact with the gate electrode layer 421 and overlaps with the oxide insulating layer 426 serving as a channel protective layer. The thin film transistor 420 is protected by the oxide insulating layer 426. Therefore, in the etching process for forming the source electrode layer 425a and the drain electrode layer 425b, This can prevent the compound semiconductor layer 422 from being etched.

[0066] In addition, the thin film transistor 420 is a light-transmitting thin film transistor having a high aperture ratio. In order to realize a display device having a light-transmitting property, the source electrode layer 425a and the drain electrode layer 425b are A conductive film having the following structure is used.

[0067] A light-transmitting conductive film is also used for a gate electrode layer 421 of the thin film transistor 420.

[0068] In addition, the pixel in which the thin film transistor 420 is disposed is provided with a pixel electrode layer 427 or other The electrode layer (such as the capacitor electrode layer) and other wiring layers (such as the capacitor wiring layer) are transparent to visible light. A display device having a high aperture ratio is realized by using a conductive film having optical properties. The insulating layer 402a, the second gate insulating layer 402b, and the oxide insulating layer 426 are also transparent to visible light. It is preferable to use a film having optical properties.

[0069] In this specification, a film that is transparent to visible light is a film that has a visible light transmittance of 75 to 100 %, and if the film is conductive, it is also called a transparent conductive film. Also, a gate electrode layer, a source electrode layer, a drain electrode layer, a pixel electrode layer, or other electrodes As a metal oxide applied to the wiring layer, a conductive film that is semi-transparent to visible light is used. Translucent to visible light means that the transmittance of visible light is 50 to 75%. .

[0070] 2 and 3(A) to 3(E), a thin film transistor 410 and a thin film transistor 420 are formed on the same substrate. The steps for manufacturing the thin film transistor 420 will be described.

[0071] First, a light-transmitting conductive film is formed on a substrate 400 having an insulating surface, and then a first photo Gate electrode layers 411 and 421 are formed by a lithography process. The first photolithography is performed using a material having the same light-transmitting property as the gate electrode layers 411 and 421. In addition, when capacitance is required not only in the pixel section but also in the drive circuit, In this case, a capacitance wiring layer is also formed on the drive circuit. If the resist mask is formed by the inkjet method, a photomask can be used. Therefore, the manufacturing cost can be reduced.

[0072] There is no significant limitation on the substrate that can be used for the substrate 400 having an insulating surface, but at least In any case, it is necessary for the insulating surface to have heat resistance to the extent that it can withstand the subsequent heat treatment. The substrate 400 is made of glass such as barium borosilicate glass or aluminoborosilicate glass. A substrate can be used.

[0073] In addition, when the temperature of the subsequent heat treatment is high, the substrate 400 has a strain point of 730° C. or higher. For the glass substrate, for example, aluminosilicate glass, aluminum Glass materials such as lumino borosilicate glass and barium borosilicate glass are used. In addition, by containing more barium oxide (BaO) than boric acid, it is more practical. Therefore, it is recommended to use a glass substrate containing more BaO than B2O3. It is preferable that:

[0074] Instead of the glass substrate, an insulating substrate such as a ceramic substrate, a quartz substrate, or a sapphire substrate may be used. A substrate made of an insulating material may also be used. Alternatively, crystallized glass or the like may also be used.

[0075] In addition, an insulating film serving as a base film may be provided between the substrate 400 and the gate electrode layers 411 and 421. The underlayer has a function of preventing the diffusion of impurity elements from the substrate 400. A stack of one or more films selected from a silicon oxide film, a silicon nitride oxide film, and a silicon oxynitride film. It can be formed in a layer structure.

[0076] The gate electrode layers 411 and 421 are made of a conductive material that is transparent to visible light, such as In-Sn-Zn-O system, In-Al-Zn-O system, Sn-Ga-Zn-O system, Al-G a-Zn-O series, Sn-Al-Zn-O series, In-Zn-O series, Sn-Zn-O series, Al -Zn-O, In-O, Sn-O, and Zn-O metal oxides can be used. The thickness of the gate electrode layer 411 is appropriately selected within the range of 50 nm to 300 nm. The metal oxide film formation method used in 21 is the sputtering method or vacuum deposition method (electron beam deposition method, etc.). ), arc discharge ion plating method, and spray method are used. Also, sputtering method is used. When using a target containing SiO2 in an amount of 2% by weight or more and 10% by weight or less, the film is formed. In the subsequent process, SiOx (X>0) that inhibits crystallization is contained in the conductive film having light-transmitting properties. It is preferable to suppress crystallization during the heat treatment for dehydration or dehydrogenation. Desirable.

[0077] Next, a gate insulating layer is formed on the gate electrode layers 411 and 421 .

[0078] The gate insulating layer is formed by depositing a silicon oxide layer, a nitride layer, or the like using a plasma CVD method or a sputtering method. The silicon layer, the silicon oxynitride layer, or the silicon nitride oxide layer can be formed as a single layer or a stacked layer. For example, SiH4, oxygen, and nitrogen are used as film-forming gases to form an oxide film by plasma CVD. A silicon nitride layer may be formed.

[0079] In this embodiment, a first gate insulating layer 402a having a thickness of 50 nm to 200 nm is provided. a second gate insulating layer 402b having a thickness of 50 nm or more and 300 nm or less; The first gate insulating layer 402a is a silicon nitride film or a nitride oxide film having a thickness of 100 nm. A silicon film is used. The second gate insulating layer 402b is a silicon oxide film having a thickness of 100 nm. A bare membrane is used.

[0080] An oxide semiconductor film 43 having a thickness of 2 nm to 200 nm is formed on the second gate insulating layer 402b. After the oxide semiconductor film 430 is formed, heat treatment for dehydration or dehydrogenation is performed. In order to make the oxide semiconductor film amorphous even after the etching treatment, the thickness of the oxide semiconductor film is set to be as thin as 50 nm or less. It is preferable that the thickness of the oxide semiconductor film is thinned, so that the heat treatment after the formation of the oxide semiconductor layer can be easily performed. When the film is processed, crystallization can be suppressed.

[0081] Note that before the oxide semiconductor film 430 was formed by a sputtering method, argon gas was introduced. Reverse sputtering is performed to generate plasma, and the film is attached to the surface of the second gate insulating layer 402b. It is preferable to remove the dust that is present on the target. In an argon atmosphere, a voltage is applied to the substrate side using an RF power supply to form plasma near the substrate. The argon atmosphere can be replaced by nitrogen, helium, or oxygen. etc. may also be used.

[0082] The oxide semiconductor film 430 is an In—Ga—Zn—O based non-single crystal film, an In—Sn—Zn—O based , In-Al-Zn-O system, Sn-Ga-Zn-O system, Al-Ga-Zn-O system, Sn- Al-Zn-O series, In-Zn-O series, Sn-Zn-O series, Al-Zn-O series, In-O In this embodiment, an In-Ga-based, Sn-O-based, or Zn-O-based oxide semiconductor film is used. -The film is formed by sputtering using a Zn-O-based oxide semiconductor target. The semiconductor film 430 is heated under a rare gas (typically argon) atmosphere, an oxygen atmosphere, or a rare gas atmosphere. It can be formed by sputtering in an atmosphere of oxygen (typically argon). In addition, when using the sputtering method, a target containing SiO2 in an amount of 2% by weight or more and 10% by weight or less is used. The oxide semiconductor film 430 is formed using a SiOx (x>0) film that inhibits crystallization. This causes crystallization during the heat treatment for dehydration or dehydrogenation in the subsequent process. It is preferable to inhibit caries.

[0083] The oxide semiconductor film is preferably an oxide semiconductor containing In, more preferably The oxide semiconductor film contains In and Ga. The oxide semiconductor film is an i-type (intrinsic) oxide semiconductor film. Therefore, dehydration or dehydrogenation is effective.

[0084] Next, the oxide semiconductor film 430 is subjected to a second photolithography process to form an island-shaped oxide semiconductor film. In addition, a resist mask for forming an island-shaped oxide semiconductor layer is applied to the substrate. If the resist mask is formed by the ink jet method, the photomask Since no disks are used, manufacturing costs can be reduced.

[0085] Next, the oxide semiconductor layer is dehydrated or dehydrogenated. The temperature of the heat treatment in step 1 is 350°C or higher and lower than the strain point of the substrate, preferably 400°C or higher. Here, the substrate is placed in an electric furnace, which is a type of heat treatment apparatus, and the oxide semiconductor layer is After the heat treatment under a nitrogen atmosphere, the oxide semiconductor layer was Re-entry of water or hydrogen is prevented, and oxide semiconductor layers 431 and 432 are obtained (see FIG. 2B). In this embodiment, the heating temperature T at which the oxide semiconductor layer is dehydrated or dehydrogenated is Use the same furnace until the temperature is high enough to prevent water from entering, specifically 100°C higher than the heating temperature T The temperature is gradually cooled in a nitrogen atmosphere until the temperature drops below 100°C. The atmosphere is not limited to nitrogen, and may be helium, neon, or the like. The dehydration or dehydrogenation is carried out under a rare gas atmosphere of argon or under reduced pressure.

[0086] In the first heat treatment, nitrogen or a rare gas such as helium, neon, or argon is used. It is preferable that the nitrogen introduced into the heat treatment device does not contain water, hydrogen, etc. Or the purity of rare gases such as helium, neon, and argon must be 6N (99.9999%) or higher. Preferably, the impurity concentration is 7N (99.99999%) or more (i.e., the impurity concentration is 1 ppm or less, It is preferable to set the concentration to 0.1 ppm or less.

[0087] Depending on the conditions of the first heat treatment or the material of the oxide semiconductor film, the oxide semiconductor film may be crystallized and microcrystalline. It may also be a crystalline or polycrystalline film.

[0088] In addition, the first heat treatment of the oxide semiconductor layer is performed on the oxide semiconductor layer before it is processed into the island-shaped oxide semiconductor layer. The semiconductor film 430 can also be subjected to the first heat treatment. In that case, after the first heat treatment, The substrate is removed and subjected to a photolithography process.

[0089] Before the oxide semiconductor film 430 is formed, an inert gas atmosphere (nitrogen, helium, or neodymium) is used. Heat treatment (400°C or higher) in an oxygen atmosphere or under reduced pressure (in a nitrogen or argon atmosphere) Even if impurities such as hydrogen and water contained in the gate insulating layer are removed by good.

[0090] Next, a metal conductive film is formed on the second gate insulating layer 402b and the oxide semiconductor layers 431 and 432. After forming the conductive film, resist masks 433a and 433b are formed by a third photolithography process. 3b is formed, and selective etching is performed to form metal electrode layers 434 and 435 (FIG. 2 (See (C)). The material of the metal conductive film is Al, Cr, Cu, Ta, Ti, Mo, or W. or an alloy containing the above elements or a combination of the above elements. Alloys, etc.

[0091] The metal conductive film may be a titanium layer, an aluminum layer on the titanium layer, and a titanium layer on the aluminum layer. A three-layer laminate structure, or an aluminum layer on a molybdenum layer and the aluminum It is preferable to use a three-layer laminate structure in which a molybdenum layer is laminated on a metal conductive film. The film may have a single layer structure, a two-layer structure, or a laminated structure of four or more layers.

[0092] In addition, a resist mask for forming metal electrode layers 434 and 435 is formed by an inkjet method. If the resist mask is formed by the inkjet method, a photomask can be used. Therefore, manufacturing costs can be reduced.

[0093] Next, the resist masks 433a and 433b are removed, and a fourth photolithography step is carried out. Resist masks 436a and 436b are formed by this, and selective etching is performed to form source electrodes. The electrode layer 415a and the drain electrode layer 415b are formed (see FIG. 2D). In the photolithography process, the oxide semiconductor layer 431 is only partially etched, and the grooves are formed. The oxide semiconductor layer 431 has a groove ( Resist masks 436a and 436b for forming recesses are formed by an inkjet method. If the resist mask is formed by the inkjet method, a photomask is not required. This reduces manufacturing costs.

[0094] Next, the resist masks 436a and 436b are removed, and a fifth photolithography step is performed. A resist mask 438 is formed to cover the oxide semiconductor layer 437, and the oxide semiconductor layer 432 is then removed. The upper metal electrode layer 435 is removed (see FIG. 2(E)).

[0095] In the fifth photolithography step, the metal electrode layer 435 overlapping with the oxide semiconductor layer 432 is In order to remove the oxide semiconductor layer 432, the oxide semiconductor layer 432 is also removed when the metal electrode layer 435 is etched. The materials and etching conditions are adjusted appropriately so that this does not occur.

[0096] The oxide semiconductor layer 437 is in contact with the upper surface and the side surface of the oxide semiconductor layer 432 and the groove (depression) of the oxide semiconductor layer 437. An oxide insulating film 439 serving as a protective insulating film is formed.

[0097] The oxide insulating film 439 has a thickness of at least 1 nm and is formed by an oxide method such as a sputtering method. The insulating film 439 can be formed by using an appropriate method that does not allow impurities such as water and hydrogen to be mixed in. In this embodiment, a silicon oxide film having a thickness of 300 nm is used as the oxide insulating film 439. The substrate temperature during film formation should be between room temperature and 300°C. In this embodiment, the temperature is set to 100° C. The silicon oxide film is formed by sputtering. Gas (typically argon) atmosphere, oxygen atmosphere, or rare gas (typically argon) atmosphere The target can be a silicon oxide target. A get or silicon target can be used. For example, a silicon target can be used to Silicon oxide can be formed by sputtering in an oxygen and nitrogen atmosphere. The oxide insulating film 439 formed in contact with the oxide semiconductor layer having resistance is resistant to moisture and hydrogen ions. , oxygen ions, OH - It does not contain impurities such as An inorganic insulating film that blocks the insulating film is used, typically a silicon oxide film, a silicon nitride oxide film, or an aluminum oxide film. A film, aluminum oxide nitride, or the like is used.

[0098] Next, a second heat treatment (preferably 2 The heating is performed at a temperature of 00°C or higher and 400°C or lower, for example, 250°C or higher and 350°C or lower (see FIG. 3(A)). For example, the second heat treatment is performed at 250°C for 1 hour in a nitrogen atmosphere. As a result, the grooves of the oxide semiconductor layer 437 and the top and side surfaces of the oxide semiconductor layer 432 are covered with oxide. The insulating film 439 is heated while in contact with the insulating film 439 .

[0099] Through the above steps, the oxide semiconductor film after deposition is dehydrated or dehydrogenated. After the heat treatment for reducing the resistance, a part of the oxide semiconductor film is selectively treated with an oxygen-excess As a result, the channel formation region 413 overlapping with the gate electrode layer 411 becomes an I-type. The first high-resistance drain region 414a overlaps the source electrode layer 415a, and the drain electrode A second high-resistance drain region 414b overlapping the pole layer 415b is formed in a self-aligned manner. In addition, the oxide semiconductor layer 422 overlapping with the gate electrode layer 421 has an i-type structure as a whole.

[0100] However, when the high-resistance (i-type) oxide semiconductor layer 422 is exposed, When heat treatment was performed under nitrogen or inert gas atmosphere or reduced pressure, the resistance increased (I-type). Since the resistance of the oxide semiconductor layer 422 is reduced when the oxide semiconductor layer 422 is exposed, Heat treatment is carried out in an oxygen gas, N2O gas atmosphere, or ultra-dry air (dew point The reaction is carried out at a temperature of -40°C or below, preferably -60°C or below.

[0101] In the oxide semiconductor layer overlapping with the drain electrode layer 415b (and the source electrode layer 415a), to form the second high-resistance drain region 414b (or the first high-resistance drain region 414a). By doing so, it is possible to improve the reliability when forming a driving circuit. By forming the second high-resistance drain region 414b, the second high-resistance The conductivity can be gradually changed from the anti-drain region 414b to the channel forming region. Therefore, the drain electrode layer 415b can be connected to the high power supply potential VDD. When the transistor is connected to a supply wiring for operation, the gate electrode layer 411 and the drain electrode layer 415b Even if a high electric field is applied between the drain and the gate, the high resistance drain region acts as a buffer and prevents a local high electric field from being applied. Therefore, the withstand voltage of the transistor can be improved.

[0102] In addition, the oxide semiconductor layer overlapping with the drain electrode layer 415b (and the source electrode layer 415a) In the second high-resistance drain region 414b (or the first high-resistance drain region 414a), By forming the gate insulating film 414, the leakage current in the channel forming region 413 when the driver circuit is formed can be reduced. It is possible to reduce this.

[0103] Next, resist masks 440a and 440b are formed by a sixth photolithography process. The oxide insulating layer 439 is selectively etched to form the oxide insulating layers 416 and 426. The oxide insulating layer 426 is formed on the oxide semiconductor layer 422. It is provided on the gate insulating film and functions as a channel protection layer. When an oxide insulating layer is used as the insulating layer 402b, etching of the oxide insulating film 439 During the process, a part of the gate insulating layer 402b is also etched, and the film thickness is reduced (the film is reduced). The gate insulating layer 402b may be a nitride insulating film having a high selectivity to the oxide insulating film 439. When an insulating film is used, it is possible to prevent a part of the gate insulating layer 402b from being etched. do.

[0104] Next, a light-transmitting conductive film was formed over the oxide semiconductor layer 422 and the oxide insulating layer 426. After forming the semiconductor layer 420, a source electrode layer 425a and a drain electrode layer 425b are formed by a seventh photolithography process. The polar layer 425b is formed (see FIG. 3(C)). Sputtering, vacuum deposition (electron beam deposition, etc.), and arc discharge ion plating The conductive film is made of a conductive material that is transparent to visible light. Materials such as In-Sn-Zn-O, In-Al-Zn-O, and Sn-Ga-Zn-O , Al-Ga-Zn-O system, Sn-Al-Zn-O system, In-Zn-O system, Sn-Zn- Applying metal oxides of O-based, Al-Zn-O-based, In-O-based, Sn-O-based, and Zn-O-based The film thickness can be appropriately selected within the range of 50 nm to 300 nm. When using the target deposition method, deposition is performed using a target containing 2% to 10% by weight of SiO2. The transparent conductive film contains SiOx (X>0) which inhibits crystallization, and the subsequent process It is preferable to suppress crystallization during the heat treatment in this step.

[0105] Note that a resist mask for forming the source electrode layer 425a and the drain electrode layer 425b is used. The resist mask may be formed by an ink-jet method. Since no photomask is used, manufacturing costs can be reduced.

[0106] Next, the oxide insulating layers 416 and 426, the source electrode layer 425a, and the drain electrode layer 425b are A protective insulating layer 403 is formed on the insulating film 402. In this embodiment, a silicon nitride film is formed by RF sputtering. The RF sputtering method is suitable for mass production, and is therefore used as a method for forming the protective insulating layer 403. The protective insulating layer 403 is preferably formed by absorbing moisture, hydrogen ions, and OH ions. - Does not contain impurities such as Inorganic insulating films are used to block these substances from entering from the outside, and silicon nitride films and aluminum nitride films are used. The protective insulating layer may be an aluminum film, a silicon nitride oxide film, or an aluminum oxide nitride film. 403 is a light-transmitting insulating film.

[0107] The protective insulating layer 403 is formed on the first gate insulating layer 402 provided below the protective insulating layer 403. a) or a structure in contact with the underlying insulating film, and Molecules, hydrogen ions, and OH - In particular, it blocks the intrusion of impurities such as The first gate insulating layer 402a in contact with the insulating layer 403 or the insulating film serving as the base is made of a silicon nitride film. That is, it is effective to form a silicon nitride film so as to surround the bottom surface, top surface, and side surfaces of the oxide semiconductor layer. The provision of the film improves the reliability of the display device.

[0108] Next, a planarization insulating layer 404 is formed over the protective insulating layer 403. For example, heat-resistant materials such as polyimide, acrylic, benzocyclobutene, polyamide, and epoxy are used. In addition to the above organic materials, low dielectric constant materials (lo wk materials), siloxane resin, PSG (phosphorus glass), BPSG (boron phosphorus glass) ) can be used. It is possible to laminate a plurality of insulating films made of these materials. In this way, the planarization insulating layer 404 may be formed.

[0109] Siloxane-based resin is a Si-OS compound formed using siloxane-based materials as starting materials. The siloxane resin corresponds to a resin containing an i bond. Alternatively, an organic group having a fluoro group may be used. That's fine.

[0110] The method for forming the planarization insulating layer 404 is not particularly limited, and may be a sputtering method, a SO 4 method, or the like, depending on the material. G method, spin coating, dip coating, spray coating, droplet ejection method (inkjet method, screen Printing methods such as inkjet printing, offset printing, doctor knife, roll coater, curtain A coater, knife coater, etc. can be used.

[0111] Next, an eighth photolithography step is performed to form a resist mask, and a planarization insulating layer 4 04, and the protective insulating layer 403 is etched to form a contact that reaches the drain electrode layer 425b. A hole 441 is formed (see FIG. 3(D)). Contact holes reaching the gate electrode layers 411 and 421 are also formed. A resist mask for forming a contact hole reaching 425b is made by inkjet printing. If the resist mask is formed by the inkjet method, a photomask can be used. Therefore, the manufacturing cost can be reduced.

[0112] Next, after removing the resist mask, a light-transmitting conductive film is formed. The conductive film material is indium oxide (In2O3) or an indium oxide tin oxide alloy. (In2O3-SnO2, abbreviated as ITO) using sputtering or vacuum deposition methods As another material for the conductive film having light-transmitting properties, an Al-Zn-O system containing nitrogen is used. Non-single crystal film, i.e. Al-Zn-ON non-single crystal film and Zn-O non-single crystal film containing nitrogen Alternatively, a single crystal film or a nitrogen-containing Sn-Zn-O-based non-single crystal film may be used. The composition ratio (atomic %) of zinc in the -ON-based non-single crystal film is 47 atomic % or less, and The aluminum composition ratio (atomic %) in the non-single crystal film is larger than that in the The composition ratio (atomic %) of nitrogen in the non-single crystal film is larger than that in the non-single crystal film. The etching process is carried out using a hydrochloric acid solution. However, when etching ITO in particular, residues are generated. Therefore, indium oxide zinc oxide alloy (In2O 3-ZnO) may also be used.

[0113] The composition ratio of the light-transmitting conductive film is expressed in atomic percent, and is measured by an electron probe microanalyzer. (EPMA:Electron Probe X-ray MicroAnalyzer ) will be evaluated by analysis.

[0114] Next, a ninth photolithography step is performed to form a resist mask and then etch the Then, unnecessary portions are removed to form a pixel electrode layer 427 and a conductive layer 417 (see FIG. 3(E)). .).

[0115] Through the above steps, the thin film transistor 410 and the thin film transistor 411 are formed on the same substrate using nine masks. The film transistor 420 can be fabricated separately for the driver circuit or the pixel portion. The thin film transistor 410 for the driving circuit has a first high-resistance drain region 414a, a second The oxide semiconductor layer 41 includes the high-resistance drain region 414b and the channel formation region 413. 2, and the pixel thin film transistor 420 is a channel-etched thin film transistor including , a channel-protective thin film transistor including an oxide semiconductor layer 422 that is entirely i-type. .

[0116] In addition, the first gate insulating layer 402a and the second gate insulating layer 402b are used as dielectrics, and the capacitance wiring The storage capacitor formed by the layer and the capacitor electrode can also be formed on the same substrate. The pixel section is configured by arranging the resistor 420 and the storage capacitor in a matrix corresponding to each pixel. By disposing a driver circuit having a thin film transistor 410 around the pixel portion, The present invention can be used as one of the substrates for manufacturing a display device of a passive matrix type. For convenience, such a substrate is called an active matrix substrate.

[0117] The pixel electrode layer 427 is formed on the planarization insulating layer 404 and the protective insulating layer 403. The capacitor electrode is electrically connected to the source electrode layer through a contact hole. The drain electrode layer 425a and the drain electrode layer 425b are formed using the same light-transmitting material and process. can be done.

[0118] The conductive layer 417 is provided so as to overlap with the channel formation region 413 of the oxide semiconductor layer. Therefore, a bias-thermal stress test (hereinafter referred to as BT) is conducted to check the reliability of thin film transistors. In the test, the threshold voltage of the thin film transistor 410 before and after the BT test was In addition, the conductive layer 417 has a potential that is the same as that of the gate electrode layer 411. It may be the same as or different from the first gate electrode layer and may also function as a second gate electrode layer. The potential of the conductive layer 417 may be GND, 0V, or may be in a floating state. .

[0119] In addition, a resist mask for forming the pixel electrode layer 427 is formed by an ink-jet method. If the resist mask is formed by the inkjet method, no photomask is required. , and manufacturing costs can be reduced.

[0120] (Embodiment 2) In this embodiment mode, the heat treatment of the pixel thin film transistor is different from that in Embodiment Mode 1. This is shown in Figure 4. Figure 4 is the same as Figures 1 to 3 except for some differences in the process. The same reference numerals are used for the same parts, and detailed explanations of the same parts will be omitted.

[0121] First, the steps up to FIG. 3(B) in the first embodiment are carried out in accordance with the first embodiment. A) shows the state after the process of FIG. 3B, where the resist masks 440a and 440b have been removed. .

[0122] On a substrate 400 having an insulating surface, gate electrode layers 411 and 421, a first gate insulating layer 4 02a, a second gate insulating layer 402b are formed, and in the driver circuit area, a channel forming region The drain region 413 includes a first high-resistance drain region 414a and a second high-resistance drain region 414b. The oxide semiconductor layer 412, the source electrode layer 415a, the drain electrode layer 415b, and the oxide insulating layer 416 are In the pixel portion, an oxide semiconductor layer 422 and an oxide insulating layer 426 are formed. The oxide semiconductor layer 422 is an i-type oxide semiconductor layer with high resistance (see FIG. 4A). .

[0123] In this embodiment, the oxide semiconductor layer 422 is exposed to nitrogen. The heat treatment is performed in an inert gas atmosphere or under reduced pressure. The oxide semiconductor layer 422 is exposed under a nitrogen or inert gas atmosphere or a reduced pressure. By the heat treatment, exposed portions of the oxide semiconductor layer 422 are made high-resistance (i-type). The resistivity of the region (which has been removed) can be reduced.

[0124] In the oxide semiconductor layer 422, a high-resistance (i-type) region is converted to a low-resistance region. The heat treatment is preferably carried out at a temperature of 200°C or higher and 400°C or lower, for example, 250°C or higher and 350°C or lower. For example, heat treatment is performed in a nitrogen atmosphere at 250° C. for 1 hour.

[0125] In this embodiment, the substrate is introduced into an electric furnace, which is one of the heat treatment devices, and the oxide semiconductor layer 4 After heat treatment under a nitrogen atmosphere, the heating temperature was The temperature is gradually cooled from T to 100°C below the heating temperature T in a nitrogen atmosphere. The atmosphere is not limited to nitrogen, and may be a rare gas atmosphere such as helium, neon, or argon, or may be under reduced pressure. In the heat treatment, dehydration or dehydrogenation is performed in the presence of nitrogen or helium. It is preferable that the rare gases such as neon and argon do not contain water, hydrogen, etc., or The purity of nitrogen or rare gases such as helium, neon, and argon introduced into the heat treatment device is 6N (99.9999%) or more, preferably 7N (99.99999%) or more (i.e., non- It is preferable to keep the concentration of impurities at 1 ppm or less, preferably 0.1 ppm or less.

[0126] The oxide semiconductor layer 422 is subjected to heat treatment in a nitrogen or inert gas atmosphere or under reduced pressure. As a result, the exposed region of the oxide semiconductor layer 422 has a low resistance, and the exposed region has a different resistance (see FIG. 4B). In this example, the oxide semiconductor layer 442 has a thin film (shown as a hatched region and a white region).

[0127] Next, a light-transmitting conductive film was formed over the oxide semiconductor layer 442 and the oxide insulating layer 426. After forming the semiconductor layer 420, a source electrode layer 425a and a drain electrode layer 425b are formed by a seventh photolithography process. The pole layer 425b is formed (see FIG. 4(C)).

[0128] Next, the oxide insulating layers 416 and 426, the source electrode layer 425a, and the drain electrode layer 425b are A protective insulating layer 403 and a planarizing insulating layer 404 are stacked on top of the insulating layer 403 .

[0129] Next, an eighth photolithography step is performed to form a resist mask, and a planarization insulating layer 4 04, and the protective insulating layer 403 is etched to form a contact that reaches the drain electrode layer 425b. A cut hole 441 is formed (see FIG. 4(D)).

[0130] Next, after removing the resist mask, a light-transmitting conductive film is formed.

[0131] Next, a ninth photolithography step is performed to form a resist mask and then etch the Then, unnecessary portions are removed to form a pixel electrode layer 427 and a conductive layer 417 (see FIG. 4(E)). .).

[0132] Through the above steps, the thin film transistor 410 and the thin film transistor 411 are formed on the same substrate using nine masks. The film transistor 448 can be fabricated separately for the driver circuit or pixel portion. The thin film transistor 410 for the driving circuit has a first high-resistance drain region 414a, a second The oxide semiconductor layer 41 includes the high-resistance drain region 414b and the channel formation region 413. 2, and the thin film transistor 448 for the pixel is also , a first high-resistance drain region 424a, a second high-resistance drain region 424b, and a channel a channel-protective thin film transistor including an oxide semiconductor layer 442 including a channel-forming region 423; Therefore, the thin film transistors 410 and 448 have a high resistance drain even when a high electric field is applied. The gate region acts as a buffer, preventing localized high electric fields from being applied, improving the breakdown voltage of the transistor. It is composed of:

[0133] In addition, the first gate insulating layer 402a and the second gate insulating layer 402b are used as dielectrics, and the capacitance wiring The storage capacitor formed by the layer and the capacitor electrode can also be formed on the same substrate. The pixel section is composed of a matrix of registers 448 and storage capacitors corresponding to each pixel. By disposing a driver circuit having a thin film transistor 410 around the pixel portion, The substrate can be used as one of the substrates for manufacturing a display device of a passive matrix type.

[0134] The conductive layer 417 is provided so as to overlap with a channel formation region of the oxide semiconductor layer 412. Therefore, a bias-thermal stress test (hereinafter referred to as BT) is conducted to check the reliability of thin film transistors. In the test, the threshold voltage of the thin film transistor 410 before and after the BT test was In addition, the conductive layer 417 has a potential that is the same as that of the gate electrode layer 411. It may be the same as or different from the first gate electrode layer and may also function as a second gate electrode layer. The potential of the conductive layer 417 may be GND, 0V, or may be in a floating state. .

[0135] (Embodiment 3) In this embodiment mode, an example in which the first heat treatment is different from that in Embodiment Mode 1 is shown in FIG. 1 to 3 except for some differences in the steps, the same reference numerals are used for the same parts. Detailed explanations of the same parts will be omitted.

[0136] First, according to the first embodiment, a light-transmitting conductive film is formed on a substrate 400 having an insulating surface. After forming the gate electrode layers 411 and 421, a first photolithography process is performed. do.

[0137] Next, a first gate insulating layer 402a and a second gate insulating layer 402b are formed on the gate electrode layers 411 and 421. The edge layer 402b is laminated (see FIG. 5(A)). Note that FIG. 5(A) is different from FIG. 2(A). The steps up to this point are the same as those in the first embodiment.

[0138] Next, an oxide semiconductor film having a thickness of 2 nm to 200 nm is deposited on the second gate insulating layer 402b. The membrane 430 is formed (see FIG. 5(A)). Note that the steps up to this point are the same as those in the first embodiment. They are the same, and FIG. 5(A) corresponds to FIG. 2(A).

[0139] Next, the oxide semiconductor film 430 is dehydrated or oxidized under an inert gas atmosphere or reduced pressure. The temperature of the first heat treatment for dehydration or dehydrogenation is 350°C or higher. The temperature is set to be lower than the distortion point of the substrate, preferably 400°C or higher. The substrate is placed in an electric furnace, and the oxide semiconductor film 430 is subjected to heat treatment in a nitrogen atmosphere. After the above, the oxide semiconductor film 430 is heated without being exposed to the air to prevent water and hydrogen from being mixed in again. The oxide semiconductor film 430 is made oxygen-deficient to have low resistance, that is, to be made N-type (N - etc.) Then, high-purity oxygen gas, high-purity N2O gas, or ultra-dry air (dew point -4 Cooling is performed by introducing oxygen gas or N2O gas (0°C or less, preferably -60°C or less). It is preferable that the oxygen gas introduced into the heat treatment device does not contain water, hydrogen, etc. The purity of the N2O or N2O gas should be 6N (99.9999%) or higher, preferably 7N (99. 99999%) or more (i.e., impurity concentration in oxygen gas or N2O gas is 1 ppm or less, Preferably, it is 0.1 ppm or less.

[0140] After the first heat treatment for dehydration or dehydrogenation, the temperature is preferably 200° C. or higher and 400° C. or lower. Or heat treatment at a temperature between 200°C and 300°C in an oxygen gas or N2O gas atmosphere. The theory may also be carried out.

[0141] By going through the above steps, the entire oxide semiconductor film is made into an oxygen-excess state, and thus a high resistance It transforms it into an anti-type, i.e., type I.

[0142] As a result, the reliability of the thin film transistors to be formed later can be improved.

[0143] Next, the oxide semiconductor film is subjected to a photolithography process to form an oxide semiconductor layer having an island shape. The resulting semiconductor layers are then processed into oxide semiconductor layers 444 and 422 (see FIG. 5(B)). The oxide semiconductor layer 422 has the same high resistance as the oxide semiconductor layer 422 in FIG. Since the oxide semiconductor layers are made i-type, the same reference numerals are used. Thin films formed using different methods have the same functions and properties (e.g., resistance). The same reference numerals may be used to denote the thin films that have the same structure.

[0144] Note that in this embodiment, an example in which dehydration or dehydrogenation is performed after the oxide semiconductor film is formed will be described. However, the first heat treatment of the oxide semiconductor film is not particularly limited to the above. Alternatively, the oxide semiconductor layer may be processed as described above.

[0145] Further, the oxide semiconductor film may be dehydrated or dehydrogenated under an inert gas atmosphere or reduced pressure. After cooling under an inert gas atmosphere, island-shaped oxide layers are formed by a photolithography process. Then, the oxide semiconductor layers 444 and 422 are processed into the oxide semiconductor layers. ° C. or less, preferably 200 to 300 ° C., under oxygen gas or N2O gas. Heat treatment may be carried out.

[0146] In addition, before the formation of the oxide semiconductor film, an inert gas atmosphere (nitrogen, helium, neon, Heat treatment (400°C or higher) in an oxygen atmosphere or reduced pressure (argon, etc.) impurities such as hydrogen and water contained in the gate insulating layer may be removed by performing a annealing treatment (below the annealing point).

[0147] However, the high-resistance (i-type) oxide semiconductor layers 444 and 422 are exposed. When heat treatment is performed under nitrogen, inert gas atmosphere, or reduced pressure in this state, the resistance becomes high ( Since the resistance of the oxide semiconductor layers 444 and 422 (which have been made i-type) is reduced, The heat treatment performed with the layers 444 and 422 exposed is performed in an oxygen gas or N2O gas atmosphere. Alternatively, use ultra-dry air (dew point of -40°C or less, preferably -60°C or less).

[0148] After that, similar to FIGS. 2(C) to 2(E) and 3(A) to 3(E) in the first embodiment, In the peripheral driver circuit section, only a part of the oxide semiconductor layer 444 is etched to form a groove ( The oxide semiconductor layer 443 having a recessed portion is formed, and the source electrode layer 415a which is a metal conductive layer is formed. The drain electrode layer 415b and the oxide insulating layer 416 in contact with the oxide semiconductor layer 443 are formed. On the other hand, in the pixel portion, a thin film transistor 449 for a driver circuit is manufactured. An oxide insulating layer 426 is formed over a channel formation region of the semiconductor layer 422, and a light-transmitting conductive layer A source electrode layer 425a and a drain electrode layer 425b are formed as thin film transistors for pixels. A transistor 420 is fabricated.

[0149] Next, a second heat treatment (preferably 2 For example, the temperature is increased by heating in a nitrogen atmosphere. A second heat treatment is carried out at 250°C under atmospheric pressure for 1 hour.

[0150] Then, the oxide insulating layers 416 and 426 and the source electrode 424 are formed over the thin film transistors 449 and 420. The protective insulating layer 403 and the planarizing insulating layer 404 are in contact with the source electrode layer 425a and the drain electrode layer 425b. The protective insulating layer 403 and the planarizing insulating layer 404 are stacked to form a drain electrode. A contact hole reaching the electrode layer 425b is formed, and the contact hole and the planarizing insulating layer 4 A light-transmitting conductive film is formed on the substrate 4. The light-transmitting conductive film is selectively etched. The pixel electrode layer 427 and the conductive layer 417 are electrically connected to the thin film transistor 420. Form.

[0151] Through the above steps, a thin film transistor 449 and a thin film transistor 448 are formed on the same substrate using nine masks. The film transistor 420 can be fabricated separately for the driver circuit or the pixel portion. The thin film transistor 449 for the driver circuit has an oxide semiconductor layer 443 that is entirely i-type. The thin film transistor 420 for the pixel is also a channel-etched thin film transistor including The channel protective thin film transistor includes an oxide semiconductor layer 422 whose body is i-type.

[0152] In addition, the first gate insulating layer 402a and the second gate insulating layer 402b are used as dielectrics, and the capacitance wiring The storage capacitor formed by the layer and the capacitor electrode can also be formed on the same substrate. The pixel section is configured by arranging the resistor 420 and the storage capacitor in a matrix corresponding to each pixel. By disposing a driver circuit having a thin film transistor 449 around the pixel portion, The substrate can be used as one of the substrates for manufacturing a display device of a passive matrix type.

[0153] The conductive layer 417 is provided so as to overlap with a channel formation region of the oxide semiconductor layer 443. Therefore, a bias-thermal stress test (hereinafter referred to as BT) is conducted to check the reliability of thin film transistors. In the test, the threshold voltage of the thin film transistor 449 before and after the BT test was In addition, the conductive layer 417 has a potential that is the same as that of the gate electrode layer 411. It may be the same as or different from the first gate electrode layer and may also function as a second gate electrode layer. The potential of the conductive layer 417 may be GND, 0V, or may be in a floating state. .

[0154] (Fourth embodiment) In this embodiment mode, the first heat treatment of the pixel thin film transistor is different from that in Embodiment Mode 3. An example of this is shown in Figure 6. Figure 6 is the same as Figures 1 to 5 except for some differences in the process. The same parts are designated by the same reference numerals, and detailed explanations of the same parts will be omitted.

[0155] First, the steps up to FIG. 5(B) in the third embodiment are carried out in accordance with the third embodiment. A) is the same as the process in FIG. 5(B).

[0156] On a substrate 400 having an insulating surface, gate electrode layers 411 and 421, a first gate insulating layer 4 02a, a second gate insulating layer 402b, and an oxide semiconductor layer In the pixel portion, an oxide semiconductor layer 422 is formed (FIG. 6(A)). ) The oxide semiconductor layers 444 and 422 are i-type with high resistance.

[0157] In the peripheral driver circuit section, only a part of the oxide semiconductor layer 444 is etched to form a groove ( The oxide semiconductor layer 443 having a recessed portion is formed, and the source electrode layer 415a which is a metal conductive layer is formed. The drain electrode layer 415b and the oxide insulating layer 416 in contact with the oxide semiconductor layer 443 are formed. On the other hand, in the pixel portion, a thin film transistor 449 for a driver circuit is manufactured. An oxide insulating layer 426 is formed over a channel formation region of the semiconductor layer 422 (see FIG. 6B). .).

[0158] In this embodiment, as in Embodiment 2, at least a part of the oxide semiconductor layer 422 is exposed. In this state, heat treatment is performed in a nitrogen or inert gas atmosphere or under reduced pressure. The oxide semiconductor layer 422 is exposed in an inert gas atmosphere containing nitrogen. When heat treatment is performed under atmospheric pressure or reduced pressure, the exposed high-temperature oxide semiconductor layer 422 is The resistive (I-type) region can be made to have a low resistance.

[0159] In the oxide semiconductor layer 422, a high-resistance (i-type) region is converted to a low-resistance region. The heat treatment is preferably carried out at a temperature of 200°C or higher and 400°C or lower, for example, 250°C or higher and 350°C or lower. For example, heat treatment is performed in a nitrogen atmosphere at 250° C. for 1 hour.

[0160] In this embodiment, the substrate is introduced into an electric furnace, which is one of the heat treatment devices, and the oxide semiconductor layer 4 After heat treatment under a nitrogen atmosphere, the heating temperature was The temperature is gradually cooled from T to 100°C below the heating temperature T in a nitrogen atmosphere. The decomposition is not limited to an oxygen atmosphere, but may be carried out under an atmosphere of helium, neon, argon, or the like, or under reduced pressure. The heat treatment is carried out by hydration or dehydrogenation. It is preferable that the rare gas such as argon does not contain water, hydrogen, etc. The purity of nitrogen or rare gases such as helium, neon, and argon introduced into the equipment is 6N (9 9.9999%) or more, preferably 7N (99.99999%) or more (i.e., impurity concentration It is preferable to set the concentration of the HCl-containing compound to 1 ppm or less, preferably 0.1 ppm or less.

[0161] The oxide semiconductor layer 422 is subjected to heat treatment in a nitrogen or inert gas atmosphere or under reduced pressure. As a result, the exposed region of the oxide semiconductor layer 422 has a low resistance, and the exposed region has a different resistance (see FIG. 6C). In this example, the oxide semiconductor layer 442 has a thin film (shown as a hatched region and a white region).

[0162] Next, a light-transmitting conductive film was formed over the oxide semiconductor layer 442 and the oxide insulating layer 426. After forming the semiconductor layer 420, a source electrode layer 425a and a drain electrode layer 425b are formed by a seventh photolithography process. The pole layer 425b is formed.

[0163] Next, the oxide insulating layers 416 and 426, the source electrode layer 425a, and the drain electrode layer 425b are A protective insulating layer 403 and a planarizing insulating layer 404 are stacked on top of the insulating layer 403 .

[0164] A contact is formed on the protective insulating layer 403 and the planarizing insulating layer 404, reaching the drain electrode layer 425b. A light-transmitting conductive film is formed over the contact holes and the planarization insulating layer 404. The light-transmitting conductive film is selectively etched to form a thin film transistor 448. A pixel electrode layer 427 and a conductive layer 417 are formed to be electrically connected to each other (see FIG. 6D). .

[0165] Through the above steps, a thin film transistor 449 and a thin film transistor 448 are formed on the same substrate using nine masks. The film transistor 448 can be fabricated separately for the driver circuit or pixel portion. The thin film transistor 449 for the driver circuit has an oxide semiconductor layer 443 that is entirely i-type. The pixel thin film transistor 448 is a channel-etched thin film transistor including the first The first high-resistance drain region 424a, the second high-resistance drain region 424b, and the channel-type The channel-protective thin film transistor includes an oxide semiconductor layer 442 including a semiconductor region 423. The thin film transistor 448 has a high resistance drain region that acts as a buffer even when a high electric field is applied. This prevents the application of a local high electric field, improving the breakdown voltage of the transistor.

[0166] In addition, the first gate insulating layer 402a and the second gate insulating layer 402b are used as dielectrics, and the capacitance wiring The storage capacitor formed by the layer and the capacitor electrode can also be formed on the same substrate. The pixel section is composed of a matrix of registers 448 and storage capacitors corresponding to each pixel. By disposing a driver circuit having a thin film transistor 449 around the pixel portion, The substrate can be used as one of the substrates for manufacturing a display device of a passive matrix type.

[0167] The conductive layer 417 is provided so as to overlap with a channel formation region of the oxide semiconductor layer 443. Therefore, a bias-thermal stress test (hereinafter referred to as BT) is conducted to check the reliability of thin film transistors. In the test, the threshold voltage of the thin film transistor 449 before and after the BT test was In addition, the conductive layer 417 has a potential that is the same as that of the gate electrode layer 411. It may be the same as or different from the first gate electrode layer and may also function as a second gate electrode layer. The potential of the conductive layer 417 may be GND, 0V, or may be in a floating state. .

[0168] (Embodiment 5) In this embodiment mode, the active matrix substrate shown in Embodiment Mode 1 is used to This embodiment shows an example of manufacturing a sub-matrix liquid crystal display device. The present invention can also be applied to the active matrix substrates shown in 2 to 4.

[0169] An example of the cross-sectional structure of an active matrix substrate is shown in FIG.

[0170] In the first embodiment, the thin film transistors of the driver circuit and the thin film transistors of the pixel section are formed on the same substrate. In this embodiment, in addition to the thin film transistors, a storage capacitor, a gate The terminals of the wiring and the source wiring are also shown in the figures. can be formed by the same manufacturing steps as those described in Embodiment 1, and the number of photomasks is This can be fabricated without increasing the number of steps or the number of wirings. In the area where the gate wiring, the source wiring, and the capacitance wiring layer are all made of a conductive material having light transmission properties. The film is made of a thin film, which realizes a high aperture ratio. The wiring layer can be made of metal wiring to reduce the wiring resistance.

[0171] In FIG. 7A, a thin film transistor 210 is a channel etched thin film transistor (TFT) provided in a driving circuit. In this embodiment, the thin film transistor 41 of the first embodiment is The thin film transistor 220 electrically connected to the pixel electrode layer 227 has the same structure as that of the thin film transistor 220. , a channel protective thin film transistor provided in a pixel portion. The same structure as the thin film transistor 420 of the first embodiment is used.

[0172] The gate electrode layer of the thin film transistor 220 is formed of the same material and in the same process as the gate electrode layer of the thin film transistor 220. The capacitor wiring layer 230 is made up of a first gate insulating layer 202a and a second gate insulating layer 202b, which are dielectrics. The capacitor electrode 231 overlaps with the insulating layer 202b, forming a storage capacitor. The thin film transistor 220 has a light-transmitting property similar to that of the source electrode layer or the drain electrode layer. Therefore, the thin film transistor 220 has a light-transmitting property. In addition, each storage capacitor is transparent, which improves the aperture ratio. can be done.

[0173] It is important for the storage capacitor to have light transmittance in order to improve the aperture ratio. In the following small LCD panels, the number of gate wirings is increased to improve the resolution of the displayed image. Even if the pixel size is made smaller to achieve higher resolution, a high aperture ratio can be achieved. By using a light-transmitting film as a component of the thin film transistor 220 and the storage capacitor, To achieve a wide viewing angle, a high aperture ratio is achieved even when one pixel is divided into multiple sub-pixels. That is, even if a group of high-density thin film transistors is arranged, a large aperture ratio can be obtained. For example, if two to four pixels are arranged in one pixel, the area of ​​the display region can be sufficiently secured. When there are four sub-pixels and a storage capacitor, the thin film transistor is transparent. In addition, each storage capacitor is also transparent, which can improve the aperture ratio. do.

[0174] The storage capacitor is provided below the pixel electrode layer 227, and the capacitor electrode 231 is connected to the pixel electrode layer 2 27 is electrically connected to the

[0175] In this embodiment, a storage capacitor is formed using a capacitor electrode 231 and a capacitor wiring layer 230. However, the structure for forming the storage capacitor is not particularly limited. The pixel electrode layer is not provided with a gate wiring of an adjacent pixel, a planarizing insulating layer, a protective insulating layer, and A storage capacitor may be formed by overlapping the first gate insulating layer and the second gate insulating layer therebetween.

[0176] Also, a plurality of gate wirings, source wirings, and capacitance wiring layers are provided depending on the pixel density. In the terminal section, a first terminal electrode having the same potential as the gate wiring, a source wiring, a second terminal electrode having the same potential as the capacitor wiring layer, a third terminal electrode having the same potential as the capacitor wiring layer, and so on are arranged in a row. The number of each terminal electrode may be any number. The contractor should make the appropriate decision.

[0177] In the terminal portion, the first terminal electrode having the same potential as the gate wiring is formed of the same light-transmitting material as the pixel electrode layer 227. The first terminal electrode can be formed of a material having a good conductivity. The contact hole is electrically connected to the gate wiring. The wiring electrically connects the drain electrode layer of the thin film transistor 220 and the pixel electrode layer 227. The same photomask as that used for the contact holes for connecting the planarization insulating layer 204 and the protective insulating layer 205 is used. The edge layer 203, the oxide insulating layer 216, the second gate insulating layer 202b, and the first gate insulating layer 202c. Layer 202a is formed by selective etching.

[0178] The gate electrode layer of the thin film transistor 210 of the driving circuit is provided above the oxide semiconductor layer. In this case, the thin film transistor 216 may be electrically connected to the conductive layer 217. A contact for electrically connecting the drain electrode layer of the transistor 220 and the pixel electrode layer 227. Using the same photomask as the tact hole, the planarization insulating layer 204, the protective insulating layer 203, and the oxide The gate insulating layer 216, the second gate insulating layer 202b, and the first gate insulating layer 202a are selected. A contact hole is formed by selectively etching the conductive layer through the contact hole. 217 and the gate electrode layer of the thin film transistor 210 of the driving circuit are electrically connected.

[0179] The second terminal electrode 235, which has the same potential as the source wiring 234 of the driving circuit, is connected to the pixel electrode layer 22. The second terminal electrode 235 can be formed of the same light-transmitting material as the source electrode 7. The source wiring is electrically connected to the source electrode via a contact hole that reaches the wiring 234. The wiring is a metal wiring, and is made of the same material and in the same process as the source electrode layer of the thin film transistor 210. are formed and are at the same potential.

[0180] The third terminal electrode, which has the same potential as the capacitor wiring layer 230, has the same light-transmitting property as the pixel electrode layer 227. In addition, the contact hole reaching the capacitor wiring layer 230 can be formed of a material having the above-mentioned properties. The contact holes are formed at the same time as the contact holes for electrically connecting the capacitor electrodes 231 to the pixel electrode layer 227. The same photomask can be used in the same process.

[0181] In addition, when an active matrix type liquid crystal display device is manufactured, A liquid crystal layer is provided between a substrate and an opposing substrate on which an opposing electrode (also called an opposing electrode layer) is provided. The active matrix substrate and the counter substrate are fixed together. A common electrode electrically connected to the electrode is provided on the active matrix substrate. A fourth terminal electrode is provided on the terminal portion, which is electrically connected to the common electrode. The fourth terminal electrode is a terminal for setting the potential, for example, GND, 0V, etc. It can be made of the same light-transmitting material as the pole layer 227 .

[0182] In addition, the source electrode layer of the thin film transistor 220 and the source electrode layer of the thin film transistor 210 The configuration for electrically connecting the source of the thin film transistor 220 is not particularly limited. A connection electrode that connects the electrode layer and the source electrode layer of the thin film transistor 210 is formed on the pixel electrode layer 227. In addition, in the portion other than the display area, the thin film transistor 2 may be formed in the same process. The source electrode layer of the thin film transistor 20 and the source electrode layer of the thin film transistor 210 are overlapped in contact with each other. That's fine.

[0183] The cross-sectional structure of the gate wiring 232 of the driving circuit is shown in FIG. is an example of a small LCD panel of 10 inches or less, so the gate wiring 23 of the driving circuit The layer 2 is made of the same light-transmitting material as the gate electrode layer of the thin film transistor 220 .

[0184] Also, a gate electrode layer, a source electrode layer, a drain electrode layer, a pixel electrode layer, or other electrodes If the same material is used for the wiring layers, a common sputtering target and common manufacturing equipment can be used. The cost of the material and the etchant (or This reduces the cost of etching gases, resulting in reduced manufacturing costs. It is possible.

[0185] In the structure of FIG. 7A, a photosensitive resin material is used as the planarization insulating layer 204. In this case, the step of forming a resist mask can be omitted.

[0186] FIG. 7(B) shows a cross-sectional structure that is partially different from that shown in FIG. 7(A). A) is the same as A) except that the planarization insulating layer 204 is not present, and therefore the same parts are designated by the same reference numerals. 7B, the protective insulating layer 203 is in contact with the protective insulating layer 203. The pixel electrode layer 227, the conductive layer 217, and the second terminal electrode 235 are formed.

[0187] With the structure of FIG. 7B, the step of forming the planarization insulating layer 204 can be omitted.

[0188] This embodiment mode can be freely combined with any of Embodiment Modes 1 to 4.

[0189] (Embodiment 6) In this embodiment, the size of the liquid crystal display panel exceeds 10 inches, and is 60 inches or even When using a 120-inch screen, the wiring resistance of the light-transmitting wiring may become a problem. An example in which a part of the gate wiring is made into a metal wiring to reduce wiring resistance will be shown.

[0190] In FIG. 8(A), the same parts as those in FIG. 7(A) are designated by the same reference numerals, and detailed explanations of the same parts will be omitted. Note that this embodiment mode is the same as the embodiment mode 1, except that the active matrix substrate shown in any of Embodiments 1 to 4 is used. can be applied to.

[0191] FIG. 8A shows a gate wiring of the driving circuit made of metal, and a thin film transistor 210 In this example, the gate electrode layer is formed in contact with a wiring having the same light-transmitting property as the gate electrode layer. Therefore, the number of photomasks increases compared to the first embodiment.

[0192] First, a layer capable of withstanding the first heat treatment for dehydration or dehydrogenation is formed on the substrate 200. A heat-resistant conductive material film (thickness: 100 nm or more and 500 nm or less) is formed.

[0193] In this embodiment, a tungsten film having a thickness of 370 nm is used as the first metal wiring layer, and a second gold A tantalum nitride film with a thickness of 50 nm is formed as a metal wiring layer. However, there is no particular limitation, and the material may be Ta, W, Ti, Mo, Al , Cu, or an alloy containing the above elements, or a combination of the above elements. The heat-resistant conductive material is formed of an alloy film made of the above elements or a nitride film made of the above elements. The film is not limited to a single layer containing the above-mentioned elements, but may be a laminate of two or more layers.

[0194] A metal wiring is formed by a first photolithography process, and a first metal wiring layer 236 and a second The metal wiring layer 237 is formed. The tungsten film and the tantalum nitride film are etched using I. CP (Inductively Coupled Plasma) It is recommended to use the etching method. The ICP etching method is used, and the etching conditions (coil type) The amount of power applied to the electrode, the amount of power applied to the electrode on the substrate side, the temperature of the electrode on the substrate side, etc. By adjusting the etching rate appropriately, the film can be etched into a desired tapered shape. The metal wiring layer 236 and the second metal wiring layer 237 are tapered to form a contact on top. Defective film formation of a light-transmitting conductive film can be reduced.

[0195] Next, a light-transmitting conductive film is formed, and then a gate is formed by a second photolithography process. the gate wiring layer 238, the gate electrode layer of the thin film transistor 210, the gate electrode layer of the thin film transistor 220, The light-transmitting conductive film is a light-transmitting conductive film that transmits light to visible light as described in Embodiment 1. A light-transmitting conductive material is used.

[0196] Note that depending on the material of the light-transmitting conductive film, for example, the gate wiring layer 238 may be made of a first gold If there is an interface in contact with the metal wiring layer 236 or the second metal wiring layer 237, the interface may be damaged during subsequent heat treatment, etc. Therefore, an oxide film is formed, which may increase the contact resistance. It is preferable to use a metal nitride film that prevents oxidation of the first metal wiring layer 236.

[0197] Next, a gate insulating layer, an oxide semiconductor layer, and the like are formed in the same steps as those in Embodiment 1. In this step, an active matrix substrate is manufactured according to the first embodiment.

[0198] In this embodiment, after the planarization insulating layer 204 is formed, a photomask is used to This shows an example of selectively removing the planarizing insulating layer in the terminal area. It is preferable not to do this in order to ensure a good connection with the FPC.

[0199] In FIG. 8A, the second terminal electrode 235 is formed on the protective insulating layer 203. 8(A) shows the gate wiring layer 238 overlapping a part of the second metal wiring layer 237. It can also be used as a gate wiring layer that covers the entire first metal wiring layer 236 and the second metal wiring layer 237. That is, the first metal wiring layer 236 and the second metal wiring layer 237 are formed on the gate wiring layer 23. 8 can be called an auxiliary wiring for reducing resistance.

[0200] In the terminal portion, the first terminal electrode having the same potential as the gate wiring is disposed on the protective insulating layer 203. The wiring from the terminal portion is also made of metal. Formed by wiring.

[0201] In addition, the gate wiring layer and the capacitance wiring layer in the non-display area are Metal wiring, that is, the first metal wiring layer 236 and the second metal wiring layer 237 are used as auxiliary wiring. It can also be used.

[0202] FIG. 8(B) shows a cross-sectional structure that is partly different from that shown in FIG. 8(A). A) and the drive circuit are the same except for the material of the gate electrode layer of the thin film transistor. Therefore, the same parts are designated by the same reference numerals, and detailed explanations of the same parts will be omitted.

[0203] FIG. 8B shows an example in which the gate electrode layer of the thin film transistor of the driver circuit is made of metal wiring. In the driver circuit, the material for the gate electrode layer is not limited to a light-transmitting material.

[0204] In FIG. 8B, the thin film transistor 240 of the driving circuit is formed on the first metal wiring layer 242. The second metal wiring layer 241 is stacked as a gate electrode layer. The second metal wiring layer 236 can be formed using the same material and process as the first metal wiring layer 236. The second metal wiring layer 241 is formed using the same material and in the same process as the second metal wiring layer 237. can be done.

[0205] In addition, when the first metal wiring layer 242 is electrically connected to the conductive layer 217, the first metal wiring The second metal wiring layer 241 is preferably a metal nitride film to prevent oxidation of the layer 242. .

[0206] In this embodiment, the wiring resistance is reduced by using a part of the metal wiring, and the size of the liquid crystal display panel is Even if the display size exceeds 10 inches and is set to 60 inches or even 120 inches, High definition and a high aperture ratio can be achieved.

[0207] (Embodiment 7) In this embodiment, an example of the configuration of the storage capacitor that is different from that of the fifth embodiment is shown in FIG. 9(A) and This is shown in Figure 9(B). Figure 9(A) is the same as Figure 7(A) except for the configuration of the storage capacitor. Therefore, the same parts are designated by the same reference numerals, and detailed explanations of the same parts will be omitted. 1A shows the cross-sectional structure of a thin film transistor 220 and a storage capacitor in the pixel portion.

[0208] FIG. 9(A) shows the dielectric layer consisting of an oxide insulating layer 216, a protective insulating layer 203, and a planarizing insulating layer 20 4, the pixel electrode layer 227 and the capacitor wiring layer 250 overlapping the pixel electrode layer 227 form a storage capacitor. The capacitor wiring layer 250 is an example of forming a capacitor. Since the electrode layer is made of the same material and formed in the same process, the thin film transistor 2 It is laid out so as not to overlap with the source wiring layer 20.

[0209] The storage capacitor shown in FIG. 9A has a pair of electrodes and a dielectric material that are transparent, and the entire storage capacitor The body is translucent.

[0210] FIG. 9B shows an example of a storage capacitor configuration different from that shown in FIG. 9A. Since this is the same as 7(A) except for the difference in the storage capacitor configuration, the same symbols are used for the same parts. Detailed explanations of the same parts will be omitted.

[0211] FIG. 9(B) shows a structure in which the dielectric is a first gate insulating layer 202a and a second gate insulating layer 202b. The capacitor wiring layer 230, the oxide semiconductor layer 251 overlapping the capacitor wiring layer 230, and the capacitor electrode In this example, a storage capacitor is formed by stacking the oxide semiconductor layer 251 with the oxide semiconductor layer 231. The electrode 231 is laminated in contact with the oxide film and functions as one electrode of the storage capacitor. The semiconductor layer 251 is the same as the source electrode layer or the drain electrode layer of the thin film transistor 220. The light-transmitting material is formed in the same process. Since the thin film transistor 220 is formed of the same material having the same light-transmitting property and in the same process as the gate electrode layer of the thin film transistor 220, The layout is such that it does not overlap with the gate wiring layer of the transistor 220 .

[0212] In addition, the capacitance electrode 231 is electrically connected to the pixel electrode layer 227 .

[0213] The storage capacitor shown in FIG. 9B also has a pair of electrodes and a dielectric material that are transparent, and the entire storage capacitor The body is translucent.

[0214] The storage capacitors shown in FIGS. 9A and 9B are transparent and have the number of gate wirings. In order to increase the resolution of the displayed image by increasing the number of pixels, it is necessary to provide sufficient capacity even if the pixel size is reduced. It is possible to obtain a high aperture ratio.

[0215] This embodiment mode can be freely combined with other embodiment modes.

[0216] (Embodiment 8) In this embodiment, at least a part of the driver circuit and a thin film transistor disposed in the pixel portion are formed on the same substrate. An example of fabricating a transistor will be described below.

[0217] The thin film transistors disposed in the pixel portion are formed according to any one of Embodiments 1 to 4. The thin film transistors shown in the first to fourth embodiments are n-channel TFTs, so that the Among them, part of the driver circuit can be configured with n-channel TFTs. It is formed on the same substrate as the resistor.

[0218] An example of a block diagram of an active matrix display device is shown in FIG. A pixel portion 5301, a first scanning line driver circuit 5302, a second scanning line driver circuit 5303, and a third scanning line driver circuit 5304 are provided on a substrate 5300. The pixel portion 5301 has a signal line driver circuit 5303 and a signal line driver circuit 5304. are arranged extending from the signal line driver circuit 5304, and a plurality of scanning lines are arranged in the first scanning line driver circuit The scanning line driver circuit 5302 and the second scanning line driver circuit 5303 are arranged to extend from each other. In the intersections of the signal lines and the wiring, pixels each having a display element are arranged in a matrix. The substrate 5300 of the display device is made of FPC (Flexible Printed Circuit). A timing control circuit 5305 (controller, control I) is connected to the timing control circuit 5305 via a connection part such as a C).

[0219] In FIG. 14A, a first scanning line driver circuit 5302, a second scanning line driver circuit 5303, a signal The signal line driver circuit 5304 is formed on the same substrate 5300 as the pixel portion 5301. This reduces the number of externally provided components such as drive circuits, thereby reducing costs. In addition, when a driving circuit is provided outside the substrate 5300, the wiring is extended to provide a connection portion. The number of connections can be reduced, and the reliability or yield can be improved.

[0220] The timing control circuit 5305 controls the first scanning line driver circuit 5302 as follows: A start signal (GSP1) for the first scanning line driver circuit (also called a start pulse) A clock signal (GCK1) for the scan line driver circuit is supplied. Also, the timing control circuit 530 5 is a second scanning line driver circuit 5303, for example, Signal line GSP2 and clock signal GCK2 for the scanning line driver circuit are supplied. The driver circuit 5304 receives a start signal (SSP) for the signal line driver circuit, a clock for the signal line driver circuit, and a Clock signal (SCK), video signal data (DATA) (also simply called video signal), Each clock signal is a multiple of clock signals with different periods. It may be a clock signal or may be supplied together with an inverted clock signal (CKB). The first scanning line driver circuit 5302 and the second scanning line driver circuit 53 It is possible to omit either 03 or 04.

[0221] In FIG. 14B, circuits with low driving frequencies (for example, the first scanning line driving circuit 5302, the The second scanning line driver circuit 5303 is formed on the same substrate 5300 as the pixel portion 5301, and the signal line driver 5 shows a structure in which the driving circuit 5304 is formed on a substrate different from that of the pixel portion 5301.

[0222] The thin film transistors described in Embodiments 1 to 4 are n-channel TFTs. 5(A) and 15(B) show the configuration and operation of a signal line driver circuit configured with n-channel TFTs. An example will be given below.

[0223] The signal line driver circuit includes a shift register 5601 and a switching circuit 5602 . The switching circuit 5602 is composed of switching circuits 5602_1 to 5602_N (N is a natural number). The switching circuits 5602_1 to 5602_N each have a plurality of circuits. , a plurality of thin film transistors 5603_1 to 5603_k (k is a natural number) The thin film transistors 5603_1 to 5603_k are N-channel TFTs. An example will be explained.

[0224] The connection relationship of the signal line driver circuit will be described using the switching circuit 5602_1 as an example. The first terminals of the thin film transistors 5603_1 to 5603_k are connected to the wirings 5604_1 The second terminals of the thin film transistors 5603_1 to 5603_k are connected to the first terminals of the thin film transistors 5603_1 to 5603_k. are connected to the signal lines S1 to Sk, respectively. The gate of k is connected to the wiring 5605_1.

[0225] The shift register 5601 sequentially outputs H level (H signal) to the wirings 5605_1 to 5605_N. , also referred to as a high power supply potential level), and the switching circuits 5602_1 to 56 It has the function of selecting 02_N in order.

[0226] The switching circuit 5602_1 is connected to the wirings 5604_1 to 5604_k and the signal lines S1 to Sk. The function of controlling the conduction state (conduction between the first terminal and the second terminal) with the wiring 5604_ The switches have the function of controlling whether or not the potentials of 1 to 5604_k are supplied to the signal lines S1 to Sk. In this way, the switching circuit 5602_1 has a function as a selector. The film transistors 5603_1 to 5603_k are connected to the wirings 5604_1 to 5604_k, respectively. and the signal lines S1 to Sk, that is, the wirings 5604_1 to 5604_k. The thin film transistor 56 has a function of supplying the potential of the signal lines S1 to Sk. Each of 03_1 to 5603_k functions as a switch.

[0227] The wirings 5604_1 to 5604_k each carry video signal data (DATA). The video signal data (DATA) is an analog signal corresponding to the image information or image signal. This is often a signal.

[0228] Next, the operation of the signal line driver circuit of FIG. 15(A) will be explained with reference to the timing chart of FIG. 15(B). 15B shows signals Sout_1 to Sout_N and An example of Vdata_1 to Vdata_k is shown. are examples of output signals of the shift register 5601, and signals Vdata_1 to Vdata _k are examples of signals input to the wirings 5604_1 to 5604_k, respectively. One operation period of the signal line driving circuit corresponds to one gate selection period in the display device. The selection period is divided into periods T1 to TN, for example. This is the period for writing video signal data (DATA) to the pixels belonging to the selected row. be.

[0229] In the drawings of the present embodiment, the signal waveforms of the components are rounded for clarity. Therefore, the scale may not necessarily be limited to that shown. It should be noted that

[0230] During the period T1 to the period TN, the shift register 5601 outputs a high-level signal to the wiring 560 For example, in the period T1, the shift registers 5 601 outputs a high-level signal to the wiring 5605_1. 5603_1 to 5603_k are turned on, so the wiring 5604_1 to 5604_k and the signal At this time, the wirings 5604_1 to 5604_k are in a conductive state. Data(S1)~Data(Sk) are input. Data(S1)~Data(Sk ) belong to the selected row via thin film transistors 5603_1 to 5603_k. In this way, during the periods T1 to TN, the pixels in the first to k-th columns are written. Then, the video signal data (DATA) is sent to the pixels belonging to the selected row in order of k columns. It will be written.

[0231] As described above, video signal data (DATA) is written to pixels in multiple columns. This makes it possible to reduce the number of video signal data (DATA) or the number of wirings. This reduces the number of connections to external circuits. By writing directly to the memory, the writing time can be increased, and the video signal can be written This can prevent under-crowding.

[0232] The shift register 5601 and the switching circuit 5602 are the same as those in the first embodiment. It is possible to use circuits configured with thin film transistors shown in the above to 4.

[0233] Regarding one form of a shift register used in a part of a scanning line driver circuit and / or a signal line driver circuit, This will be explained with reference to FIGS. 16 and 17.

[0234] The scanning line driving circuit has a shift register. In some cases, it may also have a level shifter or a buffer. In the scanning line driver circuit, a clock signal is input to the shift register. The selection signal is generated by inputting the (CLK) and start pulse signal (SP). The generated selection signal is buffered and amplified in a buffer and then supplied to the corresponding scanning line. The gate electrodes of the transistors of one line of pixels are connected to the scanning line. Since the transistors of the pixels in one line must be turned on simultaneously, a buffer is required. The capacitor used is one that can pass a large current.

[0235] The shift register includes the first pulse output circuit 10_1 to the N-th pulse output circuit 10_N ( N is a natural number of 3 or more (see FIG. 16(A)). The first pulse output circuit 10_1 to the N-th pulse output circuit 10_N of the register are A first clock signal CK1 is transmitted from a wiring 11, and a second clock signal CK2 is transmitted from a second wiring 12. , a third clock signal CK3 is transmitted from the third wiring 13, and a fourth clock signal CK4 is transmitted from the fourth wiring 14. In the first pulse output circuit 10_1, a signal CK4 is supplied from the fifth wiring 15. A start pulse SP1 (first start pulse) is input. In the pulse output circuit 10_n (n is a natural number between 2 and N), A signal from the previous stage signal OUT(n-1) is input. The circuit 10_1 receives a signal from a third pulse output circuit 10_3 located two stages later. Similarly, in the n-th pulse output circuit 10_n at the second stage or later, the (n+2)-th pulse A signal from the pulse output circuit 10_(n+2) (called the next stage signal OUT(n+2)) is input. Therefore, the pulse output circuit of each stage outputs the pulse a first output signal (OUT(1)(SR) to OUT(N)(SR)) for input to the path; Second output signals (OUT(1) to OUT(N)) are outputted to be inputted to another circuit or the like. However, as shown in FIG. 16(A), the last two stages of the shift register are connected to the next stage signal. Since OUT(n+2) is not input, for example, a second start pulse SP2 , and the third start pulse SP3 may be input.

[0236] The clock signal (CK) alternates between H level and L level (L signal, low power supply potential) at regular intervals. Here, the first clock signal (CK1) to the second clock signal (CK2) are signals that repeat a cycle of 1 / 2 levels. The fourth clock signal (CK4) is delayed by 1 / 4 cycle in order. The first clock signal (CK1) to the fourth clock signal (CK4) are used to generate a pulse output circuit. The clock signal is controlled by the GCK It is sometimes called SCK, but here we will explain it as CK.

[0237] The first input terminal 21, the second input terminal 22, and the third input terminal 23 are connected to the first wiring 11 to It is electrically connected to any one of the fourth wirings 14. For example, in FIG. The first pulse output circuit 10_1 has a first input terminal 21 electrically connected to the first wiring 11. The second input terminal 22 is electrically connected to the second wiring 12, and the third input terminal 23 is The second pulse output circuit 10_2 is electrically connected to the third wiring 13. The first input terminal 21 is electrically connected to the second wiring 12, and the second input terminal 22 is electrically connected to the third wiring The third input terminal 23 is electrically connected to the fourth wiring 14. There are.

[0238] Each of the first pulse output circuit 10_1 to the N-th pulse output circuit 10_N has a first input terminal 21, a second input terminal 22, a third input terminal 23, a fourth input terminal 24, a fifth input terminal 16B, the input terminal 25, the first output terminal 26, and the second output terminal 27. In the first pulse output circuit 10_1, a first clock signal is input to a first input terminal 21. A first clock signal CK1 is input to the first input terminal 21, a second clock signal CK2 is input to the second input terminal 22, and a third clock signal CK3 is input to the third input terminal 23. A third clock signal CK3 is input to the input terminal 23 of the clock generator 10, and a start signal CK4 is input to the fourth input terminal 24 of the clock generator 10. A pulse is input, the subsequent signal OUT(3) is input to the fifth input terminal 25, and the first output The first output signal OUT(1)(SR) is output from the terminal 26, and the second output signal OUT(1)(SR) is output from the second output terminal 27. The second output signal OUT(1) is output.

[0239] The first pulse output circuit 10_1 to the N-th pulse output circuit 10_N are three-terminal thin film transistors. In addition to transistors (also called TFTs: Thin Film Transistors), The four-terminal thin film transistors described in the above embodiments can be used. In the document, when a thin film transistor has two gate electrodes via a semiconductor layer, The gate electrode below the semiconductor layer is called the lower gate electrode, and the gate electrode above the semiconductor layer is called the upper gate electrode. It is also called the gate electrode.

[0240] When an oxide semiconductor is used for a semiconductor layer including a channel formation region of a thin film transistor, The threshold voltage may shift to the negative or positive side depending on the process. Therefore, in a thin film transistor using an oxide semiconductor for a semiconductor layer including a channel formation region, A configuration that allows for control of the threshold voltage is preferable. The threshold voltage can be adjusted to a desired value by controlling the potential of the upper and / or lower gate electrodes. The value can be controlled.

[0241] Next, an example of a specific circuit configuration of the pulse output circuit shown in FIG. 16(B) will be described with reference to FIG. This is explained in (D).

[0242] The pulse output circuit shown in FIG. 16(D) includes the first transistor 31 to the thirteenth transistor. The first input terminal 21 to the fifth input terminal 25, In addition to the first output terminal 26 and the second output terminal 27, a voltage source to which a first high power supply potential VDD is supplied is also provided. A power supply line 51, a power supply line 52 to which a second high power supply potential VCC is supplied, and a power supply line 53 to which a low power supply potential VSS is supplied. A signal is sent from the power supply line 53 to the first transistor 31 to the thirteenth transistor 43, and The power supply potential is supplied to the power supply lines. Here, the magnitude relationship of the power supply potential of each power supply line in FIG. 16(D) is as follows: The first power supply potential VDD is set to a potential equal to or higher than the second power supply potential VCC, and the second power supply potential VCC The potential of the first clock signal (CK1) to the second clock signal (CK2) is higher than the third power supply potential VSS. The fourth clock signal (CK4) is a signal that alternates between H level and L level at regular intervals. When it is at H level, it is VDD, and when it is at L level, it is VSS. By making the potential VDD higher than the potential VCC of the power supply line 52, the operation is not affected. Therefore, the potential applied to the gate electrode of the transistor can be kept low, and the transistor This reduces the shift in the threshold voltage of the first transistor, thereby suppressing deterioration. Among the first to thirteenth transistors 31 to 43, the first transistor 31 and the sixth transistor It is preferable to use four-terminal thin film transistors for the transistors 36 to 9. The first transistor 31 and the sixth to ninth transistors 36 to 39 In operation, the potential of the node to which either the source or drain electrode is connected is controlled by the gate voltage. A transistor that requires switching by a control signal from the gate electrode. The response to the input control signal is fast (the rise of the on-current is steep), This transistor can reduce malfunctions in the output circuit. By using a thin film transistor, the threshold voltage can be controlled, and malfunctions are reduced. It is possible to provide a pulse output circuit that can reduce the power consumption.

[0243] In FIG. 16(D), the first terminal of the first transistor 31 is electrically connected to the power supply line 51. a second terminal electrically connected to a first terminal of a ninth transistor 39; (the lower gate electrode and the upper gate electrode) are electrically connected to the fourth input terminal 24. The second transistor 32 has a first terminal electrically connected to the power supply line 53 and a second terminal the gate electrode of the ninth transistor 39 is electrically connected to the first terminal of the fourth transistor The third transistor 33 is electrically connected to the gate electrode of the first terminal is electrically connected to the first input terminal 21, and the second terminal is electrically connected to the first output terminal 26. The fourth transistor 34 has a first terminal electrically connected to the power supply line 53, The second terminal is electrically connected to the first output terminal 26. The fifth transistor 35 is The first terminal is electrically connected to the power supply line 53, and the second terminal is connected to the gate of the second transistor 32. and the gate electrode of the fourth transistor 34, the gate electrode of which is electrically connected to the fourth The sixth transistor 36 has a first terminal electrically connected to the input terminal 24. 52, and the second terminal is electrically connected to the gate electrode of the second transistor 32 and the fourth transistor The gate electrode (the lower gate electrode and the upper gate electrode) of the transistor 34 is electrically connected to the gate electrode of the transistor 34. The seventh transistor (the gate electrode) is electrically connected to the fifth input terminal 25. The eighth transistor 37 has a first terminal electrically connected to the power supply line 52 and a second terminal electrically connected to the eighth transistor 38. and a gate electrode (lower gate electrode and upper gate electrode) electrically connected to the second terminal of the is electrically connected to the third input terminal 23. The eighth transistor 38 is is electrically connected to the gate electrode of the second transistor 32 and the gate electrode of the fourth transistor 34. and the gate electrodes (the lower gate electrode and the upper gate electrode) are connected to the second input terminal The ninth transistor 39 has a first terminal electrically connected to the first transistor 22. The second terminal is electrically connected to the second terminal of the first transistor 31 and the second terminal of the second transistor 32. The gate electrode of the third transistor 33 and the gate electrode of the tenth transistor 40 are connected to each other. The gate electrodes (lower gate electrode and upper gate electrode) are electrically connected to the power supply line 52. The tenth transistor 40 has a first terminal electrically connected to the first input terminal 2. 1, the second terminal is electrically connected to the second output terminal 27, and the gate electrode is electrically connected to the second terminal of the ninth transistor 39. 41 has a first terminal electrically connected to the power supply line 53 and a second terminal electrically connected to the second output terminal 27. The gate electrodes of the second transistor 32 and the fourth transistor 33 are electrically connected to each other. The twelfth transistor 42 is electrically connected to the gate electrode of the first terminal of the twelfth transistor 42. The first terminal is electrically connected to the power supply line 53, and the second terminal is electrically connected to the second output terminal 27. The gate electrode of the seventh transistor 37 (the lower gate electrode and the upper gate electrode) The thirteenth transistor 43 has a first terminal electrically connected to the power supply line 5. 3, the second terminal is electrically connected to the first output terminal 26, and the gate electrode The gate electrodes (lower gate electrode and upper gate electrode) of the seventh transistor 37 are electrically connected. are electrically connected.

[0244] In FIG. 16(D), the gate electrode of the third transistor 33, the gate electrode of the tenth transistor 4 The connection point of the gate electrode of the ninth transistor 30 and the second terminal of the ninth transistor 39 is referred to as node A. The gate electrode of the second transistor 32, the gate electrode of the fourth transistor 34, the second terminal of the fifth transistor 35, the second terminal of the sixth transistor 36, the second terminal of the eighth transistor The connection point of the first terminal of the eleventh transistor 38 and the gate electrode of the eleventh transistor 41 is node B. Let's say.

[0245] FIG. 17(A) shows the pulse output circuit described in FIG. 16(D) as a first pulse output circuit 10_ 1, the first input terminal 21 to the fifth input terminal 25 and the first output terminal 26 and the signals input to or output from the second output terminal 27.

[0246] Specifically, a first clock signal CK1 is input to the first input terminal 21, and a second clock signal CK2 is input to the second input terminal 22. A second clock signal CK2 is input to the third input terminal 22, and a third clock signal CK3 is input to the third input terminal 23. A start pulse is input to the fourth input terminal 24, and a second input terminal CK3 is input. The next stage signal OUT(3) is input to the first output terminal 25, and the first output signal OUT (1)(SR) is output, and the second output signal OUT(1) is output from the second output terminal 27. will be done.

[0247] A thin film transistor is a transistor having at least three elements including a gate, a drain, and a source. The gate is a semiconductor element in which a channel region is formed in the region overlapping the gate. By controlling the gate potential, the drain and source are connected via the channel region. The source and drain are thin film transistors. Which is the source or drain depends on the transistor structure and operating conditions. Therefore, it is difficult to define the regions that function as the source and drain. In some cases, they are not called sources or drains. In such cases, for example, they are called first It may be written as terminal or second terminal.

[0248] In FIG. 16(D) and FIG. 17(A), the node A is set to the floating state. A capacitor may be provided separately to perform a strap operation. To achieve this, a capacitor having one electrode electrically connected to the node B may be provided separately.

[0249] Here, the timing of the shift register having a plurality of pulse output circuits shown in FIG. A shift chart is shown in FIG. 17(B). In this case, the period 61 in FIG. 17(B) corresponds to the vertical blanking period, and the period 62 corresponds to the gate selection period. do.

[0250] As shown in FIG. 17A, the ninth transistor, whose gate is supplied with the second power supply potential VCC, By providing the transistor 39, the following occurs before and after the bootstrap operation: There are advantages like this.

[0251] If the ninth transistor 39, to whose gate electrode the second power supply potential VCC is applied, is not present, When the potential of the node A rises due to the base strap operation, the second transistor 31 The potential of the source terminal rises and becomes greater than the first power supply potential VDD. The source of the first transistor 31 is switched to the first terminal side, that is, the power supply line 51 side. Therefore, in the first transistor 31, the gate and source, the gate and drain In both cases, a large bias voltage is applied, which causes a large stress on the transistor. Therefore, the ninth power supply potential VCC is applied to the gate electrode. By providing the transistor 39, the voltage of the node A is increased by the bootstrap operation. The potential of the second terminal of the first transistor 31 rises, but the potential of the second terminal of the first transistor 31 does not rise. That is, by providing the ninth transistor 39, the first transistor The negative bias voltage applied between the gate and source of the transistor 31 can be reduced. Therefore, by using the circuit configuration of this embodiment, the first transistor 31 The negative bias voltage applied between the gate and source can also be reduced, reducing the stress-induced Deterioration of the first transistor 31 can be suppressed.

[0252] The ninth transistor 39 is provided at a location corresponding to the second gate of the first transistor 31. and a gate of the third transistor 33 via a first terminal and a second terminal. In this embodiment, a system having a plurality of pulse output circuits may be provided. In the case of a soft register, the signal line driver circuit has more stages than the scanning line driver circuit. The resistor 39 may be omitted, which has the advantage of reducing the number of transistors.

[0253] Note that the semiconductor layers of the first to thirteenth transistors 31 to 43 are made of oxide semiconductor. By using a conductor, the off-current of the thin film transistor is reduced, and the on-current and This allows for increased field effect mobility and reduced degradation. In addition, a transistor using an oxide semiconductor, Compared to transistors using amorphous silicon, a higher potential is applied to the gate electrode. Therefore, the degree of deterioration of the transistor due to the second power supply potential VCC is small. The same operation can be obtained by supplying the first power supply potential VDD to the power supply line, and the wiring between the circuits is This allows the number of power supply lines to be reduced, thereby enabling the circuit to be made smaller.

[0254] The gate electrodes (lower gate electrode and upper gate electrode) of the seventh transistor 37 the clock signal provided by the third input terminal 23 to the gate of the eighth transistor 38 The voltage supplied to the gate electrodes (lower gate electrode and upper gate electrode) by the second input terminal 22 is The clock signal is applied to the gate electrode of the seventh transistor 37 (the lower gate electrode and the upper gate electrode). a clock signal provided by the second input terminal 22 to the gate electrode of the eighth transistor; The gate electrodes (lower gate electrode and upper gate electrode) of the gate electrode 38 are connected to the third input terminal 23. Therefore, the same effect can be achieved by rearranging the wiring so that the clock signal is supplied. In the shift register shown in FIG. 17A, the seventh transistor 37 and The seventh transistor 37 is turned off, and the eighth transistor 38 is turned on. The seventh transistor 37 is turned off, and the eighth transistor 38 is turned on. By turning off the inverter 38, the second input terminal 22 and the third input terminal 23 The voltage drop at node B is caused by the voltage drop at the gate of the seventh transistor 37. The potential of the gate electrode of the eighth transistor 38 decreases. On the other hand, the shift register shown in FIG. 17(A) is In this way, the seventh transistor 37 and the eighth transistor 38 are both turned on, and the third transistor 39 is turned off. The seventh transistor 37 is on and the eighth transistor 38 is off. By turning off the second transistor 37 and the eighth transistor 38, The potential of the first input terminal 22 and the third input terminal 23 decreases. The decrease can be reduced to a single decrease in the potential of the gate electrode of the eighth transistor 38. Therefore, the gate electrode of the seventh transistor 37 (the lower gate electrode and the upper A clock signal supplied from the third input terminal is supplied to the gate electrode of the eighth transistor. The gate electrodes (lower gate electrode and upper gate electrode) of the transistor 38 are connected to the second input terminal. It is preferable to have a wiring relationship in which the clock signal is supplied from the node B. This is because the number of fluctuations in the frequency band is reduced, and noise can also be reduced.

[0255] In this way, the potentials of the first output terminal 26 and the second output terminal 27 are maintained at the L level. By configuring the node B to periodically receive a high-level signal during this period, the pulse output This can suppress malfunction of the power circuit.

[0256] (Embodiment 9) A thin film transistor is manufactured, and the thin film transistor is used in a pixel portion and further in a driver circuit. A semiconductor device (also called a display device) having a display function can be manufactured. A part or the whole of a driver circuit having a transistor is formed integrally on the same substrate as the pixel portion, A stem-on panel can be formed.

[0257] The display device includes a display element. The display element includes a liquid crystal element (also called a liquid crystal display element), a light-emitting element, A light-emitting element (also called a light-emitting display element) can be used. This category includes elements whose brightness is controlled by the light emitted from the light source, specifically inorganic EL (Electroluminescent) luminescence elements, organic EL elements, etc. Also, electronic ink A display medium whose contrast changes due to an electrical effect can also be applied.

[0258] The display device also includes a panel in which a display element is sealed, and a controller for the panel. Furthermore, the display device is manufactured by a method for manufacturing the display device. In the process, the element substrate, which corresponds to a form before the display element is completed, is used to transmit the current to the display element. The element substrate is specifically provided with a means for supplying a voltage to each of the pixels of the display element. The electrode may be formed only, or the conductive film that will become the pixel electrode may be formed after the conductive film is formed. It may be in a state before etching to form pixel electrodes, or any other form may be used. Get hooked.

[0259] In this specification, the term "display device" refers to an image display device, a display device, or an optical device. It also refers to connectors, such as FPC (Flexible Printed Circuit) integrated circuit) or TAB (Tape Automated Bon ding) tape or TCP (Tape Carrier Package) Modules with printed wiring boards attached to the end of TAB tape or TCP or the display element is mounted on an IC (integrated circuit) by the COG (Chip On Glass) method. The display device also includes all modules in which the display device (circuit) is directly mounted.

[0260] The appearance and cross section of a liquid crystal display panel, which is one mode of a semiconductor device, will be described with reference to FIG. 10(A1) and 10(A2) show the thin film transistors 4010 and 4011 and the liquid crystal display device. The element 4013 is disposed between the first substrate 4001 and the second substrate 4006 by a sealant 4005. 10(A1) and 10(A2) are plan views of the panel sealed by the This corresponds to a cross-sectional view at MN.

[0261] A pixel portion 4002 and a scanning line driver circuit 4004 are provided on a first substrate 4001. In this way, a sealing material 4005 is provided. A second substrate 4006 is provided on the path 4004. The line driver circuit 4004 is made up of a first substrate 4001, a sealing material 4005, and a second substrate 4006. The first substrate 4001 is sealed together with the liquid crystal layer 4008. In a region different from the region surrounded by the material 4005, a single crystal is formed on a separately prepared substrate. A signal line driver circuit 4003 formed of a semiconductor film or a polycrystalline semiconductor film is mounted.

[0262] The method of connecting the separately formed drive circuit is not particularly limited, and may be a COG method, Wire bonding or TAB method can be used. is an example of mounting a signal line driver circuit 4003 by the COG method, and FIG. 10(A2) is This is an example in which a signal line driver circuit 4003 is mounted by the TAB method.

[0263] A pixel portion 4002 and a scanning line driver circuit 4004 are provided on a first substrate 4001. In FIG. 10B, the thin film transistor included in the pixel portion 4002 A transistor 4010 and a thin film transistor 4011 included in the scanning line driver circuit 4004 The insulating layers 4041 and 4042 are formed on the thin film transistors 4010 and 4011. 2, 4020, and 4021 are provided.

[0264] The thin film transistors 4010 and 4011 each include the oxide semiconductor layer described in any of Embodiments 1 to 4. Highly reliable thin film transistors including the thin film transistors for the driver circuits can be applied. The transistor 4011 may be the thin film transistors 410 and 499 shown in any of Embodiments 1 to 4. Thin film transistors 420 and 498 are used as the thin film transistor 4010 for the pixel. In this embodiment, the thin film transistors 4010 and 4011 are n-channel It is a thin film transistor.

[0265] The oxide semiconductor layer of the thin film transistor 4011 for the driver circuit is formed on the insulating layer 4021. A conductive layer 4040 is provided in a position overlapping with the channel formation region. By providing the layer at a position overlapping the channel forming region of the nitride semiconductor layer, In this case, the amount of change in the threshold voltage of the thin film transistor 4011 can be reduced. The conductive layer 4040 may have the same potential as the gate electrode layer of the thin film transistor 4011. The conductive layer may be different from the first gate electrode layer and may function as a second gate electrode layer. The potential of 4040 may be GND, 0V, or may be in a floating state.

[0266] The pixel electrode layer 4030 of the liquid crystal element 4013 is connected to the thin film transistor 4010. The counter electrode layer 4031 of the liquid crystal element 4013 is electrically connected to the second substrate 40. 06. The pixel electrode layer 4030, the counter electrode layer 4031, and the liquid crystal layer 4008 are The overlapping portion corresponds to the liquid crystal element 4013. The electrode layer 4031 is provided with insulating layers 4032 and 4033 which function as alignment films. A liquid crystal layer 4008 is sandwiched between insulating layers 4032 and 4033 .

[0267] The first substrate 4001 and the second substrate 4006 may be light-transmitting substrates. Glass, ceramics, and plastics can be used. , FRP (Fiberglass-Reinforced Plastics) board, PV F (polyvinyl fluoride) film, polyester film or acrylic resin film A room can be used.

[0268] 4035 is a columnar spacer obtained by selectively etching the insulating film. To control the distance (cell gap) between the pixel electrode layer 4030 and the counter electrode layer 4031 A spherical spacer may be used. is electrically connected to a common potential line provided on the same substrate as the thin film transistor 4010. The common connection portion is used to connect the opposing electrode layer 40 via conductive particles disposed between the pair of substrates. The conductive particles can electrically connect the sealing material 40 to the common potential line. Included in 05.

[0269] Alternatively, a liquid crystal that exhibits a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases. When the temperature of cholesteric liquid crystal is increased, the phase immediately transitions from the cholesteric phase to the isotropic phase. The blue phase appears only in a narrow temperature range, so the temperature range needs to be improved. In order to achieve this, a liquid crystal composition containing 5% by weight or more of a chiral agent is used for the liquid crystal layer 4008. The liquid crystal composition containing the liquid crystal exhibiting the blue phase and the chiral agent has a response speed of 1 msec. Since it is optically isotropic, no alignment treatment is required and the viewing angle dependency is small.

[0270] In addition to the transmissive liquid crystal display device, the present invention can also be applied to a semi-transmissive liquid crystal display device.

[0271] In addition, in a liquid crystal display device, a polarizing plate is provided on the outer side (viewing side) of the substrate, and a colored layer (color The polarizing plate is placed on the inner side of the substrate. The laminated structure of the polarizing plate and the colored layer is not limited to the present embodiment, and the polarizing plate may be provided on the The settings may be made appropriately depending on the materials of the colored layers and the manufacturing process conditions. A light-shielding film that functions as a block matrix may be provided.

[0272] The thin film transistor 4011 is in contact with the semiconductor layer including the channel formation region as a protective insulating film. The insulating layer 4041 is formed on the thin film transistor 4011 as a channel protection layer. The insulating layers 4041 and 4042 are the oxide insulating layers shown in the first embodiment. The insulating layer 416 and the insulating layer 426 may be formed using the same material and method as the insulating layer 416 and the insulating layer 426. In order to reduce the surface irregularities, the substrate is covered with an insulating layer 4021 that functions as a planarizing insulating film. Here, the insulating layers 4041 and 4042 are formed by sputtering using the method of the first embodiment. A silicon oxide film is formed.

[0273] In addition, an insulating layer 4020 is formed on the insulating layers 4041 and 4042. The protective insulating layer 4042 may be formed using a material and a method similar to those of the protective insulating layer 403 described in Embodiment 1. Here, a silicon nitride film is formed as the insulating layer 4020 by RF sputtering.

[0274] An insulating layer 4021 is formed as a planarization insulating film. The planarization insulating layer 404 may be formed using the same material and method as the planarization insulating layer 404 shown in Embodiment 1. Heat-resistant organic materials such as acrylic, benzocyclobutene, polyamide, and epoxy In addition to the above organic materials, low dielectric constant materials (low-k materials), silicon Use fluororesin, PSG (phosphorus glass), BPSG (borophosphorus glass), etc. In addition, by laminating a plurality of insulating films made of these materials, the insulating layer 40 21 may be formed.

[0275] In this embodiment, a plurality of thin film transistors in a pixel portion are collectively surrounded by a nitride insulating film. The insulating layer 4020 and the gate insulating layer may be formed using a nitride insulating film. In order to achieve this, an insulating layer 4020 is formed so as to surround at least the periphery of the pixel portion of the active matrix substrate. In this manufacturing process, an area where the external insulating layer is in contact with the gate insulating layer is provided. In addition, when a semiconductor device, for example, a device as a display device, is used, the device can be prevented from entering moisture. This prevents moisture from entering from the outside for a long period of time even after the device is completed, ensuring long-term reliability of the device. This can improve reliability.

[0276] Siloxane-based resin is a Si-OS compound formed using siloxane-based materials as starting materials. The siloxane resin corresponds to a resin containing an i bond. Alternatively, an organic group having a fluoro group may be used. That's fine.

[0277] The method for forming the insulating layer 4021 is not particularly limited, and may be a sputtering method, an SOG method, or the like, depending on the material. , spin coating, dip coating, spray coating, droplet ejection method (inkjet method, screen Printing, offset printing, etc.), doctor knife, roll coater, curtain coater A knife coater or a knife coater can be used. By using the same material as the annealing material, it becomes possible to manufacture a semiconductor device efficiently.

[0278] The pixel electrode layer 4030 and the counter electrode layer 4031 are made of indium oxide containing tungsten oxide. , indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, Indium tin oxide containing titanium oxide, indium tin oxide (hereinafter referred to as ITO), Translucent materials such as indium zinc oxide and indium tin oxide doped with silicon oxide A light-transmitting conductive material can be used.

[0279] The pixel electrode layer 4030 and the counter electrode layer 4031 are made of a conductive polymer (conductive polymer The conductive composition can be used to form the conductive film. The pixel electrode has a sheet resistance of 10,000 Ω / □ or less and a light transmittance of 550 nm. It is preferable that the sheet resistance is lower. It is preferable that the resistivity of the conductive polymer contained in the conductive composition is 0.1 Ω·cm or less. .

[0280] As the conductive polymer, a so-called π-electron conjugated conductive polymer can be used. For example, polyaniline or its derivatives, polypyrrole or its derivatives, polythiophene or or a derivative thereof, or a copolymer of two or more of these.

[0281] A signal line driver circuit 4003 and a scanning line driver circuit 4004 or a pixel section 4 Various signals and potentials applied to 002 are supplied from FPC4018.

[0282] The connection terminal electrode 4015 is made of the same conductive film as the pixel electrode layer 4030 of the liquid crystal element 4013. The terminal electrode 4016 is formed from the source electrode layers of the thin film transistors 4010 and 4011. The drain electrode layer is formed of the same conductive film as the drain electrode layer.

[0283] The connection terminal electrode 4015 is connected to the terminal of the FPC 4018 via the anisotropic conductive film 4019. are electrically connected.

[0284] In FIG. 10, a signal line driver circuit 4003 is formed separately and mounted on the first substrate 4001. The present invention is not limited to this configuration. Alternatively, only a part of the signal line driver circuit or a part of the scanning line driver circuit may be separately formed. It may be implemented.

[0285] FIG. 19 shows a semiconductor device using a TFT substrate 2600 fabricated by the fabrication method disclosed herein. 1 shows an example of a semiconductor device configured as a liquid crystal display module.

[0286] FIG. 19 shows an example of a liquid crystal display module, in which a TFT substrate 2600 and an opposing substrate 2601 are connected. The substrate is fixed by a bonding material 2602, and a pixel portion 2603 including a TFT and the like and a liquid crystal layer are disposed between the substrate and the bonding material 2602. A display element 2604 and a colored layer 2605 are provided to form a display area. is required for color display, and in the case of the RGB method, it corresponds to each color of red, green, and blue. A colored layer is provided corresponding to each pixel. On the outside, a polarizing plate 2606, a polarizing plate 2607, and a diffusion plate 2613 are arranged. It is composed of a cathode ray tube 2610 and a reflector 2611, and a circuit board 2612 is a flexible wiring board. The wiring board 2609 is connected to the wiring circuit section 2608 of the TFT substrate 2600, and the controller It also incorporates external circuits such as a polarizing plate and a power supply circuit. The layers may be laminated with a retardation film interposed therebetween.

[0287] The LCD module is available in TN (Twisted Nematic) mode, IPS (In-Plane Switching) mode, n-Plane-Switching mode, FFS (Fringe Field Switching) Switching mode, MVA (Multi-domain Vertical A alignment) mode, PVA(Patterned Vertical Alignment) mode nment) mode, ASM(Axially Symmetric aligned Micro-cell mode, OCB (Optically Compensated) Birefringence mode, FLC (Ferroelectric Liquid Crystal uid Crystal) mode, AFLC(AntiFerroelectric L You can use modes such as IQID Crystal.

[0288] By the above steps, a highly reliable liquid crystal display panel can be manufactured as a semiconductor device. do.

[0289] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0290] (Embodiment 10) An example of electronic paper will be shown as one mode of the semiconductor device.

[0291] Electronic paper that uses elements electrically connected to switching elements to drive electronic ink Electronic paper is also called an electrophoretic display. It is as easy to read as paper, consumes less power than other display devices, and is thin and light. This has the advantage that it is possible to

[0292] Electrophoretic displays can be of various forms, but the first particle has a positive charge. A microcapsule containing a negatively charged particle and a second particle is immersed in a solvent or solute. By applying an electric field to the microcapsules, The particles in the capsule are moved in opposite directions to each other, and only the color of the particles that have gathered on one side is displayed. The first particles or the second particles contain a dye, and in the absence of an electric field, The first particle and the second particle have different colors (colorless). (including

[0293] Thus, electrophoretic displays allow materials with high dielectric constants to migrate to areas of high electric field. This is a display that utilizes the so-called dielectrophoretic effect. No polarizers are required for the display.

[0294] The microcapsules dispersed in a solvent are called electronic ink. The electronic ink can be printed on surfaces such as glass, plastic, fabric, and paper. Color display is also possible by using color filters or particles containing pigments.

[0295] Furthermore, the microphone is appropriately placed on the active matrix substrate so as to be sandwiched between two electrodes. By arranging multiple microcapsules, an active matrix display device is completed. By applying an electric field to the cell, display can be performed. An active matrix substrate obtained by using transistors can be used.

[0296] The first particles and the second particles in the microcapsules may be made of a conductive material, an insulating material, Semiconductor materials, magnetic materials, liquid crystal materials, ferroelectric materials, electroluminescent materials, A material selected from magnetochromic materials, magnetophoretic materials, or a composite material thereof Just use it.

[0297] Figure 18 shows an active matrix electronic paper as an example of a semiconductor device. The thin film transistor 581 used in the device is the thin film transistor shown in Embodiment 1. The thin film transistor can be fabricated in the same manner as the oxide semiconductor layer, and is highly reliable. The thin film transistors shown in any of the second to fourth embodiments may also be used as the thin film transistor 581 of this embodiment. It can also be applied.

[0298] The electronic paper in Figure 18 is an example of a display device that uses the twisting ball display method. The spherical display method is an electrode layer that uses spherical particles painted in black and white as display elements. and a potential difference is applied between the first electrode layer and the second electrode layer. This is a method of displaying by controlling the orientation of spherical particles by generating a magnetic field.

[0299] The thin film transistor 581 formed on the substrate 580 is a thin film transistor of a bottom gate structure. The thin film transistor 581 is covered with an insulating film 583 that is in contact with the semiconductor layer. The source or drain electrode layer is formed by the first electrode layer 587 and an opening formed in the insulating layer 585. The first electrode layers 583 and 587 are in contact with and electrically connected to the substrate 596. Between the second electrode layer 588 and the black area 590a and the white area 590b, A spherical particle 589 is provided, which includes a cavity 594 filled with a liquid, The particles 589 are surrounded by a filler 595 such as a resin. The second electrode layer 588 corresponds to a thin film. The common potential line is electrically connected to the transistor 581 and is provided on the same substrate. The connecting portion is connected to the second electrode layer 588 through conductive particles disposed between the pair of substrates. It is possible to electrically connect to a potential line.

[0300] Also, instead of the twist ball, an electrophoretic element can be used. and a diameter of 10 μm to 20 μm that contains positively charged white particles and negatively charged black particles. Microcapsules of about 0 μm in size are used. When an electric field is applied by the first and second electrode layers, the microcapsules turn white. White particles and black particles move in opposite directions, allowing the display to be white or black. The display element that applies this principle is an electrophoretic display element, and devices that use electrophoretic display elements Electrophoretic display elements are generally called electronic paper. High reflectance means no auxiliary light is required, and the low power consumption means it can be displayed even in dimly lit areas. Even if the display unit is not powered, the Since it is possible to hold the image displayed, it is possible to (also simply referred to as a display device or a semiconductor device equipped with a display device) Even if the image is displayed, it is possible to save the displayed image.

[0301] Through the above steps, electronic paper with high reliability as a semiconductor device can be manufactured. .

[0302] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0303] (Embodiment 11) An example of a light-emitting display device is shown as a semiconductor device. is shown using a light-emitting element that utilizes electroluminescence. The light-emitting element that uses the light-emitting material is classified into two types depending on whether the light-emitting material is an organic compound or an inorganic compound. Generally, the former is called an organic EL element and the latter an inorganic EL element.

[0304] In an organic EL element, electrons and holes are released from a pair of electrodes by applying a voltage to the light-emitting element. are injected into the layers containing the light-emitting organic compounds, causing a current to flow. The recombination of the electrons and holes creates an excited state in the light-emitting organic compound. The excited state is then converted to the ground state, at which point light is emitted. Such a light-emitting element is called a current-excited light-emitting element.

[0305] Inorganic EL elements are divided into dispersion-type inorganic EL elements and thin-film-type inorganic EL elements depending on the element structure. Dispersion-type inorganic EL elements have a light-emitting layer in which particles of a light-emitting material are dispersed in a binder. The emission mechanism is a donor-acceptor interaction that utilizes the donor and acceptor levels. Thin-film inorganic EL devices sandwich the light-emitting layer between dielectric layers. Furthermore, this structure is sandwiched between electrodes, and the light emission mechanism utilizes the inner-shell electron transition of metal ions. In this example, the light-emitting element is an organic EL element. do.

[0306] FIG. 12 shows an example of a pixel configuration to which digital time gray scale driving can be applied as an example of a semiconductor device. This is a diagram.

[0307] The configuration and operation of a pixel to which digital time gray scale driving can be applied will be described. The figure shows an n-channel transistor using an oxide semiconductor layer as a channel formation region in one pixel. Here is an example of using two of them.

[0308] The pixel 6400 includes a switching transistor 6401, a driving transistor for a light-emitting element, and a 6402, a light emitting element 6404, and a capacitor element 6403. The transistor 6401 has a gate connected to a scanning line 6406 and a first electrode (a source electrode and a drain electrode). The second electrode (one of the source and drain electrodes) is connected to a signal line 6405, The other one) is connected to the gate of the driving transistor 6402 of the light emitting element. The gate of the driving transistor 6402 is connected to a power supply line 6407 via a capacitor element 6403. The first electrode is connected to a power supply line 6407, and the second electrode is connected to the first electrode of the light emitting element 6404. The second electrode of the light emitting element 6404 corresponds to the common electrode 6408. The common electrode 6408 is electrically connected to a common potential line formed on the same substrate.

[0309] A low power supply potential is set to the second electrode (common electrode 6408) of the light emitting element 6404. The low power supply potential is a low power supply potential with respect to the high power supply potential set to the power supply line 6407. Potential < High power supply potential. For example, GND, 0V, etc. are set as low power supply potential. The potential difference between the high power supply potential and the low power supply potential is applied to the light emitting element 6404. Then, in order to make the light emitting element 6404 emit light by passing a current through the light emitting element 6404, a high power supply potential and the low power supply potential is set to be equal to or greater than the forward threshold voltage of the light emitting element 6404. Each potential is set.

[0310] The capacitor element 6403 is substituted for the gate capacitance of the driving transistor 6402 of the light emitting element. Regarding the gate capacitance of the driving transistor 6402 of the light emitting element, In this case, a capacitance may be formed between the channel region and the gate electrode.

[0311] In the case of a voltage input voltage driving system, the gate of the driving transistor 6402 of the light emitting element is In the gate, the driving transistor 6402 of the light emitting element is turned on or off sufficiently. In other words, the video signal that changes the state of the light-emitting element driving transistor 6 is input. The driving transistor 6402 of the light emitting element is operated in the linear region. In order to operate the light emitting element, a voltage higher than the voltage of the power supply line 6407 is applied to the driving transistor 6 The signal line 6405 is connected to the gate of the light emitting element. A voltage equal to or higher than the Vth of the transistor 6402 is applied.

[0312] Furthermore, when analog grayscale driving is performed instead of digital time grayscale driving, the input of the signal is different. By doing so, the same pixel configuration as in FIG. 12 can be used.

[0313] When analog gradation driving is performed, a light emitting element is connected to the gate of a driving transistor 6402 of the light emitting element. The forward voltage of the transistor 6404 plus a voltage higher than Vth of the driving transistor 6402 of the light emitting element is The forward voltage of the light emitting element 6404 refers to the voltage required to achieve the desired brightness. , including at least a forward threshold voltage. By inputting a video signal that operates in the saturation region, a current flows in the light emitting element 6404. In order to operate the driving transistor 6402 of the light-emitting element in a saturation region, The potential of the power supply line 6407 is higher than the gate potential of the driving transistor 6402 of the light emitting element. By converting the video signal into an analog signal, the light emitting element 6404 can receive an electric current corresponding to the video signal. A current can be passed through the liquid crystal display to perform analog gray scale driving.

[0314] Note that the pixel configuration shown in Fig. 12 is not limited to this. For example, A switch, a resistor, a capacitor, a transistor, a logic circuit, or the like may be added.

[0315] Next, the configuration of the light emitting element will be described with reference to FIG. 13. Here, the driving TFT is The cross-sectional structure of a pixel will be explained using the example of the type shown in Figures 13(A), (B), and (C). The driving TFTs 7001, 7011, and 7021 used in the semiconductor device are the same as those in the first embodiment. It can be fabricated in the same way as the thin film transistor shown in Fig. 1, and is a highly reliable thin film transistor containing an oxide semiconductor layer. The thin film transistor shown in any of the second to fourth embodiments is used as the driving TFT 700. It can also be applied as 1, 7011, 7021.

[0316] The light emitting element only needs to have at least one of the anode and cathode transparent in order to extract light. Then, a thin film transistor and a light emitting element are formed on the substrate, and light is taken from the surface opposite to the substrate. Top emission, bottom emission, and top emission. There are light-emitting elements with a double-sided emission structure that emits light from the side, and the pixel configuration is It can also be applied to optical elements.

[0317] A light emitting element with a top emission structure will be described with reference to FIG.

[0318] In FIG. 13(A), a driving TFT 7001 is an n-type, and light emitted from a light emitting element 7002 is 13A shows a cross-sectional view of a pixel when the light emitting element 70 The cathode 7003 of the TFT 7002 is electrically connected to the driving TFT 7001. The cathode 7003 has a small work function. Various materials can be used as long as they are conductive and reflect light. The light-emitting layer 7004 is preferably made of a single layer. The laminate may be made of a single layer or a plurality of layers may be laminated. In this case, an electron injection layer, an electron transport layer, an emitting layer, and a hole transport layer are formed on the cathode 7003. The layer and the hole injection layer are laminated in this order. Note that it is not necessary to provide all of these layers. The light-transmitting conductive material 5 is formed using an indium-ion conductive material containing tungsten oxide. Indium oxide, indium zinc oxide with tungsten oxide, indium titanium oxide oxide, indium tin oxide containing titanium oxide, indium tin oxide (hereinafter referred to as ITO) ), indium zinc oxide, indium tin oxide doped with silicon oxide, etc. A conductive film having the above structure may be used.

[0319] In addition, a partition wall is formed between the cathode 7003 and the cathode 7008 of the adjacent pixel, covering each end portion. The partition wall 7009 is made of polyimide, acrylic, polyamide, epoxy, etc. The partition wall 7009 is formed using an organic resin film, an inorganic insulating film, or organic polysiloxane. In particular, a photosensitive resin material is used, and the side surface of the partition wall 7009 is formed with a continuous curvature. It is preferable to form the partition wall 7009 so as to have an inclined surface. In this case, the step of forming a resist mask can be omitted.

[0320] The region where the light-emitting layer 7004 is sandwiched between the cathode 7003 and the anode 7005 is the light-emitting element 7002. In the case of the pixel shown in FIG. 13(A), the light emitted from the light emitting element 7002 is The light is emitted toward the anode 7005 as shown by the mark.

[0321] Next, a light emitting element with a bottom emission structure will be described with reference to FIG. When 011 is n-type and light emitted from the light emitting element 7012 is emitted to the cathode 7013 side, 13B shows a cross-sectional view of the pixel. A cathode 7013 of a light-emitting element 7012 is formed on a light-transmitting conductive film 7017. On the cathode 7013, a light-emitting layer 7014 and an anode 7015 are laminated in this order. When the 015 has a light-transmitting property, a shielding layer for reflecting or blocking light is applied to cover the anode. The cathode 7013 may have a film 7016 formed thereon, as in the case of FIG. Various conductive materials with small electrical conductivity can be used. The thickness is set to a level that allows light to pass through (preferably, about 5 nm to 30 nm). For example, a 20 nm film An aluminum film having a thickness of 700 nm can be used as the cathode 7013. 014 is composed of a single layer, as in FIG. 13(A), but multiple layers are laminated. The anode 7015 does not need to transmit light, but as shown in FIG. As in the case of 13(A), it can be formed using a light-transmitting conductive material. The shielding film 7016 may be made of, for example, a metal that reflects light, but is not limited to a metal film. For example, a resin containing a black pigment may be used.

[0322] In addition, a conductive film 7017 and a conductive film 7018 of an adjacent pixel are provided between the conductive film 7017 and the conductive film 7018 of an adjacent pixel, covering the respective edges. A partition wall 7019 is provided. The partition wall 7019 is made of polyimide, acrylic, polyamide, or epoxy. The partition wall 7019 is formed using an organic resin film, an inorganic insulating film, or organic polysiloxane. In particular, a photosensitive resin material is used, and the side surface of the partition wall 7019 is formed with a continuous curvature. It is preferable to form the partition wall 7019 so as to have an inclined surface. When used, the step of forming a resist mask can be omitted.

[0323] The region where the light-emitting layer 7014 is sandwiched between the cathode 7013 and the anode 7015 is the light-emitting element 7012. In the case of the pixel shown in FIG. 13B, light emitted from the light-emitting element 7012 corresponds to The light is emitted toward the cathode 7013 as shown by the arrow.

[0324] Next, a light emitting element with a dual emission structure will be described with reference to FIG. Then, on the conductive film 7027 having light-transmitting properties and electrically connected to the driving TFT 7021, A cathode 7023 of the light-emitting element 7022 is formed as a film. A light-emitting layer 7024 is formed on the cathode 7023. The cathode 7023 is laminated in the same manner as in FIG. Various conductive materials with small electrical conductivity can be used. For example, Al having a thickness of 20 nm is used as the cathode 7023. The light-emitting layer 7024 can be formed of a single layer, as in FIG. The anode 70 may be formed by laminating a plurality of layers. 25 can be formed using a light-transmitting conductive material, similar to FIG. 13(A). do.

[0325] In addition, a conductive film 7027 and a conductive film 7028 of an adjacent pixel are provided between the conductive film 7027 and the conductive film 7028 of an adjacent pixel, covering the respective edges. A partition wall 7029 is provided. The partition wall 7029 is made of polyimide, acrylic, polyamide, or epoxy. The partition wall 7029 is formed using an organic resin film, an inorganic insulating film, or organic polysiloxane. In particular, a photosensitive resin material is used, and the side surface of the partition wall 7029 is formed with a continuous curvature. It is preferable to form the partition wall 7029 so as to have an inclined surface. When used, the step of forming a resist mask can be omitted.

[0326] The overlapping portion of the cathode 7023, the light-emitting layer 7024, and the anode 7025 is the light-emitting element 70. In the case of the pixel shown in FIG. 13C, the light emitted from the light emitting element 7022 is emitted to both the anode 7025 side and the cathode 7023 side as shown by the arrows.

[0327] Although organic EL elements have been described as light-emitting elements here, inorganic EL elements can also be used as light-emitting elements. It is also possible to provide an L element.

[0328] The thin film transistor (driving TFT) that controls the driving of the light emitting element and the light emitting element are electrically However, the current control TFT is connected between the driving TFT and the light emitting element. The configuration may be such that the power supply is connected to the power supply.

[0329] The semiconductor device is not limited to the configuration shown in FIG. 13, and may be any of the semiconductor devices disclosed in this specification. Various modifications based on the technical concept are possible.

[0330] Next, the appearance and structure of a light-emitting display panel (also referred to as a light-emitting panel), which is one mode of a semiconductor device, will be described. The cross section will be explained with reference to FIG. 11. FIG. 11(A) shows a thin film formed on a first substrate. A panel in which a film transistor and a light-emitting element are sealed between a second substrate and the panel by a sealant. 11(B) is a plan view of the device, and FIG. 11(B) corresponds to a cross-sectional view taken along line HI in FIG. 11(A).

[0331] A pixel portion 4502, a signal line driver circuit 4503a, and a signal line driver circuit 4504 are provided on a first substrate 4501. 3b and the scanning line driver circuits 4504a and 4504b. In addition, a pixel portion 4502, signal line driver circuits 4503a and 4503b, and A second substrate 4506 is provided on the scanning line driver circuits 4504a and 4504b. The pixel portion 4502, the signal line driver circuits 4503a and 4503b, and the scanning line driver circuit 45 4504a and 4504b are a first substrate 4501, a sealing material 4505, and a second substrate 4506. The seal is sealed together with the filler 4507 by the sealant. Highly airtight protective film with little outgassing (lamination film, UV curable resin film) It is preferable to package (enclose) the product in a protective film (such as a film) or a cover material.

[0332] A pixel portion 4502, a signal line driver circuit 4503a, and a fourth 503b and the scanning line driver circuits 4504a and 4504b have a plurality of thin film transistors. In FIG. 11B, a thin film transistor 4510 included in a pixel portion 4502 and a signal 45 shows an example of a thin film transistor 4509 included in a line driver circuit 4503a.

[0333] The thin film transistors 4509 and 4510 each include the oxide semiconductor layer described in any of Embodiments 1 to 4. Highly reliable thin film transistors including the thin film transistors for the driver circuits can be applied. The transistor 4509 may be the thin film transistors 410 and 499 shown in any of Embodiments 1 to 4. Thin film transistors 420 and 498 are used as the thin film transistor 4510 for the pixel. In this embodiment, the thin film transistors 4509 and 4510 are n-channel It is a thin film transistor.

[0334] The oxide semiconductor layer of the thin film transistor 4509 for the driver circuit is formed over the insulating layer 4544. A conductive layer 4540 is provided in a position overlapping the channel forming region. By placing the gate electrode at a position overlapping the channel formation region of the semiconductor layer, the The amount of change in the threshold voltage of the thin film transistor 4509 can be reduced. The potential of the gate electrode layer 4540 may be the same as that of the gate electrode layer of the thin film transistor 4509 or may be different. The conductive layer 4 may be formed of a metal or a silicon dioxide film, and may function as a second gate electrode layer. The potential of 540 may be GND, 0V, or may be in a floating state.

[0335] The thin film transistor 4509 is in contact with the semiconductor layer including the channel formation region as a protective insulating film. The insulating layer 4541 is formed on the thin film transistor 4510 as a channel protection layer. The insulating layers 4541 and 4542 are the oxide insulating layers shown in Embodiment 1. The insulating layer 416 and the insulating layer 426 may be formed using the same material and method as the insulating layer 416 and the insulating layer 426. In order to reduce the surface irregularities, the substrate is covered with an insulating layer 4544 that functions as a planarizing insulating film. Here, the insulating layers 4541 and 4542 are formed by sputtering using the method of Embodiment 1. A silicon oxide film is formed.

[0336] In addition, an insulating layer 4543 is formed over the insulating layers 4541 and 4542. The protective insulating layer 403 may be formed using a material and a method similar to those of the protective insulating layer 403 described in Embodiment 1. Then, a silicon nitride film is formed as the insulating layer 4543 by RF sputtering.

[0337] An insulating layer 4544 is formed as a planarization insulating film. The planarization insulating layer 404 may be formed using a material and a method similar to those of the planarization insulating layer 404 described in Embodiment 1. Acrylic is used as the insulating layer 4544 .

[0338] In this embodiment, a plurality of thin film transistors in a pixel portion are collectively surrounded by a nitride insulating film. The insulating layer 4543 and the gate insulating layer may be formed using a nitride insulating film. In order to achieve this, an insulating layer 4543 is formed so as to surround at least the periphery of the pixel portion of the active matrix substrate. In this manufacturing process, an area where the external insulating layer is in contact with the gate insulating layer is provided. In addition, when a semiconductor device, for example, a device as a display device, is used, the device can be prevented from entering moisture. This prevents moisture from entering from the outside for a long period of time even after the device is completed, ensuring long-term reliability of the device. This can improve reliability.

[0339] Further, 4511 corresponds to a light-emitting element, and a first electrode which is a pixel electrode of the light-emitting element 4511 The layer 4517 is electrically connected to the source electrode layer or the drain electrode layer of the thin film transistor 4510. The light-emitting element 4511 is configured by a first electrode layer 4517, an electroluminescent layer The light emitting element 4512 and the second electrode layer 4513 are stacked together, but the structure is not limited to the one shown. The configuration of the light emitting element 4511 can be changed appropriately according to the direction of the light extracted from the element 4511. It is possible.

[0340] The partition wall 4520 is formed using an organic resin film, an inorganic insulating film, or organic polysiloxane. In particular, a photosensitive material is used to form an opening on the first electrode layer 4517, and the sidewall of the opening It is preferable to form the inclined surface so that the inclined surface has a continuous curvature.

[0341] The electroluminescent layer 4512 may be composed of a single layer or a plurality of layers stacked. It doesn't matter whether it's done or not.

[0342] The second electrode layer is formed to prevent oxygen, hydrogen, moisture, carbon dioxide, and the like from entering the light-emitting element 4511. A protective film may be formed on the partition wall 4513 and the partition wall 4520. The protective film may be a silicon nitride film, A silicon nitride oxide film, a DLC film, or the like can be formed.

[0343] In addition, signal line driver circuits 4503a and 4503b, scanning line driver circuits 4504a and 4504b Various signals and potentials applied to the pixel portion 4502 are transmitted through the FPC 4518a, 4518b, and It is supplied by b.

[0344] The connection terminal electrode 4515 is formed of the same conductive film as the first electrode layer 4517 of the light-emitting element 4511. The terminal electrode 4516 is formed from the source of the thin film transistors 4509 and 4510. The source electrode layer and the drain electrode layer are formed from the same conductive film.

[0345] The connection terminal electrode 4515 is connected to the terminal of the FPC 4518a via the anisotropic conductive film 4519. are electrically connected to each other.

[0346] The second substrate located in the direction of light extraction from the light emitting element 4511 must be transparent. In that case, use a glass plate, plastic plate, polyester film or acrylic A light-transmitting material such as a film is used.

[0347] In addition to inert gases such as nitrogen and argon, filler 4507 can also be used as UV-curable resin. It can be made of oil or thermosetting resin, and PVC (polyvinyl chloride), acrylic, Polyimide, epoxy resin, silicone resin, PVB (polyvinyl butyral) or EV A (ethylene vinyl acetate) can be used. For example, nitrogen can be used as a filler. That's fine.

[0348] If necessary, a polarizing plate or a circular polarizing plate (including an elliptical polarizing plate) may be provided on the light-emitting surface of the light-emitting element. Optical films such as retardation plates (λ / 4 plates, λ / 2 plates) and color filters may be provided as appropriate. In addition, an anti-reflection film may be provided on the polarizing plate or the circular polarizing plate. Anti-glare treatment can be applied to diffuse reflected light and reduce glare.

[0349] The signal line driver circuits 4503a and 4503b and the scanning line driver circuits 4504a and 4504b are A driving circuit formed of a single crystal semiconductor film or a polycrystalline semiconductor film on a separately prepared substrate is Alternatively, only the signal line driver circuit, or a part of the signal line driver circuit, or the scanning line driver circuit may be mounted. Only the path or only a part of the path may be separately formed and mounted, and the configuration is not limited to that of FIG.

[0350] Through the above steps, a highly reliable light-emitting display device (display panel) can be manufactured as a semiconductor device. It is possible.

[0351] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0352] (Embodiment 12) The semiconductor device disclosed in this specification can be applied as electronic paper. Par can be used in any electronic device that displays information. For example, electronic paper can be used for electronic books, posters, trains, etc. It can be used for in-car advertising, displaying on various cards such as credit cards, etc. An example of an electronic device is shown in Figure 20.

[0353] 20 shows an electronic book 2700. For example, the electronic book 2700 includes a housing 2701 The housing 2701 and the housing 2703 are The shaft 2711 is an integral part of the opening and closing operation. This configuration makes it possible to operate like a paper book.

[0354] A display unit 2705 is incorporated in the housing 2701, and a display unit 2707 is incorporated in the housing 2703. The display unit 2705 and the display unit 2707 are configured to display a continuous screen. Alternatively, a different screen may be displayed. For example, a sentence is displayed on the right display unit (display unit 2705 in FIG. 20) and An image can be displayed on the display unit 2707 in FIG.

[0355] 20 shows an example in which the housing 2701 is provided with an operation unit. 701 includes a power supply 2721, operation keys 2723, a speaker 2725, etc. The operation keys 2723 can be used to turn pages. It may also be configured to include a touch panel, a pointing device, etc. On the side, there are external connection terminals (earphone terminal, USB terminal, or AC adapter and USB A configuration including a terminal that can be connected to various cables, a recording medium insertion section, etc. Furthermore, the electronic book 2700 may be configured to have the function of an electronic dictionary. That's fine.

[0356] The electronic book 2700 may also be configured to be able to send and receive information wirelessly. The desired book data can be purchased and downloaded from the e-book server. is also possible.

[0357] (Embodiment 13) The semiconductor device disclosed in this specification can be applied to various electronic devices (including gaming machines). The electronic device can be, for example, a television device (television or television receivers), computer monitors, digital cameras, digital video cameras digital photo frames, mobile phones (also called mobile phones or mobile phone devices), portable Examples include game machines, mobile information terminals, sound reproduction devices, and large game machines such as pachinko machines. do.

[0358] FIG. 21(A) shows a television device 9600. The television device 9600 A display portion 9603 is incorporated in the housing 9601. The display portion 9603 displays images. In addition, the housing 9601 is supported by a stand 9605. This shows the configuration.

[0359] The television device 9600 can be operated using an operation switch on the housing 9601 or a separate remote control. This can be done by the remote control operation device 9610. The channel and volume can be controlled by the 9609, and the information displayed on the display 9603 is In addition, the remote control operation device 9610 can operate the video. A display portion 9607 for displaying information output from 9610 may be provided.

[0360] The television device 9600 is configured to include a receiver, a modem, and the like. It can receive more general TV broadcasts and can also receive them via wired or wireless modems. By connecting to a communication network, it can be one-way (sender to receiver) or two-way. It is also possible to communicate information (between a sender and a receiver, or between receivers).

[0361] FIG. 21(B) shows a digital photo frame 9700. For example, The display frame 9700 has a display unit 9703 built into a housing 9701. 03 can display various images, such as images taken with a digital camera. By displaying image data, it can function like a regular photo frame.

[0362] The Digital Photo Frame 9700 has an operation panel, external connection terminals (USB terminal, US A terminal that can be connected to various cables such as B cable, etc., and a recording medium insertion section. These components may be incorporated on the same surface as the display unit, but they may be incorporated on the side or back. It is desirable to have it because it improves the design. For example, the Digital Photo Frame 9700 Insert a memory that stores image data taken with a digital camera into the recording medium insertion section of the Image data can be captured and displayed on the display unit 9703. do.

[0363] The digital photo frame 9700 may also be configured to be capable of transmitting and receiving information wirelessly. It is also possible to configure the device so that desired image data can be wirelessly acquired and displayed.

[0364] FIG. 22(A) shows a portable gaming machine, which is composed of two cabinets, a cabinet 9881 and a cabinet 9891. The housing 9881 is connected to a connector 9893 so as to be openable and closable. A display unit 9883 is incorporated in the housing 9891. The portable gaming machine shown in 22(A) also includes a speaker unit 9884, a recording medium insertion unit 988 6, LED lamp 9890, input means (operation key 9885, connection terminal 9887, sensor 9 888 (force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, Chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration (including functions for measuring movement, smell or infrared rays), microphone 9889) Of course, the configuration of the portable gaming machine is not limited to the above, and It is sufficient if the semiconductor device disclosed in the above is included, and other auxiliary equipment is appropriately provided. The portable gaming machine shown in FIG. 22(A) can be The function of reading out programs or data and displaying them on the display, and wireless communication with other portable gaming machines The portable gaming machine shown in FIG. 22(A) has the function of sharing information by performing the above. The functions are not limited to these, and various functions can be provided.

[0365] FIG. 22(B) shows a slot machine 9900, which is a large gaming machine. 9900 has a display unit 9903 built into a housing 9901. The 9900 also has other controls such as a start lever and stop switch, and a coin slot. , speakers, etc. Of course, the configuration of the slot machine 9900 is the same as that described above. There is no limitation, and it is sufficient that the configuration includes at least the semiconductor device disclosed in this specification. Other auxiliary equipment may be provided as appropriate.

[0366] FIG. 23A is a perspective view showing an example of a portable computer.

[0367] The portable computer of FIG. 23(A) has an upper housing 9301 and a lower housing 9302 connected to each other. The hinge unit is closed to form an upper housing 9301 having a display portion 9303 and a keyboard. The lower housing 9302 having the card 9304 can be stacked on top of each other, making it easy to carry. This is convenient, and when the user wants to input data on the keyboard, the hinge unit can be opened. The user can perform input operations by looking at the display portion 9303.

[0368] The lower housing 9302 also includes a keyboard 9304 and a pointing device for inputting data. If the display portion 9303 is a touch input panel, Input operations can be performed by touching the lower housing 9302. The lower housing 9302 has a computing function unit such as a hard disk. It has an external connection port 9305 into which a communication cable conforming to the SB communication standard is inserted. There are.

[0369] The upper housing 9301 further includes a display unit 93 that can be slid into the upper housing 9301 and stored therein. 07, which allows for a wide display screen. The orientation of the screen of the 9307 can be adjusted by the user. If it is a panel, input operations can be performed by touching a part of the retractable display section.

[0370] The display portion 9303 or the storable display portion 9307 may be a liquid crystal display panel, an organic light emitting element, or The display device uses a light-emitting display panel made of inorganic light-emitting elements.

[0371] The portable computer shown in FIG. 23(A) is configured with a receiver and the like, and is also used for television broadcasting. It is possible to receive broadcasts and display images on the display portion 9303 or the display portion 9307. In addition, the hinge unit connecting the upper housing 9301 and the lower housing 9302 is kept closed. Also, the display part 9307 can be slid to expose the entire screen, and the user can adjust the screen angle. You can also watch TV broadcasts. In this case, the hinge unit is opened and the display unit 9 303 is not displayed, and only the circuit that displays the TV broadcast is started. Portable computers with limited power consumption and limited battery capacity It is useful in

[0372] FIG. 23(B) shows a portable telephone that can be worn on the user's arm like a wristwatch. FIG. 10 is a perspective view showing an example of a story.

[0373] This mobile phone includes a main body having at least a communication device with a telephone function and a battery, A band part 9204 for attaching the body to the arm, and a fastening state of the band part 9204 to the arm are adjusted. The device is composed of an adjustment unit 9205, a display unit 9201, a speaker 9207, and a microphone 9208. It has been completed.

[0374] The main body also has an operation switch 9203, which is used for power input and display switching. In addition to the switch and the switch to start shooting, for example, when you press the switch, the program for the Internet Each function can be associated with another function, such as

[0375] Input operations of this mobile phone are performed by touching the display portion 9201 with a finger or an input pen, or by operating the display portion 9201. This is done by operating a switch 9203 or by inputting voice into a microphone 9208. 23(B) shows a display button 9202 displayed on a display unit 9201, and Input can be made by touching the screen.

[0376] The main body also contains an imaging device that converts the subject image formed through the photographic lens into an electronic image signal. It has a camera unit 9206 with a step. Note that it is not necessary to provide a camera unit.

[0377] The mobile phone shown in FIG. 23(B) is configured with a television broadcast receiver and the like. It can receive TV broadcasts and display the images on the display unit 9201, and can also store data in memory etc. It is possible to record television broadcasts in memory by using a storage device. The mobile phone shown in B) may have a function capable of collecting location information such as GPS.

[0378] The display unit 9201 is a light-emitting display panel such as a liquid crystal display panel, an organic light-emitting element, or an inorganic light-emitting element. The mobile phone shown in Figure 23(B) is small and lightweight. Therefore, the battery capacity is limited, and the display device used for the display portion 9201 is a low-power display device. It is preferable to use a force-actuable panel.

[0379] Although FIG. 23B illustrates an electronic device that is worn on the arm, it is not limited to this. It is sufficient that the device has a portable shape.

[0380] (Embodiment 14) In this embodiment mode, the thin film transistor shown in any of Embodiments 1 to 4 is used as one mode of a semiconductor device. An example of a display device having a display will be described with reference to FIGS. An example of a liquid crystal display device using a liquid crystal element as an element will be described with reference to FIGS. 24 to 37. The TFTs 628 and 629 used in the liquid crystal display devices of FIGS. 24 to 37 are the same as those of the first to third embodiments. The thin film transistor shown in FIG. 4 can be applied to the thin film transistor shown in FIG. The TFT628 is a thin film transistor with excellent electrical characteristics and high reliability that can be easily fabricated. The TFT 629 has a channel protection layer 611, and the TFT 629 has an oxide semiconductor This is an inverted staggered thin film transistor in which the layer serves as a channel forming region.

[0381] First, we will explain the VA (Vertical Alignment) type liquid crystal display device. VA type LCD devices are a type of LCD panel that controls the alignment of liquid crystal molecules. In a VA type LCD device, when no voltage is applied, the liquid crystal molecules are in contact with the panel surface. In this embodiment, the pixels are arranged in a vertical direction. It is designed to be divided into areas (sub-pixels) and tilt the molecules in different directions in each area. This is called multi-domain or multi-domain design. A liquid crystal display device that takes into consideration the design will be described.

[0382] 25 and 26 show the pixel electrode and the counter electrode, respectively. 1 is a plan view of a substrate on which electrodes are formed, showing a cross-sectional structure corresponding to a cutting line EF shown in the figure. 24. Also, FIG. 26 is a plan view of the substrate side on which the counter electrode is formed. The following description will be given with reference to these figures.

[0383] FIG. 24 shows a TFT 628, a pixel electrode layer 624 connected thereto, and a storage capacitor 630. The substrate 600 on which the counter electrode layer 640 and the like are formed is superimposed on the counter substrate 601. The figure shows the state in which the liquid crystal is injected.

[0384] A colored film 636 and a counter electrode layer 640 are formed on the counter substrate 601. An alignment film 648 is formed on the pixel electrode layer 624. An alignment film 646 is also formed on the counter electrode layer 640 and the protrusions 644. A liquid crystal layer 650 is formed between opposing substrates 601 .

[0385] On the substrate 600, a TFT 628, a pixel electrode layer 624 connected thereto, and a storage capacitor 6 The pixel electrode layer 624 includes a TFT 628, a wiring 616, and a storage capacitor 6 The insulating film 620 covering the insulating film 620 and the insulating film 622 covering the insulating film 620 are formed by contacts. The TFT 628 is connected to the wiring 618 through a hole 623. The storage capacitor 630 can be formed by using a thin film transistor (TFT) 628. The first capacitor wiring 604 formed at the same time as the gate wiring 602, the gate insulating film 606, and the wiring It is composed of a second capacitance wiring 617 formed at the same time as the wirings 616 and 618 .

[0386] The pixel electrode layer 624, the liquid crystal layer 650, and the counter electrode layer 640 are overlapped to form a liquid crystal element. It has been completed.

[0387] 25 shows a planar structure on a substrate 600. The pixel electrode layer 624 is made of the material shown in Embodiment 1. The pixel electrode layer 624 is formed using a slit 625. The slit 625 is formed by This is to control the crystal orientation.

[0388] The TFT 629 shown in FIG. 25 and the pixel electrode layer 626 and storage capacitor 631 connected thereto are The TFT 628, the pixel electrode layer 624, and the storage capacitor 630 can be formed in the same manner. Both the TFT 628 and the TFT 629 are connected to the wiring 616. The pixel of the panel is composed of pixel electrode layer 624 and pixel electrode layer 626. The pixel electrode layer 624 and the pixel electrode layer 626 are sub-pixels.

[0389] 26 shows the planar structure of the opposing substrate side. An opposing electrode layer 640 is formed on a light-shielding film 632. The counter electrode layer 640 is preferably formed using the same material as the pixel electrode layer 624. On the counter electrode layer 640, protrusions 644 are formed to control the alignment of the liquid crystal. In FIG. 26, the pixel electrode layer 624 and the pixel electrode layer 626 formed on the substrate 600 are indicated by dashed lines. The counter electrode layer 640, the pixel electrode layer 624, and the pixel electrode layer 626 are arranged to overlap each other. This shows how it is being used.

[0390] The equivalent circuit of this pixel structure is shown in Figure 27. Both TFT628 and TFT629 have gate electrodes. The line 602 is connected to the wiring 616. In this case, the capacitance wiring 604 and the capacitance wiring 605 are connected to each other. By making the positions different, the liquid crystal elements 651 and 652 can be made to operate differently. That is, by individually controlling the potentials of the capacitance wiring 604 and the capacitance wiring 605, the liquid crystal The orientation of the liquid crystal is precisely controlled to widen the viewing angle.

[0391] When a voltage is applied to the pixel electrode layer 624 in which the slit 625 is provided, a The slit 625 and the protrusion on the opposing substrate 601 side cause distortion of the electric field (oblique electric field). By arranging the 644 in an alternating interdigitated pattern, a diagonal electric field is effectively generated, By controlling the orientation, the direction in which the liquid crystal is oriented varies depending on the location. The multi-domain technology widens the viewing angle of the LCD panel.

[0392] Next, a VA type liquid crystal display device different from the above will be described with reference to FIGS. 28 to 31. do.

[0393] 28 and 29 show the pixel structure of a VA type liquid crystal display panel. 28 is a plan view of the above-mentioned embodiment, and a cross-sectional structure corresponding to the cutting line YZ shown in the figure is shown in FIG.

[0394] This pixel structure has multiple pixel electrodes in one pixel, and a TFT is connected to each pixel electrode. Each TFT is configured to be driven by a different gate signal. In other words, in a pixel with a multi-domain design, the signals applied to each pixel electrode are independently The system has a configuration for controlling the temperature.

[0395] The pixel electrode layer 624 is formed by contact holes passing through the insulating film 620 and the insulating film 622. In the hole 623, the wiring 618 is connected to the TFT 628. 6 is a contact hole 627 that penetrates the insulating film 620 and the insulating film 622. The wiring 619 is connected to the TFT 629. The gate wiring 602 of the TFT 628 and The gate wiring 603 of the TFT 629 is divided so that different gate signals can be applied. On the other hand, the wiring 616 functioning as a data line is separated from the TFT 628 and the TFT 62 The TFT 628 and the TFT 629 are the same as those shown in the first to fourth embodiments. A thin film transistor can be used as appropriate. A gate insulating film 606 is formed on the capacitor wiring 690 .

[0396] The pixel electrode layer 624 and the pixel electrode layer 626 have different shapes, and the pixel electrode layer 624 and the pixel electrode layer 626 are V-shaped. A pixel electrode layer 626 is formed so as to surround the outside of the pixel electrode layer 624. By applying different voltages to the electrode layer 626 to the TFTs 628 and 629, The equivalent circuit of this pixel structure is shown in Figure 31. The TFT 629 is connected to the gate wiring 602, and the TFT 629 is connected to the gate wiring 603. The TFT 628 and the TFT 629 are both connected to the wiring 616. By applying different gate signals to the gate wiring 603, the liquid crystal element 651 and the liquid crystal element 652 are operated. In other words, the operation of TFT628 and TFT629 can be controlled separately. By controlling the liquid crystals in the liquid crystal elements 651 and 652, the orientation of the liquid crystals can be precisely controlled. The corners can be widened.

[0397] A colored film 636 and a counter electrode layer 640 are formed on the counter substrate 601. A flattening film 637 is formed between the electrode layer 636 and the counter electrode layer 640 to prevent the alignment of the liquid crystal from being disturbed. FIG. 30 shows the planar structure of the opposing substrate side. The opposing electrode layer 640 is common to different pixels. The electrode is made of a metal, and a slit 641 is formed in it. The slits 625 on the element electrode layer 624 and pixel electrode layer 626 sides are arranged so as to interdigitate with each other. By doing so, it is possible to effectively generate an oblique electric field and control the alignment of the liquid crystal. This allows the orientation direction of the liquid crystal to vary depending on the location, thereby widening the viewing angle. In addition, in FIG. 30, the pixel electrode layer 624 and the pixel electrode layer 626 formed on the substrate 600 are indicated by dashed lines. The counter electrode layer 640, the pixel electrode layer 624, and the pixel electrode layer 626 are arranged in an overlapping manner. It shows how it is placed.

[0398] An alignment film 648 is formed on the pixel electrode layer 624 and the pixel electrode layer 626. An alignment film 646 is also formed on the layer 640. The liquid crystal layer 640 is disposed between the substrate 600 and the counter substrate 601. The pixel electrode layer 624, the liquid crystal layer 650, and the counter electrode layer 640 are formed. The pixel electrode layer 626 and the liquid crystal layer 627 are overlapped with each other to form a first liquid crystal element. The layer 650 and the counter electrode layer 640 overlap each other to form a second liquid crystal element. The pixel structure of the display panel described in FIGS. 28 to 31 has a first liquid crystal element and a second liquid crystal element in one pixel. It has a multi-domain structure with crystal elements.

[0399] Next, we will explain about the in-plane switching type liquid crystal display device. In the in-plane switching type, the liquid crystal molecules in the cell This method applies an electric field in the horizontal direction to drive the liquid crystal and express gradation. If this is done, the viewing angle can be widened to approximately 180 degrees. The liquid crystal display device used will be described below.

[0400] FIG. 32 shows a structure in which an electrode layer 607, a TFT 628, and a pixel electrode layer 624 connected to the TFT 628 are formed. The figure shows a state in which the substrate 600 and the opposing substrate 601 are overlapped and liquid crystal is injected. On the counter substrate 601, a colored film 636, a flattening film 637, etc. are formed. No counter electrode is provided on the counter substrate 601 side. A liquid crystal layer 650 is formed on the liquid crystal layer 642 via an alignment film 646 and an alignment film 648 .

[0401] On the substrate 600, an electrode layer 607, a capacitance wiring 604 connected to the electrode layer 607, and a T The electrode layer 607 is formed by the same method as the pixel electrode layer 427 shown in any of the first to fourth embodiments. The capacitor wiring 604 can be made of the same material as the gate wiring 602 of the TFT 628. The TFT 628 can be formed by the thin film transistor shown in any one of the first to fifth embodiments. The electrode layer 607 is partitioned into approximately pixel shapes. A gate insulating film 606 is formed on the electrode layer 607 and the capacitor wiring 604. can be.

[0402] The wiring 616 and wiring 618 of the TFT 628 are formed on the gate insulating film 606. 6 is a data line that carries a video signal in the liquid crystal display panel and is a wiring that extends in one direction. At the same time, the source and drain regions of the TFT 628 are connected. The wiring 618 serves as the other electrode of the source and drain, and the pixel electrode layer This is the wiring that connects to 624.

[0403] An insulating film 620 is formed on the wiring 616 and the wiring 618. In the contact hole formed in the insulating film 620, the pixel electrode layer 6 The pixel electrode layer 624 is formed using the same material as the pixel electrode layer described in Embodiment Mode 1. It is formed using.

[0404] In this manner, the TFT 628 and the pixel electrode layer 624 connected thereto are formed on the substrate 600. The storage capacitor is formed between the electrode layer 607 and the pixel electrode layer 624.

[0405] 33 is a plan view showing the configuration of a pixel electrode. The surface structure is shown in Figure 32. A slit 625 is provided in the pixel electrode layer 624. The liquid crystal layer 625 is for controlling the orientation of the liquid crystal. In this case, the electric field is applied to the electrode layer 607. The gate insulating layer 607 is located between the pixel electrode layer 624 and the pixel electrode layer 624. The thickness of the gate insulating film 606 is 50 to 200 nm. Since the thickness is sufficiently small compared to the thickness of the liquid crystal layer, which is about 10 μm, the thickness is substantially parallel to the substrate 600. An electric field is generated in the horizontal direction. This electric field controls the orientation of the liquid crystal. The liquid crystal molecules are rotated horizontally using an electric field in a nearly parallel direction. Since the display is horizontal even in this state, the influence of the viewing angle on contrast is minimal, and the viewing angle is wide. In addition, since both the electrode layer 607 and the pixel electrode layer 624 are light-transmitting electrodes, , the aperture ratio can be improved.

[0406] Next, another example of a liquid crystal display device of the lateral electric field type will be described.

[0407] Figures 34 and 35 show the pixel structure of an IPS type liquid crystal display device. Figure 35 is a plan view. The cross-sectional structure corresponding to the cutting line VW shown in the figure is shown in FIG. The following description will be made with reference to these two figures.

[0408] FIG. 34 shows a substrate 600 on which a TFT 628 and a pixel electrode layer 624 connected thereto are formed, The opposing substrate 601 is overlaid and liquid crystal is injected. A coloring film 636, a flattening film 637, etc. are formed on the opposing substrate 601 side. An alignment film 646 and an alignment film 647 are provided between the substrate 600 and the counter substrate 601. A liquid crystal layer 650 is formed via 48 .

[0409] A common potential line 609 and a TFT 628 are formed on the substrate 600. 9 can be formed simultaneously with the gate wiring 602 of the TFT 628. The thin film transistors described in any of Embodiments 1 to 4 can be applied to this.

[0410] The wiring 616 and wiring 618 of the TFT 628 are formed on the gate insulating film 606. 6 is a data line that carries a video signal in the liquid crystal display panel and is a wiring that extends in one direction. At the same time, the source and drain regions of the TFT 628 are connected. The wiring 618 serves as the other electrode of the source and drain, and the pixel electrode layer This is the wiring that connects to 624.

[0411] An insulating film 620 is formed on the wiring 616 and the wiring 618. A pixel electrode connected to the wiring 618 is formed through a contact hole 623 formed in the insulating film 620. The pixel electrode layer 624 is formed in the same manner as the pixel electrode layer shown in Embodiment 1. As shown in FIG. 35, the pixel electrode layer 624 is formed using a material. The pixel electrode is formed so that a horizontal electric field is generated together with the comb-shaped electrode formed at the same time as the pixel electrode. The comb-tooth portion of the layer 624 alternately interdigitates with the comb-shaped electrode formed at the same time as the common potential line 609. It is formed as follows.

[0412] When an electric field is generated between the potential applied to the pixel electrode layer 624 and the potential of the common potential line 609, The orientation of the liquid crystal is controlled by this electric field. The molecules are rotated horizontally. In this case, the liquid crystal molecules are horizontal in any state, so the viewing angle This has little effect on contrast and results in a wider viewing angle.

[0413] In this manner, the TFT 628 and the pixel electrode layer 624 connected thereto are formed on the substrate 600. The storage capacitor is formed by providing a gate insulating film 606 between a common potential line 609 and a capacitor electrode 615. The capacitor electrode 615 and the pixel electrode layer 624 are formed through the contact hole 63. It is connected via 3.

[0414] Next, the configuration of a TN type liquid crystal display device will be described.

[0415] Figures 36 and 37 show the pixel structure of a TN type liquid crystal display device. Figure 37 is a plan view. The cross-sectional structure corresponding to the cutting line KL shown in the figure is shown in FIG. The following description will be made with reference to these two figures.

[0416] The pixel electrode layer 624 is connected to the TFT 628 through the contact hole 623 and the wiring 618. The wiring 616, which functions as a data line, is connected to the TFT 628. Any of the TFTs shown in Embodiments 1 to 4 can be applied to 28.

[0417] The pixel electrode layer 624 is formed using the pixel electrode layer described in Embodiment 1. The gate wiring 604 can be formed simultaneously with the gate wiring 602 of the TFT 628. A gate insulating film 606 is formed on the capacitor wiring 604. The gate insulating film 606 is formed between the capacitor electrode 614 and the capacitor electrode 615. 5 and the pixel electrode layer 624 are connected via a contact hole 623 .

[0418] A colored film 636 and a counter electrode layer 640 are formed on the counter substrate 601. A flattening film 637 is formed between the electrode layer 636 and the counter electrode layer 640 to prevent the alignment of the liquid crystal from being disturbed. The liquid crystal layer 650 is provided between the pixel electrode layer 624 and the counter electrode layer 640 with an alignment film 648 and an alignment layer 648. It is formed through a membrane 646 .

[0419] The pixel electrode layer 624, the liquid crystal layer 650, and the counter electrode layer 640 are overlapped to form a liquid crystal element. It has been completed.

[0420] The colored film 636 may be formed on the substrate 600 side. A polarizing plate is attached to the surface opposite to the surface on which the transistors are formed, and an opposing substrate 601 A polarizing plate is attached to the surface opposite to the surface on which the counter electrode layer 640 is formed.

[0421] Through the above steps, a liquid crystal display device can be manufactured as a display device. The liquid crystal display device has a high aperture ratio.

[0422] (Embodiment 15) In this embodiment, an example of a process in which the number of steps and the number of photomasks are smaller than those in Embodiment 1 is shown. 39(A) to 39(D). FIG. 39(A) to FIG. 39(D) are similar to FIG. 1 to FIG. 3. Since the processes are the same except for some differences, the same symbols are used for the same parts and the details of the same parts are A detailed explanation will be omitted.

[0423] First, according to the first embodiment, a light-transmitting conductive film is formed on a substrate 400 having an insulating surface. After forming the gate electrode layers 411 and 421, a first photolithography process is performed. do.

[0424] Next, a first gate insulating layer 402a and a second gate insulating layer 402b are formed on the gate electrode layers 411 and 421. A stack of gate insulating layers 402b is formed.

[0425] Next, an oxide semiconductor film having a thickness of 2 nm to 200 nm is deposited on the second gate insulating layer 402b. A membrane 430 is formed (see FIG. 39(A)). Note that FIG. 39(A) is the same as FIG. 2(A). is.

[0426] Next, the oxide semiconductor film 430 is subjected to a second photolithography process to form an island-shaped oxide semiconductor film. Process into body layers.

[0427] The island-shaped oxide semiconductor layer is dehydrated or dehydrogenated. The temperature of the heat treatment is set to 350° C. or higher and lower than the strain point of the substrate, preferably 400° C. or higher. Here, the substrate is placed in an electric furnace, which is a type of heat treatment apparatus, and the oxide semiconductor layer is heated to a nitrogen atmosphere. After the heat treatment in a nitrogen atmosphere, the oxide semiconductor layer was dehydrated without being exposed to the air. Therefore, the oxide semiconductor layers 431 and 432 are obtained (see FIG. 39B). The steps up to this point are the same as those in the first embodiment, and FIG. 39(B) is the same as FIG. 2(B). be.

[0428] Next, a metal conductive film is formed on the second gate insulating layer 402b and the oxide semiconductor layers 431 and 432. After forming the conductive film, resist masks 445a and 445b are formed by a third photolithography process. 5b, and selectively etched to form the source electrode layer 415a and the drain electrode layer 415b. By using the resist masks 445a and 445b, In this embodiment, the resist masks 433a and 433b can be omitted.

[0429] Next, part of the oxide semiconductor layer is removed using the resist masks 445a and 445b. The oxide semiconductor layer 437 is thinned to have a groove (a depression) (see FIG. 39C). However, the thin film transistor can be switched without forming a groove (depression) in the oxide semiconductor layer. If the film functions as a blocking element, this etching step may not be necessary.

[0430] Next, the resist masks 445a and 445b are removed, and a fourth photolithography step is performed. A resist mask 438 is formed to cover the oxide semiconductor layer 437, and the oxide semiconductor layer 432 is then removed. The upper metal electrode layer 435 is removed (see FIG. 39(D)). Therefore, the state shown in FIG. 39(D) can be obtained by using an alkaline etchant. The material of the metal conductive film is an element selected from Al, Cr, Cu, Ta, Ti, Mo, and W. Alternatively, alloys containing the above elements or alloys of combinations of the above elements may be used. In this embodiment, a Ti film is used as the metal conductive film, and the oxide semiconductor layers 431 and 432 are In the study, an In-Ga-Zn-O oxide semiconductor film was used, and ammonium hydrogen peroxide was used as the etchant. Use water (a mixture of ammonia, water, and hydrogen peroxide).

[0431] The oxide semiconductor layer preferably has a thickness of 50 nm or less in order to maintain an amorphous state. In particular, in the case of a channel-etched thin-film transistor, the film thickness is further reduced by etching. The thickness of the thin film in the channel formation region is 30 nm or less. The film thickness of the thin film region of the transistor is set to 5 nm or more and 20 nm or less.

[0432] The channel width of the final thin-film transistor is between 0.5 μm and 10 μm. It is preferable to set the following.

[0433] The subsequent steps are the same as those in the first embodiment, and the steps shown in FIGS. 3A to 3E are carried out to form a thin film transistor. A protective insulating layer 403 and a planarizing insulating layer 404 are formed on the insulating layer 404. After forming 404, a contact hole reaching the drain electrode layer 425b is formed, and the pixel An electrode layer 427 and a conductive layer 417 are formed.

[0434] Through the above steps, a thin film transistor 410 is formed on the same substrate using eight photomasks. and the thin film transistor 420 is separately fabricated in the driver circuit or pixel portion. It is possible to allocate transistors with optimal structures on the same substrate without increasing the number of processes. Various circuits can be configured using this.

[0435] This embodiment mode can be freely combined with other embodiment modes.

[0436] (Embodiment 16) In this embodiment, the number of steps and the number of photomasks are smaller than those in the first and fifteenth embodiments. An example of a process with fewer steps is shown in Figures 40(A) to 40(C). Since this is the same as Figure 3 except for some differences in the process, the same symbols are used for the same parts and the same points are used. A detailed description of the location will be omitted.

[0437] First, according to the first embodiment, a light-transmitting conductive film is formed on a substrate 400 having an insulating surface. After forming the gate electrode layers 411 and 421, a first photolithography process is performed. do.

[0438] Next, a first gate insulating layer 402a and a second gate insulating layer 402b are formed on the gate electrode layers 411 and 421. A stack of gate insulating layers 402b is formed.

[0439] Next, an oxide semiconductor film having a thickness of 2 nm to 200 nm is deposited on the second gate insulating layer 402b. A membrane 430 is formed (see FIG. 40(A)). Note that FIG. 40(A) is the same as FIG. 2(A). is.

[0440] Next, the oxide semiconductor film 430 is subjected to a second photolithography process to form an island-shaped oxide semiconductor film. Process into body layers.

[0441] The island-shaped oxide semiconductor layer is dehydrated or dehydrogenated. The temperature of the heat treatment is set to 350° C. or higher and lower than the strain point of the substrate, preferably 400° C. or higher. Here, the substrate is placed in an electric furnace, which is a type of heat treatment apparatus, and the oxide semiconductor layer is heated to a nitrogen atmosphere. After the heat treatment in a nitrogen atmosphere, the oxide semiconductor layer was dehydrated without being exposed to the air. Therefore, the oxide semiconductor layers 431 and 432 are obtained (see FIG. 40B). The steps up to this point are the same as those in the first embodiment, and FIG. 40(B) is the same as FIG. 2(B). be.

[0442] Next, a metal conductive film is formed on the second gate insulating layer 402b and the oxide semiconductor layers 431 and 432. After forming the conductive film, resist masks 446a and 446b are formed by a third photolithography process. 6b, and selectively etched to form the source electrode layer 415a and the drain electrode layer 6b. 415b is formed, and the metal conductive film on the oxide semiconductor layer 432 is removed (FIG. 40(D) By using the resist masks 446a and 446b, the Therefore, the resist masks 433a, 433b, and 438 can be omitted.

[0443] When the etching selectivity between the oxide semiconductor layers 431 and 432 and the metal conductive film is high, As shown in FIG. 40C, the oxide semiconductor layers 431 and 432 are formed by etching the metal conductive film. This can reduce film loss during the application.

[0444] In order to perform selective etching, an alkaline etchant is used. The metal conductive film can be made of Al, Cr, Cu, Ta, Ti, etc. , Mo, W, or an alloy containing the above elements, or In this embodiment, a Ti film is used as the metal conductive film, and the Ti film is oxidized. The semiconductor layers 431 and 432 are made of In-Ga-Zn-O oxide semiconductor films. Ammonia peroxide solution (a mixture of ammonia, water, and hydrogen peroxide solution) is used as the reagent.

[0445] The subsequent steps are the same as those in the first embodiment, and the steps shown in FIGS. 3A to 3E are carried out to form a thin film transistor. A protective insulating layer 403 and a planarizing insulating layer 404 are formed on the insulating layer 404. After forming 404, a contact hole reaching the drain electrode layer 425b is formed, and the pixel An electrode layer 427 and a conductive layer 417 are formed.

[0446] Through the above steps, a thin film transistor 410 is formed on the same substrate using seven photomasks. and the thin film transistor 420 is separately fabricated in the driver circuit or pixel portion. It is possible to allocate transistors with optimal structures on the same substrate without increasing the number of processes. Various circuits can be configured using this.

[0447] This embodiment mode can be freely combined with other embodiment modes.

[0448] (Embodiment 17) In this embodiment, an example in which an oxide semiconductor layer is surrounded by a nitride insulating film as viewed from the cross section is shown in FIG. 38 is different from that in FIG. 1 in the top surface shape and end position of the oxide insulating layer 416. Since the two are the same except for the difference in the configuration of the edge layer, the same symbols are used for the same parts, and Detailed explanation will be omitted.

[0449] The thin film transistor 410 disposed in the driving circuit is a channel-etch type thin film transistor. On a substrate 400 having an insulating surface, a gate electrode layer 411 and a gate electrode made of a nitride insulating film are formed. The gate insulating layer 402, at least the channel forming region 413, the first high resistance drain region 41 4a, and the oxide semiconductor layer having the second high-resistance drain region 414b, the source electrode layer 4 The thin film transistor 410 is covered with a gate insulating layer 415a and a drain electrode layer 415b. An oxide insulating layer 416 is provided in contact with the channel formation region 413 .

[0450] The oxide insulating layer 416 serves as a channel protection layer for the thin film transistor 420 disposed in the pixel. When the oxide insulating layer 426 that functions as a thin film transistor is formed by a photolithography process, The gate insulating layer 402 outside the gate 410 is processed to be exposed. The top surface of the layer 416 is wider than the top surface of the oxide semiconductor layer. It is preferable that the upper surface has a shape that covers the

[0451] Furthermore, a protective insulating layer made of a nitride insulating film is formed so as to cover the top and side surfaces of the oxide insulating layer 416. Form 403.

[0452] Furthermore, the first high-resistance drain region 414a is in contact with the lower surface of the source electrode layer 415a and is self-aligned. In addition, a second high-resistance drain is formed in contact with the lower surface of the drain electrode layer 415b. The channel forming region 413 is formed by an oxide film. The first high-resistance drain region 414 is in contact with the oxide insulating layer 416 and has a reduced thickness. a and the second high-resistance drain region 414b are regions (I-type regions) having higher resistance than the first high-resistance drain region 414a.

[0453] The channel forming region 413, the first high-resistance drain region 414a, and the second high-resistance A gate insulating layer 402 made of a nitride insulating film is formed in contact with the lower surface of the drain region 414b. It is being done.

[0454] The protective insulating layer 403 made of a nitride insulating film is a silicon nitride film obtained by sputtering, an oxynitride film, or the like. Moisture, hydrogen ions, and O H - The inorganic insulating film does not contain impurities such as Use.

[0455] In this embodiment, the oxide semiconductor layer 41 is used as the protective insulating layer 403 made of a nitride insulating film. The bottom, top, and side surfaces of the substrate 2 were surrounded by a 100 nm thick silicon nitride film using RF sputtering. A protective insulating layer 403 is connected to a gate insulating layer 402 made of a nitride insulating film. The configuration will be as follows.

[0456] By using the structure shown in FIG. 38, the manufacturing process after forming the protective insulating layer 403 made of a nitride insulating film In the process, it is possible to prevent moisture from entering from the outside. For example, even after the device is completed as a liquid crystal display device, it will continue to prevent moisture from entering from the outside for a long period of time. This can improve the long-term reliability of the device.

[0457] Similarly, the thin film transistor 420 also has a protective insulating layer 403 made of a nitride insulating film. , a film thickness formed by RF sputtering so as to surround the top surface and side surfaces of the oxide semiconductor layer 422. A 100 nm silicon nitride film is used. The protective insulating layer 403 is made of a gate insulating film of nitride. The insulating layer 402 is in contact with the insulating layer 402 .

[0458] In addition, in this embodiment, a configuration in which one thin film transistor is surrounded by a nitride insulating film is shown. The present invention is not limited to this, and a configuration in which a plurality of thin film transistors are surrounded by a nitride insulating film may also be used. A plurality of thin film transistors in the region may be surrounded by a nitride insulating film. The protective insulating layer 403 and the gate insulating layer 404 are formed so as to surround the periphery of the pixel portion of the active matrix substrate. A region in contact with the layer 402 may be provided.

[0459] This embodiment mode can be freely combined with other embodiment modes.

Claims

1. A pixel portion having a first transistor and a driver circuit having a second transistor on a substrate, The pixel unit The gate wiring, a first oxide semiconductor layer located above the gate wiring and including a channel formation region of the first transistor; a first conductive layer having a region located above the first oxide semiconductor layer and electrically connected to the first oxide semiconductor layer; an inorganic insulating layer having a region located above the first oxide semiconductor layer and a region located above the first conductive layer; a planarizing insulating layer above the inorganic insulating layer; a pixel electrode having a region located above the planarization insulating layer and electrically connected to the first oxide semiconductor layer via the first conductive layer; The drive circuit a second conductive layer that functions as a gate electrode of the second transistor; a second oxide semiconductor layer located above the second conductive layer and including a channel formation region of the second transistor; a third conductive layer having a region located above the second oxide semiconductor layer and electrically connected to the second oxide semiconductor layer; the inorganic insulating layer having a region located above the second oxide semiconductor layer and a region located above the second conductive layer; the planarization insulating layer above the inorganic insulating layer; a fourth conductive layer provided above the planarization insulating layer and having the same material as the pixel electrode; In a plan view, the gate wiring has a first region having a first wiring width, a second region having a second wiring width smaller than the first wiring width, and a third region having a third wiring width smaller than the second wiring width; the first region overlaps with the first oxide semiconductor layer; In a plan view, the third region is located between the first region and the second region, the first conductive layer has a portion located in a region surrounded by the first region, the second region, and the third region in a plan view; the pixel electrode has a region overlapping with the first oxide semiconductor layer in a cross-sectional view in a channel length direction of the first transistor, the fourth conductive layer has a region overlapping with the second conductive layer with the second oxide semiconductor layer interposed therebetween.

2. A pixel portion having a first transistor and a driver circuit having a second transistor on a substrate, The pixel unit The gate wiring, a first oxide semiconductor layer located above the gate wiring and including a channel formation region of the first transistor; a first conductive layer having a region located above the first oxide semiconductor layer and electrically connected to the first oxide semiconductor layer; an inorganic insulating layer having a region located above the first oxide semiconductor layer and a region located above the first conductive layer; a planarizing insulating layer above the inorganic insulating layer; a pixel electrode having a region located above the planarization insulating layer and electrically connected to the first oxide semiconductor layer via the first conductive layer; The drive circuit a second conductive layer that functions as a gate electrode of the second transistor; a second oxide semiconductor layer located above the second conductive layer and including a channel formation region of the second transistor; a third conductive layer having a region located above the second oxide semiconductor layer and electrically connected to the second oxide semiconductor layer; the inorganic insulating layer having a region located above the second oxide semiconductor layer and a region located above the second conductive layer; the planarization insulating layer above the inorganic insulating layer; a fourth conductive layer provided above the planarization insulating layer and having the same material as the pixel electrode; the first oxide semiconductor layer and the second oxide semiconductor layer each contain In, Ga, and Zn; In a plan view, the gate wiring has a first region having a first wiring width, a second region having a second wiring width smaller than the first wiring width, and a third region having a third wiring width smaller than the second wiring width; the first region overlaps with the first oxide semiconductor layer; In a plan view, the third region is located between the first region and the second region, the first conductive layer has a portion located in a region surrounded by the first region, the second region, and the third region in a plan view; the pixel electrode has a region overlapping with the first oxide semiconductor layer in a cross-sectional view in a channel length direction of the first transistor, the fourth conductive layer has a region overlapping with the second conductive layer with the second oxide semiconductor layer interposed therebetween.

Images