Semiconductor Devices

Abstract

To provide a semiconductor device that can prevent inconvenience on a lamination surface and near the lamination surface, a wafer, and a method for manufacturing a wafer.SOLUTION: A semiconductor device of an embodiment has a first laminate, and a second laminate laminated on the first laminate. The first laminate has a first pad provided on a first lamination surface on which the first laminate and the second laminate are laminated. The second laminate has a second pad joined to the first pad on the first lamination surface. When a direction directed from the first laminate to the second laminate is defined as a first direction, a direction intersecting the first direction as a second direction, a direction intersecting the first direction and second direction as a third direction, the dimensions of the first pad and second pad in the third direction as PX1, PX2, and the dimensions of the first pad and second pad in the second direction as PY1, PY2, the dimensions of the first pad and second pad satisfy at least one of the following formulas (1) and (2). (1) PX1>PY1; (2) PY2>PX2.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] An embodiment of the present invention is a semiconductor device. Place Regarding. [Background technology]

[0002] NAND flash memories in which memory cells are stacked three-dimensionally are known. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent Publication No. 2021-136320 Summary of the Invention [Problem to be solved by the invention]

[0004] The problem to be solved by the present invention is to provide a semiconductor device, a wafer, and a method for manufacturing a wafer that can suppress defects on the bonding surface and in the vicinity of the bonding surface. [Means for solving the problem]

[0005] The semiconductor device of the embodiment has a first laminate and a second laminate bonded to the first laminate. The first laminate has a first wiring and a first pad. The first pad is provided on a first bonding surface where the first laminate and the second laminate are bonded and is electrically connected to the first wiring through a first via. The second laminate has a second wiring and a second pad. The second pad is electrically connected to the second wiring through a second via and is joined to the first pad on the first bonding surface. If the direction from the first laminate to the second laminate is defined as the first direction, the direction intersecting the first direction is defined as the second direction, and the direction intersecting the first and second directions is defined as the third direction, and the dimension of the first pad in the third direction is defined as PX1, the dimension of the first pad in the second direction is defined as PY1, the dimension of the second pad in the third direction is defined as PX2, and the dimension of the second pad in the second direction is defined as PY2, then the dimension of the first pad and the dimension of the second pad satisfy at least one of the following formulas (1) and (2). PX1>PY1 (1) PY2>PX2 (2) [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a block diagram showing a semiconductor device and a memory controller according to a first embodiment. [Figure 2] FIG. 2 is a diagram showing an equivalent circuit of a part of the memory cell array of the semiconductor device according to the first embodiment. [Figure 3] FIG. 1 is a cross-sectional view showing a part of a semiconductor device according to a first embodiment. [Figure 4] FIG. 2 is an enlarged cross-sectional view of the vicinity of a columnar portion of the semiconductor memory device according to the first embodiment. [Figure 5A] FIG. 2 is an enlarged cross-sectional view of the vicinity of a metal pad of the semiconductor device according to the first embodiment. [Figure 5B] FIG. 2 is an enlarged plan view of the vicinity of a metal pad 38 of the semiconductor device according to the first embodiment. [Figure 5C] FIG. 2 is an enlarged plan view of the vicinity of a metal pad 41 of the semiconductor device according to the first embodiment. [Figure 6] 2A to 2C are cross-sectional views showing a method for manufacturing the semiconductor device 1 according to the first embodiment. [Figure 7]2A to 2C are cross-sectional views showing a method for manufacturing the semiconductor device 1 according to the first embodiment. [Figure 8] FIG. 10 is a schematic perspective view showing the structure of a wafer W according to a second embodiment. [Figure 9] 9 is a cross-sectional view taken along line FF in FIG. 8. [Figure 10A] FIG. 10 is an enlarged cross-sectional view of the vicinity of a bonding surface S of a wafer according to a second embodiment. [Figure 10B] FIG. 10 is an enlarged cross-sectional view of the vicinity of the bonding surface S of the wafer in a modified example of the second embodiment. [Figure 11] 5A to 5C are cross-sectional views showing a manufacturing method according to the second embodiment. [Figure 12] FIG. 1 is a plan view of a circuit wafer for explaining MAG correction. [Figure 13] FIG. 10 is an enlarged plan view of the vicinity of a wiring layer 136b of a circuit wafer for explaining MAG correction. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, semiconductor devices, wafers, and wafer manufacturing methods according to embodiments will be described with reference to the drawings. In the following description, components having the same or similar functions will be designated by the same reference numerals. Duplicate descriptions of these components may be omitted. Furthermore, in the following description, components having substantially the same functions and configurations will be designated by the same reference numerals. The numerals following the letters of the reference numerals are used to distinguish between elements that are referred to by the reference numerals containing the same letters and have similar configurations. When there is no need to distinguish between elements indicated by reference numerals containing the same letters, these elements will be referred to by reference numerals containing only the letters. The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between parts, and the like may not necessarily be the same as in reality.

[0008] In this application, "connection" is not limited to physical connection, but also includes electrical connection. In this application, "parallel," "orthogonal," or "same" also include "substantially parallel," "substantially orthogonal," or "substantially the same," respectively. In this application, "extending in the A direction" means, for example, that the dimension in the A direction is larger than the smallest dimension among the dimensions in the X direction, Y direction, and Z direction, which will be described later. The "A direction" here refers to any direction.

[0009] First, the X direction, Y direction, and Z direction will be defined. The X direction and Y direction are directions approximately parallel to the surface of the substrate 15, which will be described later. The X direction and Y direction are perpendicular to each other. The Z direction is perpendicular to the X direction and Y direction and is a direction away from the substrate 15. However, these expressions are used for convenience and do not define the direction of gravity. In this embodiment, the Z direction is an example of the "first direction," the Y direction is an example of the "second direction," and the X direction is an example of the "third direction."

[0010] In the drawings referred to below, for example, the Y direction corresponds to the extension direction of the bit lines BL, and the Z direction corresponds to the direction perpendicular to the surface of the substrate 15 used to form the semiconductor device 1. In this specification, the +Z direction is treated as the upward direction, and the −Z direction is treated as the downward direction. The −Z direction may or may not coincide with the direction of gravity.

[0011] In the drawings referred to below, hatching is applied to some components in the plan views to make the drawings easier to understand. The hatching applied to the plan views does not necessarily relate to the materials or characteristics of the components to which the hatching is applied. In the plan views and cross-sectional views, some components such as wiring, contacts, and interlayer insulating films are omitted as appropriate to make the drawings easier to understand.

[0012] <1> First embodiment The semiconductor device 1 according to the first embodiment will be described below.

[0013] <1-1> Overall configuration of semiconductor device 1 1 is a block diagram showing a semiconductor device 1 and a memory controller 2. The semiconductor device 1 is a nonvolatile semiconductor device, such as a NAND flash memory, and includes, for example, a memory cell array 10, a row decoder 11, a sense amplifier 12, and a sequencer 13.

[0014] The memory cell array 10 includes a plurality of blocks BLK0 to BLKn (n is an integer equal to or greater than 1). Each block BLK is a collection of non-volatile memory cell transistors MT (see FIG. 2). The memory cell array 10 is provided with a plurality of bit lines and a plurality of word lines. Each memory cell transistor MT is connected to one bit line and one word line. The detailed configuration of the memory cell array 10 will be described later.

[0015] The row decoder 11 selects one block BLK based on address information ADD received from the external memory controller 2. The row decoder 11 controls data write and read operations for the memory cell array 10 by applying a desired voltage to each of a plurality of word lines.

[0016] The sense amplifier 12 applies a desired voltage to each bit line in accordance with the write data DAT received from the memory controller 2. The sense amplifier 12 determines the data stored in the memory cell transistor MT based on the voltage of the bit line, and transmits the determined read data DAT to the memory controller 2.

[0017] The sequencer 13 controls the overall operation of the semiconductor memory device 1 based on the command CMD received from the memory controller 2.

[0018] A single semiconductor device may be configured by combining the above-described semiconductor device 1 and memory controller 2. Examples of the semiconductor device include a memory card such as an SD (registered trademark) card, an SSD (Solid State Drive), and the like.

[0019] <1-2> Circuit configuration of memory cell array 10 Next, the electrical configuration of the memory cell array 10 will be described. Fig. 2 is a diagram showing an equivalent circuit of a part of the memory cell array 10. Fig. 2 shows an extracted block BLK included in the memory cell array 10. The block BLK includes a plurality of (for example, four) strings STR0 to STR3.

[0020] Each of the strings STR0 to STR3 is a collection of multiple NAND strings NS. One end of each of the NAND strings NS is connected to one of the bit lines BL0 to BLm (m is an integer equal to or greater than 1). The other end of the NAND string NS is connected to a source line SL. Each of the NAND strings NS includes multiple memory cell transistors MT0 to MTn (n is an integer equal to or greater than 1), a first selection transistor S1, and a second selection transistor S2.

[0021] The memory cell transistors MT0 to MTn are electrically connected in series with each other. Each memory cell transistor MT includes a control gate and a memory stack film (e.g., a charge storage film), and stores data in a non-volatile manner. The memory cell transistor MT changes the state of the memory stack film (e.g., stores charge in the charge storage film) in response to a voltage applied to the control gate. The control gate of each memory cell transistor MT is connected to one of the corresponding word lines WL0 to WLn. The memory cell transistor MT is electrically connected to a row decoder 11 via the word line WL.

[0022] The first select transistor S1 in each NAND string NS is connected between the plurality of memory cell transistors MT0 to MTn and one of the bit lines BL0 to BLm. The drain of the first select transistor S1 is connected to one of the bit lines BL0 to BLm. The source of the first select transistor S1 is connected to the memory cell transistor MTn. The control gate of the first select transistor S1 in each NAND string NS is connected to one of the select gate lines SGD0 to SGD3. The first select transistor S1 is electrically connected to the row decoder 11 via the select gate line SGD. When a predetermined voltage is applied to any of the select gate lines SGD0 to SGD3, the first select transistor S1 connects the NAND string NS to the bit line BL.

[0023] The second select transistor S2 in each NAND string NS is connected between the plurality of memory cell transistors MT0 to MTn and a source line SL. The drain of the second select transistor S2 is connected to the memory cell transistor MT0. The source of the second select transistor S2 is connected to the source line SL. The control gate of the second select transistor S2 is connected to a select gate line SGS. The second select transistor S2 is electrically connected to the row decoder 11 via the select gate line SGS. The second select transistor S2 connects the NAND string NS to the source line SL when a predetermined voltage is applied to the select gate line SGS.

[0024] The memory cell array 10 may have a circuit configuration other than that described above. For example, the number of strings STR included in each block BLK, the number of memory cell transistors MT included in each NAND string NS, and the number of select transistors STD and STS included in each NAND string NS may be changed. Furthermore, the NAND string NS may include one or more dummy transistors.

[0025] <1-3> Structure of semiconductor device An example of the structure of the semiconductor device 1 according to this embodiment will be described below.

[0026] In the drawings referred to below, hatching is appropriately added to the plan views to make the drawings easier to see. The hatching added to the plan views does not necessarily relate to the materials or properties of the components to which the hatching is added. In the cross-sectional views, components such as insulating layers (interlayer insulating films), wiring, and contacts are appropriately omitted to make the drawings easier to see.

[0027] Fig. 3 is a cross-sectional view showing the structure of the semiconductor device of the first embodiment. The semiconductor device 1 in Fig. 3 is a three-dimensional memory in which a circuit chip 100 and an array chip 200 are bonded together. The circuit chip 100 is an example of a "first stack," and the array chip 200 is an example of a "second stack."

[0028] The array chip 200 includes a memory cell array 10 including a plurality of memory cells, an insulating film 52 on the memory cell array 10, and an interlayer insulating film 54 below the memory cell array 10. The insulating film 52 is, for example, a silicon oxide film or a silicon nitride film. The interlayer insulating film 54 is, for example, a silicon oxide film or a laminated film including a silicon oxide film and another insulating film.

[0029] The circuit chip 100 is provided below the array chip 200. The symbol S indicates the bonding surface between the array chip 200 and the circuit chip 100. The bonding surface S is an example of a first bonding surface. The circuit chip 100 includes an interlayer insulating film 53 and a substrate 15 below the interlayer insulating film 53. The interlayer insulating film 53 is, for example, a silicon oxide film or a laminated film including a silicon oxide film and another insulating film. The substrate 15 is, for example, a semiconductor substrate such as a silicon substrate.

[0030] FIG. 1 shows an X direction and a Y direction which are parallel to the surface of the substrate 15 and perpendicular to each other, and a Z direction which is perpendicular to the surface of the substrate 15.

[0031] The array chip 200 includes a plurality of word lines WL and source lines SL as electrode layers in a memory cell array 10. FIG. 1 shows a staircase structure ST of the memory cell array 10. Each word line WL is electrically connected to a word wiring layer 23 via a contact plug 22. Each columnar portion CL penetrating the plurality of word lines WL is electrically connected to a bit line BL via a via plug 24 and is also electrically connected to a source line SL. The source line SL may include a first layer SL1 that is a semiconductor layer and a second layer SL2 that is a metal layer.

[0032] The circuit chip 100 includes a plurality of transistors 31. Each transistor 31 includes a gate electrode 32 provided on the substrate 15 via a gate insulating film, and a source diffusion layer (not shown) and a drain diffusion layer (not shown) provided in the substrate 15. The circuit chip 100 includes a plurality of contact plugs 33 provided on the gate electrodes 32, source diffusion layers, or drain diffusion layers of these transistors 31, a wiring layer 34 provided on these contact plugs 33 and including a plurality of wires, and a wiring layer 35 provided on the wiring layer 34 and including a plurality of wires.

[0033] The circuit chip 100 further includes a wiring layer 36 provided on the wiring layer 35 and including a plurality of wirings, a plurality of via plugs 37 provided on the wiring layer 36, and a plurality of metal pads 38 provided on these via plugs 37. The wiring layer 36 can be made of, for example, W (tungsten). The wiring layer 36 is an example of a "first wiring." The via plugs 37 can be made of, for example, Cu (copper) or W (tungsten). The via plugs 37 are an example of a "first via." The metal pads 38 are, for example, a Cu (copper) layer or an Al (aluminum) layer. The metal pads 38 are an example of a "first pad." Details of the metal pads 38 will be described later. The circuit chip 100 functions as a control circuit (logic circuit) that controls the operation of the array chip 200. This control circuit is composed of transistors 31 and the like, and is electrically connected to the metal pads 38.

[0034] The circuit chip 100 may further include at least one dummy pad 38A provided above the transistor 31. In this case, the dummy pad 38A is provided on the bonding surface S, similar to the metal pad 38, but is not electrically connected to the transistor 31.

[0035] The array chip 200 includes a plurality of metal pads 41 provided on the metal pads 38 and a plurality of via plugs 42 provided on the metal pads 41. The array chip 1 also includes a wiring layer 43 provided on these via plugs 42 and including a plurality of wirings. The metal pads 41 are electrically connected to the wiring layer 43 through the via plugs 42 and are joined to the metal pads 38 at the bonding surface S. The wiring layer 43 can be exemplified by W (tungsten). The wiring layer 43 is an example of a "second wiring." The via plugs 42 can be exemplified by Cu (copper) or W (tungsten). The via plugs 42 are an example of a "second via." The metal pads 41 are, for example, a Cu layer or an Al layer. The metal pads 41 are an example of a "second pad." Details of the metal pads 41 will be described later.

[0036] The array chip 200 further includes, in a region adjacent to the staircase structure portion ST in the X direction, a plurality of via plugs 45 provided above the wiring layer 43, metal pads 46 provided on the via plugs 45 and on the insulating film 52, and a passivation film 47 provided on the metal pads 46 and on the insulating film 52. The metal pads 46 are, for example, a Cu layer or an Al layer, and function as external connection pads (bonding pads) of the semiconductor device 1 of FIG. 1. The passivation film 47 is, for example, an insulating film such as a silicon oxide film, and has an opening P that exposes the top surface of the metal pads 46. The metal pads 46 can be connected to a mounting substrate or another device via a bonding wire, a solder ball, a metal bump, or the like through the opening P.

[0037] The array chip 200 may further include a dummy pad 41A on the dummy pad 38A. In this case, the dummy pad 41A is provided on the bonding surface S, similar to the metal pad 41, but is not connected to the memory cell array 10.

[0038] FIG. 4 is a cross-sectional view showing the structure of the columnar portion CL of the first embodiment.

[0039] 4, the memory cell array 10 includes a plurality of word lines WL and a plurality of insulating layers 61 alternately stacked on an interlayer insulating film 54 (see FIG. 1). The word lines WL are, for example, W (tungsten) layers. The insulating layers 61 are, for example, silicon oxide films.

[0040] The pillar CL may include a memory film 60, a semiconductor body 65, and a core 66 in this order.

[0041] The core 66 extends in the Z direction and has a columnar shape. The core 66 includes, for example, silicon oxide. The core 66 is located inside the semiconductor body 65.

[0042] The semiconductor body 65 extends in the Z direction. The semiconductor body 65 is cylindrical with a bottom. The semiconductor body 65 covers the outer surface of the core 66. The semiconductor body 65 includes, for example, silicon. The silicon is, for example, polysilicon obtained by crystallizing amorphous silicon. The semiconductor body 65 is the channel of each of the first select transistor S1, the memory cell transistor MT, and the second select transistor S2. The channel is a flow path for carriers between the source side and the drain side.

[0043] The memory film 60 extends in the Z direction. The memory film 60 covers the outer surface of the semiconductor body 65. The memory film 60 includes, for example, a tunnel insulating film 64, a charge storage film 63, and a block insulating film 62. The tunnel insulating film 64, the charge storage film 63, and the block insulating film 62 are located closer to the semiconductor body 65 in this order.

[0044] The tunnel insulating film 64 is located between the charge storage film 63 and the semiconductor body 65. The tunnel insulating film 64 includes, for example, silicon oxide or a combination of silicon oxide and silicon nitride. The tunnel insulating film 64 is a potential barrier between the semiconductor body 65 and the charge storage film 63.

[0045] The charge storage film 63 is located between each word line WL, the insulating layer 61, and the tunnel insulating film 64. The charge storage film 63 includes, for example, silicon nitride. The charge storage layer 63 may also be a semiconductor layer such as a polysilicon layer. The portions where the charge storage film 63 intersects with each of the word lines WL may function as transistors. The memory cell transistor MT retains data depending on the presence or absence of charge or the amount of accumulated charge in the portions where the charge storage film 63 intersects with the word lines WL (charge storage portions). The charge storage portions are located between each word line WL and the semiconductor body 65, and are surrounded by an insulating material.

[0046] The block insulating film 62 is located, for example, between each insulating layer 61 and the charge storage film 63. The block insulating film 62 includes, for example, silicon oxide. The block insulating film 62 protects the charge storage film 63 from etching during processing.

[0047] Next, the arrangement and dimensions of the metal pads 38, 41 of the semiconductor device 1 of the first embodiment will be described in detail.

[0048] Fig. 5A is an enlarged cross-sectional view of the vicinity of metal pads 38 and 41 of semiconductor device 1 of the first embodiment, and Fig. 5B is a plan view of the vicinity of metal pad 38 of semiconductor device 1 of the first embodiment.

[0049] As shown in Figures 5A and 5B, if the dimension of the metal pad in the X direction is PX1, the dimension of the metal pad 38 in the Y direction is PY1, the dimension of the metal pad 41 in the X direction is PX2, and the dimension of the metal pad in the Y direction is PY2, the dimensions of the metal pads 38 and 41 of the semiconductor device 1 satisfy at least one of the following formulas (1) and (2).

[0050] PX1>PY1 (1) PY2>PX2 (2)

[0051] As described above, the semiconductor device 1 of the first embodiment is a three-dimensional memory in which the circuit chip 100 and the array chip 200 are bonded together. The semiconductor device 1 is manufactured by separately manufacturing the circuit chip 100 and the array chip 200 and then bonding them together at the bonding surface S. Specifically, a circuit wafer W1 including a plurality of circuit chips 100 is bonded to an array wafer W2 including a plurality of array chips 200 (see FIGS. 6 and 7 ). During this bonding process, warping frequently occurs in the array wafer W2. When warping occurs in the array wafer W2, a deviation occurs in the X and / or Y directions between the actual and intended positions of the array chips 200. When such a deviation occurs, the contact area between the metal pads 38 and 41 becomes insufficient, which may result in insufficient bonding.

[0052] Therefore, in the semiconductor device 1 of the first embodiment, the dimensions of the metal pads 38, 41 satisfy at least one of the above formulas (1) and (2). That is, for example, by satisfying the above formula (1) for the metal pad 38 (i.e., making the dimension of the metal pad 38 in the X direction larger than the dimension in the Y direction), even if the position of the metal pad 41 is shifted due to the warpage, the bonding surfaces of the metal pads 38, 41 can be stably secured.

[0053] 5A and 5B show a case where the dimensions of the metal pad 38 are adjusted, but the first embodiment is not limited to this example. For example, as shown in Fig. 5C, the bonding surface may be secured by adjusting the dimensions of the metal pad 41. Specifically, as shown in Fig. 5C, by making the metal pad 41 satisfy the above formula (2) (i.e., making the dimension in the Y direction larger than the dimension in the X direction), the bonding surface between the metal pads 38 and 41 can be stably secured even if the position of the metal pad 41 is shifted due to the warpage.

[0054] In order to ensure a more stable bonding surface between the metal pads 38 and 41, it is preferable that both of the above formulas (1) and (2) are satisfied.

[0055] At least one of the metal pads 38, 41 of the semiconductor device 1 of the first embodiment may be substantially rectangular in plan view from the Z direction. One of the metal pads 38, 41 may be substantially rectangular and the other may be substantially square. Both the metal pads 38, 41 may be substantially rectangular.

[0056] In the first embodiment, from the viewpoint of ensuring a more stable bonding surface between the metal pads 38, 41, it is preferable that the dimensions of the metal pads 38, 41 satisfy at least one of the following formulas (3) and (4).

[0057] PX1>PX2 (3) PY2>PY1 (4)

[0058] In terms of the dimensions of the metal pads 38 and 41, by making PX1 larger than PX2, it is possible to more effectively prevent poor bonding between the circuit chip 100 and the array chip 200. Similarly, by making PY2 larger than PY1, it is possible to more effectively prevent poor bonding between the circuit chip 100 and the array chip 200.

[0059] In order to ensure a more stable bonding surface between the metal pads 38 and 41, it is preferable to satisfy both of the above formulas (3) and (4).

[0060] <1-4> Manufacturing method of semiconductor device 1 6 and 7 are cross-sectional views showing a method for manufacturing the semiconductor device 1 of the first embodiment. 6 shows an array wafer W2 including a plurality of array chips 200 and a circuit wafer W1 including a plurality of circuit chips 100. The array wafer W2 is also called a "memory wafer," and the circuit wafer W1 is also called a "CMOS wafer." The circuit wafer W1 is an example of a first wafer, and the array wafer W1 is an example of a second wafer.

[0061] The orientation of the array wafer W2 in the Z direction in Fig. 6 is opposite to the orientation of the array chip 200 in Fig. 3. In this embodiment, the semiconductor device 1 is manufactured by bonding the array wafer W2 and the circuit wafer W1 together. Fig. 6 shows the array wafer W2 before its orientation is reversed for bonding, and Fig. 3 shows the array chip 200 after its orientation is reversed for bonding, bonding, and dicing.

[0062] 6, symbol S2 denotes the upper surface of the array wafer W2, and symbol S1 denotes the upper surface of the circuit wafer W1. The array wafer W2 includes a substrate 16 provided under an insulating film 52. The substrate 16 is, for example, a semiconductor substrate such as a silicon substrate.

[0063] 6, in this embodiment, first, the memory cell array 10, the insulating film 52, the interlayer insulating film 13, the staircase structure ST, the plurality of metal pads 41, at least one dummy pad 41A, etc. are formed on the substrate 16 of the array wafer W2. For example, the plurality of via plugs 45, the plurality of wiring layers 43, the plurality of via plugs 42, and the plurality of metal pads 41 are formed in this order on the substrate 16.

[0064] 6, an interlayer insulating film 53, a transistor 31, a plurality of metal pads 38, at least one dummy pad 38A, etc. are formed on the substrate 15 of the circuit wafer W1. For example, a contact plug 33, a plurality of wiring layers 34, a plurality of wiring layers 35, a plurality of wiring layers 36, a plurality of via plugs 37, and a plurality of metal pads 38 are formed in this order on the substrate 15.

[0065] 7, the array wafer W2 and the circuit wafer W1 are bonded together. The array wafer W2 and the circuit wafer W1 may be bonded together by mechanical pressure. This bonds the interlayer insulating film 13 and the interlayer insulating film 53 together.

[0066] Next, the bonded array wafer W2 and circuit wafer W1 are annealed at 400° C. As a result, the metal pads 41 and 38, and the dummy pads 41A and 38A are bonded at the bonding surface S.

[0067] Thereafter, the substrate 16 is removed by CMP (Chemical Mechanical Polishing), and the array wafer W2 and the circuit wafer W1 are cut into a plurality of chips. At this time, the substrate 15 may be thinned by CMP. In this manner, the semiconductor device 1 shown in FIG. 3 is manufactured. FIG. 3 shows a circuit chip 100 including a plurality of metal pads 38, and an array chip 200 including a metal pad 41 disposed on each of the metal pads 38. Note that the metal pads 46 and passivation film 47 shown in FIG. 3 are formed on the insulating film 52, for example, after the substrate 16 (and the thinning of the substrate 15) is removed.

[0068] In this embodiment, the array wafer W2 and the circuit wafer W1 are bonded together, but instead, two array wafers W2 may be bonded together. The contents described above with reference to FIG. 3 are also applicable to bonding two array wafers W2 together.

[0069] 3 shows the boundary surface between the interlayer insulating film 13 and the interlayer insulating film 53 and the boundary surface between the metal pad 41 and the metal pad 38, but these boundaries generally become invisible after the above-mentioned annealing. However, the positions of these boundaries can be estimated by detecting, for example, the inclination of the side surface of the metal pad 41 or the side surface of the metal pad 38.

[0070] The semiconductor device 1 of the first embodiment may be in the state shown in FIG. 3 after being cut into a plurality of chips, or in the state shown in FIG. 7 before being cut into a plurality of chips. FIG. 3 shows the semiconductor device in the form of chips, and FIG. 7 shows the semiconductor device in the form of a wafer. In the first embodiment, a plurality of chip-shaped semiconductor devices (FIG. 3) are manufactured from one wafer-shaped semiconductor device (FIG. 7).

[0071] <2> Second embodiment The wafer W and the manufacturing method thereof according to the second embodiment will be described below.

[0072] <2-1> Overall structure of wafer W The overall configuration of the semiconductor device constituting the wafer W according to the second embodiment is the same as that of the first embodiment. That is, the semiconductor device constituting the wafer W according to the second embodiment is a nonvolatile semiconductor device, such as a NAND flash memory. Furthermore, the semiconductor device constituting the wafer W according to the second embodiment includes, for example, a memory cell array 10, a row decoder 11, a sense amplifier 12, and a sequencer 13, similar to the first embodiment (see FIG. 1).

[0073] <2-2> Circuit configuration of memory cell array 10 The electrical configuration of the memory cell array 10 constituting the wafer W according to the second embodiment is the same as that of the first embodiment.

[0074] In the following description of the configuration of the second embodiment, the description overlapping with the configuration of the first embodiment will be omitted. In the following description, the same reference numerals will be used to designate components having substantially the same functions and configurations as those in the first embodiment.

[0075] <2-3> Wafer structure An example of the structure of the wafer W in the second embodiment will be described below.

[0076] In the drawings referred to below, hatching is appropriately added to the plan views to make the drawings easier to see. The hatching added to the plan views does not necessarily relate to the materials or properties of the components to which the hatching is added. In the cross-sectional views, components such as insulating layers (interlayer insulating films), wiring, and contacts are appropriately omitted to make the drawings easier to see.

[0077] 8 is a schematic perspective view showing the structure of a wafer W according to the second embodiment. The wafer W includes a circuit wafer W3, an array wafer W4 bonded to the circuit wafer W3, and a plurality of metal pads 138a, 138b, 141a, and 141b provided on the bonding surfaces of the circuit wafer W3 and the array wafer W4 to electrically connect the circuit wafer W3 and the array wafer W4. The metal pads 138a and 138b are examples of "third pads," and the metal pads 141a and 141b are examples of "fourth pads."

[0078] The circuit wafer W3 includes a plurality of circuit chips 100A, each having a logic circuit. As shown in FIG. 8, the plurality of circuit chips 100A are arranged along the X and Y directions in the XY plane (within the wafer surface). Alternatively, the plurality of circuit chips 100A may be arranged substantially radially from the center of the wafer in a plan view from the Z direction. For convenience of explanation, FIG. 8 shows an example in which seven circuit chips 100A are arranged on the circuit wafer W3, but in this embodiment, the number of circuit chips 100A on the circuit wafer W3 is not limited to this. The circuit wafer W3 is an example of a "third wafer," and the circuit chips 100A are an example of a "first unit." The circuit wafer W3 is also called a "CMOS wafer."

[0079] The array wafer W4 includes multiple array chips 200A, each having a memory cell array 10. The array chips 200A are provided corresponding to the circuit chips 100A. As shown in FIG. 8, the multiple array chips 200A are arranged along the X and Y directions in the XY plane (within the wafer surface). Alternatively, the multiple array chips 200A may be arranged radially from the center of the wafer in a plan view from the Z direction. For convenience of explanation, FIG. 8 shows an example in which seven array chips 200A are provided on the array wafer W4. However, in this embodiment, the number of array chips 200A on the array wafer W4 is not limited to this. The array wafer W4 is an example of a "fourth wafer," and the array chips 200A are an example of a "second unit." The array wafer W4 is also called a "memory wafer."

[0080] FIG. 9 is a cross-sectional view taken along line FF in FIG. 8. FIG. 9 shows a wafer in which a circuit wafer W3 and an array wafer W4 are bonded together. FIG. 9 also shows the array chips 200A and circuit chips 100A arranged in the X direction in FIG. 8. In the following description, as shown in FIG. 9, of the multiple array chips 200A arranged in the X direction, the array chip 200A on the center side of the wafer (-X direction) will be referred to as array chip 200A1, and the array chip 200A on the edge side of the wafer (+X direction) will be referred to as array chip 200A2. Similarly, of the multiple circuit chips 100A arranged in the X direction, the circuit chip 100A on the center side of the wafer (-X direction) will be referred to as circuit chip 100A1, and the circuit chip 100A on the edge side of the wafer (+X direction) will be referred to as circuit chip 100A2. The array chip 200A1 is an example of a "fifth unit," and the array chip 200A2 is an example of a "sixth unit." The circuit chip 100A1 is an example of a "third unit," and the circuit chip 100A2 is an example of a "fourth unit."

[0081] In the second embodiment, the array chip 200A1 and the array chip 200A2 do not have to be adjacent to each other, for example, another array chip may be interposed between the array chip 200A1 and the array chip 200A2. Similarly, the circuit chip 100A1 and the circuit chip 100A2 do not have to be adjacent to each other, for example, another circuit chip may be interposed between the circuit chip 100A1 and the circuit chip 100A2.

[0082] Like the semiconductor device of the first embodiment, each array chip 200A includes a memory cell array 10 including a plurality of memory cells, an insulating film 52 on the memory cell array 10, and an interlayer insulating film 54 below the memory cell array 10. The insulating film 52 is, for example, a silicon oxide film or a silicon nitride film. The interlayer insulating film 54 is, for example, a silicon oxide film or a laminated film including a silicon oxide film and another insulating film.

[0083] The configuration of each array chip 200A is the same as that of the first embodiment, and therefore detailed description will be omitted below.

[0084] Each circuit chip 100A is provided below an array chip 200A. The symbol S indicates the bonding surface between the array chip 200A and the circuit chip 100A. The bonding surface S is an example of a "first bonding surface." Like the semiconductor device of the first embodiment, the circuit chip 100 includes an interlayer insulating film 53 and a substrate 15 below the interlayer insulating film 53.

[0085] The configuration of each circuit chip 100A is the same as that of the first embodiment except for the wiring layers 136a and 136b, via plugs 137a and 137b, and metal pads 138a and 138b. Therefore, in the following, a description of the configuration other than the wiring layers 136a and 136b, via plugs 137a and 137b, and metal pads 138a and 138b will be omitted.

[0086] The circuit chip 100A1 is provided on the wiring layer 35. The circuit chip 100A1 includes a wiring layer 136a including a plurality of wirings, via plugs 137a provided on the wiring layer 136a, and metal pads 138a provided on the via plugs 137a. The wiring layer 136a may be made of, for example, W (tungsten). The wiring layer 136a is an example of a "third wiring." The via plugs 137a may be made of, for example, Cu (copper) or W (tungsten). The via plugs 137a are an example of a "third via." The metal pads 138a are, for example, a Cu (copper) layer or an Al (aluminum) layer. The metal pads 138a are an example of a "third pad." The circuit chip 100A1 functions as a control circuit (logic circuit) that controls the operation of the array chip 200A1. As in the first embodiment, this control circuit is composed of a transistor 31 and the like, and is electrically connected to the metal pads 138a.

[0087] The circuit chip 100A2 is provided on the wiring layer 35 and includes a wiring layer 136b including a plurality of wirings, via plugs 137b provided on the wiring layer 136b, and metal pads 138b provided on these via plugs 137b. The wiring layer 136b may be made of, for example, W (tungsten). The wiring layer 136b is an example of a "third wiring." The via plugs 137b may be made of, for example, Cu (copper) or W (tungsten). The via plugs 137b are an example of a "third via." The metal pads 138b are, for example, a Cu (copper) layer or an Al (aluminum) layer. The metal pads 138b are an example of a "third pad." The circuit chip 100A2 functions as a control circuit (logic circuit) that controls the operation of the array chip 200A2. As in the first embodiment, this control circuit is composed of a transistor 31 and the like, and is electrically connected to the metal pads 138b.

[0088] The wiring layers 136a and 136b are provided between the logic circuit and the metal pads 138a and 138b in the Z direction, and electrically connect the logic circuit and the metal pads 138a and 138b.

[0089] The via plugs 137a and 137b are provided on the wiring layers 136a and 136b, and the via plugs 137a and 137b connect the wiring layers 136a and 136b to the metal pads 138a and 138b, respectively.

[0090] The metal pads 138a and 138b are provided on a bonding surface S between the circuit wafer W3 and the array wafer W4. The metal pads 138a and 138b electrically connect the logic circuits included in the circuit chips 100A1 and 100A2 to the memory cell arrays 10 included in the array chips 200A1 and 200A2.

[0091] As in the first embodiment, each circuit chip 100A may include at least one dummy pad 38A provided above the transistor 31. In this case, the dummy pad 38A is provided on the bonding surface S, similar to the metal pad 38, but is not electrically connected to the transistor 31.

[0092] Next, the positional relationship between the wiring layers 136a and 136b and the via plugs 137a and 137b in the wafer W of the second embodiment will be described.

[0093] FIG. 10A is a cross-sectional view showing the structure of the vicinity of the bonding surface S of each of the circuit chips 100A1 and 100A2.

[0094] As shown in FIG. 10A , in the wafer W of the second embodiment, the relative positions in the X direction of the via plugs 137 a and 137 b on the wiring layers 136 a and 136 b differ between the circuit chips 100A1 and 100A2. That is, the position in the X direction of the via plug 137 a on the wiring layer 136 a included in the circuit chip 100A1 differs from the position in the X direction of the via plug 137 b on the wiring layer 136 b included in the circuit chip 100A2. Note that while FIG. 10A shows the circuit chips 100A1 and 100A2 arranged in the X direction, this embodiment also applies to circuit chips arranged in the Y direction. That is, in the wafer W of the second embodiment, the relative positions in the Y direction of the via plugs on the wiring layers included in the circuit chips may differ between the circuit chips arranged in the Y direction. Naturally, the same applies to circuit chips arranged in a direction at a certain angle from the X direction or the Y direction.

[0095] The wafer W of the second embodiment is a wafer in which a circuit wafer W3 and an array wafer W4 are bonded together. The manufacturing method involves manufacturing the circuit wafer W3 and the array wafer W4 separately and then bonding them together at the bonding surface S. Specifically, the circuit wafer W3 including a plurality of circuit chips 100A (e.g., circuit chips 100A1 and 100A2) is bonded to the array wafer W4 including a plurality of array chips 200A (e.g., array chips 200A1 and 200A2) (see FIG. 11). During this bonding, warpage frequently occurs in the array wafer W4. This warpage is particularly likely to occur near the edge of the wafer.

[0096] Specifically, the array wafer W4 warps toward the center of the array wafer W4 in the direction in which the word lines WL extend (i.e., the X direction), and warps toward the periphery in the direction perpendicular to the direction in which the word lines WL extend (i.e., the Y direction). When an attempt is made to bond an array wafer W4 with such warpage to a circuit wafer W3, the positions of the metal pads on the circuit wafer W3 appear to be misaligned with the positions of the corresponding metal pads on the array wafer W4, as shown in Figure 12. The arrows in Figure 12 indicate the direction in which the metal pads on the circuit wafer W3 are misaligned relative to the metal pads on the array wafer W4 due to the warpage of the array wafer W4. The amount of misalignment of the metal pads on the circuit wafer W3 increases toward the periphery.

[0097] When the array wafer W4 warps in the X and Y directions, a misalignment occurs in the X and / or Y directions between the actual position of the array chip 100A2 provided on the edge side of the wafer and its original position. When such a misalignment occurs, the contact area between the metal pads 138b and 141b becomes insufficient, which may result in insufficient bonding.

[0098] Therefore, in the wafer W of the second embodiment, so-called "MAG correction" is performed on the position of the via plug 137b of the circuit chip 100A, taking into account the amount of warpage of the array wafer W4 in both the X and Y directions. When forming the metal pad 138b on this via plug 137b, the position of the metal pad 138b is corrected based on the position of the via plug 137b (not "MAG correction," but shift correction, which moves the metal pad 138b by a predetermined shift amount independent of the position in the X and Y directions, or rotation correction, which rotates the metal pad 138b by a predetermined angle around the center of the substrate). This allows the position of the metal pad 138b to take into account the amount of warpage of the array wafer W4 in both the X and Y directions. As a result, poor bonding between the metal pads 138b and 141b can be prevented.

[0099] Among the circuit chips 100A, the circuit chip 100A1 located toward the center of the wafer has almost no (or only a small) warpage of the array wafer W4, so poor contact between the metal pads 138a and 141a hardly occurs. However, as described above, in the circuit chip 100A2 located toward the end of the wafer in both the X and Y directions, misalignment occurs between the metal pads 138b and 141b in the X and Y directions. Therefore, in the second embodiment, MAG correction is performed on the via plug 137b of the circuit chip 100A1 during the manufacturing stage of the circuit wafer W3, taking into account the amount of warpage of the array wafer W4 in both the X and Y directions. Specifically, because the array wafer W4 warps toward the center of the array wafer W4 in the X direction (the −X direction in FIG. 10A), the position of the corresponding metal pad 141a of the array chip 200A2 also shifts toward the center (the −X direction). Therefore, in the MAG correction for the via plug 137b, the X-direction position of the via plug 137b of the circuit chip is changed toward the center of the array wafer W4 (the -X direction in FIG. 10A). On the other hand, in the Y-direction, the array wafer W4 warps toward the periphery, so the position of the corresponding metal pad 141a of the array chip 200A2 also shifts toward the periphery. Therefore, in the MAG correction for the via plug 137b, the Y-direction position of the via plug 137b of the circuit chip is changed toward the periphery (Y direction) of the array wafer W4.

[0100] 13 is an enlarged plan view of the wiring layer 136b of the circuit wafer and the vicinity of the via plug 137b to explain the MAG correction for the via plug 137b. As described above, in the Y direction, the position of the array chip 200A2 (i.e., the position of the via plug 42) shifts toward the Y direction (outer periphery) due to the warpage of the array wafer W4. Therefore, as shown in FIG. 13, the Y direction position of the corresponding via plug 137b is shifted toward the outer periphery (Y direction) by an amount corresponding to the expected amount of warpage of the array wafer W4 in the Y direction. The X direction position of the via plug 137b is also shifted in a similar manner.

[0101] Then, the metal pad 138b is formed so as to correspond to the via plug 137b whose position has been adjusted by this MAG correction, and as a result, a sufficient contact area between the metal pads 138b and 141b is ensured, preventing poor bonding.

[0102] However, if the dimensions of the wiring layer 136b remain the same as before, when the position of the via plug 137b is adjusted by MAG correction, the original positional relationship with the wiring layer 136b will be shifted, resulting in poor contact between the via plug 137b and the wiring layer 136b.

[0103] Therefore, in the wafer W of the second embodiment, the dimensions of the wiring layer 136b of the circuit chip 100A2 are adjusted in anticipation of the warpage of the array wafer W4 in the X and Y directions (i.e., the movement direction and movement amount of the via plug 137b adjusted by MAG correction). Specifically, as shown in FIG. 10A , for example, in the case of warpage in the X direction of the array wafer W4, as described above, the via plug 137b is moved toward the wafer center (−X direction) to match the position of the via plug 42, and the dimension of the wiring layer 136b in the −X direction is increased by an amount equal to or greater than the movement amount of the via plug 137b. That is, when the via plug 137b moves in the −X direction, the dimension of the wiring layer 136b in the −X direction is increased. On the other hand, in the case of warpage in the Y direction of the array wafer W4, the via plug 137b is corrected to move toward the outer periphery, and therefore the dimension of the wiring layer 136b in the Y direction is increased.

[0104] 10A, in the wafer W having the above-described configuration, the position of the via plug 137a on the wiring layer 136a in the X direction or Y direction (X direction in FIG. 10A) differs from the position of the via plug 137b on the wiring layer 136b in the X direction or Y direction (X direction in FIG. 10A). That is, the relative positions of the via plugs 137a and 137b on the wiring layers 136a and 136b in the X direction or Y direction (X direction in FIG. 10A) differ between the circuit chip 100A1 and the circuit chip 100A2. In other words, within the plane of the circuit wafer W3, the relative positions of the wiring layer 136a and the via plug 137a on the wafer center side differ from the relative positions of the wiring layer 136b and the via plug 137b on the wafer edge side.

[0105] As described above, in the second embodiment, MAG correction is performed on a circuit chip (e.g., the circuit chip 100A2) on the end side of the array wafer W4 where warpage occurs. Therefore, the position of the corresponding via plug (via plug 137b) is different from that of a circuit chip (e.g., the circuit chip 100A1) that has not been subjected to MAG correction. For example, as shown in FIG. 10A, in the circuit chip 100A1 that has not been subjected to MAG correction, the center of the X direction of the wiring layer 136a and the central axis of the via plug 137a are approximately aligned, whereas in the circuit chip 100A2 that has been subjected to MAG correction, the center of the X direction of the wiring layer 136b and the central axis of the via plug 137b are different. That is, the wafer W of the second embodiment is characterized by a different positional relationship between the wiring layer 136 and the via plug 137 within the same wafer surface.

[0106] In the second embodiment, the via plug 137b and the via plug 42 may be provided at overlapping positions in a plan view from the Z direction. This can further enhance the integration of each element in the wafer and further suppress defects in the vicinity of the bonding surface S.

[0107] Furthermore, in the second embodiment, the contact area between the metal pads 138b and 141b may be substantially the same as the area of ​​the bonding surface S between the metal pads 138b and 141b. In other words, it is preferable that the metal pads 138b and 141b are bonded together without any misalignment in the X and / or Y directions when viewed from above in the Z direction.

[0108] <2-4> Modification of the second embodiment A modified example of the second embodiment will be described below. Note that the configuration of the circuit chip 200A in this modified example is the same as that in the first embodiment, and therefore detailed description will be omitted below.

[0109] In the second embodiment described above, as shown in FIG. 10A, the dimensions of the wiring layer 136b are adjusted in accordance with the MAG correction performed on the circuit chip 100A2. In this modification, a similar measure is applied to the array chip 200A2. That is, so-called "MAG correction" is performed on the positions of the via plugs 142b of the array chip 200A2. When forming the metal pads 141b on the via plugs 142b, the positions of the metal pads 141b are corrected based on the positions of the via plugs 142b (not "MAG correction," but shift correction, which moves the metal pads 141b by a predetermined shift amount independent of their positions in the X and Y directions, or rotation correction, which rotates the metal pads by a predetermined angle around the substrate center). This allows the position of the metal pads 141b to take into account the warpage of the circuit wafer W3 in both the X and Y directions. As a result, poor bonding between the metal pads 138b and 141b can be prevented.

[0110] The positional relationship between the wiring layers 143a and 143b and the via plugs 142a and 142b in this modification will be described below.

[0111] FIG. 10B is a cross-sectional view showing the structure in the vicinity of the bonding surface S of each of the array chips 200A1 and 200A2.

[0112] As shown in FIG. 10B , in this modification, the relative positions in the X direction of the via plugs 142a and 142b on the wiring layers 143a and 143b differ between the array chip 200A1 and the array chip 200A2. That is, the position in the X direction of the via plug 142a under the wiring layer 143a included in the array chip 200A1 differs from the position in the X direction of the via plug 142b under the wiring layer 143b included in the array chip 200A2. The wiring layers 143a and 143b are examples of “fourth wirings.” The via plugs 142a and 142b are examples of “fourth vias.” Note that FIG. 10B illustrates a case in which the array chips 200A1 and 200A2 are arranged side by side in the X direction, but this modification can also be applied to array chips arranged side by side in the Y direction. That is, in this modification, the relative positions in the Y direction of the via plugs on the wiring layers included in the array chips may differ between array chips arranged side by side in the Y direction.

[0113] In this modification, MAG correction is performed as in the second embodiment, but it differs from the second embodiment in that the target of correction is the array chip 200A2. Specifically, as shown in FIG. 10B , for example, in the case of warpage of the circuit wafer W3 in the X direction, the via plug 142b is moved toward the wafer center (−X direction) to match the position of the via plug 37, and the dimension of the wiring layer 143b in the −X direction is increased by an amount equal to or greater than the amount of movement of the via plug 142b. In other words, when the via plug 142b moves in the −X direction, the dimension of the wiring layer 143b in the −X direction is increased. On the other hand, in the case of warpage of the circuit wafer W3 in the Y direction, the via plug 142b is corrected to move toward the outer periphery, and the dimension of the wiring layer 143b in the Y direction is increased.

[0114] 10B, the position of the via plug 142a in the X or Y direction (X direction in FIG. 10B) under the wiring layer 143a differs from the position of the via plug 142b in the X or Y direction (X direction in FIG. 10B) under the wiring layer 143b. That is, the relative positions of the via plugs 142a and 142b in the X or Y direction (X direction in FIG. 10B) on the wiring layers 143a and 143b differ between the array chip 200A1 and the array chip 200A2. In other words, within the plane of the array wafer W4, the relative positions of the wiring layer 143a and the via plug 142a at the center of the wafer differ from the relative positions of the wiring layer 143b and the via plug 142b at the edge of the wafer.

[0115] As described above, in this modification, MAG correction is performed on an array chip (e.g., array chip 200A2) at the end side of the circuit wafer W3 where warpage occurs. Therefore, the position of the corresponding via plug (via plug 142b) is different from that of an array chip (e.g., array chip 200A1) that has not been subjected to MAG correction. For example, as shown in FIG. 10B, in the case of the array chip 200A1 that has not been subjected to MAG correction, the center of the X direction of the wiring layer 143a and the central axis of the via plug 142a are approximately aligned, whereas in the case of the array chip 200A2 that has been subjected to MAG correction, the center of the X direction of the wiring layer 143b and the central axis of the via plug 142b are different. That is, this modification is characterized by a different positional relationship between the wiring layer 143 and the via plug 142 within the same wafer surface.

[0116] The configuration of the second embodiment and its modified examples is not limited to the case where multiple circuit chips 100A and multiple array chips 200A are arranged in the X direction as shown in Figures 9, 10A, and 10B, but can also be applied to the case where they are arranged in the Y direction.

[0117] <2-5> Manufacturing method of wafer W FIG. 11 is a cross-sectional view showing a method for manufacturing a wafer W according to the second embodiment. FIG. 11 shows an array wafer W4 including a plurality of array chips 200A and a circuit wafer W3 including a plurality of circuit chips 100A.

[0118] The orientation of the array wafer W4 in the Z direction in Fig. 11 is opposite to the orientation of the array chip 200 in Fig. 9. In the second embodiment, a wafer W is manufactured by bonding the array wafer W4 and the circuit wafer W3 together. Fig. 11 shows the array wafer W4 before its orientation is reversed for bonding, and Fig. 9 shows the array wafer W4 after its orientation is reversed for bonding and the two wafers are bonded together.

[0119] 11, symbol S2 denotes the top surface of the array wafer W4, and symbol S1 denotes the top surface of the circuit wafer W3. The array wafer W4 includes a substrate 16 provided under an insulating film 52. The substrate 16 is, for example, a semiconductor substrate such as a silicon substrate.

[0120] In this embodiment, first, as shown in FIG. 11 , a memory cell array 10, an insulating film 52, an interlayer insulating film 13, a staircase structure portion ST, and a plurality of metal pads 141 (metal pads 141a, 141b) are formed on a substrate 16 of an array wafer W2. When forming the memory cell array 10, for example, a memory cell array 10 is formed on the substrate 16 in each of a plurality of regions corresponding to an array chip 200A, each of which corresponds to a plurality of regions corresponding to a circuit chip 100A (described later). Note that the "region corresponding to the circuit chip 100A" here is an example of a "first region," and the "region corresponding to the array chip 200A" is an example of a "second region." Also, for example, a plurality of via plugs 45, a plurality of wiring layers 43, a plurality of via plugs 42, and a plurality of metal pads 141 are formed in this order on the substrate 16. The substrate 16 is an example of a "fourth wafer."

[0121] 11, an interlayer insulating film 53, a transistor 31, multiple metal pads 138a and 138b, at least one dummy pad 38A, etc. are formed on a substrate 15 of a circuit wafer W3. For example, a contact plug 33, multiple wiring layers 34, multiple wiring layers 35, multiple wiring layers 136a and 136b, multiple via plugs 137a and 137b, and multiple metal pads 138a and 138b are formed in this order on the substrate 15. The substrate 16 is an example of a "third wafer."

[0122] In the manufacturing method of the second embodiment, when forming the via plugs 137a, 137b on the wiring layers 136a, 136b, respectively, the via plug 137b corresponding to the edge of the circuit wafer W3 is positioned so as to coincide in the Z direction with the position of the via plug 42 on the array chip 200A2. The "position of the via plug 42" in this case refers to the position in the Z direction when bonding the metal pads 138a, 138b to the metal pads 141a, 141b, respectively. That is, when forming the via plugs 137a, 137b on the wiring layers 136a, 136b, respectively, the so-called "MAG correction" described above is performed. More specifically, the position of the via plug 137b on the wiring layer 136b is corrected in the X direction toward the center of the circuit wafer W3 and in the Y direction away from the center of the circuit wafer W3, and then the via plug 137b is formed. This allows the via plugs 137b in the circuit chip 100A2 and the via plugs 42 in the array chip 200A2 to be aligned in the Z direction when the circuit wafer W3 and the array wafer W4 are bonded together.

[0123] Thereafter, the circuit wafer W3 and the array wafer W4 are bonded together. The circuit wafer W3 and the array wafer W4 may be bonded together by mechanical pressure. This bonds the interlayer insulating film 13 and the interlayer insulating film 53 together.

[0124] Next, the bonded circuit wafer W3 and array wafer W4 are annealed, for example, at 400° C. As a result, the metal pads 141a and 138a, and the metal pads 141b and 138b are bonded at the bonding surface S.

[0125] 9 shows the boundary between the interlayer insulating film 13 and the interlayer insulating film 53, and the boundary between the metal pad 141a and the metal pad 138a, but these boundaries generally become invisible after the annealing. However, the positions of these boundaries can be estimated by detecting the inclination of the side surface of the metal pad 141a or the side surface of the metal pad 138a, for example.

[0126] Although several embodiments have been described above, the embodiments are not limited to the above examples. For example, the memory stacked film may be a ferroelectric film included in an FeFET (Ferroelectric FET) memory that stores data based on the direction of polarization. The ferroelectric film is formed of, for example, hafnium oxide.

[0127] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, as well as within the scope of the invention described in the claims and their equivalents. [Explanation of symbols]

[0128] 1... semiconductor device, 2... memory controller, 10... memory cell array, 11... row decoder, 12... sense amplifier, 13... sequencer, 15, 16... substrate, 32... gate electrode, 33... contact plug, 34, 35, 36, 43, 136a, 136b, 143a, 143b... wiring layer, 37, 42, 137a, 137b, 142a, 142b... via plug, 38, 41, 138a, 138b, 141a, 141b... metal pad, 38A... dummy Pad, 52...insulating film, 54...interlayer insulating film, 61...insulating layer, 60...memory film, 65...semiconductor body, 66...core, BL...bit line, BLK...block, CL...columnar portion, S...bonding surface, SL...source line, STR...string, W...wafer, W1, W3...circuit wafer, W2, W4...array wafer, WL...word line, 100, 100A, 100A1, 100A2...circuit chip, 200, 200A, 200A1, 200A2...array chip

Claims

1. A first laminate; a second laminate bonded to the first laminate, The first laminate is A first wiring; a first pad provided on a first bonding surface where the first laminate and the second laminate are bonded together, the first pad being electrically connected to the first wiring through a first via; The second laminate is A second wiring; a second pad electrically connected to the second wiring through a second via and joined to the first pad on the first bonding surface; a direction from the first stack toward the second stack is defined as a first direction, a direction intersecting the first direction is defined as a second direction, and a direction intersecting the first direction and the second direction is defined as a third direction; When the dimension of the first pad in the third direction is PX1, the dimension of the first pad in the second direction is PY1, the dimension of the second pad in the third direction is PX2, and the dimension of the second pad in the second direction is PY2, The dimensions of the first pad and the second pad satisfy at least one of the following formulas (1) and (2): When the second laminate has a warp in the central direction of the second laminate in the third direction, the dimension of the first pad in the central direction of the second laminate is larger in PX1, and when the second laminate has a warp in the outer circumferential direction of the second laminate in the second direction, the dimension of the first pad in the outer circumferential direction of the second laminate is larger in PY1. Semiconductor device. PX1>PY1...(1) PY2>PX2...(2)

2. At least one of the first pad and the second pad has a substantially rectangular shape in a plan view from the first direction. The semiconductor device according to claim 1 .

3. The dimensions of the first pad and the second pad satisfy at least one of the following formulas (3) and (4):

3. The semiconductor device according to claim 1. PX1>PX2...(3) PY2>PY1...(4)

4. The first laminate further comprises: A substrate; a logic circuit provided on the substrate; a plurality of first dummy pads disposed above the logic circuit, provided on the first bonding surface, and not electrically connected to the logic circuit; Equipped with The second laminate further comprises: a plurality of second dummy pads provided on the plurality of first dummy pads; a memory cell array provided above the plurality of second dummy pads; The semiconductor device according to any one of claims 1 to 3.

5. When the first laminate has a warp in the central direction of the first laminate in the third direction, the dimension of the second pad in the central direction of the first laminate in PX2 is larger, and when the first laminate has a warp in the outer circumferential direction of the first laminate in the second direction, the dimension of the second pad in the outer circumferential direction of the first laminate in PY2 is larger. The semiconductor device according to claim 1.

Images