Semiconductor Devices

Abstract

To provide a reliable semiconductor device including a thin film transistor with the stable electric characteristics.SOLUTION: In a manufacturing method for a semiconductor device including a thin film transistor whose semiconductor layer including a channel formation region is an oxide semiconductor film, an oxide insulating film to serve as a protective film is formed in contact with the oxide semiconductor layer and then heat treatment (heat treatment for dehydration or dehydrogenation) for reducing moisture as the impurities is performed. This can reduce the impurities such as moisture existing in a source electrode layer, a drain electrode layer, a gate insulating layer, and the oxide semiconductor film and moreover at the boundary between the oxide semiconductor film and a film above or below and in contact with the oxide semiconductor film.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device including an oxide semiconductor and a manufacturing method thereof.

[0002] In this specification, a semiconductor device is a device that can function by utilizing semiconductor characteristics. The term "semiconductor device" refers to devices in general, and electro-optical devices, semiconductor circuits, and electronic equipment are all semiconductor devices. [Background technology]

[0003] In recent years, semiconductor thin films (thickness of several to several hundred nm) formed on substrates with insulating surfaces have been used. The technology for constructing thin film transistors (TFTs) is attracting attention. It is widely used in electronic devices such as ICs and electro-optical devices, especially in switches for image display devices. Indium oxide, an example of a metal oxide, is being developed as a semiconductor device. It is used as a transparent electrode material required for liquid crystal displays and other devices.

[0004] Some metal oxides exhibit semiconducting properties. Metal oxides that exhibit semiconducting properties include: Examples of such oxides include tungsten oxide, tin oxide, indium oxide, and zinc oxide. Thin film transistors using metal oxides with excellent semiconductor properties as the channel formation region are already known. (Patent Documents 1 to 4, Non-Patent Document 1).

[0005] Incidentally, metal oxides include not only single-component oxides but also multi-component oxides. For example, InGaO3(ZnO) with homologous phase m (m: natural number) is In, Ga, and Zn It is known as a multi-component oxide semiconductor (also called In-Ga-Zn-O oxide) having the following characteristics: (Non-Patent Documents 2 to 4).

[0006] In addition, oxide semiconductors composed of the above-mentioned In-Ga-Zn-O-based oxides are used as thin film transistors. It has been confirmed that this can be applied to the channel layer of a transistor (Patent Document 5, Non-Patent Document 5 and 6). [Prior art documents] [Patent documents]

[0007] [Patent Document 1] Japanese Patent Application Publication No. 1988-1986 [Patent Document 2] Japanese Patent Application Publication No. 8-264794 [Patent Document 3] Special Publication No. 11-505377 [Patent Document 4] Japanese Patent Application Laid-Open No. 2000-150900 [Patent Document 5] Japanese Patent Application Laid-Open No. 2004-103957 [Non-patent literature]

[0008] [Non-Patent Document 1] MW Prins, KO Grosse-Holz, G. Muller, JFM Cillessen, JB Giesbers, RP Weening, and RM Wolf, "A ferroelectric transparent thin-film transistor", Appl. Phys. Lett., 17 June 1996, Vol.68 p.3650-3652 [Non-patent document 2] M. Nakamura, N. Kimizuka, and T. Mohri, "The Phase Relations in the In2O3-Ga2ZnO4-ZnO System at 1350℃", J. Solid State Chem., 1991, Vol.93, p.298-315 [Non-patent document 3] N. Kimizuka, M. Isobe, and M. Nakamura, “Syntheses and Single-Crystal Data of Homologous Compounds, In2O3(ZnO)m(m=3,4, and 5), InGaO3(ZnO)3, and Ga2O3(ZnO)m(m=7,8,9, and 16) in the In2O3-ZnGa2O4-ZnO System”, J. Solid State Chem., 1995, Vol.116, p.170-178 [Non-patent document 4] Masaaki Nakamura, Noboru Kimizuka, Takahiko Mohri, Mitsumasa Isobe, "Synthesis and Crystal Structure of Homologous Phase, InFeO3(ZnO)m (m: natural number) and Its Isomorphic Compounds," Solid State Physics, 1993, Vol. 28, No. 5, pp. 317-327 [Non-patent document 5] K. Nomura, H. Ohta, K. Ueda, T. Kamiya, M. Hirano, and H. Hosono, "Thin-film transistor fabricated in single-crystalline transparent oxide semiconductor", SCIENCE, 2003, Vol.300, p.1269-1272 [Non-patent document 6] K. Nomura, H. Ohta, A. Takagi, T. Kamiya, M. Hirano, and H. Hosono, "Room-temperature fabrication of transparent flexible thin-film transistors using amorphous oxide semiconductors", NATURE, 2004, Vol.432 p.488-492 Summary of the Invention [Problem to be solved by the invention]

[0009] To manufacture a highly reliable semiconductor device having a thin film transistor with stable electrical characteristics One of the challenges is to [Means for solving the problem]

[0010] Semiconductor device having a thin film transistor in which a semiconductor layer including a channel formation region is an oxide semiconductor film In a method for manufacturing a semiconductor device, the purity of an oxide semiconductor film is increased and impurities such as moisture are reduced. In addition, heat treatment for dehydration or dehydrogenation is performed on the oxide semiconductor film. Not only in the source electrode layer, drain electrode layer and gate insulating layer, but also in the Impurities are reduced by heat treatment, and the boundary between the oxide semiconductor film and films provided above and below it is Impurities such as moisture present on the surface are reduced by heat treatment.

[0011] An oxide semiconductor layer was formed, and an oxide insulating film serving as a protective film was formed in contact with the oxide semiconductor layer. After that, a heat treatment is carried out for dehydration or dehydrogenation. The heat treatment is carried out in the presence of nitrogen, oxygen or dilute 200℃ or higher under an inert gas atmosphere (argon, helium, etc.) or reduced pressure A heat treatment is carried out at 700°C or less, preferably at 350°C or more but less than the distortion point of the substrate, and the source electrode The moisture content of the oxide semiconductor film is reduced. By this heat treatment, an oxide insulating film that serves as a protective film in contact with the oxide semiconductor layer is formed. It is possible to recover plasma damage that the oxide semiconductor layer receives when the oxide semiconductor layer is formed. By carrying out this heat treatment, it is possible to reduce variations in the electrical characteristics of the thin film transistors. This can be done.

[0012] The oxide semiconductor film is made by reducing the moisture content in the film through heat treatment and recovering from plasma damage. By using a conductor layer, the electrical characteristics of thin-film transistors can be improved, and mass production and high performance can be achieved. A thin film transistor that has both is realized.

[0013] In this specification, an inert gas atmosphere of nitrogen, oxygen, or a rare gas (argon, helium, etc.) Heat treatment under atmospheric pressure or reduced pressure is called heat treatment for dehydration or dehydrogenation. In the detailed description, only the process of desorption as H2 by this heat treatment is called dehydrogenation. It is not necessary to use the term "dehydration" or "dehydrogenation" to refer to the elimination of H, OH, etc. I will call.

[0014] The oxide insulating film that is in contact with the oxide semiconductor layer and serves as a protective film is resistant to moisture, hydrogen ions, and O H - An inorganic insulating film is used to block impurities such as silicon dioxide and oxynitride. A silicon film, an aluminum oxide film, or an aluminum oxynitride film is used. A silicon nitride film or an aluminum nitride film may be laminated on the film.

[0015] One embodiment of the present invention disclosed in this specification is a method for forming a gate electrode layer including a heat-resistant conductive material, A gate insulating layer is formed over the gate electrode layer, an oxide semiconductor layer is formed over the gate insulating layer, and an oxide semiconductor layer is formed over the gate insulating layer. forming a source electrode layer and a drain electrode layer containing a heat-resistant conductive material on the oxide semiconductor layer; The connection electrode layer is formed in the same process as the gate electrode layer or the source and drain electrode layers. On the gate insulating layer, the oxide semiconductor layer, the connection electrode layer, the source electrode layer, and the drain electrode layer An oxide insulating film is formed in contact with a part of the oxide semiconductor layer. The present invention relates to a method for manufacturing a semiconductor device, characterized in that a compound semiconductor layer is dehydrated or dehydrogenated.

[0016] The above configuration solves at least one of the above problems.

[0017] Another embodiment of the present invention is a method for forming a gate electrode including a heat-resistant conductive material on a substrate having an insulating surface. a gate electrode layer is formed on the gate electrode layer, a gate insulating layer is formed on the gate insulating layer, and an oxide semiconductor is formed on the gate insulating layer. A conductor layer is formed, and a source electrode layer and a drain electrode layer containing a heat-resistant conductive material are formed on the oxide semiconductor layer. a connection electrode layer, a gate electrode layer, or a source electrode layer and a drain electrode layer; The gate insulating layer, the oxide semiconductor layer, the connection electrode layer, the source electrode layer, and an oxide insulating film in contact with a part of the oxide semiconductor layer is formed over the drain electrode layer; After forming the oxide semiconductor layer, the oxide semiconductor layer is dehydrated or dehydrogenated to remove part of the oxide insulating film. The first contact hole reaches the source electrode layer, and the third contact hole reaches both ends of the connection electrode layer. The first contact hole and the fourth contact hole are formed, and an oxide insulating film and a gate insulating film are formed. A portion of the border layer is removed to form a second contact hole reaching the gate electrode layer, and an oxide a source wiring connected to the source electrode layer through a first contact hole on the insulating film; The gate electrode layer is connected to the second contact hole, and the third contact hole is connected to the second contact hole. a first gate wiring connected to the connection electrode layer and a fourth contact hole connected to the connection electrode layer; and forming a second gate wiring connected to the first gate electrode. .

[0018] Another embodiment of the present invention is a method for forming a gate electrode including a heat-resistant conductive material on a substrate having an insulating surface. a gate electrode layer is formed on the gate electrode layer, a gate insulating layer is formed on the gate insulating layer, and an oxide semiconductor is formed on the gate insulating layer. A conductor layer is formed, and a source electrode layer and a drain electrode layer containing a heat-resistant conductive material are formed on the oxide semiconductor layer. a connection electrode layer, a gate electrode layer, or a source electrode layer and a drain electrode layer; The gate insulating layer, the oxide semiconductor layer, the connection electrode layer, the source electrode layer, and an oxide insulating film in contact with a part of the oxide semiconductor layer is formed over the drain electrode layer; After forming the oxide semiconductor layer, the oxide semiconductor layer is dehydrated or dehydrogenated to remove part of the oxide insulating film. The first contact hole reaches the source electrode layer, and the third contact hole reaches both ends of the connection electrode layer. The first contact hole and the fourth contact hole are formed, and an oxide insulating film and a gate insulating film are formed. A portion of the border layer is removed to form a second contact hole reaching the gate electrode layer, and an oxide On the insulating film, a third contact is formed, which is connected to the source electrode layer through the first contact hole. a first source wiring connected to the connection electrode layer through a hole; a second source wiring connected to the connection electrode layer through a second contact hole; A method for manufacturing a semiconductor device, characterized in that a gate wiring connected to an electrode layer is formed. .

[0019] In the above-described manufacturing method, the dehydration or dehydrogenation is carried out in a nitrogen atmosphere, an oxygen atmosphere, or The heating is preferably performed in a rare gas atmosphere or under reduced pressure. It is more preferable to heat the substrate at a temperature lower than the strain point of the substrate. preferable.

[0020] In addition, titanium, tantalum, tungsten, molybdenum, and chromium are used as heat-resistant conductive materials. , neodymium, scandium, or an alloy containing the element, or It is preferable to use a single layer or a laminate of nitrides containing the above. The wiring and gate wiring are made of a low-resistance conductive material having a resistivity lower than that of the source electrode layer and the drain electrode layer. It is preferable to form the insulating film using a low-resistance conductive material such as aluminum or It is preferable to use copper.

[0021] In another embodiment of the present invention, a semiconductor device is formed over a substrate having an insulating surface using a first mask. a gate electrode layer formed on the gate electrode layer; a gate insulating layer formed on the gate electrode layer; and a second mask formed on the gate insulating layer. an oxide semiconductor layer formed using a third mask; and a second mask formed over the oxide semiconductor layer. The source electrode layer and the drain electrode layer are formed by the gate electrode layer or the source electrode layer and the drain electrode layer. The connection electrode layer is formed on the same layer as the gate electrode layer, and the gate insulating layer, oxide semiconductor layer, and source an oxide insulating film covering the electrode layer and the drain electrode layer and in contact with a part of the oxide semiconductor layer; A gate wiring, a first source wiring, and a second source wiring are formed on the oxide insulating film using a fourth mask. and a second source wiring, the first source wiring being electrically connected to the source electrode layer and The source wiring is electrically connected to the gate electrode layer, and the first source wiring and the second source wiring are The connection electrode layer is electrically connected to the gate wiring, and the connection electrode layer overlaps the gate wiring via an oxide insulating film. The mask used here refers to a photomask.

[0022] In another embodiment of the present invention, a semiconductor device is formed over a substrate having an insulating surface using a first mask. a gate electrode layer formed on the gate electrode layer; a gate insulating layer formed on the gate electrode layer; and a second mask formed on the gate insulating layer. an oxide semiconductor layer formed using a third mask; and a second mask formed over the oxide semiconductor layer. The source electrode layer and the drain electrode layer are formed by the gate electrode layer or the source electrode layer and the drain electrode layer. The connection electrode layer is formed on the same layer as the gate electrode layer, and the gate insulating layer, oxide semiconductor layer, and source an oxide insulating film covering the electrode layer and the drain electrode layer and in contact with a part of the oxide semiconductor layer; A gate wiring, a first source wiring, and a second source wiring are formed on the oxide insulating film using a fourth mask. and a second source wiring, the first source wiring being electrically connected to the source electrode layer and The source wiring is electrically connected to the gate electrode layer, and the first source wiring and the second source wiring are The connection electrode layer is electrically connected to the gate wiring, and the connection electrode layer overlaps the gate wiring via an oxide insulating film. The mask used here refers to a photomask.

[0023] In the configuration of the semiconductor device, the gate electrode layer, the connection electrode layer, the source electrode layer, and the drain electrode layer The electrode layer is made of titanium, tantalum, tungsten, molybdenum, chromium, neodymium, scandium Elements selected from aluminum, alloys containing elements, or nitrides containing elements It is preferable to use either one of them as a single layer or a laminated layer. The source electrode layer and the drain electrode layer are preferably made of a low-resistance conductive material having a lower resistivity than the source electrode layer and the drain electrode layer. It is preferable that the material is aluminum or copper.

[0024] The oxide semiconductor used in this specification is InMO3(ZnO) m Thin (m>0) A thin film is formed, and a thin film transistor is fabricated using the thin film as an oxide semiconductor layer. However, m is not necessarily an integer. M can be selected from Ga, Fe, Ni, Mn, and Co. It denotes a selected metallic element or elements. For example, M can be Ga. In addition, there are cases where the above metal elements other than Ga are included, such as Ga and Ni or Ga and Fe. In addition to the metal element contained as M in the oxide semiconductor, impurity elements Contains Fe, Ni or other transition metal elements, or oxides of said transition metals In this specification, InMO3(ZnO) m Acids with structures represented by (m>0) Among the oxide semiconductor layers, oxide semiconductors with a structure containing Ga as M are called In-Ga-Zn-O systems. This is called an oxide semiconductor, and the thin film is also called an In-Ga-Zn-O based non-single crystal film.

[0025] In addition to the above, oxide semiconductors that can be used for the oxide semiconductor layer include In-Sn-Zn- O-based, In-Al-Zn-O-based, Sn-Ga-Zn-O-based, Al-Ga-Zn-O-based, S n-Al-Zn-O series, In-Zn-O series, Sn-Zn-O series, Al-Zn-O series, In In addition, the above oxide semiconductors can be used. The oxide semiconductor layer may contain silicon oxide. By including SiOx (X>0), the formation of an oxide semiconductor layer during the manufacturing process When a heat treatment is subsequently performed, crystallization can be suppressed. The conductor layer is preferably in an amorphous state, and may be partially crystallized.

[0026] In addition, depending on the conditions of the heat treatment or the material of the oxide semiconductor layer, the oxide semiconductor layer may become amorphous. In some cases, the crystals may change from a crystalline state to a microcrystalline or polycrystalline state.

[0027] In addition, thin film transistors are easily damaged by static electricity, so the gate wiring or source It is preferable to provide a protection circuit for protecting the driver circuit on the same substrate as the bus wiring. The circuit is preferably configured using a nonlinear element using an oxide semiconductor.

[0028] In addition, the gate insulating layer and the oxide semiconductor film are processed consecutively without being exposed to the air. It may be subjected to subsequent processing, in-situ processing, or continuous film formation. By performing the treatment continuously without causing the oxide semiconductor film to be broken, the interface between the gate insulating layer and the oxide semiconductor film is free from water and halogen. Each layer is free from contamination by atmospheric components and impurities floating in the air, such as hydrocarbons. Since an interface can be formed, the variation in thin film transistor characteristics can be reduced. Cut.

[0029] In this specification, the continuous treatment is performed from the first treatment step performed by the PCVD method or the sputtering method. During the series of processes from the first treatment step to the second treatment step using PCVD or sputtering, The environment in which the substrates are placed is always in a vacuum or This means that the temperature is controlled in an inert gas atmosphere (nitrogen atmosphere or rare gas atmosphere). By performing subsequent processing, reattachment of moisture etc. to the cleaned substrate can be avoided, and film formation etc. can be performed. The following processing can be performed.

[0030] A series of processes from the first process to the second process are carried out in the same chamber. is considered to be within the scope of continuous processing in this specification.

[0031] In addition, a series of processes from the first process to the second process are carried out in different chambers. In this case, after the first processing step is completed, the substrate is transported between chambers without being exposed to the atmosphere. The application of a second treatment is also considered to be within the scope of the continuous treatment in this specification.

[0032] Between the first and second processing steps, a substrate transfer step, an alignment step, and a slow cooling step are performed. a step of heating or cooling the substrate to a temperature required for the first step or the second step, Even if the process is performed in a continuous manner, it is still considered to be within the scope of continuous processing in this specification.

[0033] However, processes that use liquids, such as cleaning, wet etching, and resist formation, are the first If the processing step is between the first processing step and the second processing step, it does not fall within the scope of continuous processing as referred to in this specification. Let's say that doesn't happen. [Effects of the Invention]

[0034] A thin film transistor having stable electrical characteristics can be manufactured. A semiconductor device having a good and reliable thin film transistor can be manufactured. [Brief explanation of the drawings]

[0035] [Figure 1] 1A to 1C are cross-sectional views illustrating a manufacturing process according to one embodiment of the present invention. [Figure 2] 1A to 1C are plan views illustrating a manufacturing process according to one embodiment of the present invention. [Figure 3] 1A to 1C illustrate a semiconductor device according to one embodiment of the present invention. [Figure 4] 1A to 1C are cross-sectional views illustrating a manufacturing process according to one embodiment of the present invention. [Figure 5] 1A to 1C are plan views illustrating a manufacturing process according to one embodiment of the present invention. [Figure 6] 1A to 1C illustrate a semiconductor device according to one embodiment of the present invention. [Figure 7] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 8] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 9] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 10]1A to 1C are plan views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 11] 1A to 1C are plan views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 12] 1A to 1C are plan views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 13] 1A to 1C are plan views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 14] 1A to 1C illustrate a semiconductor device according to one embodiment of the present invention. [Figure 15] FIG. 1 is a cross-sectional view of an electric furnace. [Figure 16] FIG. 1 is a cross-sectional view of an electric furnace. [Figure 17] 1A to 1C illustrate a semiconductor device according to one embodiment of the present invention. [Figure 18] 1A to 1C illustrate a semiconductor device according to one embodiment of the present invention. [Figure 19] 1A to 1C illustrate a semiconductor device according to one embodiment of the present invention. [Figure 20] 1A to 1C illustrate a semiconductor device according to one embodiment of the present invention. [Figure 21] 1A to 1C illustrate a semiconductor device according to one embodiment of the present invention. [Figure 22] FIG. 1 is a block diagram illustrating a display device. [Figure 23] FIG. 2 illustrates a configuration of a signal line driver circuit. [Figure 24] FIG. 1 is a circuit diagram showing a configuration of a shift register. [Figure 25] 1A and 1B are a diagram showing an equivalent circuit of a shift register and a timing chart illustrating the operation of the shift register; [Figure 26] 1A to 1C illustrate a semiconductor device. [Figure 27] 1A to 1C illustrate a semiconductor device. [Figure 28] 1A to 1C illustrate a semiconductor device. [Figure 29] 1A and 1B are diagrams illustrating pixel equivalent circuits of a semiconductor device. [Figure 30] 1A to 1C illustrate a semiconductor device. [Figure 31]1A to 1C illustrate a semiconductor device. [Figure 32] FIG. 1 is an external view showing an example of an electronic book. [Figure 33] FIG. 1 is an external view showing an example of a television device and a digital photo frame. [Figure 34] FIG. 1 is an external view showing an example of a gaming machine. [Figure 35] FIG. 1 is an external view showing an example of a portable computer and a mobile phone. DETAILED DESCRIPTION OF THE INVENTION

[0036] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The present invention is not limited to the following description, and various modifications in form and details are possible by those skilled in the art. Furthermore, the present invention should not be construed as being limited to the description of the following embodiments. It is not something that can be done.

[0037] (Embodiment 1) FIG. 3A is a plan view of a thin film transistor 461 included in the semiconductor device, and FIG. 3A. The thin film transistor 461 is an inverted staggered type. The thin film transistor is a gate electrode layer 400 formed on a substrate 400 having an insulating surface. 01 is provided, a gate insulating layer 402 is provided on the gate electrode layer 401, and a gate insulating An oxide semiconductor layer 403 is provided on the layer 402, and a source electrode 404 is provided on the oxide semiconductor layer 403. The gate insulating layer 4 02, the oxide semiconductor layer 403, the source electrode layer 405a, and the drain electrode layer 405b An oxide insulating film 407 in contact with part of the oxide semiconductor layer 403 is provided.

[0038] In addition, the oxide insulating film 407 has a first contact hole reaching the source electrode layer 405a. 421, a second contact hole 422 reaching the gate electrode layer 401, and a connection electrode layer 4 The third contact hole 423 and the fourth contact hole 424 reach both ends of the substrate 20. In this embodiment, the source wiring and the gate wiring are formed in the same layer. Therefore, the first gate wiring 426 and the second gate wiring 427 are connected to the source wiring 425. The first gate wiring 426 and the second gate wiring 427 are formed so as to sandwich the source wiring. Electrical connection is made via a connection electrode layer 420 formed to overlap the line 425. The source wiring 425 is connected to the source electrode layer 405a through the first contact hole 421. The first gate wiring 426 is electrically connected to the second contact hole 42. 2, the first gate wiring 426 and the gate electrode layer 401 are electrically connected to each other. The second gate wiring 427 is connected to the third contact hole 423 and the fourth contact hole 424. The source wiring 425 and the second wiring 426 are electrically connected to the connection electrode layer 420 via the first wiring 424. The first gate wiring 426 and the second gate wiring 427 are arranged from the outer periphery of the oxide semiconductor layer 403 to the It extends outward.

[0039] The oxide semiconductor layer 403 is formed of an oxide insulating film that functions as a protective film in contact with the oxide semiconductor layer 403. After the formation of the insulating film 407, a heat treatment (dehydration or dehydrogenation) is performed to reduce impurities such as moisture. (heat treatment for the purpose) is carried out.

[0040] In addition to the oxide semiconductor layer 403, the gate insulating layer 402, the source electrode layer 405a, and in the drain electrode layer 405b and in contact with the oxide semiconductor layer 403 and above and below. Specifically, the interface between the gate insulating layer 402 and the oxide semiconductor layer 403 and the interface between the oxide semiconductor layer 403 and the gate insulating layer 402 are The impurities such as moisture present at the interface between the insulating film 407 and the oxide semiconductor layer 403 are reduced. The heat treatment reduces moisture and the like contained in the oxide semiconductor layer 403, thereby forming a thin film transistor. The electrical characteristics of the transistor can be improved.

[0041] In addition, the oxide insulating film 407 is formed in the oxide semiconductor layer 403 by this heat treatment. The oxide semiconductor layer 403 is repaired from plasma damage that the oxide semiconductor layer 403 receives during the treatment.

[0042] a gate electrode layer 401, a connection electrode layer 420, a source or drain electrode layer 405a, 405b preferably contains a heat-resistant conductive material. selected from the group consisting of tantalum, tungsten, molybdenum, chromium, neodymium, and scandium The material is either an element, an alloy containing the element, or a nitride containing the element. In addition, the gate electrode layer 401, the connection electrode layer 420, the source electrode layer or the drain electrode layer The layer electrode layers 405a and 405b may be made of titanium, tantalum, tungsten, molybdenum, or chromium. An element selected from the group consisting of chromium, neodymium, and scandium, or an alloy containing such an element; or For example, the first layer may be a nitride layer. The first layer is molybdenum nitride, and the second layer is tungsten. The second layer is tungsten, and the first layer is titanium nitride and the second layer is titanium. The combination should be:

[0043] In addition, the connection electrode layer 420 and the source and drain electrode layers 405a and 405b are formed of The heat-resistant conductive material may be a transparent conductive material containing indium, tin, or zinc. Oxides may also be used. For example, indium oxide (In2O3) or indium oxide silicon dioxide. It is preferable to use a zinc alloy (In2O3-SnO2, abbreviated as ITO). A conductive oxide may be used in combination with an insulating oxide such as silicon oxide.

[0044] By including an insulating oxide such as silicon oxide in the transparent conductive oxide, the transparent conductive oxide can be The crystallization of the transparent conductive oxide can be suppressed, and the amorphous structure can be obtained. By suppressing the crystallization and making the structure amorphous, the crystallization of the transparent conductive oxide can be prevented even when heat treatment is performed. Crystallization or the formation of fine crystal grains can be prevented.

[0045] a gate electrode layer 401, a connection electrode layer 420, a source or drain electrode layer 405a, By including the heat-resistant conductive material in the gate electrode layer 401, the contact The connection electrode layer 420 and the source or drain electrode layers 405a and 405b are formed of oxide insulating material. The film 407 can withstand the heat treatment that is performed after the film 407 is formed.

[0046] The source wiring 425, the first gate wiring 426, and the second gate wiring 427 are connected to the source electrode The conductive material has a lower resistivity than the drain electrode layer 405a and the drain electrode layer 405b. The source wiring 425 and the first gate wiring 426 are preferably made of aluminum or copper, and particularly aluminum or copper is preferably used. By using a low resistance conductive material for the gate wiring 426 and the second gate wiring 427, It is possible to reduce resistance, etc.

[0047] Low-resistivity conductive materials such as aluminum or copper have low heat resistance, but as mentioned above, they are resistant to oxidation. After the heat treatment after forming the insulating film, the source wiring 425, the first gate wiring 426 and the second By providing the gate wiring 427, the source wiring 425, the first gate wiring 426, and The second gate wiring 427 can be made of the low resistance conductive material as described above.

[0048] The oxide semiconductor layer 403 including the channel formation region is formed using an oxide material having semiconductor properties. Typically, an In-Ga-Zn-O based non-single crystal is used.

[0049] As shown in FIG. 3C, the first source wiring 428 and the second source wiring 429 are The gate wiring 430 is sandwiched between the contacts 430 and overlapped with the gate wiring 430. The first source line may be electrically connected to the second source line via the connecting electrode layer 420. The line 428 is electrically connected to the source electrode layer 405a through the first contact hole 421. The gate wiring 430 is connected to the gate electrode 422 through the second contact hole 422. The first source wiring 428 and the second source wiring 429 are electrically connected to the electrode layer 401. 429 are the third contact holes 423 and the fourth contact hole 424 that reach both ends of the connection electrode layer 420. Electrical connection is made to the connection electrode layer 420 through the contact hole 424. In this respect, it is similar to the thin film transistor shown in FIGS. 3(A) and 3(B) described above.

[0050] 3(D), the source electrode layer 405a is formed so as to overlap the gate wiring 430. The first source wiring 428 and the second source wiring 429 are formed on the source electrode layer 405. The first source wiring 428 may be electrically connected via a. The source electrode layer 405a is electrically connected to the source electrode layer 405b through the first contact hole 421. The second source wiring 429 is connected to the source electrode layer 405a through a third contact hole 429a. The other parts are electrically connected to the source electrode layer 405a via 490. This is similar to the thin film transistor shown in FIG.

[0051] 1(A) and 1(B) are cross-sectional views illustrating a manufacturing process of the thin film transistor 461 shown in FIG. 3(A) and FIG. 3(B). 1(A) to 1(E), and plan views of the manufacturing process are shown in FIGS. 2(A) to 2(D).

[0052] First, a photolithography process is performed on a substrate 400 having an insulating surface using a photomask. A gate electrode layer 401 is provided by a lithography process.

[0053] There is no significant limitation on the glass substrate that can be used, but at least it should be resistant to the subsequent heat treatment. The substrate 400 having light-transmitting properties is required to have a heat resistance sufficient to withstand the heat. A glass substrate such as aluminoborosilicate glass or aluminoborosilicate glass can be used. do.

[0054] In addition, when the temperature of the subsequent heat treatment is high, the substrate 400 has a strain point of 730° C. or higher. The substrate 400 may be made of, for example, aluminosilicate glass, aluminum, or the like. Glass materials such as lumino borosilicate glass and barium borosilicate glass are used. By containing more barium oxide (BaO) than boric acid, it has more practical heat resistance. Therefore, it is possible to use a glass substrate containing more BaO than B2O3. preferable.

[0055] Instead of the substrate 400, a ceramic substrate, a quartz glass substrate, a quartz substrate, a sapphire substrate, Alternatively, a substrate made of an insulating material such as a glass substrate may be used. This can be done.

[0056] An insulating film serving as a base film may be provided between the substrate 400 and the gate electrode layer 401. It has a function of preventing the diffusion of impurity elements from the substrate 400, and is a silicon nitride film, a silicon oxide film, a nitride film, a silicon oxide film or a silicon oxynitride film; It can be formed as follows.

[0057] Since a heat treatment is performed in a later step, the material of the gate electrode layer 401 contains a heat-resistant conductive material. The heat-resistant conductive material is preferably titanium, tantalum, tungsten, molybdenum, or the like. An element selected from the group consisting of chromium, neodymium, and scandium, or an alloy containing such an element The gate electrode layer may be a nitride of the element. 401 is made of titanium, tantalum, tungsten, molybdenum, chromium, neodymium, and scandium. Elements selected from aluminum, alloys containing elements, or nitrides containing elements It may be a single layer or a laminated structure. For example, the first layer may be tungsten nitride, the second The second layer is tungsten, and the first layer is molybdenum nitride and the second layer is tungsten. The first layer is titanium nitride and the second layer is titanium. However, the material of the gate electrode layer 401 must be at least resistant to subsequent heat treatment. It is preferable that the material has heat resistance to the extent possible.

[0058] At this time, the source electrode layer 405a and the gate electrode layer 405b are formed simultaneously with the gate electrode layer 401 in a later step. The connection electrode layer 420 may be formed at the same time as the drain electrode layer 405b. The connection electrode layer 420 is formed when the source electrode layer 405a and the drain electrode layer 405b are formed. It doesn't have to be done.

[0059] Next, a gate insulating layer 402 is formed over the gate electrode layer 401 .

[0060] The gate insulating layer is formed by depositing a silicon oxide layer, a nitride layer, or the like using plasma CVD or sputtering. A silicon nitride layer, a silicon oxynitride layer, or a silicon nitride oxide layer can be formed as a single layer or a stacked layer. For example, the plasma CVD method can be performed using SiH4, oxygen, and nitrogen as the deposition gas. A silicon oxynitride layer may be formed.

[0061] Next, an oxide semiconductor film is formed over the gate insulating layer 402.

[0062] Before the oxide semiconductor film was formed by a sputtering method, argon gas was introduced. Reverse sputtering is performed to generate plasma, and a film is formed on the surface of the gate insulating layer 402. It is preferable to remove the powdery substances (also called particles or dust) that are generated during the process. Sputtering is a process in which a voltage is applied to a substrate using an RF power supply in an argon atmosphere to form a plate near the substrate. This is a method of modifying the surface by forming a barrier. A mask or the like may also be used.

[0063] The oxide semiconductor film was formed by sputtering using an In-Ga-Zn-O oxide semiconductor target. The oxide semiconductor film is formed in a rare gas (typically, argon) atmosphere. under an oxygen atmosphere, or under a rare gas (typically argon) and oxygen atmosphere. It can be formed by a pulverizing method.

[0064] The gate insulating layer 402 and the oxide semiconductor film are formed in succession without exposure to air. By forming the film without exposing it to the atmosphere, the interface is free from water, hydrocarbons, etc. The interface between each layer is formed without being contaminated by atmospheric components or impurity elements floating in the air. Therefore, the variation in the thin film transistor characteristics can be reduced.

[0065] The oxide semiconductor film is then formed into island-shaped oxide semiconductor films by a photolithography process using a photomask. Process into a conductor layer.

[0066] Next, a first conductive film is formed over the gate insulating layer 402 and the oxide semiconductor layer.

[0067] Since a heat treatment is performed in a later step, the material of the first conductive film preferably contains a heat-resistant conductive material. The heat-resistant conductive material is preferably titanium, tantalum, tungsten, molybdenum, An element selected from chromium, neodymium, and scandium, or an alloy containing the element, or The first conductive film can be made of a nitride containing the element. Select from tantalum, tungsten, molybdenum, chromium, neodymium, and scandium. The element is either a single element, an alloy containing the element, or a nitride containing the element. For example, the first layer may be tungsten nitride and the second layer may be titanium. The first layer is molybdenum nitride and the second layer is tungsten. Alternatively, titanium nitride may be used as the first layer and titanium as the second layer. However, the material of the first conductive film must have at least sufficient heat resistance to withstand the subsequent heat treatment. It is preferable that the compound has the following structure:

[0068] The heat-resistant conductive material used for the first conductive film is indium, tin, or zinc. Transparent conductive oxides containing either of these may be used. For example, indium oxide (In2O3 ) and indium oxide tin oxide alloy (In2O3-SnO2, abbreviated as ITO) It is also preferable to add an insulating oxide such as silicon oxide to a transparent conductive oxide. may also be used.

[0069] By including an insulating oxide such as silicon oxide in the transparent conductive oxide, the transparent conductive oxide can be The crystallization of the transparent conductive oxide can be suppressed, and the amorphous structure can be obtained. By suppressing the crystallization and making the structure amorphous, the crystallization of the transparent conductive oxide can be prevented even when heat treatment is performed. Crystallization or the formation of fine crystal grains can be prevented.

[0070] The oxide semiconductor layer and the first conductive film are formed by a photolithography process using a photomask. the oxide semiconductor layer 432, the source and drain electrode layers 405a and 405b, and Then, a connection electrode layer 420 is formed (see FIGS. 1A and 2A). The oxide layer is only partially etched, resulting in an oxide semiconductor layer 432 having a groove (recess).

[0071] In addition, when the connection electrode layer 420 is formed simultaneously with the gate electrode layer 401, the connection electrode layer 420 In addition, even in the case of the structure shown in FIG. 3(D), the connection electrode layer 4 20 may not be formed.

[0072] The gate insulating layer 402, the oxide semiconductor layer 432, the source electrode layer 405a, and the drain electrode layer An oxide insulating film 407 is formed to cover the oxide semiconductor layer 405b and to be in contact with part of the oxide semiconductor layer 432. (See FIG. 1B.) The oxide insulating film 407 has a thickness of at least 1 nm. A method that does not allow impurities such as water or hydrogen to be mixed into the oxide insulating film 407, such as a deposition method or a sputtering method, Here, the oxide insulating film 407 is formed by a sputtering method. The oxide insulating film 4 formed in contact with part of the oxide semiconductor layer 432 is formed by a coating method. 07 is water, hydrogen ions, OH - It does not contain impurities such as An inorganic insulating film that blocks the light is used, typically a silicon oxide film, a silicon nitride oxide film, or an oxide film. An aluminum film or an aluminum oxynitride film is used. A silicon nitride film or an aluminum nitride film may be laminated in contact with the silicon nitride film. ions and OH - It does not contain impurities such as lactic acid bacteria and blocks them from entering from the outside. .

[0073] In addition, by gradually cooling the oxide semiconductor layer in an oxygen atmosphere after the heat treatment, the surface of the oxide semiconductor layer When a region containing a high concentration of oxygen can be formed nearby and the resistance of the oxide semiconductor layer can be made sufficiently high In this case, a silicon nitride film may be formed instead of the oxide insulating film 407. For example, when the temperature of the substrate is The temperature should be slowly cooled down to at least 50 to 100°C below the maximum temperature during heating.

[0074] In this embodiment, a silicon oxide film is formed as the oxide insulating film 407 to a thickness of 300 nm. The substrate temperature during film formation may be set to room temperature or higher and 300° C. or lower, and in this embodiment, it is set to 100° C. The silicon oxide film is formed by sputtering in a rare gas (typically argon) atmosphere. It is carried out under an atmosphere of air, oxygen, or a rare gas (typically argon) and oxygen. In addition, a silicon oxide target or a silicon target can be used as the target. For example, a silicon target can be used and sputtered under an oxygen and nitrogen atmosphere. A silicon oxide film can be formed by a tarring method.

[0075] Next, the source electrode layer 405a, the drain electrode layer 405b, the gate insulating layer 402, and the oxide The insulating film 407 and the oxide semiconductor layer 432 are heated under an oxygen gas atmosphere and an inert gas atmosphere (nitrogen, or helium, neon, argon, etc.) or under reduced pressure to oxidize The compound semiconductor layer 403 is formed (see FIGS. 1(C) and 2(B)). The temperature of the heat treatment is The temperature is 200° C. or higher and 700° C. or lower, preferably 350° C. or higher and lower than the strain point of the substrate 400 . The source electrode layer 405a, the drain electrode layer 405b, the gate insulating layer 402, and the oxide insulating film 4 The source electrode layer 407 and the oxide semiconductor layer 403 are subjected to heat treatment under the above atmosphere. 5a, the drain electrode layer 405b, the gate insulating layer 402, the oxide semiconductor layer 403, and the oxide Impurities such as hydrogen and water contained in the interface between the semiconductor layer 403 and the films provided above and below it Depending on the conditions of the heat treatment or the material of the oxide semiconductor layer, impurities can be removed. In some cases, the oxide semiconductor layer is crystallized to become a microcrystalline film or a polycrystalline film.

[0076] When the oxide insulating film 407 serving as a protective film in contact with the oxide semiconductor layer 432 is formed, Although there is a risk that the semiconductor layer 432 may be damaged by plasma, this heat treatment As a result, plasma damage to the oxide semiconductor layer 432 can be repaired.

[0077] Furthermore, this heat treatment converts oxygen in the oxide insulating film 407 into the oxide semiconductor by solid-phase diffusion. The oxide semiconductor layer 403 is supplied with the electric current. A thin film transistor with good characteristics and high reliability can be fabricated.

[0078] Furthermore, by carrying out this heat treatment, the variation in the electrical characteristics of the thin film transistors is reduced. It is possible.

[0079] In the heat treatment, nitrogen or a rare gas such as helium, neon, or argon is used. It is preferable that the nitrogen introduced into the heat treatment device does not contain hydrogen or the like. The purity of rare gases such as helium, neon, and argon is preferably 6N (99.9999%) or higher. or 7N (99.99999%) or more (i.e., impurity concentration is 1 ppm or less, preferably After the heat treatment, the material is slowly cooled in an oxygen atmosphere. For example, it is preferable that the temperature of the substrate is at least 50°C to 10°C above the maximum temperature during heating. Cool slowly until the temperature drops to about 0°C.

[0080] Heat treatment is carried out using an electric furnace or a GRTA (Gas Rapid Thermal Annealing (LRTA) method or lamp light Use instantaneous heating methods such as the mp Rapid Thermal Anneal method. It is possible.

[0081] Here, the source electrode layer 405a, the drain electrode layer 405b, the gate insulating layer 402, the oxide As one example of heat treatment of the insulating film 407 and the oxide semiconductor layer 432, an electric furnace 601 is used. The heating method will be described with reference to FIG.

[0082] FIG. 15 is a schematic diagram of an electric furnace 601. A heater 603 is installed outside a chamber 602. The chamber 602 is provided with a heating element for heating the chamber 602. A susceptor 605 for mounting a substrate 604 is provided in the chamber 602. The chamber 602 is provided with a gas supply means 606 and an exhaust means 608. 7. Gas is introduced into the chamber 602 by a gas supply means 606. Also, the inside of the chamber 602 is evacuated by the exhaust means 607, or the chamber 602 is The pressure inside the electric furnace 601 is reduced. The temperature rise rate of the electric furnace 601 is set to 0.1°C / min or more and 20°C / min or less. It is preferable that the temperature drop rate of the electric furnace 601 is 0.1°C / min or more and 15 ° C. / min or less is preferable.

[0083] The gas supply means 606 includes a gas supply source 611a, a gas supply source 611b, and a pressure adjusting valve 612a. , pressure regulating valve 612b, refiner 613a, refiner 613b, mass flow controller 61 4a, mass flow controller 614b, stop valve 615a, stop valve 61 In this embodiment, the gas supply source 611a, the gas supply source 611b, and the chamber It is preferable to provide a purifier 613a and a purifier 613b between the purifier 613 and the purifier 602. a. By providing a purifier 613b, the gas supply source 611a and the gas supply source 611b are supplied with The purifier 613a purifies impurities such as water and hydrogen from the gas introduced into the chamber 602. By removing the gas by the filter 613b, the intrusion of water, hydrogen, etc. into the chamber 602 is reduced. can be reduced.

[0084] In this embodiment, nitrogen or a rare gas is supplied from the gas supply source 611a and the gas supply source 611b. The mixture is introduced into a chamber 602, and the chamber is filled with an oxygen, nitrogen or rare gas atmosphere. C. or higher and 700.degree. C. or lower, preferably 350.degree. C. or higher and lower than the strain point of the substrate 400. In the member 602, the oxide semiconductor layer 432 formed on the substrate 400 is heated. In this way, the oxide semiconductor layer 432 can be dehydrated or dehydrogenated.

[0085] Alternatively, the temperature may be increased by an exhaust means under reduced pressure at 200°C or higher and 700°C or lower, preferably 350°C or higher. Formed on the substrate 400 in a chamber 602 heated below the strain point of the upper substrate 400 The oxide semiconductor layer 432 is heated to dehydrate or decompose the oxide semiconductor layer 432. Hydrogenation can be carried out.

[0086] Next, the introduction of nitrogen or a rare gas into the chamber 602 from the gas supply source 611a is stopped. At the same time, the heater is turned off. Next, oxygen is supplied from the gas supply source 611b to the chamber 6 602 of the heating device, and gradually cool the chamber 602. The inside of the gas supply source 611b is an oxygen atmosphere, and the substrate 604 is gradually cooled. Therefore, it is preferable that the oxygen introduced into the chamber 602 does not contain impurities such as water and hydrogen. Alternatively, the purity of oxygen introduced into the chamber 602 from the gas supply source 611b is set to 6N. (99.9999%) or more, preferably 7N (99.99999%) or more (i.e., oxygen It is preferable to keep the impurity concentration in the solution at 1 ppm or less, preferably 0.1 ppm or less.

[0087] As a result, the reliability of the thin film transistors to be formed later can be improved.

[0088] When the heat treatment is performed under reduced pressure, oxygen is introduced into the chamber 602 after the heat treatment. The pressure can be returned to atmospheric pressure and cooled.

[0089] Also, oxygen is introduced into the chamber 602 from the gas supply source 611b, and simultaneously, helium, Introduce one or both of a rare gas such as neon or argon and nitrogen into the chamber 602. You may do so.

[0090] After the substrate 604 in the chamber 602 of the heating device was cooled to 300° C., 4 may be moved to a room temperature atmosphere, which may result in a shorter cooling time for the substrate 604. can.

[0091] In addition, if the heating device is a multi-chamber device, the heating process and the cooling process are performed in different chambers. Typically, oxygen, nitrogen or a rare gas is filled and the temperature is 200°C or higher. A first chamber heated to a temperature below 300° C., preferably above 350° C. and below the strain point of the substrate 400. The oxide semiconductor layer on the substrate is heated in the bar. Then, nitrogen or a rare gas is introduced. The mixture is then transferred to a second chamber filled with oxygen and heated to a temperature of 100°C or less, preferably room temperature. The substrate that has been subjected to the above heat treatment is transferred to the cooling member and subjected to a cooling treatment. This can improve the investment.

[0092] The state of the oxide semiconductor layer 432 after heat treatment in an inert gas atmosphere or under reduced pressure is as follows: It is preferably in an amorphous state, but may be partially crystalline.

[0093] As described above, the heat treatment is performed after forming the oxide insulating film that is in contact with the oxide semiconductor layer and serves as a protective film. By this, the source electrode layer, the drain electrode layer, the gate insulating layer, the oxide insulating film and the oxide It is possible to reduce impurities (H2O, H, OH, etc.) contained in the semiconductor layer. By the heat treatment, an oxide insulating film that serves as a protective film in contact with the oxide semiconductor layer is formed. It is possible to recover plasma damage that the oxide semiconductor layer receives when the oxide semiconductor layer is formed. By carrying out the heat treatment, it is possible to reduce variations in the electrical characteristics of the thin film transistors. As described above, the electrical characteristics and reliability of the thin film transistor 461 can be improved. can.

[0094] Next, a first contact hole 421 and a second contact hole 422 are formed in the oxide insulating film 407. 22, forming a third contact hole 423 and a fourth contact hole 424 ( (See FIGS. 1D and 2C.) First, part of the oxide insulating film 407 is removed by etching. By removing the portion, a first contact hole 421 reaching the source electrode layer 405a is formed. a part of the second contact hole 422 reaching the gate electrode layer 401; and a part of the connecting electrode layer 4 The third contact hole 423 and the fourth contact hole 424 reach both ends of the substrate 20. Furthermore, a part of the gate insulating layer 402 is removed by etching. As a result, a second contact hole 422 reaching the gate electrode layer 401 is formed.

[0095] Next, a second conductive film is formed over the oxide insulating film 407. The first contact hole 421, the second contact hole 422, and the third contact hole 4 23 and the fourth contact hole 424, the source electrode layer 405a, the gate electrode The layer 401 and the connection electrode layer 420 are connected.

[0096] The second conductive film has a low resistivity lower than that of the source electrode layer 405a and the drain electrode layer 405b. The second conductor is preferably a resistive conductive material, particularly aluminum or copper. By using a low-resistance conductive material as the conductive film, it is possible to reduce wiring resistance, etc. do.

[0097] Low-resistance conductive materials such as aluminum or copper have low heat resistance, but the second conductive film can withstand heat. Since it can be applied after processing, it is possible to use low resistance conductive materials such as aluminum or copper. It is possible.

[0098] Next, the second conductive film is processed by a photolithography process using a photomask, and an acid is formed. On the oxide insulating film 407, a source wiring 425, a first gate wiring 426, and a second gate wiring 427 is formed (see FIG. 1(E) and FIG. 2(D)). The source wiring 425 is a connection electrode layer 420 and connected to the source electrode layer 405a through a first contact hole 421. The first gate wiring 426 and the second gate wiring 427 are formed so as to sandwich the source wiring 425. Here, the first gate wiring 426 is connected to the second contact hole. The gate electrode layer 401 is connected to the gate electrode layer 401 through a third contact hole 422 and the The second gate wiring 427 is formed so as to be connected to the connection electrode layer 420. , and is formed so as to be connected to the connection electrode layer 420 via the fourth contact hole 424. Therefore, the first gate wiring 426 and the second gate wiring 427 are connected to the connection electrode layer 420. are electrically connected via the

[0099] Through the above steps, the thin film transistor 461 can be formed. The structure shown in FIG. 3(D) can also be fabricated by the same process.

[0100] As described above, the heat treatment is performed after forming the oxide insulating film that is in contact with the oxide semiconductor layer and serves as a protective film. By this, the source electrode layer, the drain electrode layer, the gate insulating layer, and the oxide semiconductor layer are It is possible to reduce impurities (H2O, H, OH, etc.) contained in the molten metal. By performing the above process, when forming an oxide insulating film that serves as a protective film in contact with the oxide semiconductor layer, an oxide insulating film is formed. The above-mentioned heat treatment can recover the plasma damage to the nitride semiconductor layer. By performing this process, it is possible to reduce the variations in the electrical characteristics of thin film transistors. Therefore, the reliability of the thin film transistor 461 can be improved.

[0101] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0102] (Embodiment 2) A semiconductor device and a manufacturing method of the semiconductor device will be described with reference to FIGS. The same parts or parts having similar functions and steps can be performed in the same manner as in the first embodiment. Therefore, repeated explanations will be omitted.

[0103] FIG. 6A is a plan view of a thin film transistor 460 included in the semiconductor device, and FIG. 6A. The thin film transistor 460 is an inverted staggered type. The thin film transistor is a gate electrode layer 4 on a substrate 450 having an insulating surface. 51 is provided, a gate insulating layer 452 is provided on the gate electrode layer 451, and a gate insulating Source and drain electrode layers 455a and 455b are provided on the layer 452. The source or drain electrode layers 455a, 455b and the gate insulating layer 452 are covered with an oxide film. The gate insulating layer 452, the oxide semiconductor layer 453, The oxide semiconductor layer 453 is formed by covering the source electrode layer 455a and the drain electrode layer 455b. The oxide semiconductor layer 453 is formed of In-Ga-Zn- Use an O-based non-single crystal.

[0104] The oxide insulating film 457 has a first contact hole reaching the source electrode layer 455a. 471, a second contact hole 472 reaching the gate electrode layer 451, and a connection electrode layer 4 A third contact hole 473 and a fourth contact hole 474 reach both ends of the substrate 70. In this embodiment, the source wiring and the drain wiring are provided in the same layer. Therefore, the first gate wiring 476 and the second gate wiring 477 are formed in the same manner as the source wiring 475. The first gate wiring 476 and the second gate wiring 477 are formed so as to sandwich the source Electrical connection is made via a connection electrode layer 470 formed so as to overlap the wiring 475. Here, the source wiring 475 is connected to the source electrode layer 455 through the first contact hole 471. The first gate wiring 476 is electrically connected to the second contact hole 4 72. The first gate wiring 476 is electrically connected to the gate electrode layer 451 through the first gate wiring 476. The second gate wiring 477 is connected to the third contact hole 473 and the fourth contact hole 474. The source wiring 475 is electrically connected to the connection electrode layer 470 via a wiring 474. The first gate wiring 476 and the second gate wiring 477 are formed from the outer periphery of the oxide semiconductor layer 453. It extends outward.

[0105] The oxide semiconductor layer 453 is formed of an oxide insulating film which is in contact with the oxide semiconductor layer 453 and functions as a protective film. After the formation of the insulating film 457, a heat treatment (dehydration or dehydrogenation) is performed to reduce impurities such as moisture. (heat treatment for the purpose) is carried out.

[0106] In addition to the oxide semiconductor layer 453, the gate insulating layer 452, the source electrode layer 455a, and the like are and the drain electrode layer 455b and the oxide semiconductor layer 453. Specifically, the interface between the gate insulating layer 452 and the oxide semiconductor layer 453 and the oxide insulating layer 454 The heat treatment reduces impurities such as moisture present at the interface between the film 457 and the oxide semiconductor layer 453. The moisture content in the oxide semiconductor layer 453 is reduced by the above-described process. The electrical properties of the film can be improved.

[0107] The oxide insulating film 457 is formed over the oxide semiconductor layer 453 by this heat treatment. The oxide semiconductor layer 453 is repaired from plasma damage that the oxide semiconductor layer 453 receives during the treatment.

[0108] a gate electrode layer 451, a connection electrode layer 470, a source or drain electrode layer 455a, 455b preferably contains a heat-resistant conductive material. selected from the group consisting of tantalum, tungsten, molybdenum, chromium, neodymium, and scandium The material is either an element, an alloy containing the element, or a nitride containing the element. In addition, the gate electrode layer 451, the connection electrode layer 470, the source electrode layer or the drain electrode layer The layer electrode layers 455a and 455b may be made of titanium, tantalum, tungsten, molybdenum, or chromium. An element selected from the group consisting of chromium, neodymium, and scandium, or an alloy containing such an element; or For example, the first layer may be a nitride layer. The first layer is molybdenum nitride, and the second layer is tungsten. The second layer is tungsten, and the first layer is titanium nitride and the second layer is titanium. The combination should be:

[0109] In addition, the connection electrode layer 470 and the source and drain electrode layers 455a and 455b are formed of The heat-resistant conductive material may be a transparent conductive material containing indium, tin, or zinc. Oxides may also be used. For example, indium oxide (In2O3) or indium oxide silicon dioxide. It is preferable to use a zinc alloy (In2O3-SnO2, abbreviated as ITO). A conductive oxide may be used in combination with an insulating oxide such as silicon oxide.

[0110] By including an insulating oxide such as silicon oxide in the transparent conductive oxide, the transparent conductive oxide can be The crystallization of the transparent conductive oxide can be suppressed, and the amorphous structure can be obtained. By suppressing the crystallization and making the structure amorphous, the crystallization of the transparent conductive oxide can be prevented even when heat treatment is performed. Crystallization or the formation of fine crystal grains can be prevented.

[0111] a gate electrode layer 451, a connection electrode layer 470, a source or drain electrode layer 455a, By including the heat-resistant conductive material in the gate electrode layer 451, the contact The source electrode layer 455a and the drain electrode layer 455b are formed of an oxide insulating film. 457It can withstand the heat treatment performed after formation.

[0112] The source wiring 475, the first gate wiring 476, and the second gate wiring 477 are connected to the source electrode The conductive material has a lower resistivity than the drain electrode layer 455a and the drain electrode layer 455b. The source wiring 475 and the first gate wiring 476 are preferably made of aluminum or copper, and particularly preferably made of aluminum or copper. By using a low resistance conductive material for the gate wiring 476 and the second gate wiring 477, It is possible to reduce resistance, etc.

[0113] Low-resistivity conductive materials such as aluminum or copper have low heat resistance, but as mentioned above, they are suitable for soaking. By providing a gate wiring 475, a first gate wiring 476, and a second gate wiring 477, After the heat treatment after the oxide insulating film formation, the source wiring 475, the first gate wiring 476, and The second gate wiring 477 can be formed. The first gate wiring 476 and the second gate wiring 477 are made of a low resistance material such as aluminum or copper. A conductive material can be used.

[0114] The oxide semiconductor layer 453 including the channel formation region is formed using an oxide material having semiconductor properties. Typically, an In-Ga-Zn-O based non-single crystal is used.

[0115] As shown in FIG. 6C, the first source wiring 478 and the second source wiring 479 are The gate wiring 480 is sandwiched between the contacts 482 and 483. The first source line may be electrically connected to the second source line via the connecting electrode layer 470. The line 478 is electrically connected to the source electrode layer 455a through the first contact hole 471. The gate wiring 480 is connected to the gate electrode 472 through the second contact hole 472. The first source wiring 478 and the second source wiring 479 are electrically connected to the electrode layer 451. 479 are the third contact holes 473 and the fourth contact hole 479 that reach both ends of the connection electrode layer 470. Electrical connection is made to the connection electrode layer 470 through the contact hole 474. In this respect, it is similar to the thin film transistors shown in FIGS. 6(A) and 6(B) described above.

[0116] 6(D), the source electrode layer 455a is formed so as to overlap the gate wiring 480. A first source wiring 478 and a second source wiring 479 are formed on the source electrode layer 455. The first source wiring 478 may be electrically connected via a. The source electrode layer 455a is electrically connected to the source electrode layer 455b through the first contact hole 471. The second source wiring 479 is connected to the source electrode layer 455a through a third contact hole 479a. The other parts are electrically connected to the source electrode layer 455a via 491. This is the same as the thin film transistor shown in FIG. 6(C).

[0117] 4(A) and 4(B) are cross-sectional views of the manufacturing process of the thin film transistor 460 shown in FIG. 6(A) and FIG. 6(B). 4(A) to 4(E), and plan views of the manufacturing process are shown in FIGS. 5(A) to 5(D).

[0118] A gate electrode layer 451 is provided over a substrate 450 having an insulating surface. An insulating film serving as the gate electrode layer 451 may be provided between the substrate 450 and the gate electrode layer 451. The material for the gate electrode layer 1 can be formed similarly to that for the gate electrode layer 401 described in Embodiment 1.

[0119] In addition, similarly to the first embodiment, the source electrode layer 451 is formed at the same time as the gate electrode layer 451 in a later step. A connection electrode layer 470 may be formed simultaneously with the drain electrode layer 455a and the drain electrode layer 455b. In that case, when the source electrode layer 455a and the drain electrode layer 455b are formed, the connecting electrode Layer 470 may not be formed.

[0120] A gate insulating layer 452 is formed on the gate electrode layer 451. The gate insulating layer 452 is The gate insulating layer 402 can be formed in a manner similar to that of the gate insulating layer 402 described in Embodiment 1.

[0121] A first conductive film is formed over the gate insulating layer 452, and an island-shaped conductive film is formed by a photolithography process. The source and drain electrode layers 455a and 455b and the connection electrode layer 470 are processed. The first conductive film is formed using the same material as that of the first conductive film shown in Embodiment 1. The source and drain electrode layers 455a and 455b can be formed as described in Embodiment 1. The source electrode layer and the drain electrode layer can be formed in a similar manner to the source electrode layer and the drain electrode layer 405a and 405b shown in FIG. Cut.

[0122] In addition, when the connection electrode layer 470 is formed at the same time as the gate electrode layer 451, the connection electrode layer 470 may not be formed. Also, in the case of the structure shown in FIG. 6(D), the connection voltage The pole layer 470 may not be formed.

[0123] Next, the gate insulating layer 452 and the source and drain electrode layers 455a and 455b are formed. an oxide semiconductor film is formed on the insulating film 41 by a photolithography process, and an island-shaped oxide semiconductor layer 48 is formed on the insulating film 41 by a photolithography process. 2 (see Figure 4(A) and Figure 5(A)).

[0124] The oxide semiconductor layer 482 serves as a channel formation region. Form in the same manner as 432.

[0125] Note that before the oxide semiconductor layer 482 was formed by a sputtering method, argon gas was introduced. The reverse sputtering is performed by introducing the silicon dioxide into the gate insulating layer 452 to generate plasma. It is preferable to remove powdery substances (also called particles or dust) that are generated during film formation. .

[0126] Next, a gate insulating layer 452 and an oxide semiconductor layer are formed by sputtering or PCVD. The oxide semiconductor layer 482 covers the source electrode layer 455a and the drain electrode layer 455b. An oxide insulating film 457 is formed in contact with part of the insulating film 82 (see FIG. 4B). The oxide insulating film 457 can be formed in a manner similar to that of the oxide insulating film 407 described in Embodiment 1. In this embodiment, a silicon oxide film having a thickness of 300 nm is formed as the oxide insulating film 457. The substrate temperature may be set to a temperature between room temperature and 300° C., and is set to 100° C. in this embodiment.

[0127] Next, the source electrode layer 455a, the drain electrode layer 455b, the gate insulating layer 452, and the oxide The insulating film 457 and the oxide semiconductor layer 482 are heated under an oxygen gas atmosphere and an inert gas atmosphere (nitrogen, or helium, neon, argon, etc.) or under reduced pressure to oxidize The compound semiconductor layer 453 is formed (see FIGS. 4(C) and 5(B)). The temperature of the heat treatment is The temperature is 200° C. or higher and 700° C. or lower, preferably 350° C. or higher and lower than the strain point of the substrate 450 . The source electrode layer 455a, the drain electrode layer 455b, the gate insulating layer 452, and the oxide insulating film 4 The source electrode layer 45 is formed by heat treatment of the oxide semiconductor layer 453 under the above atmosphere. 5a, the drain electrode layer 455b, the gate insulating layer 452, the oxide semiconductor layer 453, the oxide insulating layer 454, the gate insulating layer 452, the oxide semiconductor layer 453, the oxide insulating layer 454, the drain electrode layer 455b ... drain electrode layer 455b, the drain The insulating film 457 and the oxide semiconductor layer 453 are included in the interfaces between the insulating film 457 and the oxide semiconductor layer 453 and the films provided above and below the insulating film 457. Impurities such as hydrogen and water can be removed by the heat treatment conditions or by the oxide semiconductor. Depending on the material of the oxide semiconductor layer, the oxide semiconductor layer may crystallize to become a microcrystalline film or a polycrystalline film. There are also.

[0128] When the oxide insulating film 457 serving as a protective film in contact with the oxide semiconductor layer 482 is formed, Although there is a risk that the semiconductor layer 482 may be damaged by plasma, this heat treatment As a result, plasma damage to the oxide semiconductor layer 482 can be repaired.

[0129] Furthermore, this heat treatment converts oxygen in the oxide insulating film 407 into the oxide semiconductor by solid-phase diffusion. The oxide semiconductor layer 403 is supplied with the electric current. A thin film transistor with good characteristics and high reliability can be fabricated.

[0130] Furthermore, by carrying out this heat treatment, the variation in the electrical characteristics of the thin film transistors is reduced. It is possible.

[0131] In the heat treatment for dehydration or dehydrogenation, nitrogen, helium, or neodymium is used. It is preferable that the rare gas such as argon or fluorine does not contain water or hydrogen. The purity of nitrogen or rare gases such as helium, neon, and argon introduced into the treatment equipment must be 6N( 99.9999%) or more, preferably 7N (99.99999%) or more (i.e., impurity concentration It is preferable to set the concentration to 1 ppm or less, preferably 0.1 ppm or less. After the treatment, it is preferable to slowly cool the substrate in an oxygen atmosphere. The temperature should be gradually cooled down to at least 50 to 100 degrees Celsius below the normal temperature.

[0132] Heat treatment is carried out using an electric furnace or a GRTA (Gas Rapid Thermal Annealing (LRTA) method or lamp light Use instantaneous heating methods such as the mp Rapid Thermal Anneal method. It is possible.

[0133] Here, as one example of heat treatment of the oxide semiconductor layer 482, heating using an electric furnace 1601 is performed. The method will be explained with reference to FIG.

[0134] FIG. 16 is a schematic diagram of an electric furnace 1601. A heater 1602 is installed outside a chamber 1602. 1602. The chamber 1602 is provided with a susceptor 1605 for mounting a substrate 1604. The chamber 1602 is provided with a gas supply means 1. The gas supply means 1606 supplies gas to the chamber. Gas is introduced into the chamber 602. Also, the inside of the chamber 602 is evacuated by the exhaust means 1607. The temperature rise characteristic of the electric furnace 1601 is The heating rate is preferably 0.1°C / min or more and 20°C / min or less. It is preferable that the temperature drop rate is 0.1°C / min or more and 15°C / min or less.

[0135] The gas supply means 1606 includes a gas supply source 1611, a pressure regulating valve 1612, a purifier 1613, It has a mass flow controller 1614 and a stop valve 1615. It is preferable to provide a purifier 1613 between the gas source 1611 and the chamber 1602. By providing a purifier 1613, the gas introduced from the gas supply source 1611 into the chamber 1602 can be The purifier 1613 can remove impurities such as water and hydrogen from the gas that is being introduced. This makes it possible to reduce the intrusion of water, hydrogen, etc. into the chamber 1602.

[0136] In this embodiment, oxygen, nitrogen or a rare gas is supplied from a gas supply source 1611 to the chamber 16 02, and the chamber is filled with nitrogen or rare gas atmosphere and heated to 200℃ or higher and 700℃ or lower. In a chamber 1602 heated to a temperature preferably above 350° C. but below the strain point of the substrate 450, In this case, the oxide semiconductor layer formed on the substrate 450 is heated to remove the oxide semiconductor layer. Hydrolysis or dehydrogenation can be carried out.

[0137] Alternatively, the temperature may be increased by an exhaust means under reduced pressure at 200°C or higher and 700°C or lower, preferably 350°C or higher. In a chamber 1602 heated to below the strain point of the upper substrate 450, a pattern is formed on the substrate 450. The oxide semiconductor layer is heated to dehydrate or dehydrogenate the oxide semiconductor layer. It is possible to do so.

[0138] The heater is then turned off and the chamber 1602 of the heating device is allowed to cool gradually.

[0139] As a result, the reliability of the thin film transistors to be formed later can be improved.

[0140] If the heat treatment is carried out under reduced pressure, an inert gas should be passed through the container to return it to atmospheric pressure after heating and then cooled. Just dismiss it.

[0141] After the substrate 1604 in the chamber 1602 of the heating device was cooled to 300° C., The substrate 1604 may be moved to a room temperature atmosphere, thereby reducing the cooling time of the substrate 1604. It is possible.

[0142] In addition, if the heating device is a multi-chamber device, the heating process and the cooling process are performed in different chambers. Typically, oxygen, nitrogen or a rare gas is filled and the temperature is 200°C or higher. A first chamber heated to a temperature below 300° C., preferably above 350° C. and below the strain point of the substrate 450. The oxide semiconductor layer on the substrate is heated in the bar. Then, nitrogen or a rare gas is introduced. The material is then transferred to a transfer chamber filled with nitrogen or a rare gas and heated to a temperature of 100°C or less, preferably at room temperature. The substrate that has been subjected to the heat treatment is then moved to a second chamber, where a cooling treatment is carried out. This can improve throughput.

[0143] The state of the oxide semiconductor layer 482 after heat treatment under an inert gas atmosphere or reduced pressure is as follows: It is preferably in an amorphous state, but may be partially crystalline.

[0144] As described above, the heat treatment is performed after forming the oxide insulating film that is in contact with the oxide semiconductor layer and serves as a protective film. By this, the source electrode layer, the drain electrode layer, the gate insulating layer, the oxide insulating film and the oxide It is possible to reduce impurities (H2O, H, OH, etc.) contained in the semiconductor layer. By the heat treatment, an oxide insulating film that serves as a protective film in contact with the oxide semiconductor layer is formed. It is possible to recover plasma damage that the oxide semiconductor layer receives when the oxide semiconductor layer is formed. By carrying out the heat treatment, it is possible to reduce variations in the electrical characteristics of the thin film transistors. Therefore, the electrical characteristics and reliability of the thin film transistor 460 can be improved. Cut.

[0145] Next, a first contact hole 471 and a second contact hole 472 are formed in the oxide insulating film 457. 72, a third contact hole 473 and a fourth contact hole 474 are formed ( (See FIGS. 4D and 5C.) First, part of the oxide insulating film 457 is removed by etching. By removing the portion, a first contact hole 471 reaching the source electrode layer 455a is formed. a part of the second contact hole 472 reaching the gate electrode layer 451; A third contact hole 473 and a fourth contact hole 474 reach both ends of the substrate 70. Furthermore, a part of the gate insulating layer 452 is removed by etching. As a result, a second contact hole reaching the gate electrode layer 451 is formed.

[0146] Next, a second conductive film is formed over the oxide insulating film 457. The first contact hole 471, the second contact hole 472, the third contact hole 4 73 and the fourth contact hole 474, the source electrode layer 455a, the gate electrode layer The layer 451 and the connection electrode layer 470 are connected to each other.

[0147] The second conductive film has a low resistivity lower than that of the source electrode layer 455a and the drain electrode layer 455b. The second conductor is preferably a resistive conductive material, particularly aluminum or copper. By using a low-resistance conductive material as the conductive film, it is possible to reduce wiring resistance, etc. do.

[0148] Low-resistance conductive materials such as aluminum or copper have low heat resistance, but the second conductive film can withstand heat. Since it can be applied after processing, it is possible to use low resistance conductive materials such as aluminum or copper. It is possible.

[0149] Next, the second conductive film is etched by an etching process to form a sawtooth film on the oxide insulating film 457. A gate wiring 475, a first gate wiring 476, and a second gate wiring 477 are formed (FIG. 4( 5(E) and 5(D). The source wiring 475 overlaps with the connection electrode layer 470, and the first The source electrode layer 455a is formed to be connected to the source electrode layer 455a through a contact hole 471. A first gate wiring 476 and a second gate wiring 477 are formed on either side of the gate wiring 475. Here, the first gate wiring 476 is connected to the gate electrode 472 via the second contact hole 472. It is connected to the electrode layer 451 and is connected to the connection electrode layer 470 through the third contact hole 473. The second gate wiring 477 is formed so as to be connected to the fourth contact hole. The first gate electrode layer 474 is formed to be connected to the connection electrode layer 470 via the first gate electrode layer 474. The wiring 476 and the second gate wiring 477 are electrically connected via the connection electrode layer 470. .

[0150] Through the above steps, a thin film transistor 460 can be formed. The structure shown in FIG. 6(D) can also be fabricated by the same process.

[0151] As described above, the heat treatment is performed after forming the oxide insulating film that is in contact with the oxide semiconductor layer and serves as a protective film. By this, the source electrode layer, the drain electrode layer, the gate insulating layer, and the oxide semiconductor layer are It is possible to reduce impurities (H2O, H, OH, etc.) contained in the molten metal. By performing the above process, when forming an oxide insulating film that serves as a protective film in contact with the oxide semiconductor layer, an oxide insulating film is formed. The above-mentioned heat treatment can recover the plasma damage to the nitride semiconductor layer. By performing this process, it is possible to reduce the variations in the electrical characteristics of thin film transistors. Therefore, the reliability of the thin film transistor 460 can be improved.

[0152] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0153] (Embodiment 3) A manufacturing process of a semiconductor device including a thin film transistor will be described with reference to FIGS. 7 to 9 show cross-sectional views of the manufacturing process, and FIGS. 10 to 13 show plan views of the manufacturing process.

[0154] In FIG. 7(A), a light-transmitting substrate 100 is made of barium borosilicate glass or aluminum. A glass substrate such as borosilicate glass can be used. Instead, an insulating substrate such as a ceramic substrate, a quartz glass substrate, a quartz substrate, or a sapphire substrate may be used. Alternatively, a substrate made of crystallized glass or the like may be used.

[0155] Next, a conductive layer is formed on the entire surface of the substrate 100, and then a first photolithography process is performed. A resist mask is formed, and unnecessary parts are removed by etching to form wiring and electrodes (gate The electrode layer 101, the capacitor wiring 108, and the first terminal 121 are formed. The gate electrode layer 101 is also etched so that the end portion thereof is tapered.

[0156] The gate electrode layer 101, the capacitor wiring 108, and the first terminal 121 of the terminal portion are the same as those shown in Embodiment 1. The materials for the gate electrode layer 401 can be used as appropriate. The wiring 108 and the first terminal 121 of the terminal portion are made of a resistant material so as to withstand the heat treatment in the subsequent process. It is preferable to form it from a thermally conductive material, such as titanium (Ti), tantalum (Ta), or tungsten (Tb). W, Molybdenum (Mo), Chromium (Cr), Neodymium (Nd), Scandium ( Sc), or an alloy containing the above elements, or a combination of the above elements Formed as a single layer or laminate using an alloy film made of the above elements or nitrides containing the above elements. do.

[0157] At this time, the source electrode layer 105a and the gate electrode layer 105b are formed at the same time as the gate electrode layer 101 in a later step. The connection electrode layer 220 may be formed at the same time as the drain electrode layer 105b. When the source electrode layer 105a and the drain electrode layer 105b are formed, the connection electrode layer 220 is formed. It doesn't have to be done.

[0158] Next, a gate insulating layer 102 is formed on the entire surface of the gate electrode layer 101. For 02, the sputtering method, PCVD method, etc. is used, and the film thickness is set to 50 to 250 nm.

[0159] For example, a silicon oxide film is used as the gate insulating layer 102 by sputtering. Of course, the gate insulating layer 102 is not limited to such a silicon oxide film. Other films include silicon oxynitride film, silicon nitride film, aluminum oxide film, tantalum oxide film, etc. The insulating film may be formed as a single layer or a laminated structure made of these materials.

[0160] Next, an oxide semiconductor film (In-Ga-Zn-O based non-single crystal film) After the plasma treatment, an In-Ga-Zn-O non-single crystal film is formed without exposure to the atmosphere. This method is useful in that it prevents dust and moisture from adhering to the interface between the gate insulating layer and the semiconductor film. Here, an oxide semiconductor target ( In-Ga-Zn-O oxide semiconductor target (In2O3:Ga2O3:ZnO=1 :1:1)) was used, the distance between the substrate and the target was 170 mm, the pressure was 0.4 Pa, Direct current (DC) power supply 0.5kW, oxygen only, argon only, or argon and oxygen atmosphere The film is formed under the condition that the pulsed direct current (DC) power supply is used. The thickness of the In-Ga-Zn-O based non-single crystal film is preferably 5 nm to 20 nm. The oxide semiconductor film was formed using an In-Ga-Zn-O oxide semiconductor target. A 50 nm thick In-Ga-Zn-O non-single crystal film was formed by sputtering using the To film.

[0161] The sputtering method uses a high frequency power supply as the sputtering power source. There are two methods: DC sputtering and pulsed DC sputtering, which applies a bias voltage in a pulsed manner. RF sputtering is mainly used to deposit insulating films, while DC sputtering is also used. The sputtering method is mainly used when forming a metal film.

[0162] There are also multi-target sputtering systems that can accommodate multiple targets of different materials. The sputtering equipment can deposit layers of different materials in the same chamber, or It is also possible to form films by discharging multiple types of materials simultaneously using the bar.

[0163] In addition, a magnetron sputtering method using a magnet mechanism inside the chamber is used. E using a plasma generated by microwaves without glow discharge. There is a sputtering device that uses the CR sputtering method.

[0164] In addition, as a film formation method using the sputtering method, the target material and the sputtering Reactive sputtering is a method of forming a compound thin film by chemically reacting the gas components with the There are also methods such as a sputtering method in which a voltage is applied to the substrate during film formation, and a bias sputtering method in which a voltage is also applied to the substrate during film formation.

[0165] Next, a second photolithography step is performed to form a resist mask, and the oxide semiconductor film For example, wet etching is performed using a solution of phosphoric acid, acetic acid, and nitric acid. Thus, unnecessary portions are removed to form the oxide semiconductor layer 133 (see FIG. 7A and FIG. 10). The etching here is not limited to wet etching, but may be dry etching. may also be used.

[0166] The etching gas used in dry etching is a gas containing chlorine (chlorine-based gas, for example For example, chlorine (Cl2), boron chloride (BCl3), silicon chloride (SiCl4), carbon tetrachloride (CC l4) etc.) are preferred.

[0167] In addition, as the etching gas used in dry etching, a gas containing fluorine (fluorine-based gas) Carbon tetrafluoride (CF4), sulfur hexafluoride (SF6), nitrogen trifluoride (NF3), trifluoride fluoromethane (CHF3), oxygen (O2), and these gases plus helium (He) A gas containing a rare gas such as argon (Ar) can be used.

[0168] As a dry etching method, parallel plate type RIE (Reactive Ion Etch) ing) method and ICP (Inductively Coupled Plasma) The etching method can be used to etch the desired shape. In order to achieve this, the etching conditions (the amount of power applied to the coil-type electrode, the amount of power applied to the electrode on the substrate side) were set. The amount of power applied, the temperature of the electrode on the substrate, etc. are adjusted appropriately.

[0169] The etching solution used for wet etching is a mixture of phosphoric acid, acetic acid, and nitric acid. Alternatively, ITO07N (manufactured by Kanto Chemical Co., Ltd.) may be used.

[0170] In addition, the etching solution after wet etching is washed away together with the etched material. The waste etching solution containing the removed material is purified to remove the contained material. The indium and the like contained in the oxide semiconductor layer may be recycled from the waste liquid after etching. By recovering and reusing materials, resources can be used more effectively and costs can be reduced. .

[0171] In order to etch into the desired shape, the etching conditions (etching) should be adjusted according to the material. The etching conditions (etching solution, etching time, temperature, etc.) are adjusted appropriately.

[0172] Next, a first conductive film 132 made of a metal material is formed on the oxide semiconductor layer 133 by sputtering. It is formed by a deposition method or a vacuum deposition method (see FIG. 7(B)).

[0173] The first conductive film 132 may be formed from a material similar to that of the source electrode layer or the drain electrode layer shown in Embodiment 1. The same material as that of the electrode layers 405a and 405b can be used as appropriate. It is preferable to form the conductive layer from a heat-resistant material so that it can withstand the heat treatment in the subsequent process. Titanium (Ti), Tantalum (Ta), Tungsten (W), Molybdenum (Mo), Chromium (Cr), neodymium (Nd), scandium (Sc), or any of the elements mentioned above An alloy containing the elements as components, an alloy film combining the above elements, or an alloy film containing the above elements The insulating film is formed as a single layer or a multilayer using nitride as a component.

[0174] The heat-resistant conductive material used for the first conductive film 132 is indium, tin, or Transparent conductive oxides containing either indium oxide or zinc may also be used. 2O3) and indium oxide tin oxide alloy (In2O3-SnO2, abbreviated as ITO) It is also preferable to add an insulating oxide such as silicon oxide to the transparent conductive oxide. The above materials may also be used.

[0175] By including an insulating oxide such as silicon oxide in the transparent conductive oxide, the transparent conductive oxide can be The crystallization of the transparent conductive oxide can be suppressed, and the amorphous structure can be obtained. By suppressing the crystallization and making the structure amorphous, the crystallization of the transparent conductive oxide can be prevented even when heat treatment is performed. Crystallization or the formation of fine crystal grains can be prevented.

[0176] Next, a third photolithography process is performed to form a resist mask, and then etching is performed. By removing unnecessary portions, the source electrode layer or the drain electrode layer 105a, 105b, the connecting electrode layer, and the like are formed. The electrode layer 220 and the second terminal 122 are formed (see FIG. 7(C) and FIG. 11). Wet etching or dry etching is used as the etching method. Wet etching using ammonia peroxide water (hydrogen peroxide:ammonia:water=5:2:2) The first conductive film 132 is etched by the etching, and the source or drain electrode layer 105 is In this etching step, the oxide semiconductor layer 133 may be formed as follows: The exposed region is also partially etched to form the oxide semiconductor layer 135. Therefore, the oxide semiconductor layer 135 between the drain electrode layers 105a and 105b is a thin region. The thickness of the thin film region is about 30 nm, which is a film thickness that is difficult to crystallize. This is useful when you want to keep the channel part amorphous. , the source and drain electrode layers 105a and 105b, and the edge of the oxide semiconductor layer 135. Since the etching is performed at once by dry etching, the source electrode layer or the drain electrode layer The ends of the oxide semiconductor layer 135 and the oxide semiconductor layer 105a and 105b are aligned, forming a continuous structure. do.

[0177] In this third photolithography step, the source electrode layer or the drain electrode layer The second terminal 122 made of the same material as the terminals 105a and 105b is left in the terminal portion. The terminal 122 is electrically connected to a source wiring that will be formed in a later step.

[0178] In addition, when the connection electrode layer 420 is formed at the same time as the gate electrode layer 401, the connection electrode layer 420 does not have to be formed.

[0179] Also, a resist having regions of multiple thicknesses (typically two types) formed by a multi-tone mask is used. By using a resist mask, the number of resist masks can be reduced, which simplifies the process and reduces Cost reduction is possible.

[0180] Next, the resist mask is removed, and the gate insulating layer 102, the oxide semiconductor layer 135, and the source electrode A protective insulating layer 107 is formed to cover the electrode layers or drain electrode layers 105a and 105b (FIG. 7). (See (D)). The protective insulating layer 107 has a thickness of at least 1 nm or more and is formed by a CVD method, a sintering method, or the like. A method such as sputtering is appropriately used to prevent impurities such as water and hydrogen from being mixed into the protective insulating layer 107. Here, the protective insulating layer 107 can be formed by a sputtering method. The protective insulating layer 107 formed in contact with part of the oxide semiconductor layer 135 is , hydrogen ions, OH - It does not contain impurities such as An inorganic insulating film that blocks the insulating film is used, typically a silicon oxide film, a silicon nitride oxide film, or an aluminum oxide film. A silicon nitride film or an aluminum oxynitride film is used. The silicon nitride film can absorb moisture, hydrogen ions, and OH - It does not contain impurities such as these, and blocks them from entering from the outside.

[0181] In addition, a protective layer is formed in contact with the oxide semiconductor layer 135 by a sputtering method, a PCVD method, or the like. When the insulating layer 107 is formed, at least the protective insulating layer 107 The area in contact with the substrate is made highly resistive (the carrier concentration is reduced, preferably to 1×10 18 / cm 3 less than ) and can also be a high resistance oxide semiconductor region.

[0182] Next, the source electrode layer 105a, the drain electrode layer 105b, the gate insulating layer 102, and the oxide The compound semiconductor layer 135 is heated in an oxygen gas atmosphere, an inert gas atmosphere (nitrogen, helium, neodymium, etc.), and The oxide semiconductor layer 103 is formed by heat treatment under an atmosphere of nitrogen, argon, or the like or under reduced pressure. (See FIG. 8(A)). The temperature of the heat treatment is preferably 200° C. or higher and 700° C. or lower. The temperature is preferably 350° C. or higher and lower than the distortion point of the substrate 100. The layer 105b, the gate insulating layer 102, and the oxide semiconductor layer 103 are subjected to heat treatment in the above atmosphere. By this, the source electrode layer 105a, the drain electrode layer 105b, the gate insulating layer 102, and the oxide The oxide semiconductor layer 103 and the films provided above and below the oxide semiconductor layer 103 are included in the interfaces of the oxide semiconductor layer 103 and the films provided above and below the oxide semiconductor layer 103. Impurities such as hydrogen and water can be removed by the heat treatment conditions or by the oxide semiconductor. Depending on the material of the oxide semiconductor layer, the oxide semiconductor layer may crystallize to become a microcrystalline film or a polycrystalline film. There are also.

[0183] In addition, when the protective insulating layer 107 serving as a protective film in contact with the oxide semiconductor layer 133 is formed, Although there is a risk that the compound semiconductor layer 133 may be damaged by plasma, this heat treatment This makes it possible to repair the plasma damage that the oxide semiconductor layer 133 has received.

[0184] Furthermore, this heat treatment causes oxygen in the protective insulating layer 107 to diffuse into the oxide semiconductor layer 107 through solid-phase diffusion. Therefore, the oxide semiconductor layer 103 has a high resistance, and the electrical characteristics Therefore, a thin film transistor having good properties and high reliability can be manufactured.

[0185] Furthermore, by carrying out this heat treatment, the variation in the electrical characteristics of the thin film transistors is reduced. After the heat treatment, it is preferable to slowly cool the material in an oxygen atmosphere. For example, gradually reduce the temperature of the substrate by at least 50 to 100 degrees Celsius from the maximum temperature during heating. Just chill it.

[0186] Next, a fourth photolithography step is performed to form a resist mask, and a protective insulating layer 10 7 and the gate insulating layer 102 are etched to form a first contact hole 221 and a second contact hole 222. The contact hole 222, the third contact hole 223, and the fourth contact hole 224 is formed (see FIG. 8(B) and FIG. 12). First, a protective insulating film is formed by etching. By removing a portion of the layer 107, a first contact is formed that reaches the source electrode layer 105a. a hole 221 and a part of a second contact hole 222 reaching the gate electrode layer 101; The third contact hole 223 and the fourth contact hole 224 reach both ends of the connection electrode layer 220. A hole 224 is formed. Furthermore, a part of the gate insulating layer 102 is removed by etching. By removing the second contact hole 222, a second contact hole 222 reaching the gate electrode layer 101 is formed. do.

[0187] In addition, when a reflective display device is manufactured, the contact that reaches the drain electrode layer 105b is When forming contact holes and forming source wiring and gate wiring, the pixel electrode layer 1 It may also be configured to form 10.

[0188] Next, a second conductive film made of a metal material is formed on the protective insulating layer 107 by sputtering or vacuum evaporation. Here, the second conductive film is formed in the first contact hole 221 and the second contact hole 222. The contact hole 222, the third contact hole 223 and the fourth contact hole 22 4, the source electrode layer 105a, the gate electrode layer 101, and the connection electrode layer 220 are connected to each other. can be.

[0189] As a material for the second conductive film, the same material as that for the second conductive film shown in Embodiment Mode 1 is appropriately used. The resistivity of the source electrode layer 105a and the drain electrode layer 105b can be lower than that of the source electrode layer 105a and the drain electrode layer 105b. The second conductor is preferably a resistive conductive material, particularly aluminum or copper. By using a low-resistance conductive material as the conductive film, it is possible to reduce wiring resistance, etc. do.

[0190] Next, a fifth photolithography step is performed to form a resist mask, and By etching, the source wiring 225, the first gate wiring 226 and the The source wiring 22 and the second gate wiring 227 are formed (see FIG. 8(C) and FIG. 12). 5 overlaps the connection electrode layer 220 and is connected to the source electrode layer 1 through the first contact hole 221. The first gate wiring 205 is formed so as to be connected to the source wiring 225. 26 and the second gate wiring 227 are formed. Here, the first gate wiring 226 is The gate electrode layer 101 is connected to the third contact hole 222. The second gate electrode layer 222 is formed so as to be connected to the connection electrode layer 220 via the gate electrode 223. The contact wiring 227 is connected to the connection electrode layer 220 through the fourth contact hole 224. Therefore, the first gate wiring 226 and the second gate wiring 427 are connected. Electrical connection is made via the electrode layer 220 .

[0191] Through the above steps, the thin film transistor 170 can be manufactured.

[0192] Next, a sixth photolithography step is performed to form a resist mask, and a protective insulating layer 10 7, a contact hole 125 reaching the drain electrode layer 105b is formed. Furthermore, a contact hole 127 reaching the second terminal 122 is formed by this etching. A contact hole 126 reaching the first terminal 121 is also formed. 9(A). Note that the contact holes 125, 126 and The formation of the contact hole 127 is carried out simultaneously in the fourth photolithography process described above. You can also do this.

[0193] Next, the resist mask is removed, and then a transparent conductive film is formed. are indium oxide (In2O3) and indium oxide tin oxide alloy (In2O3-SnO 2, abbreviated as ITO) is formed using a sputtering method or a vacuum deposition method. Etching of such materials is done with hydrochloric acid based solutions. However, etching of ITO in particular Since etching tends to leave residue, indium oxide oxide was used to improve etching processability. Zinc alloy (In2O3-ZnO) may also be used. When heat treatment is performed for this purpose, the resistance of the oxide semiconductor layer 103 is increased, and the electrical characteristics of the transistor are improved. This can also serve as a heat treatment to improve the thermal conductivity and reduce the variation in electrical characteristics.

[0194] Next, a seventh photolithography step is performed to form a resist mask and then etch the The pixel electrode layer 110 is formed by removing unnecessary portions.

[0195] In this seventh photolithography step, the gate insulating layer 102 in the capacitance section The protective insulating layer 107 serves as a dielectric, and the capacitor wiring 108 and the pixel electrode layer 110 form a storage capacitor. is formed.

[0196] In the seventh photolithography step, the first terminal 121 and the second terminal 1 22 is covered with a resist mask, and the transparent conductive films 128 and 129 formed on the terminal portions are left. The conductive films 128 and 129 serve as electrodes or wiring used for connection with the FPC. The transparent conductive film 128 formed on the gate electrode 121 is a connecting film that functions as an input terminal of the gate wiring. The transparent conductive film 129 formed on the second terminal 122 serves as a terminal electrode of the source line. This is a connection terminal electrode that functions as an input terminal.

[0197] Next, the resist mask is removed, and the cross-sectional view at this stage is shown in FIG. The plan view at this stage corresponds to FIG.

[0198] 14(A1) and 14(A2) are plan views of the gate wiring terminal portion at this stage, and The cross-sectional views are shown in Fig. 14(A1) and Fig. 14(A2) along the line E1-E2. In FIG. 14(A1), a transparent insulating film formed on the protective insulating film 154 The conductive film 155 is a terminal electrode for connection that functions as an input terminal. ), the terminal portion includes a first terminal 151 made of the same material as the gate wiring, and a source The gate insulating layer 152 is formed on the connection electrode layer 153, which is made of the same material as the gate wiring. 9B, the transparent conductive film 155 is electrically conductive. The portion in contact with the first terminal 121 is the transparent conductive film 155 and the first This corresponds to the portion with which the terminal 151 is in contact.

[0199] 14(B1) and 14(B2) are different from the source wiring terminal portion shown in FIG. 9(B). The plan view and cross-sectional view of different source wiring terminal portions are shown. 1) corresponds to a cross-sectional view taken along the line F1-F2 in FIG. 14(B2). The transparent conductive film 155 formed on the protective insulating film 154 is a contact that functions as an input terminal. In addition, in FIG. 14(B1), the terminal portion is the same as the gate wiring. The electrode layer 156 made of the material is formed on the second terminal 150 electrically connected to the source line. The electrode layer 156 is electrically connected to the second terminal 150 via the gate insulating layer 152. The electrode layer 156 is not connected to the second terminal 150, and is set to a potential different from that of the second terminal 150, for example, floating. If you set it to GND, GND, 0V, etc., you can set capacitance for noise prevention or capacitance for static electricity prevention. The second terminal 150 is transparent via a protective insulating film 154. It is electrically connected to the transparent conductive film 155 .

[0200] A plurality of gate wirings, source wirings, and capacitance wirings are provided depending on the pixel density. In addition, in the terminal section, a first terminal has the same potential as the gate wiring, a second terminal has the same potential as the source wiring, and The second terminal, the third terminal with the same potential as the capacitance wiring, and so on are arranged in a row. The number of terminals may be any number and may be determined appropriately by the implementer.

[0201] In this way, seven photolithography processes were performed using seven photomasks to create the bottom A pixel thin film transistor having a thin film transistor 170 which is a gate-type staggered thin film transistor. The film transistor part and storage capacitor can be completed. Then, these are connected to individual pixels. By arranging the pixels in a matrix, an active matrix type It can be one of the substrates for manufacturing a display device. Such a substrate is called an active matrix substrate.

[0202] When manufacturing an active matrix liquid crystal display device, an active matrix substrate a liquid crystal layer is provided between the active matrix substrate and an opposing substrate on which an opposing electrode is provided; The common electrode is electrically connected to the counter electrode provided on the counter substrate. A fourth terminal electrically connected to the common electrode is provided on the active matrix substrate. This fourth terminal is used to set the common electrode to a fixed potential, such as GND or 0V. This is a terminal for connecting the

[0203] In addition, the capacitance wiring is not provided, and the pixel electrode is connected to the gate wiring of the adjacent pixel, the protective insulating film, and the gate A storage capacitor may be formed by stacking the layers with an insulating layer interposed therebetween.

[0204] In an active matrix liquid crystal display device, pixel electrodes arranged in a matrix form By driving the selected pixels, a display pattern is formed on the screen. A voltage is applied between the electrode and the counter electrode corresponding to the pixel electrode. The liquid crystal layer disposed between the electrode and the counter electrode is optically modulated, and this optical modulation produces a display pattern. is perceived by the observer as

[0205] When displaying moving images on a liquid crystal display device, the response of the liquid crystal molecules themselves is slow, which can cause afterimages. In order to improve the moving image characteristics of the LCD device, There is a driving technique called black insertion, which displays black every other frame.

[0206] In addition, video characteristics can be improved by increasing the normal vertical synchronization frequency by 1.5 or 2 times or more. There is also a driving technology called double speed driving, in which the speed is increased by 100 ps.

[0207] In addition, in order to improve the video characteristics of the LCD display, multiple LEDs (light emitting diodes) are used as backlights. A surface light source is formed by using a diode) light source or multiple EL light sources, etc., and a surface light source is formed. There is also a driving technology that drives each light source to light intermittently within one frame period. Therefore, three or more types of LEDs may be used, or white-emitting LEDs may be used. Since multiple LEDs can be controlled, the LE can be switched in accordance with the timing of the optical modulation of the liquid crystal layer. This driving technology can also synchronize the timing of the LEDs to be turned off. This is especially useful when displaying images with a large proportion of black areas occupying the entire screen. This can reduce power consumption.

[0208] By combining these driving technologies, the display characteristics such as the video characteristics of the LCD device can be improved. can be improved compared to the past.

[0209] The n-channel transistor disclosed in this specification has an oxide semiconductor film as a channel formation region. These drive technologies can be combined due to their good dynamic characteristics. do.

[0210] In addition, when a light-emitting display device is manufactured, one electrode (also called a cathode) of the organic light-emitting element is In order to set the low power supply potential, for example, GND or 0V, the cathode is connected to the terminal. A fourth terminal is provided for setting the voltage level, for example, GND, 0V, etc. When manufacturing a device, a power supply line is provided in addition to a source line and a gate line. Therefore, the terminal section is provided with a fifth terminal that is electrically connected to the power supply line.

[0211] In addition, when manufacturing a light-emitting display device, a partition wall using an organic resin layer is provided between each organic light-emitting element. In that case, the oxide semiconductor layer 103 is heated to perform the heat treatment on the organic resin layer. By increasing the resistance, the electrical characteristics of the transistor are improved and the thermal It can also be used for processing.

[0212] The purity of the oxide semiconductor film is increased by reducing impurities such as moisture through heat treatment. Therefore, special sputtering equipment with a lowered dew point in the deposition chamber and ultra-high purity oxide Even without using a semiconductor target, it is possible to produce thin film transistors with good electrical properties and high reliability. A semiconductor device can be manufactured.

[0213] The oxide semiconductor layer in the channel formation region is a high resistance region, so the electrical conductivity of the thin film transistor is The characteristics are stabilized and the increase in off-current can be prevented. Therefore, the electrical characteristics are good. Therefore, it is possible to obtain a semiconductor device having a highly reliable thin film transistor.

[0214] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0215] (Fourth embodiment) A semiconductor device and a manufacturing method thereof will be described with reference to FIGS. The parts or parts having similar functions and steps can be performed in the same manner as in the first embodiment. , and repeated explanations will be omitted.

[0216] The thin film transistor 462 shown in FIG. 17 includes a gate electrode layer 401 and an oxide semiconductor layer 403. The source wiring 425 is formed in the same layer as the source wiring 425 via an oxide insulating film 407 so as to overlap the channel region of the source wiring 425. In this example, a conductive layer 409 is provided.

[0217] 17 is a cross-sectional view of a thin film transistor 462 included in the semiconductor device. 462 is a bottom gate type thin film transistor, and a substrate 4 400, a gate electrode layer 401, a gate insulating layer 402, an oxide semiconductor layer 403, a source electrode Polar or drain electrode layers 405a and 405b, an oxide insulating film 407, and a source wiring 425 and a conductive layer 409. The conductive layer 409 is formed by depositing an oxide film over the gate electrode layer 401. It is provided on an insulating film 407. Although not shown in FIG. 17, the same Similarly, gate wiring and connection electrode layers are also provided.

[0218] The conductive layer 409 is formed using a material and a method similar to those of the source wiring 425 described in Embodiment 1. When a pixel electrode layer is provided, the same material and method as those for the pixel electrode layer can be used. In this embodiment, the conductive layer 409 is formed of a low-temperature material such as aluminum or copper. A resistive conductive material is used.

[0219] The conductive layer 409 may have a potential that is the same as or different from that of the gate electrode layer 401. The conductive layer 409 can also function as a gate electrode layer of the floating gate electrode 402. It may be in a state.

[0220] By providing the conductive layer 409 so as to overlap with the oxide semiconductor layer 403, a thin film transistor In the bias-thermal stress test (hereinafter referred to as BT test) to check the reliability of the This reduces the amount of change in the threshold voltage of the thin film transistor 462 before and after the BT test. In particular, after the substrate temperature is raised to 150°C, the voltage applied to the gate is reduced to -2 In the -BT test where the voltage is set to 0 V, the fluctuation of the threshold voltage can be suppressed.

[0221] This embodiment mode can be freely combined with Embodiment Mode 1.

[0222] (Embodiment 5) A semiconductor device and a manufacturing method thereof will be described with reference to FIGS. The parts or parts having similar functions and steps can be performed in the same manner as in the first embodiment. , and repeated explanations will be omitted.

[0223] The thin film transistor 463 shown in FIG. 18 includes a gate electrode layer 401 and an oxide semiconductor layer 403. The conductive layer 4 is formed on the channel region 401 via the oxide insulating film 407 and the insulating layer 410. 19 is provided.

[0224] FIG. 18 is a cross-sectional view of a thin film transistor 463 included in the semiconductor device. The transistor 463 is a bottom-gate thin film transistor, and the substrate 463 is a substrate having an insulating surface. On the substrate 400, a gate electrode layer 401, a gate insulating layer 402, an oxide semiconductor layer 403, a source regions or drain regions 404a, 404b, a source electrode layer or drain electrode layer 405 a, 405b, the oxide insulating film 407, the insulating layer 410, the source wiring 425, and the conductive layer 419 The conductive layer 419 is provided over the insulating layer 410 so as to overlap with the gate electrode layer 401. Although not shown in FIG. 18, gate wiring and connecting voltage are provided in the same manner as in the first embodiment. A pole layer is also provided.

[0225] In this embodiment, an oxide semiconductor layer is formed over the gate insulating layer 402, and then an oxide semiconductor The source and drain regions 404a and 404b are then formed on the layer. Layers 405a and 405b are formed, and an oxide insulating film 407 is formed. After the oxide insulating film 407 is formed, heat treatment for dehydration or dehydrogenation is performed to form an oxide semiconductor film. The heat treatment is carried out in an oxygen gas atmosphere or an inert gas atmosphere (nitrogen, or helium, neon, argon, etc.) or under reduced pressure at 200°C to 700°C Preferably, the temperature is 350° C. or higher and lower than the distortion point of the substrate 400. After the heat treatment, the substrate is inactivated. It is preferable to perform slow cooling in an atmosphere or an oxygen atmosphere. This makes it possible to recover from plasma damage that occurs when the oxide insulating film 407 is formed. A contact hole is formed in the oxide insulating film 407, and a source electrode layer 405a is formed therein. The source wiring 425 is formed.

[0226] In this embodiment, the source and drain regions 404a and 404b are made of Zn—O-based polycrystalline silicon. The oxide semiconductor layer 403 is formed under different conditions from those for forming the oxide semiconductor layer 403. The source region is formed of a silicon dioxide film and has a lower resistance than the oxide semiconductor layer. The drain and gate regions 404a, 404b are polycrystalline or microcrystalline, and the oxide The semiconductor layer 403 is also polycrystalline or microcrystalline. It can be crystallized by heat treatment to a polycrystalline or microcrystalline state.

[0227] The thin film transistor described in this embodiment has a film formed on the oxide insulating film 407 which functions as a planarizing film. The insulating layer 410 is then stacked over the oxide insulating film 407 and the insulating layer 410. An oxide insulating film 407 having an opening reaching the drain electrode layer 405b and an insulating layer 410 are formed. A conductive film is formed in the opening and etched into a desired shape to form the conductive layer 419 and the pixel electrode layer In this way, in the process of forming the pixel electrode layer 411, the conductive layer 419 is formed. In this embodiment mode, the pixel electrode layer 411 and the conductive layer 419 are made of silicon oxide. Indium oxide tin oxide alloy (In-Sn-O oxide containing silicon oxide) is used. .

[0228] The conductive layer 419 is formed between the gate electrode layer 401 and the source or drain electrode layer 405. The wirings 405a and 405b may be formed using the same material and manufacturing method as the source wiring 425.

[0229] The conductive layer 419 may have the same potential as the gate electrode layer 401. Alternatively, the conductive layer 419 may have a different potential. The conductive layer 419 can also function as a second gate electrode layer. 419 may be in a floating state.

[0230] By providing the conductive layer 419 so as to overlap with the oxide semiconductor layer 403, a thin film transistor The threshold voltage of the transistor 463 can be controlled.

[0231] This embodiment mode can be freely combined with Embodiment Mode 1.

[0232] (Embodiment 6) In this embodiment, an example of a channel stop thin film transistor 1430 will be described with reference to FIG. 9(A), 19(B) and 19(C). Also, FIG. 19(C) shows a thin film. This is an example of a top view of a transistor, and the cross section taken along the chain line Z1-Z2 in the figure is shown in Figure 19( In addition, the oxide semiconductor layer of the thin film transistor 1430 does not contain gallium. This embodiment shows a configuration in which a thin oxide semiconductor material is used.

[0233] In FIG. 19A, a gate electrode layer 1401 is formed over a substrate 1400. The base electrode layer is formed in the same manner as in the first embodiment so as to be able to withstand the heat treatment to be performed in the subsequent step. It is preferable to use a heat-resistant conductive material such as the above. A gate insulating layer 1402 is formed. Then, an oxide semiconductor layer Form 1403.

[0234] In this embodiment, the oxide semiconductor layer 1403 is formed by a sputtering method using Sn—Zn By not using gallium in the oxide semiconductor layer, Since it is possible to form the film without using a high-quality target, costs can be reduced.

[0235] Next, a channel protective layer 1418 is formed in contact with the oxide semiconductor layer 1403. By forming a channel protection layer 1418 on the semiconductor layer 1403, the source region and damage during the process of forming the drain regions 1406a and 1406b (during etching) This prevents the thin film from being thinned by plasma or etching agents. This can improve the reliability of the controller 1430.

[0236] After the oxide semiconductor layer 1403 is formed, a channel protective layer is successively formed without being exposed to the air. 1418 can also be formed. By continuously treating without exposure to air, The interface is contaminated with atmospheric components such as water and hydrocarbons, or impurity elements floating in the air. Since each lamination interface can be formed without any defects, variations in thin film transistor characteristics can be reduced. can be reduced.

[0237] The channel protection layer 1418 is made of an inorganic material containing oxygen (silicon oxide, silicon oxynitride, nitride, etc.). The method of fabrication can be plasma CVD or thermal CVD. The channel protection layer 1418 can be formed by vapor deposition or sputtering. After film formation, the shape is processed by etching. Here, a silicon oxide film is formed by sputtering. Then, a channel is formed by etching using a photolithography mask. A protective layer 1418 is formed.

[0238] Next, a source region and a drain region are formed on the channel protection layer 1418 and the oxide semiconductor layer 1403. In this embodiment, source and drain regions 1406a and 1406b are formed. The regions 1406a and 1406b are Zn—O-based microcrystalline films or Zn—O-based polycrystalline films, The oxide semiconductor layer 1402 is formed under different deposition conditions from those of the oxide semiconductor layer 1403 and has lower resistance. do.

[0239] Next, a source electrode layer 1405a is formed on the source region 1406a, and a drain electrode layer 1406b is formed on the drain region 1406b. A drain electrode layer 1405b is formed on each of the thin film transistors 1430. (See FIG. 19B). The source electrode layer 1405a and the drain electrode layer 1405b are The source electrode layer 405a and the drain electrode layer 405b can be formed in a manner similar to that of the source electrode layer 405a and the drain electrode layer 405b described in Mode 1. It is preferable to use a heat-resistant conductive material. A connection electrode layer 1420 is formed for this purpose.

[0240] The source and drain regions 1406a and 1406b are formed by the oxide semiconductor layer 1403 and the source By providing the metal layer between the source electrode layer 1405a and the drain electrode layer 1405b, A source electrode layer 1405a, a drain electrode layer 1405b, and an oxide semiconductor layer 1403 It is possible to achieve a good junction between the electrodes, and the junction is thermally stable compared to a Schottky junction. In addition, the low resistance allows good mobility to be maintained even at high drain voltages. Cut.

[0241] Furthermore, the present invention is not limited to the structure having the source and drain regions 1406a and 1406b described above. For example, a structure without a source region and a drain region may be used.

[0242] Next, the source electrode layer 1405a, the drain electrode layer 1405b, and the channel protective layer 141 The oxide insulating film 1407 is formed to cover the insulating film 8. The oxide insulating film 1407 is formed to a thickness of 1 nm or more by a CVD method, a sputtering method, or the like. The oxide insulating film can be formed by appropriately using a method that does not allow impurities such as hydrogen to be mixed in. 1407 is water, hydrogen ions, OH - It does not contain impurities such as An inorganic insulating film that blocks the intrusion of silicon is used. Typically, a silicon oxide film or a silicon nitride oxide film is used. An aluminum oxide film or an aluminum oxynitride film is used. A silicon nitride film or an aluminum nitride film may be laminated on and in contact with O7.

[0243] Next, for dehydration or dehydrogenation, the mixture is heated in an oxygen gas atmosphere or an inert gas atmosphere (nitrogen, Heat treatment is carried out under a gas such as helium, neon, argon, etc., or under reduced pressure. The treatment is carried out at a temperature of 200° C. or higher and 700° C. or lower, preferably 350° C. or higher and lower than the strain point of the substrate 1400. After the heat treatment, it is preferable to slowly cool the substrate in an oxygen atmosphere. It is enough to slowly cool it down until the temperature drops by at least 50 to 100 degrees Celsius from the highest temperature during heating. In this embodiment, the oxide semiconductor layer 1403 is in a microcrystalline state or a polycrystalline state. In addition, by carrying out this heat treatment, the variations in the electrical characteristics of the thin film transistors are reduced. It is possible.

[0244] Next, a first contact hole, a second contact hole, and a third contact hole were formed in the oxide insulating film 1407. First, the first contact hole and the fourth contact hole are formed by etching. By removing part of the oxide insulating film 1407, a layer reaching the source electrode layer 1405a is formed. The first contact hole and one of the second contact holes reaching the gate electrode layer 1401 and a third contact hole and a fourth contact hole reaching both ends of the connection electrode layer 1420. Further, a part of the gate insulating layer 1402 is removed by etching. By this, a second contact hole reaching the gate electrode layer 1401 is formed.

[0245] Next, a second conductive film is formed over the oxide insulating film 1407. A gate wiring 1425, a first gate wiring 1426, and a second gate wiring 1427 are formed ( (See FIG. 19C.) The second conductive film is formed using the same material as that of the second conductive film shown in Embodiment 1. It is preferable to use a low resistance conductive material such as aluminum or copper. The source wiring 1425 overlaps with the connection electrode layer 1420, and the first contact hole The source wiring 1425 is formed so as to be connected to the source electrode layer 1405a via the source wiring 1425. A first gate wiring 1426 and a second gate wiring 1427 are formed so as to surround the first gate wiring 1426 and the second gate wiring 1427. The first gate wiring 1426 is connected to the gate electrode layer 1401 through the second contact hole. and formed to be connected to the connection electrode layer 1420 via the third contact hole. The second gate wiring 1427 is connected to the connection electrode 1428 through a fourth contact hole. The first gate wiring 1426 and the second gate wiring 1427 are connected to each other. The gate wiring 1427 is electrically connected via the connection electrode layer 1420 .

[0246] Through the above steps, the thin film transistor 1430 can be formed.

[0247] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0248] (Embodiment 7) A semiconductor device and a manufacturing method thereof will be described with reference to FIGS. 20A and 20B. The same parts as those in the sixth embodiment or parts and steps having similar functions are the same as those in the sixth embodiment. The same procedure can be carried out as above, and a repeated explanation will be omitted.

[0249] The thin film transistor 1431 shown in FIG. 20A includes a gate electrode layer 1401 and an oxide semiconductor A channel protection layer 1418 and an oxide insulating film 1414 are formed so as to overlap the channel region of the layer 1403. In this example, the conductive layer 1409 is provided with the insulating film 07 interposed therebetween.

[0250] FIG. 20A is a cross-sectional view of a thin film transistor 1431 included in a semiconductor device. The transistor 1431 is a bottom-gate thin film transistor, and is mounted on a substrate with an insulating surface. On a substrate 1400, a gate electrode layer 1401, a gate insulating layer 1402, an oxide semiconductor layer 1403, source or drain regions 1406a, 1406b, and a source electrode layer or or drain electrode layers 1405a and 1405b, an oxide insulating film 1407, and a source wiring 142 5, a conductive layer 1409. The conductive layer 1409 is formed so as to overlap the gate electrode layer 1401. The insulating film 1407 is formed over the oxide insulating film 1407. Note that although not shown in FIG. As in the first embodiment, gate wiring and connection electrode layers are also provided.

[0251] As in Embodiment 6, after the oxide insulating film 1407 is formed, heat treatment is performed to dehydrate or A dehydrogenated or hydrogenated oxide semiconductor layer 1403 is formed.

[0252] In this embodiment, the source and drain regions 14 formed on the oxide semiconductor layer 06a, 1406b are Zn-O based microcrystalline films or Zn-O based polycrystalline films, and are oxide semiconductors. The oxide semiconductor layer 1403 is formed under different deposition conditions from those of the conductor layer 1403. The oxide semiconductor layer 1403 has low resistance and is amorphous.

[0253] The conductive layer 1409 is formed using a material and a method similar to those of the source wiring 1425 described in Embodiment 1. When a pixel electrode layer is provided, the same material and method as those for the pixel electrode layer can be used. In this embodiment, the conductive layer 1409 is formed of aluminum, copper, or the like. Which low resistance conductive material is used?

[0254] The conductive layer 1409 may have the same potential as the gate electrode layer 1401 or may have a different potential. The conductive layer 1409 can also function as a second gate electrode layer. It may be in a moving state.

[0255] By providing the conductive layer 1409 so as to overlap with the oxide semiconductor layer 1403, a thin film transistor Bias-thermal stress test (hereinafter referred to as BT test) is used to check the reliability of transistors. In this test, the amount of change in the threshold voltage of the thin film transistor 1431 before and after the BT test is reduced. It is possible.

[0256] Also, Fig. 20(B) shows an example that is partially different from Fig. 20(A). The parts and steps having the same functions as those in FIG. 20(A) can be carried out repeatedly. The explanation of this will be omitted.

[0257] The thin film transistor 1432 shown in FIG. 20B includes a gate electrode layer 1401 and an oxide semiconductor A channel protection layer 1418 and an oxide insulating film 140 are formed so as to overlap the channel region of the layer 1403. 7 and a conductive layer 1409 is provided with an insulating layer 1408 interposed therebetween.

[0258] The thin film transistor 1432 is formed as follows: Heat treatment for dehydration or dehydrogenation is performed to form the oxide semiconductor layer 1403. under an oxygen gas atmosphere, an inert gas atmosphere (nitrogen, helium, neon, argon, etc.) ) or under reduced pressure at 200° C. or higher and 700° C. or lower, preferably 350° C. or higher, for the substrate 14 After heat treatment, the temperature is lowered to below the strain point of 0.00. Then, a contact hole is formed in the oxide insulating film 1407. A source wiring 1425 connected to the source electrode layer 1405a is formed.

[0259] In FIG. 20B, an insulating layer 1408 functioning as a planarizing film is formed over the oxide insulating film 1407. Layering.

[0260] 20B, the source region or the drain region is not provided, and the oxide semiconductor layer 14 03 and the source electrode layer or the drain electrode layer 1405a, 1405b are in direct contact with each other. It is.

[0261] In the structure of FIG. 20B, the conductive layer 1409 is By providing this, in the BT test to check the reliability of thin film transistors, The amount of change in the threshold voltage of the thin film transistor 1432 before and after the T test can be reduced. can.

[0262] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0263] (Embodiment 8) In this embodiment, an example in which the structure is partially different from that of the first embodiment is shown in FIG. The same parts or parts having similar functions and steps can be performed in the same manner as in the first embodiment. Therefore, repeated explanations will be omitted.

[0264] In this embodiment, after the first oxide semiconductor layer is formed, a thin film transistor is formed on the first oxide semiconductor layer. The source and drain regions of the transistor (n + layer, also called buffer layer) After the oxide semiconductor film 2 is formed, a conductive film is formed.

[0265] Next, the first oxide semiconductor layer, the second oxide semiconductor film, and the conductive film are subjected to an etching process. The oxide semiconductor layer 403 and the source or drain region are removed by more selective etching. 404a and 404b, and source and drain electrode layers 405a and 405b are formed. Note that the oxide semiconductor layer 403 is only partly etched to have a groove (a depression). .

[0266] Next, a silicon oxide film is formed on the oxide semiconductor layer 403 by a sputtering method or a PCVD method. The oxide insulating film 407 is formed in contact with the oxide semiconductor layer having a low resistance. The oxide insulating film 407 is resistant to moisture, hydrogen ions, and OH ions. - It does not contain impurities such as Inorganic insulating films are used to block the intrusion of foreign substances from the outside. Specifically, silicon oxide films and nitride films are used. A silicon oxide film, an aluminum oxide film, or an aluminum oxynitride film is used. A silicon nitride film or an aluminum nitride film may be laminated on the insulating film 407 .

[0267] As in Embodiment 1, after the oxide insulating film 407 is formed, heat treatment for dehydration or dehydrogenation is performed. The heat treatment is performed in an oxygen gas atmosphere or an inert gas atmosphere to form the oxide semiconductor layer 403. 20 under a gas atmosphere (nitrogen, helium, neon, argon, etc.) or reduced pressure The temperature is set to 0° C. or higher and 700° C. or lower, preferably 350° C. or higher and lower than the strain point of the substrate 400. After the heat treatment, it is preferable to slowly cool the material in an inert atmosphere or an oxygen atmosphere. In addition, this heat treatment serves to repair plasma damage caused during the formation of the oxide insulating film 407. Then, a contact hole is formed in the oxide insulating film 407, and a source electrode A source wiring 425 connected to the layer 405a is formed. In this way, a thin film transistor 464 can be produced (see Figure 21).

[0268] In the structure of FIG. 21, the source and drain regions 404a and 404b are The source and drain regions 404a are made of In-Ga-Zn-O based non-single crystal. , 404b can be made of an Al-Zn-O based amorphous film. The drain regions 404a and 404b are made of an Al-Zn-O-based amorphous film containing nitrogen, i.e., A A l-Zn-ON amorphous film (also called AZON film) may also be used.

[0269] A source region is formed between the oxide semiconductor layer 403 and the source electrode layer. A drain region is formed between the gate electrode layer and the gate electrode layer.

[0270] The source and drain regions 404a and 404b of the thin film transistor 464 are The second oxide semiconductor layer used as a channel formation region is a second oxide semiconductor layer used as a channel formation region. It is preferable that the thickness of the film is thinner than that of the film 403 and that the film has a higher electrical conductivity.

[0271] The first oxide semiconductor layer 403 used as a channel formation region has an amorphous structure. The second oxide semiconductor layer used as the source and drain regions has an amorphous structure with crystalline grains. The source and drain regions may contain nanocrystals. The crystal grains (nanocrystals) in the oxide semiconductor layer 2 have a diameter of 1 nm to 10 nm, typically It is about 2nm to 4nm.

[0272] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0273] (Embodiment 9) In this embodiment, at least a part of the driver circuit and a thin film transistor disposed in the pixel portion are formed on the same substrate. An example of fabricating a transistor will be described below.

[0274] The thin film transistors arranged in the pixel portion are formed according to any one of the first to eighth embodiments. The thin film transistors described in Embodiments 1 to 8 are n-channel TFTs. Therefore, some of the driver circuits can be configured with n-channel TFTs. The thin film transistors in the pixel portion are formed on the same substrate.

[0275] An example of a block diagram of an active matrix display device is shown in FIG. A pixel portion 5301, a first scanning line driver circuit 5302, a second scanning line driver circuit 5303, and a third scanning line driver circuit 5304 are provided on a substrate 5300. The pixel portion 5301 has a signal line driver circuit 5303 and a signal line driver circuit 5304. are arranged extending from the signal line driver circuit 5304, and a plurality of scanning lines are arranged in the first scanning line driver circuit The scanning line driver circuit 5302 and the second scanning line driver circuit 5303 are arranged to extend from each other. In the intersections of the signal lines and the wiring, pixels each having a display element are arranged in a matrix. The substrate 5300 of the display device is made of FPC (Flexible Printed Circuit). A timing control circuit 5305 (controller, control I) is connected to the timing control circuit 5305 via a connection part such as a C).

[0276] In FIG. 22A, a first scanning line driver circuit 5302, a second scanning line driver circuit 5303, a signal The signal line driver circuit 5304 is formed on the same substrate 5300 as the pixel portion 5301. This reduces the number of externally provided components such as drive circuits, thereby reducing costs. In addition, when a driving circuit is provided outside the substrate 5300, the wiring is extended to provide a connection portion. The number of connections can be reduced, and the reliability or yield can be improved.

[0277] The timing control circuit 5305 controls the first scanning line driver circuit 5302 as follows: The first scanning line driving circuit start signal (GSP1), the scanning line driving circuit clock signal (GCK1). The timing control circuit 5305 also supplies the second scanning line driving circuit For example, the second scanning line driver circuit start signal (GSP2) (start The signal line supplies the clock signal (GCK2) for the scanning line driver circuit. The driver circuit 5304 is provided with a start signal (SSP) for the signal line driver circuit, a clock for the signal line driver circuit, and a Clock signal (SCK), video signal data (DATA) (also simply called video signal), Each clock signal is a multiple of clock signals with different periods. It may be a clock signal or may be supplied together with an inverted clock signal (CKB). The first scanning line driver circuit 5302 and the second scanning line driver circuit 53 It is possible to omit either 03 or 04.

[0278] In FIG. 22B, circuits with low driving frequencies (for example, the first scanning line driving circuit 5302, the The second scanning line driver circuit 5303 is formed on the same substrate 5300 as the pixel portion 5301, and the signal line driver The configuration in which the driving circuit 5304 is formed on a substrate different from that of the pixel portion 5301 is shown. Due to its structure, thin-film transistors have lower field-effect mobility than transistors using single-crystal semiconductors. The driving circuit formed on the substrate 5300 can be configured by the film transistor. Therefore, it is possible to increase the size of the display device, reduce the number of processes, reduce costs, or improve yields. This can be achieved.

[0279] The thin film transistors described in any of Embodiments 1 to 8 are n-channel TFTs. In FIG. 23(A) and FIG. 23(B), a signal line driver circuit configured with an n-channel TFT is shown. An example of the configuration and operation will be described below.

[0280] The signal line driver circuit includes a shift register 5601 and a switching circuit 5602 . The switching circuit 5602 is composed of switching circuits 5602_1 to 5602_N (N is a natural number). The switching circuits 5602_1 to 5602_N each have a plurality of circuits. , a plurality of thin film transistors 5603_1 to 5603_k (k is a natural number) The thin film transistors 5603_1 to 5603_k are N-channel TFTs. An example will be explained.

[0281] The connection relationship of the signal line driver circuit will be described using the switching circuit 5602_1 as an example. The first terminals of the thin film transistors 5603_1 to 5603_k are connected to the wirings 5604_1 The second terminals of the thin film transistors 5603_1 to 5603_k are connected to the first terminals of the thin film transistors 5603_1 to 5603_k. are connected to the signal lines S1 to Sk, respectively. The gate of k is connected to the wiring 5605_1.

[0282] The shift register 5601 sequentially outputs H level (H signal) to the wirings 5605_1 to 5605_N. , also referred to as a high power supply potential level), and the switching circuits 5602_1 to 56 It has the function of selecting 02_N in order.

[0283] The switching circuit 5602_1 is connected to the wirings 5604_1 to 5604_k and the signal lines S1 to Sk. the wiring 5604_ The switches have the function of controlling whether or not the potentials of 1 to 5604_k are supplied to the signal lines S1 to Sk. In this way, the switching circuit 5602_1 has a function as a selector. The film transistors 5603_1 to 5603_k are connected to the wirings 5604_1 to 5604_k, respectively. and the signal lines S1 to Sk, that is, the wirings 5604_1 to 5604_k. The thin film transistor 56 has a function of supplying the potential of the signal lines S1 to Sk. Each of 03_1 to 5603_k functions as a switch.

[0284] The wirings 5604_1 to 5604_k each carry video signal data (DATA). The video signal data (DATA) is an analog signal corresponding to the image information or image signal. This is often a signal.

[0285] Next, the operation of the signal line driver circuit of FIG. 23(A) will be explained with reference to the timing chart of FIG. 23(B). 23B shows signals Sout_1 to Sout_N and An example of Vdata_1 to Vdata_k is shown. are examples of output signals of the shift register 5601, and signals Vdata_1 to Vdata _k are examples of signals input to the wirings 5604_1 to 5604_k, respectively. One operation period of the signal line driving circuit corresponds to one gate selection period in the display device. The selection period is divided into periods T1 to TN, for example. This is the period for writing video signal data (DATA) to the pixels belonging to the selected row. be.

[0286] During the period T1 to the period TN, the shift register 5601 outputs a high-level signal to the wiring 560 For example, in the period T1, the shift registers 5 601 outputs a high-level signal to the wiring 5605_1. 5603_1 to 5603_k are turned on, so the wiring 5604_1 to 5604_k and the signal At this time, the wirings 5604_1 to 5604_k are in a conductive state. Data(S1)~Data(Sk) are input. Data(S1)~Data(Sk ) belong to the selected row via thin film transistors 5603_1 to 5603_k. In this way, during the periods T1 to TN, the pixels in the first to k-th columns are written. Then, the video signal data (DATA) is sent to the pixels belonging to the selected row in order of k columns. It will be written.

[0287] As described above, video signal data (DATA) is written to pixels in multiple columns. This makes it possible to reduce the number of video signal data (DATA) or the number of wirings. This reduces the number of connections to external circuits. A) By writing to pixels in multiple columns, the writing time can be extended. This makes it possible to prevent insufficient writing of video signal data (DATA).

[0288] The shift register 5601 and the switching circuit 5602 are the same as those in the first embodiment. It is possible to use a circuit configured with the thin film transistors shown in the eighth embodiment. In this case, the polarity of all the transistors in the shift register 5601 is changed to N-channel type or can be constructed with only one polarity of P-channel type.

[0289] Regarding one form of a shift register used in a part of a scanning line driver circuit and / or a signal line driver circuit, This will be explained with reference to FIGS. 24 and 25.

[0290] The scanning line driving circuit has a shift register. In some cases, it may also have a level shifter or a buffer. In the scanning line driver circuit, a clock signal is input to the shift register. A selection signal is generated by inputting a clock (CK) and a start pulse signal (SP). The generated selection signal is buffered and amplified in a buffer and then supplied to the corresponding scanning line. The gate electrodes of the transistors of the pixels for one line are connected to the scanning line. Therefore, the transistors of the pixels in one line must be turned on simultaneously, so a buffer The resistor is capable of passing a large current.

[0291] The shift register includes the first pulse output circuit 10_1 to the N-th pulse output circuit 10_N ( N is a natural number of 3 or more (see FIG. 24(A)). The first pulse output circuit 10_1 to the N-th pulse output circuit 10_N of the register are A first clock signal CK1 is transmitted from a wiring 11, and a second clock signal CK2 is transmitted from a second wiring 12. , a third clock signal CK3 is transmitted from the third wiring 13, and a fourth clock signal CK4 is transmitted from the fourth wiring 14. In the first pulse output circuit 10_1, a signal CK4 is supplied from the fifth wiring 15. A start pulse SP1 (first start pulse) is input. In the pulse output circuit 10_n (n is a natural number between 2 and N), A signal from the previous stage (called OUT(n-1)) (n is a natural number greater than or equal to 2) is input. In addition, the first pulse output circuit 10_1 receives a pulse from the third pulse output circuit 10_3, which is two stages later. In the n-th pulse output circuit 10_n of the second stage or later, the (n+ 2) The signal from the pulse output circuit 10_(n+2) (called the subsequent signal OUT(n+2)) Also, the pulse output circuit of each stage outputs the pulse to the previous and / or next stage. A first output signal OUT(1)(SR) to be input to a line, a second output signal OUT(2)(SR) to be input to another line, etc. As shown in FIG. 24(A), the output signal OUT(1) is output. The last two stages of the converter do not receive the next stage signal OUT(n+2). separately input the second start pulse SP2 and the third start pulse SP3, respectively. This can be configured as follows.

[0292] The clock signal (CK) alternates between H level and L level (L signal, low power supply potential) at regular intervals. Here, the first clock signal (CK1) to the second clock signal (CK2) are signals that repeat a cycle of 1 / 2 levels. The fourth clock signal (CK4) is delayed by 1 / 4 cycle in order. The first clock signal (CK1) to the fourth clock signal (CK4) are used to generate a pulse output circuit. The clock signal is controlled by the GCK It is sometimes called SCK, but here we will explain it as CK.

[0293] The first input terminal 21, the second input terminal 22, and the third input terminal 23 are connected to the first wiring 11. 24(A) is electrically connected to any one of the first to fourth wirings 14. For example, in FIG. The first pulse output circuit 10_1 has a first input terminal 21 electrically connected to the first wiring 11. The second input terminal 22 is electrically connected to the second wiring 12, and the third input terminal 23 is is electrically connected to the third wiring 13. In addition, the second pulse output circuit 10_2 has The first input terminal 21 is electrically connected to the second wiring 12, and the second input terminal 22 is electrically connected to the third wiring 13. The third input terminal 23 is electrically connected to the wiring 13, and the third input terminal 24 is electrically connected to the fourth wiring 14. are.

[0294] Each of the first pulse output circuit 10_1 to the N-th pulse output circuit 10_N has a first input terminal 21, a second input terminal 22, a third input terminal 23, a fourth input terminal 24, a fifth input terminal 24(B) , the first output terminal 25, the second output terminal 26, and the second output terminal 27. In the first pulse output circuit 10_1, a first clock signal is input to a first input terminal 21. A first clock signal CK1 is input to the first input terminal 21, a second clock signal CK2 is input to the second input terminal 22, and a third clock signal CK3 is input to the third input terminal 23. A third clock signal CK3 is input to the input terminal 23 of the clock generator 10, and a start signal CK4 is input to the fourth input terminal 24 of the clock generator 10. A pulse is input, the subsequent signal OUT(3) is input to the fifth input terminal 25, and the first output The first output signal OUT(1)(SR) is output from the terminal 26, and the second output signal OUT(1)(SR) is output from the second output terminal 27. The second output signal OUT(1) is output.

[0295] Next, an example of a specific circuit configuration of the pulse output circuit shown in FIG. 24(B) will be described with reference to FIG. This is explained in (C).

[0296] The pulse output circuit shown in FIG. 24(C) includes the first transistor 31 to the thirteenth transistor. The first input terminal 21 to the fifth input terminal 25, In addition to the first output terminal 26 and the second output terminal 27, a voltage source to which a first high power supply potential VDD is supplied is also provided. A power supply line 51, a power supply line 52 to which a second high power supply potential VCC is supplied, and a power supply line 53 to which a low power supply potential VSS is supplied. A signal is sent from the power supply line 53 to the first transistor 31 to the thirteenth transistor 43, and The power supply potential is supplied to the power supply lines. Here, the magnitude relationship of the power supply potentials of the power supply lines in FIG. 24(C) is as follows: The power supply potential VDD of the third power supply is set to a potential equal to or higher than the second power supply potential VCC. The potential is set to be higher than the power supply potential VSS of the first clock signal (CK1) to the fourth clock signal (CK2). The clock signal (CK4) is a signal that alternates between H level and L level at regular intervals. When it is at H level, it is VDD, and when it is at L level, it is VSS. By making D higher than the potential VCC of the power supply line 52, The potential applied to the gate electrode of the transistor can be kept low, This reduces the threshold shift and suppresses degradation.

[0297] In FIG. 24C, the first terminal of the first transistor 31 is electrically connected to the power supply line 51. the second terminal of the ninth transistor 39 is electrically connected to the first terminal of the ninth transistor 39, and the gate electrode of the The second transistor 32 has a first terminal electrically connected to the fourth input terminal 24. The second terminal is electrically connected to the power supply line 53, and the second terminal is electrically connected to the first terminal of the ninth transistor 39. and a gate electrode electrically connected to the gate electrode of the fourth transistor 34. The third transistor 33 has a first terminal electrically connected to the first input terminal 21 and a second terminal electrically connected to the first input terminal 21. The second terminal is electrically connected to the first output terminal 26. The fourth transistor 34 One terminal is electrically connected to the power supply line 53, and the second terminal is electrically connected to the first output terminal 26. The fifth transistor 35 has a first terminal electrically connected to the power supply line 53 and a second terminal electrically connected to the power supply line 53. The two terminals are the gate electrode of the second transistor 32 and the gate electrode of the fourth transistor 34. and the gate electrode is electrically connected to the fourth input terminal 24. The transistor 36 has a first terminal electrically connected to the power supply line 52 and a second terminal electrically connected to the second transistor 36. The gate electrode of the fourth transistor 32 and the gate electrode of the fourth transistor 34 are electrically connected to each other. The seventh transistor 3 has a gate electrode electrically connected to the fifth input terminal 25. The first terminal of the transistor 7 is electrically connected to the power supply line 52, and the second terminal of the transistor 38 is electrically connected to the power supply line 52. The gate electrode is electrically connected to the second terminal and the gate electrode is electrically connected to the third input terminal 23. The eighth transistor 38 has a first terminal connected to the gate electrode of the second transistor 32 and a second terminal connected to the gate electrode of the second transistor 32. 4, and the gate electrode is electrically connected to the second input terminal 2 The ninth transistor 39 has a first terminal electrically connected to the first transistor 2. The second terminal is electrically connected to the second terminal of the first transistor 31 and the second terminal of the second transistor 32. The gate electrode of the third transistor 33 and the gate electrode of the tenth transistor 40 are supplied with a voltage. The gate electrode is electrically connected to the power supply line 51. The first terminal of the sigma 40 is electrically connected to the first input terminal 21, and the second terminal is electrically connected to the second output terminal 22. the gate electrode of the ninth transistor 39 is electrically connected to the second terminal of the ninth transistor 39. The eleventh transistor 41 has a first terminal electrically connected to the power supply line 53. The second terminal is electrically connected to the second output terminal 27, and the gate electrode is The gate electrode of the fourth transistor 32 and the gate electrode of the fourth transistor 34 are electrically connected to each other. The twelfth transistor 42 has a first terminal electrically connected to the power supply line 53 and a second terminal is electrically connected to the second output terminal 27, and the gate electrode is connected to the gate of the seventh transistor 37. The first terminal of the thirteenth transistor 43 is electrically connected to the power supply line 53. , the second terminal is electrically connected to the first output terminal 26, and the gate electrode is It is electrically connected to the gate electrode of the seventh transistor 37 .

[0298] In FIG. 24C, the gate electrode of the third transistor 33, the gate electrode of the tenth transistor 4 The connection point of the gate electrode of the ninth transistor 30 and the second terminal of the ninth transistor 39 is referred to as node A. The gate electrode of the second transistor 32, the gate electrode of the fourth transistor 34, the second terminal of the fifth transistor 35, the second terminal of the sixth transistor 36, the second terminal of the eighth transistor The connection point of the first terminal of the eleventh transistor 38 and the gate electrode of the eleventh transistor 41 is node B. Let's say.

[0299] FIG. 25(A) shows the pulse output circuit described in FIG. 24(C) as a first pulse output circuit 10_ 1, the first input terminal 21 to the fifth input terminal 25 and the first output terminal 26 and the signals input to or output from the second output terminal 27.

[0300] Specifically, a first clock signal CK1 is input to the first input terminal 21, and a second clock signal CK2 is input to the second input terminal 22. A second clock signal CK2 is input to the third input terminal 22, and a third clock signal CK3 is input to the third input terminal 23. A start pulse is input to the fourth input terminal 24, and a second input terminal CK3 is input. The next stage signal OUT(3) is input to the first output terminal 25, and the first output signal OUT (1)(SR) is output, and the second output signal OUT(1) is output from the second output terminal 27. will be done.

[0301] A thin film transistor is a transistor having at least three elements including a gate, a drain, and a source. The gate is a semiconductor element in which a channel region is formed in the region overlapping the gate. By controlling the gate potential, the drain and source are connected via the channel region. The source and drain are thin film transistors. Which is the source or drain depends on the transistor structure and operating conditions. Therefore, it is difficult to define the regions that function as the source and drain. In some cases, they are not called sources or drains. In such cases, for example, they are called first It may be written as terminal or second terminal.

[0302] In FIG. 24(C) and FIG. 25(A), the node A is set to a floating state. A capacitor may be provided separately to perform a strap operation. To achieve this, a capacitor having one electrode electrically connected to the node B may be provided separately.

[0303] Here, the timing of the shift register having a plurality of pulse output circuits shown in FIG. A shift chart is shown in FIG. 25(B). In this case, the period 61 in FIG. 25(B) corresponds to the vertical blanking period, and the period 62 corresponds to the gate selection period. do.

[0304] As shown in FIG. 25A, the ninth transistor, whose gate is supplied with the second power supply potential VCC, By providing the transistor 39, the following occurs before and after the bootstrap operation: There are advantages like this.

[0305] If the ninth transistor 39 having the second potential VCC applied to its gate electrode is not present, the boot When the potential at node A rises due to the strapping operation, the second terminal of the first transistor 31 The potential of the source, which is the first power supply potential VDD, rises and becomes higher than the first power supply potential VDD. The source of the first transistor 31 is switched to the first terminal side, that is, the power supply line 51 side. In the first transistor 31, the gate and source are electrically connected to each other, and the gate and drain are electrically connected to each other. In addition, a large bias voltage is applied, which causes a large stress and leads to transistor deterioration. Therefore, the ninth transistor, to whose gate electrode the second power supply potential VCC is applied, By providing transistor 39, the potential of node A is However, the potential of the second terminal of the first transistor 31 does not increase. That is, by providing the ninth transistor 39, the first transistor The negative bias voltage applied between the gate and source of the transistor 31 can be reduced. Therefore, by using the circuit configuration of this embodiment, the gate of the first transistor 31 The negative bias voltage applied between the gate and source can also be reduced, reducing the first-order This can suppress the deterioration of the transistor 31.

[0306] The ninth transistor 39 is provided at a location corresponding to the second gate of the first transistor 31. and a gate of the third transistor 33 via a first terminal and a second terminal. In this embodiment, a system having a plurality of pulse output circuits may be provided. In the case of a soft register, the signal line driver circuit has more stages than the scanning line driver circuit. The resistor 39 may be omitted, which has the advantage of reducing the number of transistors.

[0307] Note that the semiconductor layers of the first to thirteenth transistors 31 to 43 are made of oxide semiconductor. By using a conductor, the off-current of the thin film transistor is reduced, and the on-current and This allows for increased field effect mobility and reduced degradation. In addition, a transistor using an oxide semiconductor, Compared to transistors using amorphous silicon, a higher potential is applied to the gate electrode. Therefore, the degree of deterioration of the transistor due to the second power supply potential VCC is small. The same operation can be obtained by supplying the first power supply potential VDD to the power supply line, and the wiring between the circuits is This allows the number of power supply lines to be reduced, thereby enabling the circuit to be made smaller.

[0308] The gate electrode of the seventh transistor 37 is connected to the clock signal supplied from the third input terminal 23. A lock signal, supplied by the second input terminal 22 to the gate electrode of the eighth transistor 38 The clock signal to be output is input to the gate electrode of the seventh transistor 37 by the second input terminal 22. the gate electrode of the eighth transistor 38 is connected to the third input terminal 23 The same effect can be achieved by switching the wiring so that the clock signal is supplied by In the shift register shown in FIG. 25(A), the seventh transistor 37 and The seventh transistor 37 is turned off and the eighth transistor 38 is turned on. The transistor 38 is on, then the seventh transistor 37 is off, and the eighth transistor The voltage at node B is decreased by the second input. When the potential of the input terminal 22 drops, the voltage applied to the gate electrode of the seventh transistor 37 decreases. The potential of the third input terminal 23 decreases, and the gate of the eighth transistor 38 This occurs twice due to the decrease in the potential applied to the electrode. The shift register shown in FIG. 25B is turned on by the seventh transistor 37 and eighth transistor 38 are both on, the seventh transistor 37 is on, and the The eighth transistor 38 is in the off state, then the seventh transistor 37 is in the off state, and the eighth transistor The transistor 38 is sequentially turned on and off, so that the second input terminal 22 and the third input terminal The drop in the potential of the node B caused by the drop in the potential of the input terminal 23 is transmitted to the eighth transistor 24. The number of times can be reduced to one by lowering the potential applied to the gate electrode of the transistor 38. Therefore, the clock signal is supplied to the gate electrode of the seventh transistor 37 from the third input terminal 23. The clock signal is supplied from the second input terminal 22 to the gate electrode of the eighth transistor 38. It is preferable to have a wiring relationship in which the potential of node B is supplied. This is because the noise can be reduced.

[0309] In this way, the potentials of the first output terminal 26 and the second output terminal 27 are maintained at the L level. By configuring the node B to periodically receive a high-level signal during this period, the pulse output This can suppress malfunction of the power circuit.

[0310] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0311] (Embodiment 10) A thin film transistor is manufactured, and the thin film transistor is used in a pixel portion and further in a driver circuit. A semiconductor device (also called a display device) having a display function can be manufactured. A part or the whole of the driver circuit using transistors is formed on the same substrate as the pixel section, A stem-on panel can be formed.

[0312] The display device includes a display element. The display element includes a liquid crystal element (also called a liquid crystal display element), a light-emitting element, A light-emitting element (also called a light-emitting display element) can be used. This category includes elements whose brightness is controlled by the light emitted from the light source, specifically inorganic EL (Electroluminescent) Also, electronic inks and other electronic devices are also included. A display medium whose contrast changes due to mechanical action can also be applied.

[0313] The display device also includes a panel in which a display element is sealed, and a controller for the panel. Furthermore, the display device is manufactured by a method for manufacturing the display device. In the process, the element substrate corresponds to one form before the display element is completed, and the element substrate is Each of the plurality of pixels includes a means for supplying a current to the display element. The pixel electrode of the display element may be formed only, or the conductive film that becomes the pixel electrode may be formed. may be in a state after the film is formed and before the pixel electrode is formed by etching, All forms apply.

[0314] In this specification, the term "display device" refers to an image display device, a display device, or an optical device. It also refers to connectors, such as FPC (Flexible Printed Circuit) integrated circuit) or TAB (Tape Automated Bon ding) tape or TCP (Tape Carrier Package) Modules with printed wiring boards attached to the end of TAB tape or TCP or the display element is mounted on an IC (integrated circuit) by the COG (Chip On Glass) method. The display device also includes all modules in which the display device (circuit) is directly mounted.

[0315] The appearance and cross section of a liquid crystal display panel, which is one mode of a semiconductor device, will be described with reference to FIG. 26(A1)(A2) show the first embodiment formed on the first substrate 4001. Highly reliable thin film transistor 4010 including an oxide semiconductor layer described in Embodiment 8 4011 and a liquid crystal element 4013 are disposed between a second substrate 4006 and a sealant 4005. 26(A1) and 26(A2) are plan views of the sealed panel. Equivalent to the cross-sectional view at -N.

[0316] A pixel portion 4002 and a scanning line driver circuit 4004 are provided on a first substrate 4001. In this way, a sealing material 4005 is provided. A second substrate 4006 is provided on the path 4004. The line driver circuit 4004 is made up of a first substrate 4001, a sealing material 4005, and a second substrate 4006. The first substrate 4001 is sealed together with the liquid crystal layer 4008. In a region different from the region surrounded by the material 4005, a single crystal is formed on a separately prepared substrate. A signal line driver circuit 4003 formed of a semiconductor film or a polycrystalline semiconductor film is mounted.

[0317] The method of connecting the separately formed drive circuit is not particularly limited, and may be a COG method, Wire bonding or TAB method can be used. is an example of mounting a signal line driver circuit 4003 by the COG method, and FIG. 26(A2) shows This is an example in which a signal line driver circuit 4003 is mounted by the TAB method.

[0318] A pixel portion 4002 and a scanning line driver circuit 4004 are provided on a first substrate 4001. 26B, the thin film transistor included in the pixel portion 4002 is A transistor 4010 and a thin film transistor 4011 included in the scanning line driver circuit 4004 Insulating layers 4020 and 4022 are formed on the thin film transistors 4010 and 4011. 1 is provided.

[0319] The thin film transistors 4010 and 4011 are made of the oxide thin film transistors shown in any of Embodiments 1 to 8. A highly reliable thin film transistor including a semiconductor layer can be applied. In this example, the thin film transistors 4010 and 4011 are n-channel thin film transistors.

[0320] The pixel electrode layer 4030 of the liquid crystal element 4013 is connected to the thin film transistor 4010. The counter electrode layer 4031 of the liquid crystal element 4013 is electrically connected to the second substrate 40. 06. The pixel electrode layer 4030, the counter electrode layer 4031, and the liquid crystal layer 4008 are The overlapping portion corresponds to the liquid crystal element 4013. The electrode layer 4031 is provided with insulating layers 4032 and 4033 which function as alignment films. A liquid crystal layer 4008 is sandwiched between insulating layers 4032 and 4033 .

[0321] The first substrate 4001 and the second substrate 4006 may be made of glass or metal (typically, stainless steel). Stainless steel, ceramics, and plastics can be used. , FRP (Fiberglass-Reinforced Plastics) board, PV F (polyvinyl fluoride) film, polyester film or acrylic resin film Aluminum foil can also be used with PVF film or polyester film. A sheet sandwiched between films can also be used.

[0322] The spacers 4035 are columnar spacers obtained by selectively etching the insulating film. and the distance (cell gap) between the pixel electrode layer 4030 and the counter electrode layer 4031 is controlled. A spherical spacer may be used. 4031 is electrically connected to a common potential line provided on the same substrate as the thin film transistor 4010. The common connection portion is used to connect the opposing electrodes via conductive particles disposed between the pair of substrates. The electrode layer 4031 can be electrically connected to a common potential line. It is contained in material 4005.

[0323] Alternatively, a liquid crystal that exhibits a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases. When the temperature of cholesteric liquid crystal is increased, the phase immediately transitions from the cholesteric phase to the isotropic phase. The blue phase appears only in a narrow temperature range, so the temperature range needs to be improved. In order to achieve this, a liquid crystal composition containing 5% by weight or more of a chiral agent is used for the liquid crystal layer 4008. The liquid crystal composition containing the liquid crystal exhibiting the blue phase and the chiral agent has a response speed of 1 msec. Since it is optically isotropic, no alignment treatment is required and the viewing angle dependency is small.

[0324] In addition to transmissive LCD devices, this can also be applied to reflective LCD devices and semi-transmissive LCD devices. can.

[0325] In addition, in a liquid crystal display device, a polarizing plate is provided on the outer side (viewing side) of the substrate, and a colored layer (color The polarizing plate is placed in the order of the substrate. The laminated structure of the polarizing plate and the colored layer is not limited to the present embodiment, and may be provided on the polarizing side. The thickness may be appropriately set depending on the materials of the plate and the colored layer and the manufacturing process conditions. A light-shielding film that functions as a shield may be provided.

[0326] In addition, in order to reduce the surface irregularities of the thin film transistor and improve the reliability of the thin film transistor, In order to improve the performance, the thin film transistor obtained in the above embodiment is used as a protective film or a planarizing insulating film. The insulating layer 4020 and the insulating layer 4021 are used to cover the insulating layer 4020 and the insulating layer 4021. The protective film prevents the intrusion of polluting impurities such as organic matter, metals, and water vapor floating in the air. The protective film is preferably a silicon oxide film or a nitride film formed by sputtering. Silicon film, silicon oxynitride film, silicon nitride oxide film, aluminum oxide film, aluminum nitride film, The aluminum oxide nitride film may be formed as a single layer or a stack of layers of an aluminum nitride oxide film. Although an example of forming the protective film by sputtering is shown, the method is not particularly limited and may be formed by various methods. good.

[0327] Here, an insulating layer 4020 having a stacked structure is formed as a protective film. As the first layer of the silicon dioxide film, a silicon dioxide film is formed by sputtering. By using the above, it is possible to prevent hillocks in the aluminum film used as the source electrode layer and the drain electrode layer. It is effective in stopping.

[0328] In addition, an insulating layer is formed as the second layer of the protective film. Then, a silicon nitride film is formed by sputtering. When a silicon nitride film is used as a protective film, Mobile ions such as thorium penetrate into the semiconductor region and change the electrical properties of the TFT. can be suppressed.

[0329] After forming the protective film, heat treatment (300°C or higher) is performed in a nitrogen atmosphere or in the air. (below) may also be performed.

[0330] An insulating layer 4021 is formed as a planarization insulating film. Heat-resistant organic compounds such as amide, acrylic, benzocyclobutene, polyamide, and epoxy. In addition to the above organic materials, low-k materials can also be used. , siloxane resin, PSG (phosphorus glass), BPSG (borophosphorus glass), etc. In addition, by stacking multiple insulating films made of these materials, it is possible to obtain an insulating layer. 4021 may be formed.

[0331] Siloxane-based resin is a Si-OS compound formed using siloxane-based materials as starting materials. The siloxane resin corresponds to a resin containing an i bond. Alternatively, an organic group having a fluoro group may be used. That's fine.

[0332] The method for forming the insulating layer 4021 is not particularly limited, and may be a sputtering method, an SOG method, or the like, depending on the material. , spin coating, dip coating, spray coating, droplet ejection method (inkjet method, screen printing, offset printing, etc.), doctor knife, roll coater, curtain coater, knife The baking process of the insulating layer 4021 and the annealing of the semiconductor layer can be performed by using a baking machine. By using both, it becomes possible to manufacture a semiconductor device efficiently.

[0333] The pixel electrode layer 4030 and the counter electrode layer 4031 are made of indium oxide containing tungsten oxide. , indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, Indium tin oxide containing titanium oxide, indium tin oxide (hereinafter referred to as ITO), Translucent materials such as indium zinc oxide and indium tin oxide doped with silicon oxide A conductive material can be used.

[0334] The pixel electrode layer 4030 and the counter electrode layer 4031 are made of a conductive polymer (conductive polymer The conductive composition can be used to form the conductive film. The pixel electrode has a sheet resistance of 10,000 Ω / □ or less and a light transmittance of 550 nm. It is preferable that the resistance of the conductive polymer contained in the conductive composition is 70% or more. It is preferable that the electrical conductivity is 0.1 Ω·cm or less.

[0335] As the conductive polymer, a so-called π-electron conjugated conductive polymer can be used. For example, polyaniline or its derivatives, polypyrrole or its derivatives, polythiophene or or a derivative thereof, or a copolymer of two or more of these.

[0336] A signal line driver circuit 4003 and a scanning line driver circuit 4004 or a pixel section 4 Various signals and potentials applied to 002 are supplied from FPC4018.

[0337] The connection terminal electrode 4015 is made of the same conductive film as the pixel electrode layer 4030 of the liquid crystal element 4013. The terminal electrode 4016 is formed from the source electrode layer and the drain electrode layer of the thin film transistor 4011. It is formed of the same conductive film as the gate electrode layer.

[0338] The connection terminal electrode 4015 is connected to the terminal of the FPC 4018 via the anisotropic conductive film 4019. are electrically connected.

[0339] In FIG. 26, a signal line driver circuit 4003 is separately formed and mounted on a first substrate 4001. The present invention is not limited to this configuration. Alternatively, only a part of the signal line driver circuit or a part of the scanning line driver circuit may be separately formed. It may be implemented.

[0340] FIG. 27 shows a semiconductor device using a TFT substrate 2600 fabricated by the fabrication method disclosed herein. 1 shows an example of a semiconductor device configured as a liquid crystal display module.

[0341] FIG. 27 shows an example of a liquid crystal display module, in which a TFT substrate 2600 and an opposing substrate 2601 are connected. The substrate is fixed by a bonding material 2602, and a pixel portion 2603 including a TFT and the like and a liquid crystal layer are disposed between the substrate and the bonding material 2602. A display element 2604 and a colored layer 2605 are provided to form a display area. is required for color display, and in the case of the RGB method, it corresponds to each color of red, green, and blue. A colored layer is provided corresponding to each pixel. On the outside, a polarizing plate 2606, a polarizing plate 2607, and a diffusion plate 2613 are arranged. It is composed of a cathode ray tube 2610 and a reflector 2611, and a circuit board 2612 is a flexible wiring board. The wiring board 2609 is connected to the wiring circuit section 2608 of the TFT substrate 2600, and the controller It also incorporates external circuits such as a polarizing plate and a power supply circuit. The layers may be laminated with a retardation film interposed therebetween.

[0342] The LCD module is available in TN (Twisted Nematic) mode, IPS (In-Plane Switching) mode, n-Plane-Switching mode, FFS (Fringe Field Switching) Switching mode, MVA (Multi-domain Vertical A alignment) mode, PVA(Patterned Vertical Alignment) mode, PVA(Patterned Vertical Alignment) mode nment) mode, ASM(Axially Symmetric aligned Micro-cell mode, OCB (Optical Compensated B) refrigeration mode, FLC (Ferroelectric Liquid d Crystal) mode, AFLC (AntiFerroelectric Liq. uid Crystal) mode can be used.

[0343] By the above steps, a highly reliable liquid crystal display panel can be manufactured as a semiconductor device. do.

[0344] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0345] (Embodiment 11) An example of the semiconductor device is electronic paper.

[0346] Electronic paper that uses elements electrically connected to switching elements to drive electronic ink Electronic paper is also called an electrophoretic display. It has the same readability as paper, consumes less power than other display devices, and is thin and light. This has the advantage that it is possible to

[0347] Electrophoretic displays can be of various forms, but the first particle has a positive charge. A microcapsule containing a negatively charged particle and a second particle is immersed in a solvent or solute. By applying an electric field to the microcapsules, The particles in the capsule are moved in opposite directions to each other, and only the color of the particles that have gathered on one side is displayed. The first particles or the second particles contain a dye, and in the absence of an electric field, The first particle and the second particle have different colors (colorless). (including

[0348] Thus, electrophoretic displays allow materials with high dielectric constants to migrate to areas of high electric field. This is a display that utilizes the so-called dielectrophoretic effect. Therefore, no polarizing plate, which is required for a liquid crystal display device, is required.

[0349] The microcapsules dispersed in a solvent are called electronic ink. The electronic ink can be printed on surfaces such as glass, plastic, fabric, and paper. Color display is also possible by using color filters or particles containing pigments.

[0350] Furthermore, the microphone is appropriately placed on the active matrix substrate so as to be sandwiched between two electrodes. By arranging multiple microcapsules, an active matrix display device is completed. Display can be achieved by applying an electric field to the cell. An active matrix substrate obtained by the thin film transistor shown in FIG. 8 can be used. Cut.

[0351] The first particles and the second particles in the microcapsules may be made of a conductive material, an insulating material, Semiconductor materials, magnetic materials, liquid crystal materials, ferroelectric materials, electroluminescent materials, A material selected from magnetochromic materials, magnetophoretic materials, or a composite material thereof Just use it.

[0352] Figure 28 shows an active matrix electronic paper as an example of a semiconductor device. The thin film transistor 581 used in the device may be any of the thin film transistors shown in any of Embodiments 1 to 8. It can be fabricated in the same way as a thin-film transistor containing an oxide semiconductor layer, and is a highly reliable thin-film transistor. It is a star.

[0353] The electronic paper in Figure 28 is an example of a display device that uses the twisting ball display method. The spherical display method is an electrode layer that uses spherical particles painted in black and white as display elements. and a potential difference is applied between the first electrode layer and the second electrode layer. This is a method of displaying by controlling the orientation of spherical particles by generating a magnetic field.

[0354] The thin film transistor 581 formed on the substrate 580 is a thin film transistor of a bottom gate structure. The thin film transistor 581 is covered with an insulating film 583 that is in contact with the semiconductor layer. The first electrode layer 587 and the insulating layer 585 are formed as a source electrode layer or a drain electrode layer. The first electrode layer 587 and the substrate 596 are in contact with each other through the opening and are electrically connected. Between the second electrode layer 588 and the black area 590a and the white area 590b, A spherical particle 589 is provided that includes a cavity 594 that is filled with a liquid, The area around the pixel 589 is filled with a filler 595 such as resin. The second electrode layer 588 corresponds to a thin film transistor. The transistor 581 is electrically connected to a common potential line provided on the same substrate 580. The through connection is used to connect the second substrate 580 to the second substrate 596 through conductive particles disposed between the substrate 580 and the substrate 596. The electrode layer 588 can be electrically connected to a common potential line.

[0355] Also, instead of the twist ball, an electrophoretic element can be used. and a diameter of 10 μm to 20 μm that contains positively charged white particles and negatively charged black particles. Microcapsules of about 0 μm in size are used. When an electric field is applied by the first and second electrode layers, the microcapsules turn white. White particles and black particles move in opposite directions, allowing the display to be white or black. The display element that applies this principle is an electrophoretic display element, which is generally called electronic paper. Electrophoretic display elements have a higher reflectivity than liquid crystal display elements, so auxiliary lights are not required. It also consumes little power and the display can be seen even in dimly lit places. Even if power is not supplied to the display unit, the image that has been displayed can be retained. Therefore, the semiconductor device with a display function (simply a display device, or a device equipped with a display device) is The ability to preserve the displayed image even when the device (also known as a semiconductor device) is moved away This becomes possible.

[0356] Through the above steps, electronic paper with high reliability as a semiconductor device can be manufactured. .

[0357] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0358] (Embodiment 12) An example of a light-emitting display device is shown as a semiconductor device. is shown using a light-emitting element that utilizes electroluminescence. The light-emitting element that uses the light-emitting material is classified into two types depending on whether the light-emitting material is an organic compound or an inorganic compound. Generally, the former is called an organic EL element and the latter an inorganic EL element.

[0359] In an organic EL element, electrons and holes are released from a pair of electrodes by applying a voltage to the light-emitting element. are injected into the layers containing the light-emitting organic compounds, causing a current to flow. The recombination of the electrons and holes creates an excited state in the light-emitting organic compound. The excited state is then converted to the ground state, at which point light is emitted. Such a light-emitting element is called a current-excited light-emitting element.

[0360] Inorganic EL elements are divided into dispersion-type inorganic EL elements and thin-film-type inorganic EL elements depending on the element structure. Dispersion-type inorganic EL elements have a light-emitting layer in which particles of a light-emitting material are dispersed in a binder. The emission mechanism is a donor-acceptor interaction that utilizes the donor and acceptor levels. Thin-film inorganic EL devices sandwich the light-emitting layer between dielectric layers. Furthermore, this structure is sandwiched between electrodes, and the light emission mechanism utilizes the inner-shell electron transition of metal ions. In this example, the light-emitting element is an organic EL element. do.

[0361] FIG. 29 shows an example of a pixel configuration to which digital time gray scale driving can be applied as an example of a semiconductor device. This is a diagram.

[0362] The configuration and operation of a pixel to which digital time gray scale driving can be applied will be described. The figure shows an n-channel transistor using an oxide semiconductor layer as a channel formation region in one pixel. Here is an example of using two of them.

[0363] The pixel 6400 includes a switching transistor 6401 and a light-emitting element driving transistor 6402. 402, a light emitting element 6404 and a capacitor element 6403. The gate of the gate electrode 6401 is connected to the scanning line 6406, and the first electrode (the source electrode and the drain electrode) The second electrode (one of the source and drain electrodes) is connected to a signal line 6405, and the second electrode (the other of the source and drain electrodes) is connected to a signal line 6405. The other end is connected to the gate of the light-emitting element driving transistor 6402. The transistor 6402 has a gate connected to a power supply line 6407 through a capacitor element 6403. The first electrode is connected to a power supply line 6407, and the second electrode is connected to a first electrode (pixel The second electrode of the light emitting element 6404 corresponds to the common electrode 6408. The common electrode 6408 is electrically connected to a common potential line formed on the same substrate.

[0364] A low power supply potential is set to the second electrode (common electrode 6408) of the light emitting element 6404. The low power supply potential is a low power supply potential with respect to the high power supply potential set to the power supply line 6407. Potential < High power supply potential. For example, GND, 0V, etc. are set as low power supply potential. The potential difference between the high power supply potential and the low power supply potential is applied to the light emitting element 6404. Then, in order to make the light emitting element 6404 emit light by passing a current through the light emitting element 6404, a high power supply potential and the low power supply potential is set to be equal to or greater than the forward threshold voltage of the light emitting element 6404. Each potential is set.

[0365] The capacitor element 6403 is substituted for the gate capacitance of the light-emitting element driving transistor 6402. It is possible to omit it. Regarding the gate capacitance of the light-emitting element driving transistor 6402 Alternatively, a capacitance may be formed between the channel region and the gate electrode.

[0366] In the case of a voltage input voltage driving method, the gate of the light emitting element driving transistor 6402 The light emitting element driving transistor 6402 is either fully turned on or off. In other words, the light emitting element driving transistor 6402 The light emitting element driving transistor 6402 is operated in the linear region. Therefore, a voltage higher than the voltage of the power supply line 6407 is applied to the gate of the light emitting element driving transistor 6402. The signal line 6405 is connected to the power supply line voltage + transistor for driving the light emitting element. Apply a voltage higher than the Vth of 6402.

[0367] Furthermore, when analog grayscale driving is performed instead of digital time grayscale driving, the input of the signal is different. By doing so, the same pixel configuration as in FIG. 29 can be used.

[0368] When analog gradation driving is performed, a light emitting element is connected to the gate of the light emitting element driving transistor 6402. Apply a voltage equal to or greater than the forward voltage of 6404 and the Vth of the light-emitting element driving transistor 6402. The forward voltage of the light emitting element 6404 refers to the voltage required to achieve a desired luminance. At least the forward threshold voltage is included. By inputting a video signal that operates in the region, a current is passed through the light emitting element 6404. In order to operate the light emitting element driving transistor 6402 in the saturation region, The potential of the transistor 407 is set higher than the gate potential of the light emitting element driving transistor 6402. By converting the video signal into an analog signal, a current corresponding to the video signal flows to the light emitting element 6404, Analog gray scale driving is possible.

[0369] Note that the pixel configuration shown in Fig. 29 is not limited to this. For example, A switch, a resistor, a capacitor, a transistor, a logic circuit, or the like may be added.

[0370] Next, the configuration of the light emitting element will be described with reference to FIG. The cross-sectional structure of a pixel will be described using an example in which FT is n-type. (C) TFTs 7001 and 7011 are TFTs for driving light emitting elements used in the semiconductor device , 7021 are thin film transistors arranged in the pixels shown in any of Embodiments 1 to 8. The thin film transistor can be fabricated in the same manner as described above, and is highly reliable and includes an oxide semiconductor layer.

[0371] The light emitting element only needs to have at least one of the anode and cathode transparent in order to extract light. Then, a thin film transistor and a light emitting element are formed on the substrate, and light is taken from the surface opposite to the substrate. Top emission, bottom emission, and top emission. There are light-emitting elements with a double-sided emission structure that emits light from the side, and the pixel configuration is It can also be applied to optical elements.

[0372] A light emitting element with a top emission structure will be described with reference to FIG.

[0373] In FIG. 30(A), a TFT 7001 for driving a light emitting element is an n-type TFT, and a light emitting element 700 30(A) shows a cross-sectional view of a pixel when light emitted from the cathode 2 exits to the anode 7005 side. ) is a cathode 7003 of a light emitting element 7002 and a TFT 7001 which is a TFT for driving the light emitting element. are electrically connected, and a light-emitting layer 7004 and an anode 7005 are stacked in this order on a cathode 7003. The cathode 7003 can be made of any conductive film as long as it has a small work function and reflects light. Various materials can be used. For example, Ca, Al, MgAg, AlLi, etc. are preferable. The light-emitting layer 7004 may be made up of a single layer or a plurality of layers stacked together. When it is made up of multiple layers, an electrode is placed on the cathode 7003. The electron injection layer, electron transport layer, light emitting layer, hole transport layer, and hole injection layer are laminated in this order. It is not necessary to provide all of these layers. The anode 7005 is made of a conductive material that is transparent to light. For example, indium oxide containing tungsten oxide, tungsten oxide Indium zinc oxide containing titanium oxide, indium oxide containing titanium oxide Indium tin oxide, indium tin oxide (hereinafter referred to as ITO), indium zinc oxide Alternatively, a light-transmitting conductive film such as indium tin oxide to which silicon oxide is added may be used. .

[0374] A partition wall 7009 is provided to cover a part of the cathode 7003. The partition wall 7009 is made of polyimide. , an organic resin film such as acrylic, polyamide, or epoxy, an inorganic insulating film, or an organic polysiloxane The partition wall 7009 is formed by using a photosensitive resin material. It is preferable that the surface is formed as an inclined surface having a continuous curvature. When a photosensitive resin material is used as 7009, the process of forming a resist mask can be omitted. It is possible.

[0375] The region where the light-emitting layer 7004 is sandwiched between the cathode 7003 and the anode 7005 is the light-emitting element 7002. In the case of the pixel shown in FIG. 30(A), the light emitted from the light emitting element 7002 is The light is emitted toward the anode 7005 as shown by the mark.

[0376] Next, a light emitting element with a bottom emission structure will be described with reference to FIG. The TFT 7011 is n-type, and light emitted from the light-emitting element 7012 is emitted to the cathode 7013 side. FIG. 30(B) shows a cross-sectional view of a pixel in the case where a light-emitting element driving TFT 7011 and a The cathode 7013 of the light-emitting element 7012 is formed on the electrically conductive film 7017 having light-transmitting properties. A light-emitting layer 7014 and an anode 7015 are laminated in this order on the cathode 7013. In addition, when the anode 7015 is light-transmitting, a light-reflecting or light-blocking layer is provided so as to cover the anode. A shielding film 7016 for shielding may be formed on the cathode 7013. As in the case of the first embodiment, various conductive materials with small work functions can be used. However, the film thickness should be such that light can pass through (preferably about 5 nm to 30 nm). For example, an aluminum film having a thickness of 20 nm can be used as the cathode 7013. The light-emitting layer 7014 may be composed of a single layer or a plurality of layers, as in FIG. The anode 7015 is a light-transmitting layer. Although not necessary, it may be formed using a light-transmitting conductive material as in FIG. 30(A). The shielding film 7016 can be made of, for example, a metal that reflects light. The material is not limited to a metal film, and for example, a resin to which a black pigment is added may also be used.

[0377] In addition, a partition wall 7019 is provided to cover part of the conductive film 7017. The partition wall 7019 is made of polyimide. organic resin films such as acrylic, polyamide, and epoxy, inorganic insulating films, or organic polysiloxane The partition wall 7019 is formed by using a photosensitive resin material. It is preferable that the side surface is formed as an inclined surface having a continuous curvature. When a photosensitive resin material is used for the wall 7019, the process of forming a resist mask can be omitted. It is possible.

[0378] The region where the light-emitting layer 7014 is sandwiched between the cathode 7013 and the anode 7015 is the light-emitting element 7012. In the case of the pixel shown in FIG. 30(B), the light emitted from the light-emitting element 7012 corresponds to The light is emitted toward the cathode 7013 as shown by the arrow.

[0379] Next, a light emitting element with a dual emission structure will be described with reference to FIG. In the example, a light-transmitting conductive film 702 electrically connected to a light-emitting element driving TFT 7021 is A cathode 7023 of the light-emitting element 7022 is formed on the cathode 7023. 30(A) and an anode 7025 are laminated in this order. Similarly, various conductive materials with small work functions can be used. The thickness of the cathode 702 is set to a level that allows light to pass through. For example, Al having a thickness of 20 nm is used as the cathode 702. 3. The light-emitting layer 7024 can be formed as a single It may be configured as a layer or as a laminate of multiple layers. The anode 7025 is made of a light-transmitting conductive material, similar to that shown in FIG. It can be formed by

[0380] In addition, a partition wall 7029 is provided to cover part of the conductive film 7027. The partition wall 7029 is made of polyimide. organic resin films such as acrylic, polyamide, and epoxy, inorganic insulating films, or organic polysiloxane The partition wall 7029 is formed by using a photosensitive resin material. It is preferable that the side surface is formed as an inclined surface having a continuous curvature. When a photosensitive resin material is used for the wall 7029, the process of forming a resist mask can be omitted. It is possible.

[0381] The overlapping portion of the cathode 7023, the light-emitting layer 7024, and the anode 7025 is the light-emitting element 70. In the case of the pixel shown in FIG. 30(C), the light emitted from the light emitting element 7022 is is emitted to both the anode 7025 side and the cathode 7023 side as shown by the arrows.

[0382] Although organic EL elements have been described as light-emitting elements here, inorganic EL elements can also be used as light-emitting elements. It is also possible to provide an L element.

[0383] In addition, a thin film transistor (TFT for driving light-emitting elements) that controls the driving of light-emitting elements and a light-emitting element However, if a current flows between the light-emitting element driving TFT and the light-emitting element, A control TFT may be connected.

[0384] The semiconductor device is not limited to the configuration shown in FIG. 30, and may be any of the semiconductor devices disclosed in this specification. Various modifications based on the technical concept are possible.

[0385] Next, the appearance and structure of a light-emitting display panel (also referred to as a light-emitting panel), which is one mode of a semiconductor device, will be described. The cross section will be explained with reference to FIG. 31. FIG. 31 shows a thin film transistor formed on a first substrate. The flat surface of the panel is formed by sealing the transistor and the light-emitting element between the second substrate and the panel with a sealing material. 31(B) corresponds to a cross-sectional view taken along line HI in FIG. 31(A).

[0386] A pixel portion 4502, a signal line driver circuit 4503a, and a signal line driver circuit 4504 are provided on a first substrate 4501. 3b and the scanning line driver circuits 4504a and 4504b. In addition, a pixel portion 4502, signal line driver circuits 4503a and 4503b, and A second substrate 4506 is provided on the scanning line driver circuits 4504a and 4504b. The pixel portion 4502, the signal line driver circuits 4503a and 4503b, and the scanning line driver circuit 45 4504a and 4504b are a first substrate 4501, a sealing material 4505, and a second substrate 4506. The seal is sealed together with the filler 4507 by the sealant. Highly airtight protective film with little outgassing (lamination film, UV curable resin film) It is preferable to package (enclose) the product in a protective film (such as a film) or a cover material.

[0387] A pixel portion 4502, a signal line driver circuit 4503a, and a fourth 503b and the scanning line driver circuits 4504a and 4504b have a plurality of thin film transistors. In FIG. 31B, a thin film transistor 4510 included in a pixel portion 4502 and a signal 45 shows an example of a thin film transistor 4509 included in a line driver circuit 4503a.

[0388] The thin film transistors 4509 and 4510 are made of the oxide thin film transistors described in any of Embodiments 1 to 8. A highly reliable thin film transistor including a semiconductor layer can be applied. The transistors 4509 and 4510 are n-channel thin film transistors.

[0389] Further, 4511 corresponds to a light-emitting element, and a first electrode which is a pixel electrode of the light-emitting element 4511 The layer 4517 is electrically connected to the source electrode layer or the drain electrode layer of the thin film transistor 4510. The light-emitting element 4511 is configured by a first electrode layer 4517, an electroluminescent layer The light emitting element 4512 and the second electrode layer 4513 are stacked together, but the structure is not limited to the one shown. The configuration of the light emitting element 4511 can be changed appropriately according to the direction of the light extracted from the element 4511. It is possible.

[0390] The partition wall 4520 is formed using an organic resin film, an inorganic insulating film, or organic polysiloxane. In particular, a photosensitive material is used to form an opening on the first electrode layer 4517, and the sidewall of the opening It is preferable to form the inclined surface so that the inclined surface has a continuous curvature.

[0391] The electroluminescent layer 4512 may be composed of a single layer or a plurality of layers stacked. It doesn't matter whether it's done or not.

[0392] The second electrode layer is formed to prevent oxygen, hydrogen, moisture, carbon dioxide, and the like from entering the light-emitting element 4511. A protective film may be formed on the partition wall 4513 and the partition wall 4520. The protective film may be a silicon nitride film, A silicon nitride oxide film, a DLC film, or the like can be formed.

[0393] In addition, signal line driver circuits 4503a and 4503b, scanning line driver circuits 4504a and 4504b Various signals and potentials applied to the pixel portion 4502 are transmitted through the FPC 4518a, 4518b, and It is supplied by b.

[0394] The connection terminal electrode 4515 is formed of the same conductive film as the first electrode layer 4517 of the light-emitting element 4511. The terminal electrode 4516 is formed from a source electrode layer and a The drain electrode layer is formed from the same conductive film as the drain electrode layer.

[0395] The connection terminal electrode 4515 is connected to the terminal of the FPC 4518a via the anisotropic conductive film 4519. are electrically connected to each other.

[0396] The second substrate 4506, which is positioned in the direction in which light from the light emitting element 4511 is extracted, is not light-transmitting. In this case, glass plates, plastic plates, polyester films or A light-transmitting material such as an acrylic film is used.

[0397] In addition to inert gases such as nitrogen and argon, filler 4507 can also be used as UV-curable resin. It can be made of oil or thermosetting resin, and PVC (polyvinyl chloride), acrylic, Polyimide, epoxy resin, silicone resin, PVB (polyvinyl butyral) or EV For example, nitrogen can be used as filler 4507. Just use the element.

[0398] If necessary, a polarizing plate or a circular polarizing plate (including an elliptical polarizing plate) may be provided on the light-emitting surface of the light-emitting element. Optical films such as retardation plates (λ / 4 plates, λ / 2 plates) and color filters may be provided as appropriate. In addition, an anti-reflection film may be provided on the polarizing plate or the circular polarizing plate. Anti-glare treatment can be applied to diffuse reflected light and reduce glare.

[0399] The signal line driver circuits 4503a and 4503b and the scanning line driver circuits 4504a and 4504b are A driving circuit formed of a single crystal semiconductor film or a polycrystalline semiconductor film on a separately prepared substrate is Alternatively, only the signal line driver circuit, or a part of the signal line driver circuit, or the scanning line driver circuit may be mounted. Only the path or only a part of the path may be separately formed and mounted, and the configuration is not limited to that of FIG.

[0400] Through the above steps, a highly reliable light-emitting display device (display panel) can be manufactured as a semiconductor device. It is possible.

[0401] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0402] (Embodiment 13) The semiconductor device disclosed in this specification can be applied as electronic paper. Par can be used in any electronic device that displays information. For example, electronic paper can be used for electronic books, posters, trains, etc. It can be used for in-car advertising, display on various cards such as credit cards, etc. An example of an electronic device is shown in Figure 32.

[0403] FIG. 32 shows an example of an electronic book 2700. For example, the electronic book 2700 has a housing 2 It consists of two housings, housing 2701 and housing 2703. 03 is integrated with a shaft portion 2711, and performs opening and closing operations around the shaft portion 2711. This configuration allows the device to operate like a paper book. .

[0404] A display unit 2705 is incorporated in the housing 2701, and a display unit 2707 is incorporated in the housing 2703. The display unit 2705 and the display unit 2707 are configured to display a continuous screen. Alternatively, a different screen may be displayed. For example, a sentence is displayed on the right display unit (display unit 2705 in FIG. 32) and An image can be displayed on the display unit 2707 in FIG.

[0405] 32 shows an example in which the housing 2701 is provided with an operation unit. 701 includes a power supply 2721, operation keys 2723, a speaker 2725, etc. The operation keys 2723 can be used to turn pages. It may also be configured to include a touch panel, a pointing device, etc. On the side, there are external connection terminals (earphone terminal, USB terminal, or AC adapter and USB A configuration including a terminal that can be connected to various cables, a recording medium insertion section, etc. Furthermore, the electronic book 2700 may be configured to have the function of an electronic dictionary. That's fine.

[0406] The electronic book 2700 may also be configured to be able to send and receive information wirelessly. The desired book data can be purchased and downloaded from the e-book server. is also possible.

[0407] (Embodiment 14) The semiconductor device disclosed in this specification can be applied to various electronic devices (including gaming machines). The electronic device can be, for example, a television device (television or television receivers), computer monitors, digital cameras, digital video cameras digital photo frames, mobile phones (also called mobile phones or mobile phone devices), portable Examples include game machines, mobile information terminals, sound reproduction devices, and large game machines such as pachinko machines. do.

[0408] FIG. 33(A) shows an example of a television device 9600. The display unit 9603 is incorporated in the housing 9601. In this case, the housing 9601 is supported by a stand 9605. This shows a configuration in which the above is supported.

[0409] The television device 9600 can be operated using an operation switch on the housing 9601 or a separate remote control. This can be done by the remote control operation device 9610. The channel and volume can be controlled by the 9609, and the information displayed on the display 9603 is In addition, the remote control operation device 9610 can operate the video. A display portion 9607 for displaying information output from 9610 may be provided.

[0410] The television device 9600 is configured to include a receiver, a modem, and the like. It can receive more general TV broadcasts and can also receive them via wired or wireless modems. By connecting to a communication network, it can be one-way (sender to receiver) or two-way. It is also possible to communicate information (between a sender and a receiver, or between receivers).

[0411] FIG. 33(B) shows an example of a digital photo frame 9700. The photo frame 9700 has a display unit 9703 built into a housing 9701. The unit 9703 is capable of displaying various images, for example, images taken with a digital camera. By displaying the image data, it can function like a normal photo frame.

[0412] The Digital Photo Frame 9700 has an operation panel, external connection terminals (USB terminal, US A terminal that can be connected to various cables such as B cable, etc., and a recording medium insertion section. These components may be incorporated on the same surface as the display unit, but they may be incorporated on the side or back. It is preferable to have a recording medium for a digital photo frame as it improves the design. A memory that stores image data taken with a digital camera is inserted into the body insertion section. The image data can be captured and the captured image data can be displayed on the display portion 9703 .

[0413] The digital photo frame 9700 may also be configured to be capable of transmitting and receiving information wirelessly. It is also possible to configure the device so that desired image data can be wirelessly acquired and displayed.

[0414] FIG. 34(A) shows a portable gaming machine, which is composed of two cabinets, a cabinet 9881 and a cabinet 9891. The housing 9881 is connected to a connector 9893 so as to be openable and closable. A display unit 9883 is incorporated in the housing 9891. The portable gaming machine shown in 34(A) also includes a speaker unit 9884, a recording medium insertion unit 988 6, LED lamp 9890, input means (operation key 9885, connection terminal 9887, sensor 9 888 (force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, Chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration (including functions for measuring movement, smell, or infrared rays), microphone 9889) Of course, the configuration of the portable gaming machine is not limited to the above, and It is sufficient if the semiconductor device disclosed in the above is included, and other auxiliary equipment is appropriately provided. The portable gaming machine shown in FIG. 34(A) can be The function of reading out programs or data and displaying them on the display, and wireless communication with other portable gaming machines The portable gaming machine shown in FIG. 34(A) has the function of sharing information by performing the above. The functions are not limited to these, and various functions can be provided.

[0415] FIG. 34(B) shows an example of a slot machine 9900, which is a large gaming machine. The machine 9900 has a display unit 9903 built into a housing 9901. Machine 9900 also has other operating means such as a start lever and stop switch, coin It is equipped with an insertion slot, a speaker, etc. Of course, the configuration of the slot machine 9900 is The present invention is not limited to the above, and may be configured to include at least the semiconductor device disclosed in this specification. , and other auxiliary equipment may be provided as appropriate.

[0416] FIG. 35(A) is a perspective view showing an example of a portable computer.

[0417] The portable computer of FIG. 35(A) has an upper housing 9301 and a lower housing 9302 connected to each other. The hinge unit is closed to form an upper housing 9301 having a display portion 9303 and a keyboard. The lower housing 9302 having the card 9304 can be stacked on top of each other, making it easy to carry. This is convenient, and when the user wants to input data on the keyboard, the hinge unit can be opened. The user can perform input operations by looking at the display portion 9303.

[0418] The lower housing 9302 also includes a keyboard 9304 and a pointing device for inputting data. If the display portion 9303 is a touch input panel, Input operations can be performed by touching the lower housing 9302. The lower housing 9302 has a computing function unit such as a hard disk. It has an external connection port 9305 into which a communication cable conforming to the SB communication standard is inserted. There are.

[0419] The upper housing 9301 further includes a display unit 93 that can be slid into the upper housing 9301 and stored therein. 07, which allows for a wide display screen. The orientation of the screen of the 9307 can be adjusted by the user. If it is a panel, input operations can be performed by touching a part of the retractable display section.

[0420] The display portion 9303 or the storable display portion 9307 may be a liquid crystal display panel, an organic light emitting element, or The display device uses a light-emitting display panel made of inorganic light-emitting elements.

[0421] The portable computer shown in FIG. 35(A) is configured with a receiver and the like, and is also used for television broadcasting. It is possible to receive broadcasts and display images on the display unit. The display unit 9307 is slid open while the hinge unit connecting the display unit 9307 to the body 9302 is kept closed. The entire screen is exposed by tilting the screen, and the user can watch TV broadcasts by adjusting the screen angle. In this case, the hinge unit is opened to prevent the display unit 9303 from displaying anything. It only activates the circuitry to display the TV broadcast, so it consumes the minimum amount of power. This is useful in portable computers with limited battery capacity.

[0422] FIG. 35(B) shows a portable telephone that can be worn on the user's arm like a wristwatch. FIG. 10 is a perspective view showing an example of a story.

[0423] This mobile phone includes a main body having at least a communication device with a telephone function and a battery, A band part 9204 for attaching the body to the arm, an adjustment part for adjusting the fastening state of the band part to the arm It is composed of a joint part 9205, a display part 9201, a speaker 9207, and a microphone 9208. There are.

[0424] The main body also has an operation switch 9203, which is used for power input and display switching. In addition to the switch and the switch to start shooting, for example, when you press a button, a program for the Internet Each function can be associated with another function, such as being started.

[0425] Input operations of this mobile phone are performed by touching the display portion 9201 with a finger or an input pen, or by operating the display portion 9201. This is done by operating a switch 9203 or by inputting voice into a microphone 9208. 35(B) shows a display button 9202 displayed on a display unit 9201, and Input can be made by touching the screen.

[0426] The main body also contains an imaging device that converts the subject image formed through the photographic lens into an electronic image signal. It has a camera unit 9206 with a step. Note that it is not necessary to provide a camera unit.

[0427] The mobile phone shown in FIG. 35(B) is configured with a television broadcast receiver and the like. It can receive TV broadcasts and display the images on the display unit 9201, and can also store data in memory etc. It is possible to record television broadcasts in memory by using a storage device. The mobile phone shown in B) may have a function capable of collecting location information such as GPS.

[0428] The display unit 9201 is a light-emitting display panel such as a liquid crystal display panel, an organic light-emitting element, or an inorganic light-emitting element. The mobile phone shown in Figure 35(B) is small and lightweight. Therefore, the battery capacity is limited, and the display device used for the display portion 9201 is a low-power display device. It is preferable to use a force-actuable panel.

[0429] Although FIG. 35(B) illustrates an electronic device that is worn on the arm, it is not limited to this. It is sufficient that the device has a portable shape. [Explanation of symbols]

[0430] 11 Wiring 12 Wiring 13 Wiring 14 Wiring 15 Wiring 21 terminals 22 terminals 23 terminals 24 terminals 25 terminals 26 terminals 27 terminals 31 Transistor 32 transistors 33 Transistor 34 transistors 35 transistors 36 transistors 37 Transistor 38 transistors 39 Transistor 40 transistors 41 Transistor 42 transistors 43 Transistor 51 Power line 52 Power line 53 Power line 61 period 62 period 100 boards 101 gate electrode layer 102 Gate insulating layer 103 Oxide semiconductor layer 105a Source electrode layer 105b drain electrode layer 107 Protective insulation layer 108 Capacitance wiring 110 Pixel electrode layer 121 terminal 122 terminals 125 Contact Hole 126 Contact Hole 127 Contact Hole 128 Transparent conductive film 129 Transparent conductive film 132 Conductive film 133 Oxide semiconductor layer 135 Oxide semiconductor layer 150 terminals 151 terminals 152 Gate insulating layer 153 Connection electrode layer 154 Protective insulating film 155 Transparent conductive film 156 Electrode layer 170 Thin-Film Transistor 220 Connection electrode layer 221 First Contact Hole 222 Second Contact Hole 223 Third Contact Hole 224 4th Contact Hole 225 Source wiring 226 First gate wiring 227 Second gate wiring 400 boards 401 Gate electrode layer 402 Gate insulating layer 403 Oxide semiconductor layer 404a Source Area 404b Drain region 405a Source electrode layer 405b Drain electrode layer 407 Oxide insulating film 409 Conductive Layer 410 Insulating layer 411 Pixel electrode layer 419 Conductive Layer 420 Connection electrode layer 421 First Contact Hole 422 Second Contact Hole 423 Third Contact Hole 424 4th Contact Hole 425 source wiring 426 First gate wiring 427 Second gate wiring 428 First source wiring 429 Second source wiring 430 Gate wiring 432 Oxide semiconductor layer 450 board 451 Gate electrode layer 452 Gate insulating layer 453 Oxide semiconductor layer 455a Source electrode layer 455b Drain electrode layer 457 Oxide insulating film 460 Thin Film Transistor 461 Thin-Film Transistor 462 Thin-film transistor 463 Thin-Film Transistor 464 Thin Film Transistor 470 Connection electrode layer 471 First Contact Hole 472 Second Contact Hole 473 Third Contact Hole 474 4th Contact Hole 475 Source wiring 476 First gate wiring 477 Second gate wiring 478 First source wiring 479 Second source wiring 480 Gate Wiring 482 Oxide semiconductor layer 490 Third Contact Hole 491 Third Contact Hole 580 board 581 Thin-film transistor 583 Insulating Film 585 Insulation Layer 587 Electrode layer 588 Electrode layer 589 Spherical particles 590a black area 590b White area 594 Cavity 595 Filling material 596 PCB 601 Electric furnace 602 Chamber 603 Heater 604 Substrate 605 Susceptor 606 Gas supply means 607 Exhaust means 611a Gas Supply Source 611b Gas Source 612a Pressure Regulating Valve 612b Pressure Regulating Valve 613a Purifier 613b Purifier 614a Mass Flow Controller 614b Mass Flow Controller 615a Stop valve 615b Stop valve 1400 board 1401 gate electrode layer 1402 Gate insulating layer 1403 Oxide semiconductor layer 1405a Source electrode layer 1405b Drain electrode layer 1406a Source region 1406b Drain region 1407 Oxide insulating film 1408 Insulation layer 1409 Conductive layer 1418 Channel Protection Layer 1420 Connection electrode layer 1425 Source wiring 1426 First gate wiring 1427 Second gate wiring 1430 Thin-film transistor 1431 Thin-film transistor 1432 Thin-film transistor 1601 Electric furnace 1602 Chamber 1603 Heater 1604 PCB 1605 Susceptor 1606 Gas supply means 1607 Exhaust means 1611 Gas Supply Source 1612 Pressure Regulating Valve 1613 Purifier 1614 Mass Flow Controller 1615 Stop valve 2600 TFT substrate 2601 Opposing substrate 2602 Sealing material 2603 Pixel section 2604 Display element 2605 Colored layer 2606 Polarizing plate 2607 Polarizing plate 2608 Wiring circuit section 2609 Flexible wiring board 2610 cold cathode tube 2611 Reflector 2612 Circuit Board 2613 Diffuser 2700 e-books 2701 Housing 2703 Housing 2705 ​​Display section 2707 Display section 2711 Shaft 2721 Power supply 2723 Operation Key 2725 Speaker 4001 board 4002 Pixel section 4003 Signal line driver circuit 4004 Scanning line driver circuit 4005 Sealing material 4006 board 4008 Liquid crystal layer 4010 Thin Film Transistor 4011 Thin-film transistor 4013 Liquid crystal element 4015 Connection terminal electrode 4016 Terminal electrode 4018 FPC 4019 Anisotropic conductive film 4020 Insulation layer 4021 Insulation layer 4030 Pixel electrode layer 4031 Counter electrode layer 4032 Insulation layer 4033 Insulation layer 4035 Spacer 4501 Circuit Board 4502 Pixel section 4503a Signal line driver circuit 4503b Signal line driver circuit 4504a Scanning line driver circuit 4504b Scanning line driver circuit 4505 Sealing material 4506 board 4507 Filling material 4509 Thin-film transistor 4510 Thin-film transistor 4511 Light-emitting element 4512 Electroluminescent layer 4513 Electrode layer 4515 Connection terminal electrode 4516 Terminal electrode 4517 Electrode layer 4518a FPC 4518b FPC 4519 Anisotropic conductive film 4520 Bulkhead 5300 board 5301 Pixel unit 5302 Scanning line driver circuit 5303 Scanning line driver circuit 5304 Signal line driver circuit 5305 Timing control circuit 5601 Shift Register 5602 Switching Circuit 5603 Thin-film transistor 5604 Wiring 5605 Wiring 6400 pixels 6401 Switching transistor 6402 Drive transistor 6403 Capacitor element 6404 Light-emitting element 6405 signal line 6406 scan lines 6407 Power line 6408 Common electrode 7001 Driving TFT 7002 Light-emitting element 7003 Cathode 7004 Light-emitting layer 7005 Anode 7009 Bulkhead 7011 Driving TFT 7012 Light-emitting element 7013 Cathode 7014 Light-emitting layer 7015 Anode 7016 Shielding membrane 7017 Conductive film 7019 Bulkhead 7021 Driving TFT 7022 Light-emitting element 7023 Cathode 7024 Light-emitting layer 7025 Anode 7027 Conductive film 7029 Bulkhead 9201 Display section 9202 Display button 9203 Operation switch 9204 Band Club 9205 Adjustment part 9206 Camera Department 9207 Speaker 9208 Microphone 9301 Upper housing 9302 Lower housing 9303 Display section 9304 Keyboard 9305 External connection port 9306 Pointing Device 9307 Display section 9600 Television Equipment 9601 Housing 9603 Display section 9605 Stand 9607 Display section 9609 Operation Key 9610 Remote Control Machine 9700 Digital Photo Frame 9701 Housing 9703 Display section 9881 Case 9882 Display section 9883 Display section 9884 Speaker section 9885 Input means (operation keys 9886 Recording medium insertion section 9887 Connection terminal 9888 Sensor 9889 Microphone 9890 LED Lamp 9891 Case 9893 Connection section 9900 slot machine 9901 Housing 9903 Display section

Claims

1. a first conductive layer having a function as a wiring for supplying a signal to a gate electrode of a transistor; a second conductive layer having a function as a wiring for supplying a signal to one of a source electrode and a drain electrode of the transistor; a third conductive layer electrically connected to the second conductive layer and having the same material as the first conductive layer and the second conductive layer; an oxide semiconductor layer including a channel formation region of the transistor and electrically connected to the third conductive layer; a fourth conductive layer having a region in contact with a top surface of the oxide semiconductor layer and functioning as one of a source electrode and a drain electrode of the transistor; a fifth conductive layer having a region in contact with a top surface of the oxide semiconductor layer and functioning as the other of the source electrode and the drain electrode of the transistor; a sixth conductive layer having the same material as the fourth conductive layer and the fifth conductive layer; a first insulating layer having a region located between the fourth conductive layer and the third conductive layer, a region located between the sixth conductive layer and the third conductive layer, and a region located between the sixth conductive layer and the second conductive layer; the third conductive layer has a region in contact with the fourth conductive layer in a first opening of the first insulating layer and a region in contact with the sixth conductive layer in a second opening of the first insulating layer; the second conductive layer has a region in contact with the sixth conductive layer in the third opening of the first insulating layer; the sixth conductive layer has a region that intersects with the first conductive layer in a plan view, the first conductive layer has a region extending in a channel length direction of the transistor in a plan view; The first conductive layer functions as a wiring for supplying a signal to a gate of another transistor arranged in parallel along a channel length direction of the transistor.

2. A first conductive layer having a function as wiring for supplying a signal to a gate electrode of a transistor; a second conductive layer having a function as a wiring for supplying a signal to one of a source electrode and a drain electrode of the transistor; a third conductive layer electrically connected to the second conductive layer and having the same material as the first conductive layer and the second conductive layer; an oxide semiconductor layer including a channel formation region of the transistor and electrically connected to the third conductive layer; a fourth conductive layer having a region in contact with a top surface of the oxide semiconductor layer and functioning as one of a source electrode and a drain electrode of the transistor; a fifth conductive layer having a region in contact with a top surface of the oxide semiconductor layer and functioning as the other of the source electrode and the drain electrode of the transistor; a sixth conductive layer having the same material as the fourth conductive layer and the fifth conductive layer; a first insulating layer having a region located between the fourth conductive layer and the third conductive layer, a region located between the sixth conductive layer and the third conductive layer, and a region located between the sixth conductive layer and the second conductive layer; the third conductive layer has a region in contact with the fourth conductive layer in a first opening of the first insulating layer and a region in contact with the sixth conductive layer in a second opening of the first insulating layer; the second conductive layer has a region in contact with the sixth conductive layer in the third opening of the first insulating layer; the sixth conductive layer has a region that intersects with the first conductive layer in a plan view, the first conductive layer has a region extending in a channel length direction of the transistor in a plan view; the first conductive layer functions as a wiring for supplying a signal to a gate of another transistor arranged in parallel along a channel length direction of the transistor, In a plan view, the fifth conductive layer has a region that extends in a direction intersecting a channel length direction of the transistor.

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