Bias circuit and class AB amplifier circuit

Abstract

To provide a bias circuit and a class-AB amplifier circuit capable of outputting an input bias voltage with accuracy even when a power supply voltage fluctuates in a wide range.SOLUTION: A first voltage mirror circuit 3 from whose first terminal T31 a current depending on a voltage input to a control terminal Tc is output, has a function of operating so that the current output from the first terminal T31, a current input from a second terminal T32, and a current output from a third terminal T33 are substantially equal to each other and operating so that a voltage input to the first terminal T31 and a voltage output to the third terminal T33 are substantially equal to each other. An input T61 and an output T62 of a cascode circuit 6 are connected with a first current source circuit 4 and a second current source circuit 5, respectively. The output T62 of the cascode circuit 6 is connected with the control terminal Tc of the first voltage mirror circuit 3.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a bias circuit and a class AB amplifier circuit. [Background technology]

[0002] The output stage of an amplifier circuit is often configured as a class AB amplifier to improve power efficiency and power supply driving capacity. The class AB amplifier circuit described in Non-Patent Document 1 has been proposed as a method for stabilizing the quiescent current and input bias voltage of a class AB output circuit.

[0003] A class AB output circuit constituting a conventional class AB amplifier circuit and a bias circuit that supplies an input bias voltage to the class AB output circuit will be described with reference to Fig. 16. As shown in Fig. 16, a class AB output circuit 12G has an N-channel transistor Mn1 and a P-channel transistor Mp1 connected in series with each other.

[0004] 16 is a circuit that applies an input bias voltage to a transistor Mn1. The Nch bias circuit 100 has a current source 101 configured from a transistor M104 whose gate is supplied with a bias voltage Vb, a transistor M101 to which current is supplied from the current source 101, a transistor M102 connected to the transistor M101 as a current mirror, a current source 102 that supplies current to the transistor M102, and a diode-connected transistor M103. The source of the transistor M102 is connected to the gate of the transistor Mn1.

[0005] The above-described current sources 101 and 102 supply equal currents to the transistors M101 and M102. Because equal currents flow through the transistors M101 and M102, the gate-source voltages of the transistors M101 and M102 are equal. Therefore, when the class-AB output circuit 12G is in a quiescent state, the source voltage of the transistor M102 is equal to the gate-source voltage of the transistor M103. In other words, the gate-source voltage of the transistor M103 is input to the gate of the transistor Mn1 as an input bias voltage.

[0006] The above-described Nch bias circuit 100 may be required to have a high breakdown voltage so that it can operate even when the power supply voltage of the class AB amplifier circuit is as high as 40V or 60V. For this reason, the class AB output circuit 12G further includes an Nch, high-breakdown-voltage transistor Mn2 cascode-connected to the transistor Mn1, and a Pch, high-breakdown-voltage transistor Mp2 cascode-connected to the transistor Mp1. This configuration can protect the drain-sources of the transistors Mp1 and Mn1 from excessive voltage. Furthermore, the Nch bias circuit 100 uses high-breakdown-voltage transistors for the transistors M101, M102, and M104.

[0007] The drain-source voltage Vds of the transistor M104 that constitutes the current source 101 is expressed by the following equation (1). Vds=VDD-(Vgsm101+Vgsm103) …(1) VDD: Power supply voltage Vgsm101: Gate-source voltage of transistor M101 Vgsm103: Gate-source voltage of transistor M103

[0008] When the power supply voltage VDD decreases and the voltage Vds decreases, transistor M104 cannot operate in the saturation region and instead operates in the triode region, causing a decrease in the drain current of transistor M104. When the drain current of transistor M104 decreases, the current flowing through transistors M101 and M102 decreases, changing the input bias voltage of transistor Mn1. Therefore, the power supply voltage VDD must be set to a minimum operating voltage that prevents transistor M104 from operating in the triode region. However, the high-voltage transistor M101 described above has a thick gate oxide film, resulting in a high threshold voltage and a large gate-source voltage Vgsm101. As the gate-source voltage Vgsm101 increases, the minimum operating voltage of the power supply voltage VDD is limited, as is clear from equation (1) above.

[0009] The Pch bias circuit that applies an input bias voltage to the transistor Mp1 can be explained by replacing "Pch" of the Nch bias circuit 100 with "Nch" and reversing the connections of the positive and negative power supplies, so a detailed explanation will be omitted here. [Prior art documents] [Non-patent literature]

[0010] [Non-Patent Document 1] Ron Hogervorst, John P. Tero, Ruud GH Eschauzier, and Johan H. Huijsing, “A Compact Power-Efficient 3 V CMOS Rail-to-Rail Input / Output Operational Amplifier for VLSI Cell Libraries”, IEEE JOURNAL OF SOLID-STATE CIRCUITS. VOL. 29. NO 12. DECEMBER 1994. Summary of the Invention [Problem to be solved by the invention]

[0011] The present invention has been made in view of the above-mentioned circumstances, and an object of the present invention is to provide a bias circuit and a class AB amplifier circuit that can output an input bias voltage with high precision even when the power supply voltage fluctuates over a wide range. [Means for solving the problem]

[0012] In order to achieve the above-mentioned object, the bias circuit and class AB amplifier circuit according to the present invention are characterized by the following [1] to

[16] . [1] a first voltage mirror circuit having a function of outputting from a first terminal a current corresponding to a voltage input to a control terminal, operating so that the current output from the first terminal, the current input from the second terminal, and the current output from the third terminal are approximately equal, and operating so that the voltage input to the first terminal and the voltage output to the third terminal are approximately equal; a first voltage generating circuit that inputs an output voltage to the first terminal of the first voltage mirror circuit; a cascode circuit having an output connected to the control terminal of the first voltage mirror circuit, an input connected to the second terminal of the first voltage mirror circuit, and having a function of outputting a current substantially equal to an input current and outputting a voltage corresponding to the output current; a first current source circuit connected to the input of the cascode circuit and the second terminal of the first voltage mirror circuit; a second current source circuit connected to the output of the cascode circuit and the control terminal of the first voltage mirror circuit; a negative feedback path is provided from the output to the input of the cascode circuit; the first voltage mirror circuit includes a first transistor and a second transistor whose gates or bases are commonly connected to form the control terminal, and a third current source circuit connected in series to the second transistor and supplying a current to the second transistor; the source or emitter of the first transistor is the first terminal, the drain or collector of the first transistor is the second terminal, and the source or emitter of the second transistor is the third terminal; The cascode circuit has a fourth transistor whose drain or collector serves as an output and whose source or emitter serves as an input. It is a bias circuit. [2] In the bias circuit according to [1], a phase compensation circuit, It is a bias circuit. [3] [1 In the bias circuit according to The first transistor and the second transistor are depletion-type transistors. It is a bias circuit. [4] [1]~[ 3 In the bias circuit according to any one of the above items, the first voltage generating circuit has a diode-connected third transistor; It is a bias circuit. [5] [1]~[ 4 In the bias circuit according to any one of the above items, a second voltage mirror circuit that operates to input a current substantially equal to the current output from the third terminal from a fourth terminal and output the current from a fifth terminal, and that operates so that the voltage input to the fifth terminal and the voltage output to a sixth terminal become substantially equal; a second voltage generating circuit that supplies an output voltage to the fifth terminal of the second voltage mirror circuit; It is a bias circuit. [6] [ 1] or [3 In the bias circuit according to a second voltage mirror circuit including a fifth transistor whose gate or base is commonly connected to the gates or bases of the first transistor and the second transistor, a sixth transistor cascode-connected to the second transistor, a seventh transistor current-mirror-connected to the sixth transistor and cascode-connected to the fifth transistor, and a fourth current source circuit connected in series to the fifth transistor and the seventh transistor; a second voltage generating circuit that supplies an output voltage to the source or emitter of the sixth transistor; It is a bias circuit. [7] [ 6 In the bias circuit according to the first transistor, the second transistor, and the fifth transistor are configured as transistors with a higher breakdown voltage than the sixth transistor and the seventh transistor; It is a bias circuit. [8] [ 6] or [7 In the bias circuit according to the fifth transistor is a depletion-type transistor. Bias circuit. [9] [ 5]~[8 In the bias circuit according to any one of the above items, the second voltage generating circuit includes a diode-connected eighth transistor; It is a bias circuit.

[10] [ 1]~[4 In the bias circuit according to any one of the above items, the transistors constituting the first voltage mirror circuit and the first voltage generating circuit are N-channel transistors; The transistors constituting the cascode circuit are Pch transistors. It is a bias circuit.

[11] [ 5]~[9 In the bias circuit according to any one of the above items, the transistors constituting the first voltage mirror circuit, the second voltage mirror circuit, the first voltage generating circuit, and the second voltage generating circuit are each composed of N-channel transistors; The transistors constituting the cascode circuit are Pch transistors. It is a bias circuit.

[12] [ 1]~[4 In the bias circuit according to any one of the above items, the transistors constituting the first voltage mirror circuit and the first voltage generating circuit are Pch transistors, The transistors constituting the cascode circuit are composed of N-channel transistors. It is a bias circuit.

[13] [ 5]~[9 In the bias circuit according to any one of the above items, the transistors constituting the first voltage mirror circuit, the second voltage mirror circuit, the first voltage generating circuit, and the second voltage generating circuit are Pch transistors; The transistors constituting the cascode circuit are composed of N-channel transistors. It is a bias circuit.

[14] a differential input section that outputs a differential current according to an input voltage; a class AB output circuit having an Nch ninth transistor and a Pch tenth transistor connected in series with each other, and an output terminal connected between the ninth transistor and the tenth transistor;

[0043] connected to the gate or base of the ninth transistor 10 ] or [ 11 ] and a bias circuit according to the tenth transistor [ 12 ] or 13 and a control circuit that controls the ninth transistor and the tenth transistor so as to output an output voltage and an output current corresponding to the differential current output from the differential input section to the output terminal. It must be an AB class amplifier circuit.

[15] [ 14 In the class AB amplifier circuit described in [ 10] or [11 a first positive power supply terminal for supplying a positive first positive power supply voltage to the bias circuit according to the present invention; a second positive power supply terminal for supplying a second positive power supply voltage to the class AB output circuit; [ 10] or [11 and a negative power supply terminal for supplying a negative power supply voltage to the bias circuit and the class AB output circuit, the first positive power supply voltage and the second positive power supply voltage are different voltages; It must be an AB class amplifier circuit.

[16] [ 14 In the class AB amplifier circuit described in [ 12] or [13 a first negative power supply terminal for supplying a negative first negative power supply voltage to the bias circuit according to a second negative power supply terminal for supplying a negative second negative power supply voltage to the class AB output circuit; [ 12] or [13 and a positive power supply terminal for supplying a positive power supply voltage to the bias circuit according to the present invention and the class-AB output circuit, the first negative power supply voltage and the second negative power supply voltage are different voltages; It must be an AB class amplifier circuit. [Effects of the Invention]

[0013] According to the present invention, a bias circuit and a class AB amplifier circuit are provided that can output an input bias voltage with high precision even when the power supply voltage fluctuates over a wide range.

[0014] The present invention has been briefly described above. The details of the present invention will become clearer by reading the following detailed description of the invention (hereinafter referred to as "embodiments") with reference to the accompanying drawings. [Brief explanation of the drawings]

[0015] [Figure 1] FIG. 1 is a block diagram showing an Nch bias circuit according to the first embodiment. [Figure 2] FIG. 2 is a circuit diagram showing details of the Nch bias circuit shown in FIG. 1 according to the first embodiment. [Figure 3] FIG. 3 is a circuit diagram showing details of the Nch bias circuit shown in FIG. 1 according to the second embodiment. [Figure 4] FIG. 4 is a block diagram showing a Pch bias circuit according to the third embodiment. [Figure 5] FIG. 5 is a circuit diagram showing details of the Pch bias circuit shown in FIG. 4 in the third embodiment. [Figure 6]FIG. 6 is a circuit diagram showing details of the Pch bias circuit shown in FIG. 4 in the fourth embodiment. [Figure 7] FIG. 7 is a circuit diagram of a class AB amplifier circuit according to the fifth embodiment. [Figure 8] FIG. 8 is a circuit diagram showing a part of the class AB amplifier circuit according to the sixth embodiment. [Figure 9] FIG. 9 is a circuit diagram showing a part of the class AB amplifier circuit according to the seventh embodiment. [Figure 10] FIG. 10 is a circuit diagram showing a part of the class AB amplifier circuit according to the eighth embodiment. [Figure 11] FIG. 11 is a block diagram showing an Nch bias circuit according to the ninth embodiment. [Figure 12] FIG. 12 is a circuit diagram showing details of the Nch bias circuit shown in FIG. [Figure 13] FIG. 13 is a circuit diagram showing a part of the class-AB amplifier circuit according to the tenth embodiment. [Figure 14] FIG. 14 is a block diagram showing a Pch bias circuit in the eleventh embodiment. [Figure 15] FIG. 15 is a circuit diagram showing details of the Pch bias circuit shown in FIG. [Figure 16] FIG. 16 is a circuit diagram showing an example of an AB class output circuit and an Nch bias circuit that constitute a conventional AB class amplifier circuit. DETAILED DESCRIPTION OF THE INVENTION

[0016] (First embodiment) Fig. 1 is a circuit diagram showing one embodiment of the present invention, an Nch bias circuit 1. The Nch bias circuit 1 (= bias circuit) shown in Fig. 1 is a circuit that generates an input bias voltage Vb1 for an Nch transistor from a positive power supply voltage VDD1 and a negative power supply voltage VSS1, and outputs it from an output terminal T1.

[0017] The Nch bias circuit 1 includes a first voltage generating circuit 2, a first voltage mirror circuit 3, a first current source circuit 4, a second current source circuit 5, and a cascode circuit 6.

[0018] The first voltage generating circuit 2 has one end connected to a negative power supply terminal T22 and the other end connected to a first terminal T31 of a first voltage mirror circuit 3 (described later), and outputs a voltage V11 to the first terminal T31. A negative power supply voltage VSS1 is supplied to the negative power supply terminal T22.

[0019] The first voltage mirror circuit 3 operates so that a current corresponding to the voltage input to the control terminal Tc is output from the first terminal T31, and so that the current output from the first terminal T31, the current input from the second terminal T32, and the current output from the third terminal T33 are all approximately equal. The first voltage mirror circuit 3 also operates so that the voltage input to the first terminal T31 and the voltage output from the third terminal T33 are all approximately equal. The third terminal T33 is connected to the output terminal T1, and outputs an input bias voltage Vb1 that is approximately equal to the voltage V11.

[0020] One end of the first current source circuit 4 is connected to a positive power supply terminal T21, and the other end is connected to a second terminal T32 of the first voltage mirror circuit 3 and an input T61 of a cascode circuit 6 (described later). A positive power supply voltage VDD1 is supplied to the positive power supply terminal T21. The first current source circuit 4 supplies a current I4.

[0021] The second current source circuit 5 has one end connected to the negative power supply terminal T22 and the other end connected to the control terminal Tc of the first voltage mirror circuit 3 and the output T62 of the cascode circuit 6. The second current source circuit 5 supplies a current I5. The cascode circuit 6 outputs from the output T62 a current that is substantially the same as the current input from the input T61, and outputs from the output T62 a voltage that corresponds to the output current.

[0022] With the above configuration, the voltage V11 input to the first terminal T31 of the first voltage mirror circuit 3 and the input bias voltage Vb1 output from the third terminal T33 can be designed and controlled to be equal. In addition, a negative feedback path is formed from the output T62 to the input T61 of the cascode circuit 6. Therefore, the voltage input to the control terminal Tc is adjusted so that the current I3 input to the second terminal T32 of the first voltage mirror circuit 3 and output from the first terminal T31 becomes equal to the current I4 supplied by the first current source circuit 4 minus the current I5 supplied to the second current source circuit 5. This allows the first voltage generation circuit 2 to be designed and controlled so that a desired current flows.

[0023] Next, the Nch bias circuit 1 outlined above will be described in further detail with reference to Figure 2. As shown in the figure, the first voltage generating circuit 2 has a diode-connected transistor M21 (=third transistor). Transistor M21 is an Nch, low-voltage field-effect transistor, and generates a gate-source voltage as voltage V11.

[0024] The first voltage mirror circuit 3 has a transistor M31 (=first transistor) and a transistor M32 (=second transistor) whose gates are commonly connected, and a third current source circuit 33 connected to the transistor M32. The transistors M31 and M32 are configured by N-channel, low-voltage, depletion-type field-effect transistors.

[0025] The gate of the transistor M31 is connected to the drain of the transistor M61 (described later) and the second current source circuit 5, the source is connected to the gate and drain of the transistor M21, and the drain is connected to the source of the transistor M61 and the first current source circuit 4. The source of the transistor M31 serves as the first terminal T31 and the drain serves as the second terminal T32. The gate of the transistor M32 is connected to the gate of the transistor M31 and the source is connected to the third current source circuit 33. The commonly connected gates of the transistors M31 and M32 serve as the control terminal Tc. The source of the transistor M32 serves as the third terminal T33.

[0026] The cascode circuit 6 has a transistor M61 (=fourth transistor). The transistor M61 is configured as a Pch, low-voltage field-effect transistor. The source of the transistor M61 is connected to the first current source circuit 4, and the drain is connected to the second current source circuit 5. A constant bias voltage Vb3 is supplied to the gate of the transistor M61. The source of this transistor M61 serves as the input T61 of the cascode circuit 6, and the drain serves as the output T62 of the cascode circuit 6.

[0027] With the above configuration, the negative feedback path formed by transistor M61 allows transistor M31 to be designed so that current I3, calculated by subtracting current I5 from current I4, flows through it. Therefore, if third current source circuit 33 is designed to supply a current equal to current I3, current I3 will also flow through transistor M32. In other words, because the same current I3 flows through transistors M31 and M32, the gate-to-source voltages of transistors M31 and M32 are equal. Furthermore, because the gates of transistors M31 and M32 are connected together, the source voltage of transistor M32 (input bias voltage Vb1) becomes approximately equal to the source voltage V11 of transistor M31.

[0028] According to the above configuration, for the transistor M31 to operate in the saturation region, the drain-source voltage of the transistor M31 only needs to be greater than the gate-source voltage. Since the depletion-mode transistor M31 has a negative gate-source voltage, the drain-source voltage required to operate in the saturation region can also be low. Therefore, even if the power supply voltage (= VDD1 - VSS1) drops, the drain-source voltage required to operate in the saturation region can be ensured. In other words, the Nch bias circuit 1 of the first embodiment can output the input bias voltage Vb1 with high precision even if the power supply voltage fluctuates over a wide range.

[0029] (Modification of the first embodiment) In the first embodiment described above, the transistors M31 and M32 are configured as depletion-type transistors, but this is not limiting. The transistors M31 and M32 may be configured as enhancement-type transistors with a low threshold voltage (for example, a threshold voltage lower than that of the transistors M61 and M21). Even enhancement-type transistors can achieve the same effect as long as they have a low threshold voltage and a low gate-source voltage.

[0030] In the first embodiment described above, the transistors M31 and M32 are configured as low-voltage transistors, but this is not limitative and the transistors M31 and M32 may be configured as high-voltage transistors.

[0031] (Second embodiment) Next, an Nch bias circuit 1B in a second embodiment will be described with reference to Fig. 3. In Fig. 3, parts equivalent to those in the Nch bias circuit 1 shown in Fig. 2 already described in the first embodiment are designated by the same reference numerals, and detailed description thereof will be omitted. The difference between the first and second embodiments is that the Nch bias circuit 1B further includes a phase compensation capacitance C1. One end of the phase compensation capacitance C1 is connected to the gate of the transistor M31, and the other end is connected to the negative power supply terminal T22.

[0032] In the first embodiment described above, the transistor M61 forms a negative feedback path, which may result in oscillation. Therefore, in the second embodiment, a phase compensation capacitor C1 is connected to the gate of the transistor M31 as a phase compensation circuit. This makes it possible to suppress oscillation of the Nch bias circuit 1B. Note that, although the other end of the phase compensation capacitor C1 is connected to the negative power supply terminal T22 in the example shown in FIG. 3, the other end of the phase compensation capacitor C1 may be connected to any terminal with low impedance, such as the positive power supply terminal T21.

[0033] (Third embodiment) Next, a Pch bias circuit 1C (=bias circuit) of a third embodiment will be described with reference to Figures 4 and 5. The Pch bias circuit 1C shown in Figures 4 and 5 is a circuit that generates an input bias voltage Vb2 for a Pch transistor from a positive power supply voltage VDD1 and a negative power supply voltage VSS1.

[0034] The Pch bias circuit 1C of the third embodiment can be explained by replacing Nch with Pch in the explanation of the Nch bias circuit 1 of the first embodiment, replacing the symbols 1 to 6, T1, M31, M32, 33, M21, and M61 with symbols 1C to 6C, T1C, M31C, M32C, 33C, M21C, and M61C, replacing the negative power supply terminal T22 and negative power supply voltage VSS1 with a positive power supply terminal T21 and a positive power supply voltage VDD1, replacing the positive power supply terminal T21 and positive power supply voltage VDD1 with a negative power supply terminal T22 and a negative power supply voltage VSS1, replacing the voltages V11 and Vb1 with voltages V21 and Vb2, and replacing Figures 1 and 2 with Figures 4 and 5, and therefore a detailed explanation will be omitted here.

[0035] The Pch bias circuit 1C of the third embodiment can also achieve the same effects as the Nch bias circuit 1 of the first embodiment.

[0036] (Modification of the third embodiment) In the third embodiment described above, the transistors M31C and M32C are configured as depletion-type transistors, but this is not limiting. The transistors M31C and M32C may be configured as enhancement-type transistors with a low threshold voltage (for example, a threshold voltage lower than that of the transistors M61C and M21C). Even enhancement-type transistors can achieve the same effect as long as they have a low threshold voltage and a low gate-source voltage.

[0037] In the third embodiment described above, the transistors M31C and M32C are configured as low-voltage transistors, but this is not limiting. The transistors M31C and M32C may also be configured as high-voltage transistors.

[0038] (Fourth embodiment) Next, a Pch bias circuit 1D according to the fourth embodiment will be described with reference to FIG. 6. In FIG. 6, parts equivalent to those in the Pch bias circuit 1C shown in FIG. 5 and already described in the third embodiment are designated by the same reference numerals, and detailed description thereof will be omitted. The difference between the third and fourth embodiments is that the Pch bias circuit 1D further includes a phase compensation capacitance C1D. One end of the phase compensation capacitance C1D is connected to the gate of the transistor M31C, and the other end is connected to the positive power supply terminal T21.

[0039] In the third embodiment described above, the transistor M61C forms a negative feedback path, which may result in oscillation. Therefore, in the fourth embodiment, a phase compensation capacitor C1D is connected to the gate of the transistor M31C as a phase compensation circuit. This makes it possible to suppress oscillation of the Pch bias circuit 1D. Note that, although the other end of the phase compensation capacitor C1D is connected to the positive power supply terminal T21 in the example shown in FIG. 6, the other end of the phase compensation capacitor C1D may be connected to any low-impedance terminal, such as the negative power supply terminal T22.

[0040] (Fifth embodiment) Next, a class-AB amplifier circuit 10 according to a fifth embodiment incorporating the Nch bias circuit 1 shown in the first embodiment and the Pch bias circuit 1C shown in the third embodiment will be described with reference to Fig. 7. To simplify the drawing, in Fig. 7, the transistor M32 and third current source circuit 33 that constitute the Nch bias circuit 1 are shown outside the block representing the Nch bias circuit 1, and the transistor M32C and third current source circuit 33C that constitute the Pch bias circuit 1C are shown outside the block representing the Pch bias circuit 1C.

[0041] The class AB amplifier circuit 10 shown in the figure is a circuit that amplifies an input voltage, which is the difference between an input potential INM input to an input terminal T41 and an input potential INP input to an input terminal T42, and outputs the amplified voltage as an output signal VOUT from an output terminal T4.

[0042] The class AB amplifier circuit 10 includes a differential input section 11, a class AB output circuit 12, and a floating-type control circuit 13.

[0043] The differential input section 11 outputs a differential current corresponding to the input current. The differential input section 11 has differential transistors M1 and M2 whose sources are connected in common, and a constant current source 111. The differential transistors M1 and M2 are configured by Pch field effect transistors. The gate of the differential transistor M1 is connected to the input terminal T41, and the gate of the differential transistor M2 is connected to the input terminal T42. The sources of the differential transistors M1 and M2 are connected in common and are connected to the constant current source 111.

[0044] The constant current source 111 is connected between the positive power supply terminal T21 and the sources of the differential transistors M1 and M2, which are connected in common. The differential input unit 11 divides the constant current supplied by the constant current source 111 into the differential transistors M1 and M2. The current ratio (dividing ratio) of the currents flowing through the differential transistors M1 and M2 is a value that corresponds to the input potentials INM and INP. The difference between the currents flowing through the differential transistors M1 and M2 is output as a differential current.

[0045] The class-AB output circuit 12 has a transistor Mp1 (=tenth transistor), a capacitor Cm1, a transistor Mn1 (=ninth transistor), and a capacitor Cm2. The transistor Mp1 is configured as a Pch field-effect transistor. The transistor Mp1 is configured as a low-voltage transistor. The transistor Mp1 has a source connected to a positive power supply terminal T21, a drain connected to the drain of the transistor Mn1, and a gate connected to the output terminal T1C of the Pch bias circuit 1C. The transistor Mn2 has a source connected to a negative power supply terminal T22, a drain connected to the drain of the transistor Mp1, and a gate connected to the output terminal T1 of the Nch bias circuit 1C. The connection point between the drains of the transistors Mp1 and Mn1 is connected to the output terminal T4. The capacitor Cm1 is connected between the gate and drain of the transistor Mp1. The capacitor Cm2 is connected between the gate and drain of the transistor Mn1.

[0046] The control circuit 13 is a circuit for controlling the output voltage of the class-AB output circuit 12 and the output current flowing to the output terminal T4 in accordance with the current difference (differential current) flowing through the differential transistors M1 and M2. The output signal VOUT has a value according to the output voltage and output current. The control circuit 13 has an Nch bias circuit 1 and a Pch bias circuit 1C.

[0047] The Nch bias circuit 1 and the Pch bias circuit 1C are the same as those in the first embodiment, and therefore detailed description thereof will be omitted here. The transistor M32 constituting the Nch bias circuit 1 and the transistor M32C constituting the Pch bias circuit 1C are connected in parallel. Specifically, the source of the transistor M32 is connected to the drain of the transistor M32C, and the drain of the transistor M32 is connected to the source of the transistor M32C. Therefore, the third current source circuit 33C supplies a current I3 and shunts the current I3 in accordance with the gate-source voltages of the transistors M32 and M32C.

[0048] In this embodiment, the third current source circuit 33 is composed of transistors M3 to M7 and a constant current source 331. The transistors M3 to M6 are composed of Nch, low-voltage field-effect transistors. The transistor M7 is composed of a Pch, low-voltage field-effect transistor. The transistor M3 has a drain connected to the source of the transistor M5, a source connected to the negative power supply terminal T22, and a gate connected to the drain of the transistor M5. The transistor M4 has a drain connected to the source of the transistor M6, a source connected to the negative power supply terminal T22, and a gate connected to the gate of the transistor M3.

[0049] The drain of transistor M5 is connected to the drain of transistor M7, and the gate is connected to the gate of transistor M6. The drain of transistor M6 is connected to the drain of transistor M32C and the source of transistor M32. A bias voltage Vb7 is supplied to the gates of transistors M5 and M6. The gate of transistor M7 is connected to the gates of transistors M31C and M32C, and the source is connected to a constant current source 331. The constant current source 331 is connected between the positive power supply terminal T21 and the source of transistor M7, and supplies a current I3.

[0050] The drain of the differential transistor M1 is connected to the connection point between the drain of the transistor M3 and the source of the transistor M5, and the drain of the differential transistor M2 is connected to the connection point between the drain of the transistor M4 and the source of the transistor M6.

[0051] Transistors M3 to M7 form a cascode current mirror circuit, which operates to control the current and gate voltage of transistor M4 according to the current flowing through transistor M3. When the current flowing through differential transistor M2 is smaller than the current flowing through differential transistor M1, the current flowing from differential transistor M2 to transistor M4 is smaller, resulting in a smaller voltage drop due to the resistance component between the drain and source of transistor M4. This increases the gate-source voltage of transistor M6, and decreases the drain voltage of transistor M6. As a result, the gate-source voltage of transistor Mn1 decreases, and the current flowing through transistor Mn1 decreases. Furthermore, as the drain voltage of transistor M6 decreases, the gate-source voltage of transistor M32 increases, and the proportion of the current flowing from the third current source circuit 33C that flows through transistor M32 increases, and the proportion that flows through transistor M32C decreases. As a result, the source voltage of transistor M32C drops so that the gate-source voltage decreases, the gate-source voltage of transistor Mp1 connected to the source of transistor M32C increases, and the current flowing through transistor Mp1 increases.

[0052] On the other hand, if the current flowing through differential transistor M1 is less than the current flowing through transistor M2, the current flowing from differential transistor M2 to transistor M4 is greater, resulting in a larger voltage drop due to the drain-source resistance of transistor M4. This reduces the gate-source voltage of transistor M6 and increases the drain voltage of transistor M6. As a result, the gate-source voltage of transistor Mn1 increases, and the current flowing through transistor Mn1 increases. Furthermore, as the drain voltage of transistor M6 increases, the gate-source voltage of transistor M32 decreases, and less of the current from the third current source circuit 33C flows through transistor M32, and more of it flows through transistor M32C. This causes the source voltage of transistor M32C to increase its gate-source voltage, reducing the gate-source voltage of transistor Mp1, which is connected to the source of transistor M32C, and reducing the current flowing through transistor Mp1.

[0053] Furthermore, when the currents flowing through the differential transistors M1 and M2 are equal (in the quiescent state), the current flowing from capacitor Cm1 to the drain of transistor M32 and the source of transistor M32C is equal to the current flowing from the source of transistor M32 and the drain of transistor M32C to capacitor Cm2, and the output current is 0. At this time, an input bias voltage Vb2 is supplied to transistor Mp1 by the Pch bias circuit 1C, and an input bias voltage Vb1 is supplied to transistor Mn1 by the Nch bias circuit 1, so both transistors Mp1 and Mn1 are turned on.

[0054] (Sixth embodiment) Next, a class-AB amplifier circuit 10F according to the sixth embodiment will be described with reference to Fig. 8. In Fig. 8, the same components as those in the Nch bias circuit 1 shown in Fig. 2 and described in the first embodiment and the class-AB amplifier circuit 10 shown in Fig. 7 and described in the fifth embodiment are designated by the same reference numerals, and detailed description thereof will be omitted.

[0055] In the fifth embodiment, both the class AB output circuit 12 and the Nch bias circuit 1 are connected to the same positive power supply terminal T21. In contrast, in the sixth embodiment, the class AB output circuit 12 is connected to a positive power supply terminal T23 (= second positive power supply terminal), and the Nch bias circuit 1 is connected to a positive power supply terminal T21 (= first positive power supply terminal). A positive power supply voltage VDD2 (= second positive power supply voltage) is supplied to the positive power supply terminal T23, and the positive power supply voltage VDD2 is a voltage higher than the positive power supply voltage VDD1 (= first positive power supply voltage). The positive power supply voltage VDD1 may be generated from the positive power supply voltage VDD2. As described above, by using separate power supplies for the positive power supply voltage VDD2 supplied to the class AB output circuit 12 and the positive power supply voltage VDD1 supplied to the Nch bias circuit 1, the Nch bias circuit 1 becomes less susceptible to fluctuations in the positive power supply voltage VDD2.

[0056] Seventh embodiment Next, a class-AB amplifier circuit 10G according to the seventh embodiment will be described with reference to Fig. 9. In Fig. 9, the same components as those in the class-AB amplifier circuit 10F shown in Fig. 8 and described in the sixth embodiment above are designated by the same reference numerals, and detailed description thereof will be omitted.

[0057] In the seventh embodiment, the power supply voltage (VDD2-VSS1) is a high voltage. Therefore, in order to protect the transistors Mp1 and Mn2 from high voltage, the class-AB output circuit 12G further includes transistors Mp2 and Mn2. The transistor Mp2 is a P-channel, high-voltage transistor, cascode-connected to the transistor Mp1, and a bias voltage Vb5 is input to its gate. The transistor Mn2 is an N-channel, high-voltage transistor, cascode-connected to the transistor Mn2, and a bias voltage Vb6 is input to its gate. Furthermore, the transistors M31 and M32 that constitute the N-channel bias circuit 1 and the transistors M31C (not shown) and M32C that constitute the P-channel bias circuit 1C also use high-voltage transistors. With the above configuration, a class-AB amplifier circuit 10G that can withstand high voltages can be obtained.

[0058] (Eighth embodiment) Next, a class-AB amplifier circuit 10H according to the eighth embodiment will be described with reference to Fig. 10. In Fig. 10, the same components as those in the Pch bias circuit 1C shown in Fig. 5 and described in the third embodiment and the class-AB amplifier circuit 10 shown in Fig. 7 and described in the fifth embodiment are designated by the same reference numerals, and detailed description thereof will be omitted.

[0059] In the fifth embodiment, both the class AB output circuit 12 and the Pch bias circuit 1C are connected to the same negative power supply terminal T22. In contrast, in the eighth embodiment, the class AB output circuit 12 is connected to the negative power supply terminal T24 (= second negative power supply terminal), and the Pch bias circuit 1C is connected to the negative power supply terminal T22 (= first negative power supply terminal). A negative power supply voltage VSS2 (= second negative power supply voltage) is supplied to the negative power supply terminal T24, and the negative power supply voltage VSS2 is a voltage lower than the negative power supply voltage VSS1 (= first negative power supply voltage). The negative power supply voltage VSS1 may be generated from the negative power supply voltage VSS2. As described above, by using separate power supplies for the negative power supply voltage VSS2 supplied to the class AB output circuit 12 and the negative power supply voltage VSS2 supplied to the Pch bias circuit 1C, the Pch bias circuit 1C becomes less susceptible to fluctuations in the negative power supply voltage VSS2.

[0060] (Modification of the eighth embodiment) In the eighth embodiment, a low-voltage class AB amplifier circuit 10H has been described, but the eighth embodiment may be modified to form a high-voltage class AB amplifier circuit. In this case, in the class AB amplifier circuit 10H shown in Fig. 10, the class AB output circuit 12 is replaced with the high-voltage class AB output circuit 12G shown in Fig. 9 described in the seventh embodiment, and the transistors M31C, M32C, M31 (not shown), and M32 are replaced with high-voltage transistors, thereby forming a high-voltage class AB amplifier circuit. With the above configuration, a class AB amplifier capable of withstanding high voltages can be obtained.

[0061] (Ninth embodiment) Next, an Nch bias circuit 1I of the ninth embodiment will be described with reference to Fig. 11. In Fig. 11, parts equivalent to those in the Nch bias circuit 1 shown in Fig. 1 already described in the first embodiment are designated by the same reference numerals, and detailed description thereof will be omitted. The Nch bias circuit 1I of the ninth embodiment includes a first voltage generating circuit 2, a first voltage mirror circuit 3I, a first current source circuit 4, a second current source circuit 5, a cascode circuit 6, a second voltage generating circuit 7, and a second voltage mirror circuit 8.

[0062] The first voltage generating circuit 2, the first current source circuit 4, the second current source circuit 5, and the cascode circuit 6 are the same as those already explained in the first embodiment, and therefore detailed explanations will be omitted here. The first voltage mirror circuit 3I will be described later.

[0063] The second voltage generation circuit 7 has one end connected to the negative power supply terminal T22 and the other end connected to the fifth terminal T81 of the second voltage mirror circuit 8 (described later), and outputs a voltage V12 to the fifth terminal T81. The second voltage mirror circuit 8 has a fourth terminal T82 connected to the third terminal T33 of the first voltage mirror circuit 3I. The second voltage mirror circuit 8 operates to input a current from the fourth terminal T82 that is approximately equal to the current output from the third terminal T33 and output it from the fifth terminal T81, so that the voltage input to the fifth terminal T81 and the voltage output to the sixth terminal T83 are approximately equal. The sixth terminal T83 is connected to the output terminal T1, and outputs an input bias voltage Vb1 that is approximately equal to the voltage V12.

[0064] Next, the Nch bias circuit 1I outlined above will be described in further detail with reference to Fig. 12. The details of the first voltage generating circuit 2, the first current source circuit 4, the second current source circuit 5, and the cascode circuit 6 are the same as those in the first embodiment described above, and therefore will not be described in detail here.

[0065] Next, a first voltage mirror circuit 3I, which has a different configuration from that of the first embodiment, will be described. The first voltage mirror circuit 3I has transistors M31I and M32I whose gates are commonly connected, and a third current source circuit 33I connected to transistor M32I. The transistors M31I and M32I are composed of N-channel, high-voltage, depletion-type field-effect transistors.

[0066] The connections of the transistors M31I and M32I are similar to those of the transistors M31 and M32 in the first embodiment, and therefore detailed description thereof will be omitted here. In this embodiment, unlike the first embodiment, the third current source circuit 33I is connected between the drain of the transistor M32I and the positive power supply terminal T21.

[0067] The second voltage generating circuit 7 has a diode-connected transistor M71 (=eighth transistor). The transistor M71 is an N-channel, low-voltage field-effect transistor, and generates a gate-source voltage as the voltage V12.

[0068] The second voltage mirror circuit 7 has transistors M81 to M83 and a fourth current source circuit 84. The transistor M81 is composed of an N-channel, high-voltage, depletion-type field-effect transistor. The gate of the transistor M81 (=fifth transistor) is commonly connected to the gates of the transistors M31I and M32I. The transistor M82 (=sixth transistor) and the transistor M83 (=seventh transistor) are composed of N-channel, low-voltage field-effect transistors. The transistor M82 is cascode-connected to the transistor M32I. More specifically, the gate of the transistor M82 is connected to the drain of the transistor M32I, the drain is connected to the source of the transistor M32I, and the source is connected to the gate and drain of the transistor M71.

[0069] The transistor M83 is connected to the transistor M82 in a current mirror configuration and is also connected to the transistor M81 in cascode. More specifically, the gate of the transistor M83 is connected to the gate of the transistor M82, and the drain of the transistor M83 is connected to the source of the transistor M81. The fourth current source circuit 84 is connected between the source of the transistor M83 and the negative power supply terminal T22.

[0070] According to the above configuration, as in the first embodiment, transistor M31I can be designed so that current I3, which is current I4 minus current I5, flows through it. Therefore, if third current source circuit 33I and fourth current source circuit 84 are designed to supply a current equal to current I3, equal currents will flow through transistors M31I, M32I, and M81, resulting in equal gate-source voltages. Furthermore, because the gates of transistors M31I, M32I, and M81 are commonly connected, the source voltages of transistors M32I and M81 will be approximately equal to source voltage V11 of transistor M31I.

[0071] In addition, an equal current I3 flows through transistors M82 and M83, so the gate-source voltages are equal. Furthermore, because the gates of transistors M82 and M83 are connected in common, the source voltage (input bias voltage Vb1) of transistor M83 becomes approximately equal to the source voltage V12 of transistor M82.

[0072] As described above, the drain of transistor M82 (the source of transistor M32I) is at voltage V11, and the source is at voltage V12. If voltage V11 is set higher than voltage V12, transistor M82 can be operated in the saturation region. Furthermore, because the gate of transistor M82 is connected to the drain of transistor M32I, the drain of transistor M32I is fixed to a voltage obtained by adding the gate-source voltage of transistor M82 to voltage V12, which allows transistor M32I to operate in the saturation region.

[0073] High-voltage, depletion-type transistors have larger manufacturing variations in threshold voltage and higher temperature dependency than low-voltage transistors. Therefore, the Nch bias circuit 1 of the first embodiment shown in FIG. 2, in which the transistors M31 and M32 are high-voltage, depletion-type transistors, has high manufacturing variations and temperature dependency in the input bias voltage Vb1. In contrast, the Nch bias circuit 1I of the ninth embodiment reduces manufacturing variations and temperature dependency because the input bias voltage Vb1 becomes voltage V12 due to the operation of the low-voltage transistors M82 and M83. Furthermore, because the high-voltage transistors M32I and M81 are cascode-connected to the low-voltage transistors M82 and M83, respectively, the low-voltage transistors M82 and M82 can be protected from high voltages.

[0074] (Tenth embodiment) Next, a class-AB amplifier circuit 10J of the tenth embodiment will be described with reference to Fig. 13. In Fig. 13, parts equivalent to those of the class-AB amplifier circuit 10G shown in Fig. 9 already described in the seventh embodiment are designated by the same reference numerals, and detailed description thereof will be omitted. The class-AB amplifier circuit 10G of the seventh embodiment differs from the class-AB amplifier circuit 10J shown in the tenth embodiment in the following respects: The class-AB amplifier circuit 10J of the tenth embodiment is provided with the Nch bias circuit 1I described in the ninth embodiment instead of the Nch bias circuit 1 of the seventh embodiment.

[0075] (Eleventh embodiment) Next, a Pch bias circuit 1K of an eleventh embodiment will be described with reference to Fig. 14. The Pch bias circuit 1K of the eleventh embodiment can be described by replacing "Nch" with "Pch" in the description of the Nch bias circuit 1I of the ninth embodiment shown in Fig. 11, replacing the symbols 1, 1I, 2, 3I, and 4 to 8 with symbols 1C, 1K, 2C, 3K, and 4C to 8C, replacing Fig. 11 with Fig. 14, replacing the first and ninth embodiments with the third and eleventh embodiments, replacing the positive power supply terminal T21 and the positive power supply voltage VDD1 with the negative power supply terminal T22 and the negative power supply voltage VSS1, and replacing V12 with V22 and Vb1 with Vb2, and therefore a detailed description thereof will be omitted here.

[0076] Next, the Pch bias circuit 1K outlined above will be described in further detail with reference to Fig. 15. The Pch bias circuit 1K of the eleventh embodiment can be described by replacing the reference symbols M31I, M32I, 33I, M71, M81 to M83, and 84 with M31K, M32K, 33K, M71C, M81C to M83C, and 84C in the Nch bias circuit 1I of the ninth embodiment shown in Fig. 12, in addition to the above-mentioned replacements, and therefore a detailed description will be omitted here. The Pch bias circuit 1K of the eleventh embodiment can also obtain the same effects as the Nch bias circuit 1I of the ninth embodiment.

[0077] (Twelfth embodiment) Next, a class AB amplifier circuit according to a twelfth embodiment will be described. The class AB amplifier circuit according to the twelfth embodiment may use the Pch bias circuit 1K shown in Fig. 15 described in the eleventh embodiment, instead of the Pch bias circuit 1C constituting the class AB amplifier circuit 10H according to the eighth embodiment shown in Fig. 10.

[0078] The present invention is not limited to the above-described embodiments, and can be appropriately modified, improved, etc. Furthermore, the material, shape, size, number, location, etc. of each component in the above-described embodiments are arbitrary and not limited as long as they can achieve the present invention.

[0079] For example, the Nch bias circuit 1B described in the second embodiment may be used in place of the Nch bias circuit 1 constituting the class-AB amplifier circuit 10 shown in the fifth embodiment. Similarly, the Pch bias circuit 1C may be used in place of the Pch bias circuit 1D described in the fourth embodiment.

[0080] In the first to twelfth embodiments, the transistors are configured as field-effect transistors, but this is not limiting. The transistors may be configured as bipolar transistors. In this case, the transistor gate can be considered as the base, the source as the emitter, and the drain as the collector. [Explanation of symbols]

[0081] 1, 1B, 1I Nch bias circuit (bias circuit) 1C, 1D, 1K Pch bias circuit (bias circuit) 2, 2C First voltage generating circuit 3, 3C, 3I, 3K First voltage mirror circuit 4, 4C 1st current source circuit 5, 5C 2nd current source circuit 6, 6C cascode circuit 7, 7C Second voltage generating circuit 8, 8C Second voltage mirror circuit 10, 10F, 10G, 10H, 10J Class AB amplifier circuit 11 Differential input section 12, 12G AB class output circuit 13 Control circuit 33, 33C, 33I, 33K 3rd current source circuit 84, 84C 4th current source circuit C1, C1D Phase compensation capacitance (phase compensation circuit) M21, M21C transistors (third transistor) M31, M31C, M31I, M31K transistors (first transistor) M32, M32C, M32I, M32K transistors (second transistor) M61, M61C transistor (fourth transistor) M71, M71C transistor (8th transistor) M81, M81C transistor (fifth transistor) M82, M82C transistor (6th transistor) M83, M83C transistor (7th transistor) Mn1 transistor (9th transistor) Mp1 transistor (10th transistor) T21 Positive power supply terminal (first positive power supply terminal) T22 Negative power supply terminal (first negative power supply terminal) T23 Positive power supply terminal (second positive power supply terminal) T24 Negative power supply terminal (second negative power supply terminal) T4 output terminal T31 1st terminal T32 2nd terminal T33 Third terminal T81 Terminal 5 T82 4th terminal T83 6th terminal Tc control terminal V11, V21, V12, V22 voltage VDD1 Positive power supply voltage (first positive power supply voltage) VDD2 Positive power supply voltage (second positive power supply voltage) VSS1 Negative power supply voltage (first negative power supply voltage) VSS2 Negative power supply voltage (second negative power supply voltage)

Claims

1. a first voltage mirror circuit having a function of outputting from a first terminal a current corresponding to a voltage input to a control terminal, operating so that the current output from the first terminal, the current input from the second terminal, and the current output from the third terminal are approximately equal, and operating so that the voltage input to the first terminal and the voltage output to the third terminal are approximately equal; a first voltage generating circuit that inputs an output voltage to the first terminal of the first voltage mirror circuit; a cascode circuit having an output connected to the control terminal of the first voltage mirror circuit, an input connected to the second terminal of the first voltage mirror circuit, and having a function of outputting a current substantially equal to an input current and outputting a voltage corresponding to the output current; a first current source circuit connected to the input of the cascode circuit and the second terminal of the first voltage mirror circuit; a second current source circuit connected to the output of the cascode circuit and the control terminal of the first voltage mirror circuit; a negative feedback path is provided from the output to the input of the cascode circuit; the first voltage mirror circuit includes a first transistor and a second transistor whose gates or bases are commonly connected to form the control terminal, and a third current source circuit connected in series to the second transistor and supplying a current to the second transistor; the source or emitter of the first transistor is the first terminal, the drain or collector of the first transistor is the second terminal, and the source or emitter of the second transistor is the third terminal; the cascode circuit has a fourth transistor whose drain or collector serves as an output and whose source or emitter serves as an input; Bias circuit.

2. 2. The bias circuit according to claim 1, a phase compensation circuit, Bias circuit.

3. 2. The bias circuit according to claim 1, the first transistor and the second transistor are configured as depletion-type transistors; Bias circuit.

4. The bias circuit according to any one of claims 1 to 3, the first voltage generating circuit has a diode-connected third transistor; Bias circuit.

5. The bias circuit according to any one of claims 1 to 4, a second voltage mirror circuit that operates to input a current substantially equal to the current output from the third terminal from a fourth terminal and output the current from a fifth terminal, and that operates so that the voltage input to the fifth terminal and the voltage output to a sixth terminal become substantially equal; a second voltage generating circuit that supplies an output voltage to the fifth terminal of the second voltage mirror circuit; Bias circuit.

6. 4. The bias circuit according to claim 1, a second voltage mirror circuit including a fifth transistor whose gate or base is commonly connected to the gates or bases of the first transistor and the second transistor, a sixth transistor cascode-connected to the second transistor, a seventh transistor current-mirror-connected to the sixth transistor and cascode-connected to the fifth transistor, and a fourth current source circuit connected in series to the fifth transistor and the seventh transistor; a second voltage generating circuit that supplies an output voltage to the source or the emitter of the sixth transistor; Bias circuit.

7. 7. The bias circuit according to claim 6, the first transistor, the second transistor, and the fifth transistor are configured as transistors having a higher withstand voltage than the sixth transistor and the seventh transistor; Bias circuit.

8. 8. The bias circuit according to claim 6, the fifth transistor is a depletion-type transistor. Bias circuit.

9. The bias circuit according to any one of claims 5 to 8, the second voltage generating circuit includes an eighth transistor that is diode-connected; Bias circuit.

10. The bias circuit according to any one of claims 1 to 4, the transistors constituting the first voltage mirror circuit and the first voltage generating circuit are N-channel transistors, The transistors constituting the cascode circuit are Pch transistors. Bias circuit.

11. The bias circuit according to any one of claims 5 to 9, the transistors constituting the first voltage mirror circuit, the second voltage mirror circuit, the first voltage generating circuit, and the second voltage generating circuit are each composed of N-channel transistors; The transistors constituting the cascode circuit are Pch transistors. Bias circuit.

12. The bias circuit according to any one of claims 1 to 4, the transistors constituting the first voltage mirror circuit and the first voltage generating circuit are P-channel transistors, The transistors constituting the cascode circuit are composed of N-channel transistors. Bias circuit.

13. The bias circuit according to any one of claims 5 to 9, the transistors constituting the first voltage mirror circuit, the second voltage mirror circuit, the first voltage generating circuit, and the second voltage generating circuit are each composed of Pch transistors; The transistors constituting the cascode circuit are composed of N-channel transistors. Bias circuit.

14. a differential input section that outputs a differential current according to an input voltage; a class AB output circuit having an N-channel ninth transistor and a P-channel tenth transistor connected in series with each other, and an output terminal connected between the ninth transistor and the tenth transistor; a bias circuit connected to a gate or a base of the ninth transistor according to claim 10 or 11, and a bias circuit connected to a gate or a base of the tenth transistor according to claim 12 or 13, and a control circuit that controls the ninth transistor and the tenth transistor so as to output an output voltage and an output current corresponding to a differential current output from the differential input section to the output terminal. Class AB amplifier circuit.

15. 15. The class AB amplifier circuit according to claim 14, a first positive power supply terminal for supplying a first positive power supply voltage to the bias circuit according to claim 10 or 11; a second positive power supply terminal for supplying a second positive power supply voltage to the class AB output circuit; a negative power supply terminal for supplying a negative power supply voltage to the bias circuit according to claim 10 or 11 and the class AB output circuit; the first positive power supply voltage and the second positive power supply voltage are different voltages; Class AB amplifier circuit.

16. 15. The class AB amplifier circuit according to claim 14, a first negative power supply terminal for supplying a negative first negative power supply voltage to the bias circuit according to claim 12 or 13; a second negative power supply terminal for supplying a negative second negative power supply voltage to the class AB output circuit; a bias circuit according to claim 12 or 13 and a positive power supply terminal for supplying a positive power supply voltage to the class AB output circuit; the first negative power supply voltage and the second negative power supply voltage are different voltages; Class AB amplifier circuit.

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