Power amplifier

Abstract

A power amplifier capable of appropriately suppressing an output voltage according to a temperature is provided. A first member including a semiconductor region is joined to a second member including a semiconductor region of a compound semiconductor system on a first surface of the first member. The second member includes an amplification circuit including a semiconductor element of a compound semiconductor system, and a plurality of clamp diodes connected in multiple stages and inserted between an output port of the amplification circuit and a ground line. The first member includes a switch connected between a lead-out point that is a point halfway through the plurality of clamp diodes connected in multiple stages and the ground line, a temperature sensor, and a switch control circuit that performs on-off control of the switch based on a measurement result of the temperature sensor. The lead-out point is connected to the switch via a path including an inter-member connection wiring composed of a metal pattern disposed on an interlayer insulating film from the first surface of the first member to a surface of the second member, or a path crossing an interface at which the first member and the second member are joined.

Description

Technical Field

[0001] This invention relates to power amplifiers. Background Technology

[0002] One of the key components in mobile terminals is the high-frequency power amplifier. To maximize the wireless transmission capacity of mobile terminals, wireless communication standards utilizing multiple frequency bands, such as carrier aggregation (CA), have become practical. With the increase in the number of frequency bands used, the circuit configuration of the RF front-end becomes more complex. Furthermore, in order to utilize the Sub-6GHz frequency band of fifth-generation mobile communication systems (5G), the circuit configuration of the RF front-end becomes even more complex.

[0003] If the RF front-end circuitry becomes more complex, the losses caused by filters, switches, and other components inserted into the transmission line from the high-frequency power amplifier to the antenna increase. As a result, in addition to corresponding to multiple frequency bands, high output is required in the high-frequency power amplifier.

[0004] The output current and voltage of a high-frequency power amplifier vary significantly depending on the phase change of the load. High-frequency power amplifiers require high output power and improved withstand voltage characteristics under load variations. Generally, there is a trade-off between power amplification and withstand voltage characteristics; it is difficult to improve the withstand voltage simultaneously while increasing the power amplification.

[0005] Patent Document 1 discloses a high-frequency power amplifier with multiple stages of clamping diodes connected to the output port. This power amplifier includes a feedback circuit that takes a voltage signal from the middle of the multi-stage clamping diodes and, if a high voltage signal is detected, changes the bias current to reduce the amplifier's gain.

[0006] Patent Document 1: US Patent No. 6580321

[0007] The breakdown voltage of transistors in amplifier circuits is temperature-dependent, especially decreasing at low temperatures. For example, if feedback control is implemented to prevent transistor breakdown at high temperatures, there is a concern that the transistor may break down at low temperatures. Conversely, if feedback control is implemented to prevent transistor breakdown at low temperatures, although there is still a margin up to the breakdown voltage limit at high temperatures, the output is suppressed, violating the high output optimization principle. Summary of the Invention

[0008] The purpose of this invention is to provide a power amplifier that can appropriately suppress the output voltage according to temperature.

[0009] According to one aspect of the present invention, a power amplifier is provided, comprising:

[0010] The first component includes a semiconductor region; and

[0011] The second component is coupled to a first surface that is one side of the first component, and includes a semiconductor region of a compound semiconductor system.

[0012] The second component mentioned above includes:

[0013] Amplifier circuits, including compound semiconductor semiconductor elements; and

[0014] Multiple clamping diodes are connected in multiple stages and inserted between the output port of the aforementioned amplifier circuit and the ground line.

[0015] The aforementioned first component includes:

[0016] The switch is connected between the lead-out point and the ground wire. The lead-out point is the midpoint of the multiple clamping diodes connected in a multi-stage manner.

[0017] Temperature sensor; and

[0018] The switch control circuit controls the opening and closing of the switch based on the measurement results from the aforementioned temperature sensor.

[0019] The aforementioned lead-out point is connected to the aforementioned switch via a path including inter-component connection wiring, or via a path intersecting the interface where the aforementioned first component and the aforementioned second component are joined. The aforementioned inter-component connection wiring is disposed on an interlayer insulating film from the aforementioned first surface of the aforementioned first component to the surface of the aforementioned second component and is formed by a metal pattern.

[0020] According to another aspect of the present invention, a power amplifier is provided, comprising:

[0021] The first component includes a semiconductor region; and

[0022] The second component is coupled to a first surface that is one side of the first component, and includes a semiconductor region of a compound semiconductor system.

[0023] The second component mentioned above includes:

[0024] Amplification circuits, including compound semiconductor semiconductor elements;

[0025] Multiple clamping diodes are inserted between the output port of the aforementioned amplifier circuit and ground, and are connected in series with each other; and

[0026] The switch is connected between the lead-out point and the ground wire. This lead-out point is a midway point in the multi-stage connection of the aforementioned clamping diodes.

[0027] The aforementioned first component includes:

[0028] Temperature sensor; and

[0029] The switch control circuit controls the opening and closing of the switch based on the measurement results of the temperature sensor.

[0030] By controlling the switching on and off based on measurements from a temperature sensor, the effective number of stages of a multi-stage clamping diode can be adjusted according to temperature. The number of stages of the clamping diode can be set to an appropriate value corresponding to the temperature, thus appropriately suppressing transient voltage at the output port. Furthermore, since the leads are connected to the switch via inter-component wiring or via a path intersecting the interface between the first and second components, the increase in parasitic inductance along the path from the leads of the multi-stage clamping diode to ground can be suppressed. Therefore, connecting the leads to ground effectively reduces the number of effective stages of the clamping diode. Attached Figure Description

[0031] Figure 1 This is a block diagram of the power amplifier in the first embodiment.

[0032] Figure 2 This is a schematic cross-sectional view of the power amplifier of the first embodiment.

[0033] Figure 3 This is a cross-sectional view of a first component and a portion of a second component of the power amplifier in the first embodiment.

[0034] Figures 4A to 4F The attached figure is a cross-sectional view of a power amplifier during the manufacturing process.

[0035] Figures 5A to 5C The attached diagram is a cross-sectional view of a power amplifier during the manufacturing process. Figure 5D This is a cross-sectional view of the completed power amplifier.

[0036] Figure 6 This is a graph representing an example of the breakdown withstand voltage characteristics of HBT.

[0037] Figure 7A as well as Figure 7B It means to apply to Figure 1 The graph shows the simulation results of the instantaneous collector voltage and instantaneous collector current of the transistor in the power stage amplifier circuit shown.

[0038] Figure 8 It means to apply to Figure 1 The graph shows the simulation results of the instantaneous collector voltage and instantaneous collector current of the transistor in the power stage amplifier circuit shown.

[0039] Figure 9A as well as Figure 9B It means to apply to Figure 1The graph shows the simulation results of the instantaneous collector voltage and instantaneous collector current of the transistor in the power stage amplifier circuit shown.

[0040] Figure 10 It means to apply to Figure 1 The graph shows the simulation results of the instantaneous collector voltage and instantaneous collector current of the transistor in the power stage amplifier circuit shown.

[0041] Figure 11 This is a schematic cross-sectional view of the power amplifier in the second embodiment.

[0042] Figure 12 This is a cross-sectional view of a first component and a portion of a second component of the power amplifier in the second embodiment.

[0043] Figure 13 This is a block diagram of the power amplifier in the third embodiment.

[0044] Figure 14 This is a schematic cross-sectional view of the power amplifier in the fourth embodiment.

[0045] Explanation of reference numerals: 20…power amplifier, 21…driver stage amplifier circuit, 21out…output port of the driver stage amplifier circuit, 22…power stage amplifier circuit, 22out…output port of the power stage amplifier circuit, 22T…transistor of the power stage amplifier circuit, 23…output matching circuit, 25…interstage matching circuit, 30…clamping diode, 31…lead point, 32…ground, 35…clamping diode, 36…lead point, 40…switch control circuit, 41…temperature sensor, 42, 43…switch, 51…first component, 51A…first surface of the first component, 52…semiconductor substrate, 53…multilayer wiring structure, 54, 55…wiring, 56…adhesive layer, 56A, 56B, 56D…metallic region, 56C…insulating region, 57…wiring, 61…second component, 62…substrate semiconductor layer 62A, 62B…Conductive regions, 62C…Component separation regions, 63B…Base layer, 63C…Collector layer, 63E…Emitter layer, 63N…Cathode layer, 63P…Anode layer, 64B…Base electrode, 64C…Collector electrode, 64E…Emitter electrode, 64N…Cathode electrode, 64P…Anode electrode, 65C…Collector wiring, 65E…Emitter wiring, 65N…Cathode wiring, 65P…Anode wiring, 66…Interlayer insulating film, 71…Inter-component connection wiring, 72, 73…Solder pads, 75…Inter-component connection wiring, 77…Interlayer insulating film, 78…Protective film, 82…Conductor protrusion, 82A…Cu pillar, 82B…Solder layer, 83…Conductor protrusion, 200…Mother substrate, 201…Release layer, 202…Component forming layer, 204…Connector support, 210…Substrate. Detailed Implementation

[0046] [First Embodiment]

[0047] Reference Figures 1-10 The power amplifier of the first embodiment is described in the accompanying drawings.

[0048] Figure 1 This is a block diagram of the power amplifier of the first embodiment. The power amplifier of the first embodiment consists of two stages: a driver stage amplifier circuit 21 and a power stage amplifier circuit 22. The high-frequency signal input from the input terminal Pin is amplified in the driver stage amplifier circuit 21, and the amplified high-frequency signal is further amplified in the power stage amplifier circuit 22.

[0049] The high-frequency signal amplified by the power stage amplifier circuit 22 and output from the output port 22out is output from the output terminal Pout via the output matching circuit 23. Multiple clamping diodes 30 with multi-stage connections are connected between the output port 22out of the power stage amplifier circuit 22 and the ground line 32. The multiple clamping diodes 30 are connected with positive polarity in the direction from the output port 22out towards the ground line 32.

[0050] A switch 42 is connected between a point (hereinafter referred to as lead-out point 31) in the middle of a multi-stage connection of clamping diodes 30 and ground 32. For example, six clamping diodes 30 are connected in a multi-stage configuration, with lead-out point 31 located between the second and third clamping diodes 30 from the ground 32 side. When switch 42 is turned on, the parasitic inductance of the path from lead-out point 31 to ground 32 is denoted as PL. For example, a high-frequency current flows through this path. In this case, the path formed by the conductor functions as a "current path". Furthermore, there are also cases where high-frequency voltage signals are primarily transmitted through this path.

[0051] Temperature sensor 41 measures the temperature of the transistor constituting the power stage amplifier circuit 22. As an example, temperature sensor 41 indirectly measures the transistor temperature by measuring the temperature of the portion of the transistor that experiences a temperature rise due to heat conduction, i.e., the temperature of the portion of the transistor affected by heat. Switch control circuit 40 controls the on / off state of switch 42 based on the measurement result of temperature sensor 41. For example, if the measured value of temperature sensor 41 is below a first threshold, switch control circuit 40 turns switch 42 on. If the measured value of temperature sensor 41 becomes above a second threshold when switch 42 is on, switch 42 returns to the off state.

[0052] Figure 2 This is a schematic cross-sectional view of the power amplifier of the first embodiment. Furthermore, in Figure 2 In the diagram, a portion of the circuit is schematically shown using circuit diagram symbols and dashed lines.

[0053] The power amplifier of the first embodiment includes a first component 51 and a second component 61. For example, the first component 51 is made of a monolithic semiconductor system, and the second component 61 is made of a compound semiconductor system. The first component 51 includes a semiconductor region of the monolithic semiconductor system. For example, the first component 51 includes a semiconductor substrate 52 and a multilayer wiring structure 53 disposed on one side thereof. In addition, a protective film may be disposed covering the surface of the multilayer wiring structure 53. As the semiconductor substrate 52, a monolithic semiconductor substrate such as a silicon substrate or a silicon-on-insulator (SOI) substrate can be used.

[0054] The second component 61 contacts and engages with the surface of the multilayer wiring structure 53 (hereinafter referred to as the first surface 51A). When a protective film is configured to cover the surface of the multilayer wiring structure 53, the surface of this protective film is defined as the first surface 51A. The second component 61 includes a semiconductor region of a compound semiconductor system. (See below for further details.) Figure 3 The structure of the second component 61 is described in detail.

[0055] The first component 51 includes a switch 42, a switch control circuit 40, and a temperature sensor 41. The switch 42 is, for example, a MOSFET formed on the surface layer of the semiconductor substrate 52. The temperature sensor 41 includes, for example, a diode formed on the surface layer of the semiconductor substrate 52. The switch control circuit 40 includes an AD conversion circuit, a memory circuit, and a voltage generation circuit, all composed of multiple semiconductor elements formed on the surface layer of the semiconductor substrate 52. The AD conversion circuit converts the analog temperature-related measured value from the temperature sensor 41 into a digital signal. The voltage generation circuit generates a voltage signal to control the switch 42 based on control information stored in the memory circuit and the measured value from the temperature sensor 41.

[0056] The second component 61 includes a driver stage amplifier circuit 21. Figure 1 ), power stage amplifier circuit 22 ( Figure 1 The power stage amplifier circuit 22 includes multiple clamping diodes 30 connected in multiple stages. An interlayer insulating film 77 is configured to cover the first surface 51A of the first component 51 and the second component 61. The upper surface of the interlayer insulating film 77 is planarized. Inter-component connection wiring 71, solder pads 72, 73, etc., formed by metallic patterns are disposed on the interlayer insulating film 77.

[0057] The solder pad 72 is connected to the emitter of the transistor 22T in the power stage amplifier circuit 22 through an opening in the interlayer insulating film 77. Another solder pad 73 is connected to wiring within the multilayer wiring structure 53 through an opening in the interlayer insulating film 77. The inter-component connection wiring 71 is connected to the lead-out point 31 of the multi-stage clamping diode 30 through an opening in the interlayer insulating film 77, and is connected to the switch 42 through other openings in the interlayer insulating film 77 and via wiring 54 within the multilayer wiring structure 53.

[0058] The wiring layer containing inter-component connection wiring 71, solder pads 72, 73, etc., is sometimes referred to as a rewiring layer. An insulating protective film 78 is disposed on top of the interlayer insulating film 77 to cover the rewiring layer. The protective film 78 is provided with openings that are respectively included in the solder pads 72, 73, etc. when viewed from above. Conductor protrusions 82, 83 are respectively provided on the solder pads 72, 73 exposed in the openings. The conductor protrusions 82, 83 protrude from the upper surface of the protective film 78 and extend to the upper surface of the protective film 78 around the openings.

[0059] The conductor protrusion 82 includes a Cu pillar 82A connected to the solder pad 72 and a solder layer 82B disposed on the upper surface of the Cu pillar 82A. This type of conductor protrusion 82 is called a Cu pillar bump. Furthermore, a bump under-metal layer can be disposed on the bottom surface of the Cu pillar 82A to improve adhesion. Other conductor protrusions 83 also have the same stacked structure as the conductor protrusion 82. In addition, conductor protrusions 82, 83, etc., can replace Cu pillar bumps with Au bumps, solder ball bumps, conductor pillars erected on the solder pad, etc. Bumps without a solder layer, such as Au bumps, are also called pillars. Conductor pillars erected on the solder pad are also called posts.

[0060] The grounding conductor in the second component 61 and the grounding conductor in the first component 51 are interconnected through rewiring in the rewiring layer. Alternatively, the grounding conductor in the second component 61 and the grounding conductor in the first component 51 may be connected to a common grounding conductor of the module substrate via conductor protrusions respectively provided in the first component 51 and the second component 61.

[0061] Figure 3 This is a cross-sectional view of a portion of the first component 51 and the second component 61 of the power amplifier 20 according to the first embodiment. The second component 61 includes a substrate semiconductor layer 62 and a power stage amplifier circuit 22 disposed thereon. Figure 1The transistor 22T, clamping diode 30, etc. are included. The substrate semiconductor layer 62 is in contact with and bonded to the first surface 51A of the first component 51. The substrate semiconductor layer 62 is divided into multiple conductive regions 62A, 62B, etc., and a component separation region 62C that electrically separates the multiple conductive regions 62A, 62B, etc. from each other. For example, the conductive regions 62A, 62B, etc. are formed of n-type GaAs. The component separation region 62C is formed by insulating by implanting impurities into the n-type GaAs.

[0062] A transistor 22T is disposed above conductive region 62A, and a clamping diode 30 is disposed above conductive region 62B. Figure 3 The diagram shows one of a plurality of transistors 22T and one of a plurality of clamping diodes 30. The power stage amplifier circuit 22 includes a plurality of transistors 22T connected in parallel.

[0063] Transistor 22T includes a collector layer 63C, a base layer 63B, and an emitter layer 63E sequentially stacked on a conductive region 62A. The emitter layer 63E is disposed on a portion of the base layer 63B. The collector layer 63C is formed, for example, of n-type GaAs and is electrically connected to the conductive region 62A. The base layer 63B is formed, for example, of p-type GaAs. The emitter layer 63E is formed, for example, of n-type InGaP. Alternatively, a layer made of n-type GaAs may be disposed on the emitter layer 63E. A heterojunction bipolar transistor (HBT) is constructed using the collector layer 63C, the base layer 63B, and the emitter layer 63E.

[0064] An emitter electrode 64E is disposed on the emitter layer 63E. The emitter electrode 64E is electrically connected to the emitter layer 63E. A base electrode 64B is disposed on the base layer 63B. The base electrode 64B is electrically connected to the base layer 63B. A collector electrode 64C is disposed on the conductive region 62A. The collector electrode 64C is electrically connected to the collector layer 63C via the conductive region 62A.

[0065] The clamping diode 30 includes a cathode layer 63N and an anode layer 63P sequentially stacked on a conductive region 62B. The cathode layer 63N and the collector layer 63C are formed by patterning the same semiconductor layer, and the anode layer 63P and the base layer 63B are formed by patterning the same semiconductor layer. The cathode layer 63N is electrically connected to the conductive region 62B.

[0066] An anode electrode 64P is disposed on the anode layer 63P. The anode electrode 64P is electrically connected to the anode layer 63P. A cathode electrode 64N is disposed on the conductive region 62B. The cathode electrode 64N is electrically connected to the cathode layer 63N via the conductive region 62B.

[0067] An interlayer insulating film 66 is configured on the substrate semiconductor layer 62 to cover the transistor 22T and the clamping diode 30. Openings are provided at predetermined positions on the interlayer insulating film 66. A first wiring layer is disposed on the interlayer insulating film 66. The first wiring layer includes an emitter wiring 65E, a collector wiring 65C, an anode wiring 65P, and a cathode wiring 65N. The emitter wiring 65E and the collector wiring 65C are respectively connected to the emitter electrode 64E and the collector electrode 64C through the openings in the interlayer insulating film 66. The anode wiring 65P and the cathode wiring 65N are respectively connected to the anode electrode 64P and the cathode electrode 64N through the openings in the interlayer insulating film 66.

[0068] An interlayer insulating film 77 is disposed above the first wiring layer. The interlayer insulating film 77 is as follows: Figure 2 It extends to the first surface 51A of the first component 51 as shown. An opening is provided at a predetermined position on the interlayer insulating film 77.

[0069] A redistribution layer including a solder pad 72 is disposed on the interlayer insulating film 77. The solder pad 72 is connected to the emitter wiring 65E through an opening provided in the interlayer insulating film 77. A protective film 78 is disposed to cover the solder pad 72. An opening is provided in the protective film 78 to expose the solder pad 72. A conductor protrusion 82 is disposed on the exposed solder pad 72 within the opening and on the protective film 78 around the opening. The conductor protrusion 82 includes a Cu pillar 82A and a solder layer 82B. The conductor protrusion 82 serves as an external connection terminal for connecting the emitter of the transistor 22T to an external circuit.

[0070] Next, refer to Figures 4A to 5D The accompanying drawings illustrate the manufacturing method of the power amplifier according to the first embodiment. Figures 4A to 5C The attached diagram is a cross-sectional view of a power amplifier during the manufacturing process. Figure 5D This is a cross-sectional view of the completed power amplifier.

[0071] like Figure 4A As shown, a release layer 201 is epitaxially grown on a single-crystal mother substrate 200 of a compound semiconductor such as GaAs, and a device forming layer 202 is formed on the release layer 201. A device forming layer 202 is formed on the device forming layer 202. Figure 3 The second component 61 shown includes transistor 22T, clamping diode 30, first wiring layer, etc. These circuit elements are formed using conventional semiconductor processes. Figure 4A The element structure formed on the element forming layer 202 is omitted from the description. At this stage, the element forming layer 202 is not separated into individual second components 61.

[0072] Next, as Figure 4B As shown, the resist pattern (not shown) is used as an etching mask to form the element layer 202. Figure 4A The element forming layer 202 is patterned, along with the release layer 201. Figure 4A They are separated according to each of the second components 61.

[0073] Next, as Figure 4C As shown, a connecting support 204 is attached to the separated second component 61. Thus, multiple second components 61 are interconnected via the connecting support 204. Furthermore, it is also possible to... Figure 4B The resist pattern used as an etching mask during the patterning process remains, and the resist pattern is sandwiched between the second component 61 and the connecting support 204.

[0074] Next, as Figure 4D As shown, the release layer 201 is selectively etched onto the mother substrate 200 and the second component 61. As a result, the second component 61 and the connecting support 204 are peeled off from the mother substrate 200. To selectively etch the release layer 201, a compound semiconductor with an etching resistance different from either the mother substrate 200 or the second component 61 is used as the release layer 201.

[0075] like Figure 4E As shown, a structure is prepared to be formed on the first component 51 ( Figure 2 The substrate 210 includes the switch 42, switch control circuit 40, temperature sensor 41, and multilayer wiring structure 53. At this stage, the substrate 210 is not separated into individual first components 51.

[0076] like Figure 4F As shown, the second component 61 is bonded to the substrate 210. The bonding between the second component 61 and the substrate 210 is based on van der Waals bonds or hydrogen bonds. Alternatively, the second component 61 can be bonded to the substrate 210 via electrostatic forces, covalent bonds, eutectic alloy bonds, etc. For example, if a portion of the surface of the substrate 210 is formed of Au, the two can be bonded by pressing the second component 61 tightly against the Au region.

[0077] Next, as Figure 5A As shown, the connecting support 204 is peeled off from the second component 61. After peeling off the connecting support 204, as... Figure 5B As shown, an interlayer insulating film 77 and a redistribution layer are formed on the substrate 210 and the second component 61. The redistribution layer includes inter-component interconnect wiring 71, solder pads 72, etc.

[0078] Next, as Figure 5C As shown, a protective film 78 is formed on the redistribution layer, and an opening is formed at a predetermined position on the protective film 78. Subsequently, a conductor protrusion 82 is formed within the opening and on the protective film 78.

[0079] Finally, as Figure 5D As shown, substrate 210 is cut. This yields power amplifier 20. In the monolithic power amplifier 20, the first component 51 is larger than the second component 61 when viewed from above. Power amplifier 20 is flip-chip mounted on a module substrate, etc.

[0080] Next, refer to Figures 6-8 The accompanying drawings illustrate the excellent effect of setting switch 42 on the power amplifier 20 in the first embodiment.

[0081] Figure 6 This is a graph illustrating an example of the breakdown voltage characteristics of an HBT. The horizontal axis represents the collector voltage, and the vertical axis represents the collector current. Figure 6 The solid and dashed lines in the graph represent the breakdown boundaries at room temperature and low temperature, respectively. If the collector voltage and collector current of the HBT exceed the breakdown boundaries, the HBT breaks down. If the collector voltage increases at room temperature, a region appears where the collector current drops sharply, representing the breakdown boundary. This collector voltage is called the breakdown voltage. The HBT must operate within a range where the collector voltage does not exceed the breakdown voltage. If the HBT temperature becomes low, then... Figure 6 The middle arrow indicates a decrease in breakdown voltage.

[0082] Figure 7A , Figure 7B as well as Figure 8 It means to apply to Figure 1 The graph shows the simulation results of the instantaneous collector voltage and instantaneous collector current of transistor 22T in the power stage amplifier circuit 22 shown. Figure 7A as well as Figure 7B The horizontal axis represents time in units of "ns". Figure 7A The vertical axis represents the instantaneous collector voltage in arbitrary units. Figure 7B The vertical axis represents the instantaneous collector current in arbitrary units. Figure 8 The horizontal axis represents instantaneous collector voltage in arbitrary units, and the vertical axis represents instantaneous collector current in arbitrary units.

[0083] In this simulation, the input signal frequency was set to 1.9 GHz. Furthermore, the simulation assumed an impedance mismatch due to load variations, resulting in a voltage standing wave ratio (VSWR) of 5. Figure 1 The parasitic inductance PL shown is zero. The thick solid line, thin solid line, and dashed line in the graph represent the parasitic inductance PL being zero. Figure 1The simulation results for the clamping diode 30 with six, four, and two stages are shown in the equivalent circuit diagram. Let Vf denote the forward voltage of each clamping diode 30, and N denote the number of stages of the clamping diode 30. If the instantaneous collector voltage exceeds Vf × N, a forward current flows through the clamping diode 30, suppressing the rise of the instantaneous collector voltage. Therefore, the fewer the stages N of the clamping diode 30, the better it can suppress the peak value of the instantaneous collector voltage.

[0084] Furthermore, increasing the number of stages in the clamping diode 30 ensures sufficient dynamic load line for the collector voltage, thus increasing the peak value of the instantaneous collector voltage. Under this condition, the peak value of the instantaneous collector current is suppressed in the current-voltage characteristics compared to the case with fewer stages in the clamping diode 30.

[0085] according to Figure 7A , Figure 7B , Figure 8 The simulation results show that reducing the number of clamping diodes 30 increases the reduction in the peak value of the instantaneous collector voltage. This is to ensure that the instantaneous collector voltage of the transistor does not exceed the breakdown boundary (…). Figure 6 At low temperatures, the number of stages of clamping diode 30 can be reduced. In the first embodiment, when the measured value of temperature sensor 41 is below a first threshold, switch 42 ( Figure 1 The clamping diode 30 is switched on, thereby reducing the effective number of stages. Therefore, even with load variations, the peak value of the instantaneous collector voltage of transistor 22T at low temperatures can be suppressed. This, in turn, prevents the breakdown of transistor 22T.

[0086] Furthermore, in the first embodiment, if the temperature of the transistor exceeds the second threshold, switch 42 is turned off, causing the effective number of the clamping diode 30 to return to its original number. Therefore, for example at room temperature, the instantaneous collector voltage can be made to fluctuate within a range approximately up to the upper limit of the breakdown boundary of transistor 22T, thus suppressing unnecessary reductions in output.

[0087] Next, refer to Figure 9A , Figure 9B as well as Figure 10 In the power amplifier 20 of the first embodiment, the lead 31 of the multi-stage clamping diode 30 is connected by the inter-component connection wiring 71. Figure 2 The excellent effect of switch 42 will be explained.

[0088] Figure 9A , Figure 9B as well as Figure 10 It means to apply to Figure 1 The graph shows the simulation results of the instantaneous collector voltage and instantaneous collector current of transistor 22T in the power stage amplifier circuit 22 shown. Figure 9A as well as Figure 9B The horizontal axis represents time in units of "ns". Figure 9A The vertical axis represents the instantaneous collector voltage in arbitrary units. Figure 9B The vertical axis represents the instantaneous collector current in arbitrary units. Figure 10 The horizontal axis represents instantaneous collector voltage in arbitrary units, and the vertical axis represents instantaneous collector current in arbitrary units.

[0089] In this simulation, the frequency of the input signal and the voltage standing wave ratio based on load variation are... Figure 7A , Figure 7B , Figure 8 The simulation conditions are the same. The thick and thin solid lines in the graph represent the conditions for... Figure 1 The equivalent circuit diagram shown has zero parasitic inductance PL, and simulation results are obtained with six and three stages of clamping diode 30. The dashed line in the graph represents the result when... Figure 1 The equivalent circuit diagram shown has a parasitic inductance PL of 1nH and simulates the effect when the clamping diode 30 has three stages.

[0090] When the parasitic inductance PL is zero, reducing the number of stages of the clamping diode 30 from six to three, as shown by the thick and thin solid lines, suppresses the peak value of the instantaneous collector voltage. However, when the parasitic inductance PL is 1nH, as shown by the thick and dashed lines, it is evident that even reducing the number of stages of the clamping diode 30 does not achieve the effect of suppressing the peak value of the instantaneous collector voltage. For example, if the lead 31 of the multi-stage clamping diode 30 is connected to the switch 42 using a bonding wire, a parasitic inductance of approximately 1nH is generated. Therefore, when using a bonding wire, even if the switch 42 is turned on to reduce the effective number of stages of the clamping diode 30, the effect of further suppressing the peak value of the instantaneous collector voltage is almost negligible.

[0091] The following explains why it is almost impossible to suppress the peak value of the transient collector voltage. If the parasitic inductance PL increases, the voltage drop from the power stage amplifier circuit 22 ( Figure 1 The impedance of the output port of the power stage amplifier circuit 22 towards the ground line increases via switch 42. Additionally, since the output impedance of the power stage amplifier circuit 22 is originally low, the output matching circuit 23 is configured to be lower. Figure 1 The load impedance is relatively high due to the parasitic inductance PL. Therefore, it is not easy to achieve the effect of allowing the peak voltage of the instantaneous collector voltage to escape to the ground.

[0092] In the first embodiment, the lead 31 of the multi-stage clamping diode 30 and the switch 42 are connected via the component interconnect wiring 71 included in the redistribution layer. Figure 2The connection is made so that the parasitic inductance LPL is reduced compared to the configuration that connects the two via a junction line. Therefore, by turning on switch 42, the effective number of clamping diodes 30 can be reduced, thereby achieving a sufficient effect to further suppress the peak value of the transient collector voltage.

[0093] Next, other superior effects of the first embodiment will be described.

[0094] In the first embodiment ( Figure 2 In this configuration, the second component 61 is in surface contact with the first component 51, resulting in a lower thermal resistance along the heat conduction path from the transistor 22T disposed on the second component 61 to the first component 51. Heat generated by the transistor 22T is conducted to the first component 51 through the interface between the first component 51 and the second component 61. The heat conducted to the first component 51 diffuses within it and dissipates from its surface to the outside. Furthermore, since the first component 51 has a larger heat capacity compared to the second component 61, it functions as a heat sink.

[0095] To improve the heat dissipation characteristics of the first component 51, it is preferable to use a semiconductor material with a higher thermal conductivity than the compound semiconductor material constituting the transistor 22T for the semiconductor region of the first component 51, such as the semiconductor substrate 52. For example, it is preferable to use a monomeric semiconductor, SiC, etc., for the semiconductor region of the first component 51.

[0096] Furthermore, in the first embodiment ( Figure 2 In the module, the heat generated by transistor 22T is conducted to the module substrate via solder pad 72 and conductor protrusion 82. This forms two heat conduction paths: one from transistor 22T to the first component 51 and the other from conductor protrusion 82 to the module substrate, thus improving the effect of suppressing the temperature rise of transistor 22T.

[0097] Furthermore, in the first embodiment, the temperature sensor 41 is disposed on the first component 51 which is in contact with the surface of the second component 61. Therefore, the temperature rise caused by the self-heating of the transistor 22T disposed on the second component 61 can be quickly reflected in the measured value of the temperature sensor 41. Therefore, it is possible to obtain the excellent effect that the temperature change of the transistor 22T can be quickly reflected in the on / off control of the switch 42. In order to make the temperature change of the transistor 22T easily reflected in the measured value of the temperature sensor 41, such as Figure 2 As shown, the temperature sensor 41 and the second component 61 are preferably configured to overlap each other when viewed from above.

[0098] Furthermore, in the first embodiment, the second component 61, which includes the compound semiconductor transistor 22T, is in surface contact with the first component 51, which is provided with the switch control circuit 40, etc. Therefore, compared with the configuration in which the compound semiconductor chip including the transistor 22T and the chip including the switch control circuit 40 are independently mounted on the module substrate, the power amplifier 20 can be miniaturized.

[0099] [Second Embodiment]

[0100] Next, refer to Figure 11 as well as Figure 12 The power amplifier of the second embodiment will be described below. Hereinafter, the power amplifier will be compared with that of the referenced... Figures 1-10 The power amplifier of the first embodiment, which is illustrated in the accompanying drawings, has the same configuration as described above and is omitted from the description.

[0101] Figure 11 This is a schematic cross-sectional view of the power amplifier 20 according to the second embodiment. Furthermore, in Figure 11 In the diagram, a portion of the circuit is schematically shown using circuit diagram symbols and dashed lines. In the first embodiment ( Figure 2 In the first embodiment, the lead 31 of the multi-stage clamping diode 30 and the switch 42 are connected via inter-component connection wiring 71 in the redistribution layer. In contrast, in the second embodiment, the lead 31 of the multi-stage clamping diode 30 and the switch 42 are connected via a path that intersects the interface that contacts the second component 61 and the first component 51.

[0102] The first component 51 of the power amplifier 20 in the second embodiment includes an adhesive layer 56 disposed on a multilayer wiring structure 53. The adhesive layer 56 is divided into multiple metal regions 56B, 56D, etc., and an insulating region 56C that insulates the multiple metal regions from each other. For example, the adhesive layer 56 can be formed using a metal inlay method. Figure 4E In the manufacturing process shown, an adhesive layer 56 is formed on the substrate 210. The lead 31 of the multi-level clamping diode 30 is electrically connected to the switch 42 via a path including the metal region 56B and the wiring 55 within the multilayer wiring structure 53. This path intersects the interface where the first component 51 and the second component 61 are in surface contact.

[0103] Another solder pad 73 is connected to the wiring within the multilayer wiring structure 53 via the metal region 56D of the adhesive layer 56.

[0104] Figure 12 This is a cross-sectional view of a portion of the first component 51 and the second component 61 of the power amplifier in the second embodiment. In the first embodiment ( Figure 3In the first embodiment, the substrate semiconductor layer 62 of the second component 61 is bonded to the multilayer wiring structure 53 of the first component 51. Conversely, in the second embodiment, the substrate semiconductor layer 62 of the second component 61 is bonded to the adhesive layer 56 of the first component 51. In top view, the conductive region 62A containing the transistor 22T overlaps with the metal region 56A of the adhesive layer 56, and the two are electrically connected. In top view, the conductive region 62B containing a clamping diode 30 overlaps with the metal region 56B of the adhesive layer 56, and the two are electrically connected. The component separation region 62C of the substrate semiconductor layer 62 overlaps with the insulating region 56C of the adhesive layer 56 in top view, ensuring electrical insulation between the multiple conductive regions within the substrate semiconductor layer 62 and between the multiple metal regions of the adhesive layer 56.

[0105] Metal region 56B is electrically connected to switch 42 via wiring 55 within multilayer wiring structure 53. Figure 12 The cathode layer 63N of the clamping diode 30 in the cross-section shown corresponds to the lead-out point 31. Figure 1 The conductive region 62B, the metallic region 56B, and the wiring 55 constitute the lead-out point 31. Figure 1 The path between ) and switch 42.

[0106] Next, the superior effects of the second embodiment will be explained.

[0107] In the second embodiment, bonding wires are not used either; instead, the leads 31 of the multi-stage clamping diodes 30 are connected. Figure 1 The circuit is electrically connected to switch 42. The parasitic inductance of the path formed by the conductive region 62B, the metal region 56B, and the wiring 55 connecting the two is smaller than the parasitic inductance of the junction line. Therefore, in the second embodiment, as in the first embodiment, sufficient effect to further suppress the peak value of the instantaneous collector voltage can be obtained by reducing the effective number of stages of the clamping diode 30 by turning on switch 42.

[0108] Furthermore, in the second embodiment, the same as in the first embodiment, the effect of suppressing the temperature rise of transistor 22T can be obtained, and the miniaturization of power amplifier 20 can be achieved.

[0109] [Third Embodiment]

[0110] Next, refer to Figure 13 The power amplifier of the third embodiment will be described below. Hereinafter, the power amplifier will be compared with that of the referenced... Figures 1-10 The power amplifier of the first embodiment, which is illustrated in the accompanying drawings, has the same configuration as described above and is omitted from the description.

[0111] Figure 13 This is a block diagram of the power amplifier in the third embodiment. In the first embodiment ( Figure 1In the first embodiment, a multi-stage clamping diode 30 is connected between the output port 22out of the power stage amplifier circuit 22 and the ground line 32, while no clamping diode is connected at the output port of the driver stage amplifier circuit 21. In contrast, in the third embodiment, a multi-stage clamping diode 35 is also connected between the output port 21out of the driver stage amplifier circuit 21 and the ground line 32. The number of stages of the clamping diode 35 connected to the driver stage amplifier circuit 21 does not need to be the same as the number of stages of the clamping diode 30 connected to the same power stage amplifier circuit 22. An inter-stage matching circuit 25 is connected between the driver stage amplifier circuit 21 and the power stage amplifier circuit 22.

[0112] The lead-out point 36 of the multi-stage clamping diodes 35 in the driver stage amplifier circuit 21 is connected to ground 32 via switch 43. The lead-out point 36 on the driver stage amplifier circuit 21 side is connected to the component connection wiring 71 via... Figure 2 The wiring between other components on the same redistribution layer is connected to switch 43. Switch control circuit 40 controls the on / off state of switch 42 and switch 43.

[0113] Next, the superior effects of the third embodiment will be explained.

[0114] In the third embodiment, the leads 36 of the multi-stage clamping diodes 35 in the driver stage amplifier circuit 21 are connected to the switch 43 via inter-component connection wiring within the redistribution layer, instead of using bonding wires. Therefore, in the driver stage amplifier circuit 21, by turning on the switch 43, the effective number of clamping diodes 35 can be reduced, thus achieving a sufficient effect of suppressing the peak value of the transient collector voltage. Furthermore, similar to the first embodiment, the third embodiment also achieves the effect of suppressing the temperature rise of the transistor 22T, and enables miniaturization of the power amplifier 20.

[0115] Next, a variation of the third embodiment will be described.

[0116] In the third embodiment, the lead 36 of the multi-stage clamping diode 35 of the driver amplifier circuit 21 is connected to the switch 43 via inter-component interconnect wiring within the redistribution layer. However, it can also be done as follows: Figure 11 as well as Figure 12 As shown in the second embodiment, the switch 43 is connected via a path that intersects the interface that contacts the surfaces of the first component 51 and the second component 61.

[0117] In the third embodiment, two switches 42 and 43 are used, but a single SPDT switch can also be used instead. In this case, the common terminal of the SPDT switch is connected to ground 32, one contact is connected to one lead-out point 31, and the other contact is connected to another lead-out point 36. Alternatively, the driver stage amplifier circuit 21 and the power stage amplifier circuit 22 can share a single SPST switch. In this case, one contact of the SPST switch is connected to both leads 31 and 36.

[0118] [Fourth Embodiment]

[0119] Next, refer to Figure 14 The power amplifier of the fourth embodiment will be described below. Hereinafter, the power amplifier will be compared with that of the referenced... Figures 1-10 The power amplifier of the first embodiment, which is illustrated in the accompanying drawings, has the same configuration as described above and is omitted from the description.

[0120] Figure 14 This is a schematic cross-sectional view of the power amplifier according to the fourth embodiment. Furthermore, in Figure 14 In the diagram, a portion of the circuit is schematically shown using circuit diagram symbols and dashed lines. In the first embodiment ( Figure 2 In the first embodiment, switch 42 is located in the first component 51. In contrast, in the fourth embodiment, switch 42 is located in the second component 61. Switch 42 is, for example, a compound semiconductor FET or HEMT. Furthermore, the transistor 22T of the power stage amplifier circuit 22 is a heterojunction bipolar transistor. Therefore, the second component 61 uses a BiFET structure or a BiHEMT structure.

[0121] The multi-stage clamping diode 30 and the switch 42 are both located in the second component 61. The lead 31 of the multi-stage clamping diode 30 and the switch 42 are interconnected via wiring formed by metal patterns within the second component 61. The switch control circuit 40 located in the first component 51 provides control signals to the switch 42 to control its on / off state via wiring 57 within the multi-layer wiring structure 53 and inter-component connection wiring 75 within the re-wiring layer.

[0122] Next, the superior effects of the fourth embodiment will be explained.

[0123] In the fourth embodiment, the lead 31 of the multi-stage clamping diode 30 is connected to the switch 42 via wiring formed by a metal pattern within the second component 61, and the connection between the two does not use a bonding wire. Therefore, when the switch 42 is turned on, the connection from lead 31 to ground 32 is made possible. Figure 1The parasitic inductance PL of the path is reduced. Therefore, turning on switch 42 provides sufficient suppression of the instantaneous collector voltage peak. Furthermore, in the fourth embodiment, similar to the first embodiment, the temperature rise of transistor 22T is suppressed, and miniaturization of the power amplifier 20 is achieved.

[0124] The above embodiments are illustrative examples, and of course, different substitutions or combinations of the components shown in the embodiments are possible. The same effects resulting from the same configuration in multiple embodiments are not mentioned sequentially for each embodiment. Furthermore, the present invention is not limited to the above embodiments. For example, those skilled in the art will recognize that various changes, improvements, combinations, etc., can be made.

Claims

1. A power amplifier, comprising: The first component includes a semiconductor region; and The second component is coupled to a first surface that is one side of the first component, and includes a semiconductor region of a compound semiconductor system. The second component mentioned above includes: Amplification circuits, including compound semiconductor transistors; as well as Multiple clamping diodes are connected in multiple stages and inserted between the output port of the amplifier circuit and the ground line, so that the direction from the output port to the ground line is positive. The aforementioned first component includes: The switch is connected between the lead-out point and the ground wire. The lead-out point is the midpoint of the multiple clamping diodes connected in a multi-stage manner. A temperature sensor measures the temperature of the aforementioned transistor; and The switch control circuit, if the measured value of the temperature sensor is below a first threshold, then turns on the switch; if the measured value of the temperature sensor becomes above a second threshold when the switch is on, then turns the switch back to off. The aforementioned lead-out point is connected to the aforementioned switch via a path including inter-component connection wiring, or via a path intersecting the interface where the aforementioned first component and the aforementioned second component are joined. The aforementioned inter-component connection wiring is disposed on an interlayer insulating film from the aforementioned first surface of the aforementioned first component to the surface of the aforementioned second component and is formed by a metal pattern.

2. The power amplifier according to claim 1, wherein, The temperature sensor is positioned at a location that overlaps with the second component when viewed from above.

3. The power amplifier according to claim 1 or 2, wherein, It also has conductor protrusions that protrude from the first surface of the first component and the surface of the second component, respectively.

4. The power amplifier according to claim 1 or 2, wherein, The second component is in contact with the first surface of the first component.

5. The power amplifier according to claim 3, wherein, The second component is in contact with the first surface of the first component.

6. A power amplifier, comprising: The first component includes a semiconductor region; and The second component is coupled to a first surface that is one side of the first component, and includes a semiconductor region of a compound semiconductor system. The second component mentioned above includes: Amplification circuits, including compound semiconductor transistors; Multiple clamping diodes are inserted between the output port of the aforementioned amplifier circuit and the ground wire, such that the direction from the output port towards the ground wire is positive, and are connected in series with each other; and The switch is connected between the lead-out point and the ground wire. This lead-out point is a midway point in the multi-stage connection of the aforementioned clamping diodes. The aforementioned first component includes: A temperature sensor measures the temperature of the aforementioned transistor; as well as The switch control circuit turns on the switch if the measured value of the temperature sensor is below a first threshold, and turns off the switch if the measured value of the temperature sensor becomes above a second threshold when the switch is turned on.

7. The power amplifier according to claim 6, wherein, The temperature sensor is positioned at a location that overlaps with the second component when viewed from above.

8. The power amplifier according to claim 6 or 7, wherein, It also has conductor protrusions that protrude from the first surface of the first component and the surface of the second component, respectively.

9. The power amplifier according to claim 6 or 7, wherein, The second component is in contact with the first surface of the first component.

10. The power amplifier according to claim 8, wherein, The second component is in contact with the first surface of the first component.

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